Reg.No.

:
VIVEKANANDHA COLLEGE OF ENGINEERING FOR WOMEN
[AUTONOMOUS INSTITUTION AFFILIATED TO ANNA
UNIVERSITY, CHENNAI]
Elayampalayam 637 205, Tiruchengode, Namakkal Dt., Tamil
Nadu.
Answer Key
B.E. / B.Tech. DEGREE END- SEMESTER EXAMINATION, NOV. / DEC. 2016.
Fifth Semester
U14EC518 DIGITAL SIGNAL PROESSING
(Regulation 2014)
Time : Three hours

Maximum : 100 marks

PART A

Answer ALL Questions

(20 x 1 = 20 marks)

(Objective type with every wrong answer carrying 0.25 Negative Mark)
1.
b)
25,20
2.
d)
32,64
1
3.
c)

x1 (n) x2 (n)

4.
5.
6.
7.
8.
9.

a)
d)
a)
b)
d)
c)

X 1 (k ) N

1
Has linear phase response
(3.11 )/N
Relative side lobe , Main lobe
All the above
| H a ( ) |

2
2
1 C N

10.

a)
N

11.

a)

12.
13.
14.
15.
16.
17.
18.

d)
c)
d)
b)
d)
c)
a)

X 2 (k )

N 1,2,3,

1
2

1

1
log 2 1 2 1
s
p
1

2

log s

p

h( n) 0

for n 0 and

Ts

| h(k ) |

2 ( b1) e 2 ( b1)

Signal scaling
1.111
Multirate
TMS320C67x
TM320C50
1

19.
20.

d)
b)

IREG
Output data from data memory location to I/O port
PART B

Answer ALL Questions

(10 x 2 = 20 marks)

(Objective type with every wrong answer carrying 0.5 Negative Mark)
21. b) -2 & -2+j2
22. d) {14,16,14,16}
23. c) 1/4
24. a) 7
25. d) 7
26. a) 4
27. b) 0.11101 2 01001
28. c) y(n) = {1,0,2,0,4,0,-2,0,3,0,2,0,1,0,. }
29. b) 20h
30. d) 2s complement of 5
PART C
Answer ALL Questions

(6 x 10 = 60 marks)

31. a) x(n)= {1,2,3,4,-5,6,7,8}

N=8, No of twiddle factor required =N/2= 8/2=4.
WNK W8K

For k=0, W80 W40 W20 1

j sin
0.707 j 0.707
4
4

1
j / 4
cos
For k=1, W8 e

j sin j
2
2

2
1
j / 2
cos
For k=1, W8 W4 e

3
3
j sin
0.707 j 0.707
4
4

3
j 3 / 4
cos
For k=3, W8 e

x(0)=1

Bit reversed
input x(n)
x(0)=1

x(1)=2

x(4)=-5

6+j4

6+j9.656

x(2)=3

x(2)=3

10

-14

-14+j4

x(3)=4

x(6)=7

-4

6-j4

6+j1.656

X(3)=6+j1.656

x(4)=-5
x(5)=6

x(1)=2
x(5)=6

8
-4

20
-4+j4

-14
6-j1.656

X(4)=-14
X(5)=6-j1.656

x(6)=7

x(3)=4

12

-4

-14-j4

Input x(n)

Stage I

Stage- II

Stage- III

-4

26

Output X(k)
X(0)=26
X(1)=6+j9.656
X(2)=-14+j4

X(6)=-14-j4

x(7)=8

x(7)=8

-4

-4-j4

6-j9.656

X(7)=6-j9.656

X(k)={ 26, 6+j9.656, -14+j4, 6+j1.656, -14, 6-j1.656, -14-j4, 6-j9.656}

(OR)
b) i. Overlap-save method
The input sequence can be divided into blocks of data as follows.

x1 ( n) {0,0

3,1,0}

x 2 (n )

{
1,0

M 1 2 Zeros

L3 data
points

1,3,2}

datas from provious block

new

data

po int s

x3(n) = {3,2,0,1,2} and x4(n) = {1,2,1,0,0}

given h(n)={1,1,1}
Increase the length of the sequence to L+M-1=5 by adding two zeros.
i.e. h(n) = {1,1,1,0,0}
y1 (n) = x1(n) N h (n) = {-1, 0, 3, 2, 2}
y2 (n) = x2(n) N
N h (n) = {4, 1, 0, 4, 6}
y3 (n) = x3(n) N h n) = {6, 7, 5, 3, 3}
y4 (n) = x4(n) N h (n) = {1, 3, 4, 3, 1}
-1, 0, 3, 2, 2
N
N
discard

4, 2, 0, 4, 6
discard

6, 7, 5, 3, 3

discard

1, 3, 4, 3, 1

discard

y (n)= {3, 2, 2, 0, 4, 6, 5, 3, 3, 4, 3, 1}
ii. Overlap-add method
Let the length of data block be 3. Two zeros are added to bring the length to
five (L+M+-1=5).
Therefore,
x1 (n) = {3, -1, 0, 0, 0}
x2 (n) = {0, 1, 2, 0, 0}
x3 (n) = {0, 1, 2, 0, 0}
x4 (n) = {1, 0, 0, 0, 0}
y1 (n) = x1 (n)
y2 (n) = x2(n)
y3 (n) = x3(n)
y4 (n) = x4(n)

h (n) = {3, 2, 2, -1, 0}

h (n) = {1, 4, 6, 5, 2}
h (n) = {0, 1, 3, 3, 2}
h (n) = {1, 1, 1, 0, 0}

N
N
N
N

3, 2, 2, -1, 0
add
1, 4, 6, 5, 2
add
0, 1, 3, 3, 2
add
1, 1, 1, 0, 0

y (n)= {3, 2, 2, 0, 4, 6, 5, 3, 3, 4, 3, 1}
34. a)

hd (n)

1
[
2

/ 4

j n
e d

jn

d ]

/4

1
n
[sin n sin ] for n and
n
4
/ 4

1
3
hd (0)
[ d d ] 0.75
2
4
/4
hd ( n)

hd(0) = 0.75
hd(1) = hd(-1)= -0.225
hd(2) = hd(-2)= -0.159
4

n0

hd(3) = hd(-3)= -0.075

hd(4) = hd(-4)= 0
hd(5) = hd(-5) = 0.045
The hamming window function is given by
2n
M 1
otherwise

whn (n) 0.5 0.5 cos

0
for

M 1
M 1
)n(
)
2
2

N 11

whn (n) 0.5 0.5 cos

n
5

5 n 5

whn(0) = 1
whn(1) = whn(-1)=0.9045
whn(2)= whn(-2)=0.655
whn(3)= whn(-3)= 0.345
whn(4)= whn(-4)=0.0945
whn(5)= whn(-5)=0
h(n)= whn(n)hd(n)

b)

h(n)=[0 0 -0.026 -0.104 -0.204 0.75 -0.204 -0.104 -0.026 0 0]

(OR)
The desired response can be expressed as
H d (e j ) e
with

j (

M 1
)
2

for

| | c

0
otherwise
M 17 and c / 2

H d ( e j ) e j 8
0

Selecting k

for

0 /2

for

/2

2k 2k

M
17

H ( k ) H d ( e j ) |

for

k 0,1,......16

2k
17

2k
8
17

2k

17
2
2k
0
for
/2

17
16k
j
17
H ( k ) e 17
for 0 k
4
17
17
0
for
k
4
2
H (k ) e

for

The range for k can be adjusted to be an integer such as

0k 4
and 5 k 8

The freq response is given by

H (k ) e
0

2k
8
17

for

for 0 k 4
5k 8

Using these value of H(k) we obtain h(n) from the equation

( M 1) / 2
1
h(n)
( H (0) 2 Re( H ( k )e j 2kn / M ))
M
k 1
i.e., h( n)
h( n)

4
1
(1 2 Re(e j16k / 17 e j 2kn / 17 ))
17
k 1

4
1
2k (8 n)
( H (0) 2 cos(
)
17
17
k 1

for

n 0,1,........16

37. a)

Even though k varies from 0 to 16 since we considered varying between 0

and /2 only k values from 0 to 8 are considered
While finding h(n) we observe symmetry in h(n) such that n varying 0 to 7 and
9 to 16 have same set of h(n)
= 1 , =4.89 , N2.3583 therefore N=3
=2.414
Minor axis a=0.4643
Minor axis b=0.7824
s k a cos k jb sin k Where k=1, 2, 3. Where k

1
2

2 6
3

s1 0.46398 j 0.677732

2 6

2k 1

; k 1,2,3.
2 2 N

5
4

2 6
3

s 2 0.46398 j 4.63692 10 4

s3 0.232186398 j 0.0571488

Nr of the transfer function is 0.6861+j0.0607

6

0.6861 + j0.0607
s 0.46398 j 0.677732 s 0.46398 4.63692 10 4 s 0.232186398 j 0.0571488

H ( s)

(OR)
b)

= 0.8822 , =31.607 , N3.9

Therefore N=4
For N=4,
The Ideal low pass Butterworth filter response is denoted as
H (s)

1
s 0.76537 s 1 s 2 1.8477 s 1

c 21.087 rad / sec .(or ) 20.6366 rad / sec

Therefore c 21 rad / sec

Frequency transformation :
Ideal low pass to required High Pass filter
s

c 21

s
s

H a ( s)

21

s

H a (s)

1
21
21
0.76537
1

s
s

21
1.8477
1
s

s4
s 2 16.073s 441 s 2 38.8017 s 441

Analog to Digital transformation: (Bilinear Transformation Technique)

2 1 z 1

1
T 1 z

H ( z ) H a ( s ), with s

H ( z)

2 1 z

1
T 1 z
1

H ( z)

2 z 1

T z 1

2 1 z 1

T 1 z 1

441

2 1 z
16.073

T 1 z 1

249358.1219[1 3.50412 z 1

(or ) s

2 1 z 1

1
1 z

2 1 z 1
38.8017

T 1 z 1

16 1 z 1
4.631639 z 2 2.73477 z 3 0.60828 z 4 ]

0.00006416 1 z 1
1 3.50412 z 1 4.631639 z 2 2.73477 z 3 0.60828 z 4
The round off noise model for H (z)= H1(z)H2(z) is given by,

H ( z)

40. a)

441

H1 (z)
x (n)

H2 (z)

y (n)

e2

e1 (n)

(n)

-1

a1

-1

a
2

From the realization we can find that the noise transfer function seen by noise
source e1(n) is H(z), where H ( z )

1
1 a1 z 1 a2 z 1

Whereas the noise transfer function seen by e2(n) is H 2 ( z )

1
1 a2 z 1

2
2
The total steady state noise variance can be obtained from 0 0 k . Thus
k

2
2
2
we have 0 01 02
2
2 1
H k ( z ) H k ( z 1 ) z 1dz k
Where 0 k e

2j
1
012 e2
H ( z ) H ( z 1 ) z 1dz

c
2j
1
1
1
1
1
e2
z 1dz

2j c1 a1 z 1 a 2 z 1 a1 z 1 a2 z

e2

of residue of H ( z) H ( z

) z 1 at poles z a1 , z a 2 , z 1

a1

andz 1

a 2

If a1 and a2 are less than 1 then the poles z 1 a and z 1 a lies outside of
1
2
the circle |z|=1. So, the residues of H (z) H (z-1) z-1at z 1 a and z 1 a are
1
2
zero. Consequently we have
012 of residue of H ( z ) H ( z 1 ) z 1 at poles z a1 , z a2

z 1
z a1
1 a1 z 1 1 a2 z 1 1 a1 z 1 a 2 z

z a2
z a1

z 1
1 a2 z 1 1 a1 z 1 a2 z

1 a z
1

z a2

1
1

2
2
a2
a1

a
1

a
1
a
2

a
1
a
2
1

a
1
2
a
1
a
2

e2

a1
1
1
a2
1
1
.
.

.
.
2
2
a1 a 2 1 a1 1 a1a 2 a1 a 2 1 a1a 2 1 a 2
In the same way
e2
2
02
H 2( z ) H 2( z 1 ) z 1dz

c
2j

012 e2

e2
1
1
.
z 1 dz
1

c
2j 1 a2 z 1 a2 z

z 1
2e z a2
z a 2
1
1 a 2 z 1 a 2 z

1
2e 1 a2 z 1
z a 2
1
1 a 2 z 1 a 2 z

1
e2
2
1 a2
Submitting the above equation

1
a1
1
1
a
1
1
2
2
0 e

.
.
21 .
.
2
2 a1 a2 1 a1 1 a1a2 a2 a1 1 a1a2 1 a22
1 a
2

a1 1 a22 a2 1 a12

2
2
2
1 a2 1 a1 1 a2 1 a1a2 a1 a2

1
a1 a2 1 a1a2

2
2
2
1 a2 1 a1 1 a2 1 a1a2 a1 a2

2 2 b 1
1 a1a2

2
2
2
12 1 a2 1 a1 1 a2 1 a1a2

e2

The steady state noise power for a1 0.5, a2 0.6 is given by,

2 2b
1
1 0.5 0.6

2
2
2
12 1 0.6
1 0.5 1 0.6 1 0.5 0.6

2 2b
5.4315
12

(OR)
b) Assume 4-bit sign magnitude representation (excluding sign bit)
The input is given by,
x(n) 0.875
for n 0
0
otherwise
Because of infinite length register the product 0.95y (n-1) in the difference equation
must be rounded to 4 bits before adding to x (n).
9

The output y (n) with rounding is given by y(n) = x(n) + Q[0.95y(n - 1)]
Where Q [] stands for quantization.
For n=0
y(n) = Q[0.95 y(-1)] + x(0) = 0.875
y(-1) 0
For n=1
y(1) Q[0,95y(0)] x(1)
Q[0.95(.875) ] 0
Q[0.83125]
(0.83125)10 (0.1101010 ....) 2
After rounding we get Q [0.83125] = (0.1101)2 = (0.8125)10
Therefore, y (1) =0.8125
For n=2
y(2) Q[0,95y(1)] x(2)
Q[0.95(.8125) ]
Q[0.771875]
(0.771875)10 (0.110001 ....) 2
After rounding we get (0.771875)10 (0.1100 ) 2 (0.75)10
Therefore y (2) = 0.75
For n=3
y (3) = Q[0.95(0.75)] + x(3)
= Q (0.7125]
Q[0.7125]10 0.101101 ... 2
After rounding we get,
Q[0.7125] 0.1011 2 0.6875 10
y (3) 0.6875
For n = 4

y (4) Q[(0.95)(0.6875)]x(4)
Q[0.653125] 0.101001... 2
After rounding we get,
Q[0.653125] 0.1010 2 0.625 10
y (4) 0.625

For n = 5

y (5) Q[(0.95)(0.625)]x (5)

Q[0.59375] 0.10011... 2
After rounding we get,
Q[0.59375] 0.1010 2 0.625 10
y (5) 0.625

For n = 6

y (6) Q[(0.95)(0.625)]x(6)
Q[0.59375] 0.1010... 2
After rounding we get,
Q[0.59375] 0.1010 2 0.625 10
10

From the above calculations it can be observed that for n 5 the output remains
constant at 0.625 causing limit cycle behavior.
Dead band
1 b
2
The dead band is given by, Deadband 2
1
1 4
2
Deadband 2
0.625
1 0.95
All general DSP Processors Core is composed of the Data Path, Control Path and
For b = 4
43. a)

Address Generation Unit (AGU). The Memory Subsystem is located out of the
processor core. These in turn are built up of various modules. A basic DSP processor
supports RISC and CISC instructions. The RISC uses the general registers for operands
and writes them back to the Register File (RF). The CISC used the memory subsystem
to compute vector elements like in the case of convolution.

11

Figure Functional Block diagram for TMS320C50

The CISC reads from the memory and write them to the accumulator special registers
located in the Multiplication and Accumulation (MAC). The memory bus is distributed
to the memory and DSP core DP components MAC and RF. However, there could be
more components that can be connected to the memory bus. This depends on the
choice of the instruction set which specifies all the operands required to perform a
certain instruction. If there are instructions that ALU performs by fetching operands
from the memory subsystem then the memory bus would also be connected to the ALU
and so on. The Control Path generates the control signals for all components in the
core, keeps track of the Program Counter and has a stack to service subroutines.
A part for the DSP core the DSP Processor will also contain the Direct Memory Access
(DMA), Memory Management Unit (MMU), Timer and Interrupt controller. The DMA
enhances the data transfer in parallel with core execution. The MMU is used to ensure
memory access reliability and efficiency. The Timer is used to check the execution
limit of a routine service. The interrupt controller handles the Processor core interrupts.
1. Multipliers
The multiplier takes the values from two registers, multiplies them, and places the
result into another register.
2. Shifter
In digital filtering, to prevent overflow, a scaling operation is required. A simple
scaling-down operation shifts data to the right, while a scaling-up operation shifts data
to the left.
3. MAC Unit
The MAC performs iterative computations and supports double precision. It is the
module which implements the hardware supporting auto correlation, filtering and
transform functions. The convolution, the most common DSP instruction is performed
in the MAC.

12

The MAC as its name needs hardware to perform multiplication and accumulation. The
multiplication is done by a signed multiplier and the accumulation of the multiplied
value with accumulator is done by adder.
4. ALU
As the name describes, the ALU does all the logic and arithmetic computations. In
some cases the ALU could also cover shifting and rotation operations.
There are 2 ways to design the ALU.
1.
The ALU could be a part of the MAC
2.
The ALU as an individual module

5. Bus Architecture
Separate program and data buses in the advance Harvard architecture of C5x maximize
the processing power and provide a high degree of parallelism.
i.
Program bus (PB)
ii.
Program address bus (PAB)
iii.
Data read bus (DB)
iv.
Data read address bus (DAB)
6. Memory
The memories are usually classified as Read Only Memory (ROM) and Random
13

Access Memory (RAM). RAM can further be classified as static and dynamic. In
general DSP processors there is RAM implemented as Program Memory and Data
Memories.
Program Memory (PM)
The PM in general is a single port synchronous static RAM. The application program is
loaded into the PM during start. The PC counter value determines the address from
where to fetch the instruction. The output of the PM is connected to the Instruction
Decoder. Other inputs to the PM will be the clock and reset.
Data Memory (DM)
The DM in general is a single port synchronous static RAM. There could be more than
one DM in the processor to support convolution instruction coefficients. The address
generators determine the address to where the data has to be written or read from. The
other inputs to the DM could be the operands from RF, clock and reset. The output of
the DM is connected to the MAC, RF and ALU.
Program Counter (PC)
The PC is a register that keeps the address of the next instruction to be fetched from the
Program Memory. The PC has a Finite State Machine (FSM) that points to the next
address to be loaded in to the PC register for instruction fetch.
Loop Controller (LC)
The Loop Controller (LC) has a register which loads the number of iterations to
perform. The LC keeps decrementing until it reaches a 0 and generated a loop flag
which will be used to check the iteration completion. The LC can support only one
instruction repeating n times. To perform m instructions n iterations we need to have an
advanced LC to support repeating m instructions n times.
Hardware Stack
A stack is used to support fast interrupts, register push/pop and call/return instructions.
When fast interrupts are used, there is a need to save the register and flag values to
service the interrupt. The stack is a normal stack with Last in First out (LIFO).
Conditional Execution Logic
The conditional execution logic checks if the condition satisfies so that the instruction
can be executed.
Instruction Decoder
The instruction decoder decodes the instruction fetched from Program Memory and
generates control signals to different parts of the core. Every instruction will drive a
number of control signals and every control signal could be driven by many
instructions.
On-chip peripherals
- 64K parallel I/O ports (16 I/O ports are memory mapped)
14

Sixteen software-programmable wait-state generators for program, data, and I/O

memory spaces
Interval timer with period, control, and counter registers for software stop, start,

and reset
Phase-locked loop (PLL) clock generator with internal oscillator or external clock

source
Multiple PLL clocking option (x1, x2, x3, x4, x5, x9, depending on the device)
Full-duplex synchronous serial port interface for direct communication between the

C5x and another serial device

- Time-division multiplexed (TDM) serial port (C50, C51, C53)
- Buffered serial port (BSP) (LC56, C57S, LC57)
- 8-bit parallel host port interface (HPI) (C57, C57S)
Central processing unit (CPU)
Central arithmetic logic unit (CALU) consisting of the following:
32-bit arithmetic logic unit (ALU), 32-bit accumulator (ACC), and 32-bit
accumulator buffer (ACCB)
16-bit 16-bit parallel multiplier with a 32-bit product capability
to 16-bit left and right data barrel-shifters and a 64-bit incremental data shifter
16-bit parallel logic unit (PLU)
Dedicated auxiliary register arithmetic unit (ARAU) for indirect addressing
Eight auxiliary registers
Program control
8-level hardware stack
4-deep pipelined operation for delayed branch, call, and return instructions
Eleven shadow registers for storing strategic CPU-controlled registers during an

b)

interrupt service routine (ISR)

Extended hold operation for concurrent external direct memory access (DMA) of

external memory or on-chip RAM

Two indirectly addressed circular buffers for circular addressing
Instruction set
Single-cycle multiply/accumulate instructions
Single-instruction repeat and block repeat operations
Block memory move instructions for better program and data management
Memory-mapped register load and store instructions
Conditional branch and call instructions
Delayed execution of branch and call instructions
Fast return from interrupt instructions
Index-addressing mode
Bit-reversed index-addressing mode for radix-2 fast Fourier transforms (FFTs)
(OR)
i.
Von Neumann architecture:
It refers to computer architectures that use the same data storage for their
15

instructions and data. A von Neumann Architecture computer has five pats: an
arithmetic-logic unit, a control unit, a memory, some form of input/output and a bus
that provides a data path between these parts.
A von Neumann Architecture computer performs or emulates the following sequence
of steps:
1. Fetch the next instruction from memory at the address in the program counter.
2. Add 1 to the program counter.
3. Decode the instruction using the control unit. The control unit commands the
rest of the computer to perform some operations. The instruction may change
the address in the program counter, permitting repetitive operations the
instruction ay also change the

program counter only if some arithmetic

condition is true, giving the effect of a decision which can be calculated to any
degree of complexity by the preceding arithmetic and logic.
4. Go back to step 1.
Von Neumann computers spend a lot of time moving data to and from the memory,
and his slows the computer (this problem is called Von Neumann bottleneck). So,
engineers often separate the bus into two or more buses, usually one for instructions
and the other for data.
This type of architecture is cheap requiring less pins that the Harvard architecture,
and simple to use because the programmer can place instructions or data anywhere
throughout the available memory. But it does not permit multiple memory accesses.
ii.

Harvard Architecture:

The term Harvard Architecture originally referred to computer architectures that used
separate data storage for their instructions and data.
The term Harvard Architecture is usually used now to refer to a particular
computer architecture design philosophy where separate data paths exist for the
transfer of instructions and data. All computers consist primary of two pats, the CPU
which processes data, and the memory which holds the data.

16

Memory can be made much faster, but only at high cost. The solution then is to
provide a small amount of very fast memory known as a cache.
The Harvard architecture refers to one particular solution to this problem.
Instructions and data are stored in separate caches to improve performance.
However this has the disadvantage of halving the amount of cache available to
either one, so it works best only if the CPU reads instructions and data at about the
same frequency.
The Harvard architecture requires two memory buses. This makes it expensive
to bring off the chip for example a DSP using 32 bit words and with a 32 bit address
space requires at least 64 pins for each memory bus a total of 128 pins if the Harvard
architecture is brought off the chip. This result is very large chips, which are difficult to
design into a circuit.
The true Harvard Architecture dedicates on bus for fetching instructions, with
the other available to fetch operands.

46. a)

Program
.mmregs
.text
START:
LDP #02H
LAR AR1,#8100H ; x(n) datas
lar ar0,#08200H ;h(n) datas
LAR AR3,#8300H ;y(n) starting
17

LAR AR4,#0007 ;N1+N2-1

;to fold the h(n) values
;************************
lar ar0,#8203H ; data mem 8200 to program mem c100(tblw)
lacc #0c100h
mar *,ar0
rpt #3
tblw *- ;to move 8203- 8200 to c100- c103
;padding of zerros for x(n) values
;**********************************
lar ar6,#8104h
mar *,ar6
lacc #0h
rpt #3h
sacl *+
;convolution operation starts
;******************************
LOP: MAR *,AR1
LACC *+
SACL 050H ;starting of the scope of multiplication
LAR AR2,#0153H ; end of the array, to be multiplied with h(n) {150+N1-1}
MAR *,AR2
ZAP
RPT #03H ;N1-1 times so that N1 times
MACD 0C100H,*APAC
;to accmulate the final product sample
MAR *,AR3
SACL *+
MAR *,AR4
BANZ LOP,*H: B H
(OR)
b)

Sine wave generator

The sine wave is given by the function
x=sin(2*pi*f*t)
FREQ .set 1
LENGTH .SET 360
AMPLITUDE .set 5
TEMP .set 0
TEMP1 .set 1
.mmregs
.text
18

START:
LDP #100H
SPLK #0C100H,TEMP ;load start address of table
lar AR2,#LENGTH
CONT:
LACC TEMP
;load address of sine value
TBLR TEMP1
;read sine data to TEMP1
LT TEMP1
MPY #AMPLITUDE
PAC
SACL TEMP1
OUT TEMP1,4
;send sine data to DAC
LACC TEMP
ADD #FREQ
;increase table value
SACL TEMP
;store it
MAR *,AR2
BANZ CONT,*b
START
.end

19