Introduction to Logic Design

EEE-248/CNG232
Lecture Notes
Dr. Ali Muhtarolu
Spring 2015
METU Northern Cyprus Campus

Introduction
Lecture 1

We live in the Digital Age

even though the world around us is analog

We live in the Digital Age

even though the world around us is analog
A typical embedded system:
Analog
Input
Devices

A-to-D
Converter
(ADC)

Digital
Input
Devices

Microcontroller
or Digital Signal
Processor (DSP)

D-to-A
Converter
(DAC)

Analog
Output
Devices

Digital
Output
Devices

External
Memory

Digital domain for main processing

(where logic design is applicable)

General Purpose Mobile Computer Example

Based on Pentium M processor
We will learn about the digital building blocks that make up such systems:

S. Thakkar, Second-Generation Intel CentrinoTM Mobile Technology, Intel Technology Journal,

Volume 9, Issue 1, 2005
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Sample Custom Digital IC Design Flow

Architecture
Design &
Verification

Logic
Design &
Verification

Circuit
Design &
Verification

Silicon
Validation

Firmware
Design

Sample Custom Digital IC Design Flow

Architecture
Design &
Verification

Logic
Design &
Verification

Circuit
Design &
Verification

Silicon
Validation

Firmware
Design

Sample System Design Flow using

Programmable Logic (FPGAs)
Architecture
Design &
Verification

Logic
Design &
Verification

System
Validation

Firmware
Design

Sample Custom Digital IC Design Flow

Architecture
Design &
Verification

Logic
Design &
Verification

Circuit
Design &
Verification

Silicon
Validation

Firmware
Design

Sample System Design Flow using

Programmable Logic (FPGAs)
Architecture
Design &
Verification

Logic
Design &
Verification

System
Validation

Firmware
Design

Boolean algebra and theorems form the basis for computing system design.
Engineers working on logic design and verification are experts in this area.
Engineers working in any portion of the design flow need to know about logic
design in order to achieve good quality.
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Design Abstraction Levels

SYSTEM

Tools:
MODULE

+
GATE
CIRCUIT
Vin

Vout

DEVICE
G
S
n+

Schematic
Capture
VHDL / Verilog
(high level
description)
Simulation based
verification
Formal verification

D
n+

Binary modeling of signals

Receiver (Input)

Transmitter (Output)
Transmission Line

10

Binary modeling of signals

Receiver (Input)

Transmitter (Output)
Transmission Line

Vdd
VOH
VIH

Real
Signal:
VOL

VIL

GND

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Binary modeling of signals

Receiver (Input)

Transmitter (Output)
Transmission Line

Vdd
VOH
VIH

Real
Signal:
VOL

VIL

GND
1
Binary
Model:

0
VOH: (Min.) Voltage Output High
VOL: (Max.) Voltage Output Low

VIH: (Min.) Voltage Input High

VIL: (Max.) Voltage Input Low

12

Positive Logic
TRUE (T)

FALSE (F)

HIGH (H)

LOW (L)

Note: If implementation is through negative logic, TRUE will

correspond to binary 0 and FALSE to binary 1.

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