State University of New York at Stony Brook

Department of Electrical and Computer Engineering

ESE 314 Electronics Laboratory B

Fall 2012
Leon Shterengas

Lab 7: Switched capacitor integrator.

1. OBJECTIVES
Understand the operation of a switched capacitor network.
Characterize switched capacitor integrator and compare its operation with that of Miller integrator.
2. INTRODUCTION
2.1. Switched capacitor network.
Switched capacitor techniques allow for the integration on a single silicon chip of both digital and analog
functions. Integrated circuits (especially very or ultra large scale ones) rely on MOS capacitors and field effect
transistors. Whenever analog circuit is required anywhere on a chip it is better be build around these two types
of MOS elements. For filter (passive or active) the critical parameter is product of R and C. In discrete circuit
world this does not sound like a problem at all. However, for integrated circuits it becomes an issue. On a
silicon chip it is very easy to realize switches, small-value capacitors (order of 10 pF or less) and linear
amplifiers. At the same time it is highly undesirable to waste valuable chip area on making resistors and largevalue capacitors (inductors are also not welcome). To get a low-pass filter with corner (- 3dB) frequency of
about 1 kHz one needs to use about 16 M resistor if the maximum attainable capacitor value is 10 pF. This
would consume substantial chip area. On top of that the integrated circuit resistors are not linear. Tolerance for
integrated circuit resistances and capacitors are also far from perfect.
It was realized that resistors can be replaced by combination of (1) capacitor and (2) MOS switches that can
be rapidly turned on and off using clock signal. Figure 1 illustrates this circuit that can be called simulated
resistor. In this circuit the switch is controlled by clock frequency (fclk) that is higher than the frequencies of
V1 and V2 signals.

V1

V2

C
0

Figure 1.
Under this assumption the average current IAVE flowing between V1 and V2 is:
I AVE V1 V2 C fclk

(1).

Hence, rapidly switched MOS capacitor behaves as a resistor when current is averaged over time:
I AVE

V1 V2 ,
R EQ

R EQ

1
C fclk

(2)

The time constant arising from using such a simulated resistance with another MOS capacitance C2 in filter:
1

State University of New York at Stony Brook

Department of Electrical and Computer Engineering

ESE 314 Electronics Laboratory B

Fall 2012
Leon Shterengas

C2 1
.
(3)
R EQ C2

C fclk

The fact that capacitor ratios control the time constants means that these constants now can take advantage of
the superior matching of capacitances fabricated on silicon, as well as their ability to track each other with
temperature. The accuracy of capacitor ratios can be controlled within 0.1 %. Moreover, the change of clock
frequency can be used to tune filters.
2.2. Switched capacitor integrator.
OpAmp integrator is building block for switched capacitor filters. We have learned the operation of regular
Miller integrator in lab 6. Here we will see what happens if the actual resistor is replaces with a simulated one.

Figure 2.
In Figure 2a circuit (Figure 12.35 from 5th Sedra/Smith) the capacitor C1 and two MOS switches controlled by
T
nonoverlaping clock signals (1 and 2) form an equivalent resistor of the value R EQ C , where TC is period
C
of the clock, i.e. TC = 1/fclk. This will result into equivalent integrator frequency:
f int

1 C1

fclk .
2 C2

(4)

The circuit will behave like Miller integrator as long as switched-capacitor can be treated like a resistor. The
principal constrain in using switched-capacitor is that the clock frequency (switching speed) must be much
higher than the critical frequency set by the equivalent Req*C product. Furthermore, on either side of analog
switches, i.e. the MOSFETs, there must be voltage sources, i.e. zero impedance nodes. Finite impedance of the
closed switch (Ron) adversely affects the switched-capacitor circuit performance by delaying capacitor charging
process. Also, stray and parasitic capacitances would call for adjustment/modification of the basic design.
2.3. Two-phase clock and switches for switched-capacitor equivalent resistor.
Operation of Figure 2 circuit will require availability of the two phase clocks. There are numerous circuit
solutions to construct such a clock. We will use simple OpAmp-based waveform generator followed by two
OpAmp-based comparators. Figure 3 below shows the suggested topology. We will use JFET-input wideband
LF356 OpAmp amplifiers and operate clock at 100 kHz frequency. As you can see the waveform generator in
1
, where C = 5 nF
Figure 3 is a simple Schmitt trigger oscillator. The oscillation frequency: fclk
2.2 R3 C
and R3 is adjustable.
2

State University of New York at Stony Brook

Department of Electrical and Computer Engineering

ESE 314 Electronics Laboratory B

Fall 2012
Leon Shterengas

Use 50 k potentiometers for R1, R2 and R3. Firstly, adjust R3 to obtain 100 kHz frequency for V1
waveform. Then adjust R1 and R2 so that 1 and 2 are symmetrical square waves which do not overlap.
During adjustment observe first V1 and then 1 and 2 on oscilloscope screen.
10k

R1
-5V

+5V

V1

OUT

OUT

OUT
+
-

R3
-

10k
5n

-5V
0

+5V
R2

Figure 3.
The switches or better to say pass transistors will be taken from 4066 CMOS quad analog switch. This chip is
using 5 V power supply like LF356 OpAmps. On-state resistance of the switch can be estimated from 4066
datasheet provided.
3. PRELIMINARY LAB
3.1. Estimate the clock frequency required for switched capacitor integrator (Figure 2, C1 = 4 nF, C2 = 0.22 F)
to have the same integrator frequency as for Miller integrator with R = 2.5 k and C = 0.22 F (lab 6: 4.1).
3.2. Estimate the maximum tolerable on-state resistance Ron of the NMOS transistor switches (Figure 2) for C1
= 4 nF and fclk found in previous question. (Ron*C1 should be about 10 times shorter than the clock period).
3.3. Explain operation of the circuit in Figure 3. Select R3 to obtain clock frequency found in question 3.1.
3.4. Run simulation using circuit file lab07.cir. Plot on 4 separate graphs simulated waveforms of the: (1)
clock signals VS1 and VS2; (2) Currents through switches S1 and S2; (3) current through C2 and voltage across
C2; (4) Average current through switched capacitor and compare it with DC current that would flow through
corresponding equivalent resistor. Explain each graph.

State University of New York at Stony Brook

Department of Electrical and Computer Engineering

ESE 314 Electronics Laboratory B

Fall 2012
Leon Shterengas

4. EXPERIMENT.
Assemble Schmitt trigger oscillator on separate board to minimize crosstalk between signal and clock
waveforms (clock feedthrough).
4.1. Assemble Schmitt trigger oscillator (use LF356 OpAmp). Obtain waveforms of the voltages at the output of
OpAmp and across 5 nF capacitor on oscilloscope screen. Vary R3 and observe its effect on frequency of V1
waveform. Explain your observations. Set frequency to the value calculated in 3.1.
4.2. Assemble full circuit from Figure 3 (use LF356 OpAmp for comparators). Obtain both clock signals on
oscilloscope screen. Vary R1 and R2 and observe their effect on clock duty cycles. Explain your observations.
4.3. Obtain nonoverlaping clocks. Initially adjust them to miss overlapping each other by only a very small
amount. Use them in switched-capacitor integrator from Figure 2. Use 741 OpAmp to build this integrator.
Select C1 = 4 nF and C2 = 0.22 F. Apply square wave input (1 Vpp and 1 kHz). Obtain input and output
waveforms on oscilloscope screen. Sketch the waveforms. Compare with data obtained in lab 6: 4.2.
4.4. Change C1 to 10 nF. Apply square wave input (1 Vpp and 1 kHz). Obtain input and output waveforms on
oscilloscope screen. Sketch the waveforms. Repeat for C1 = 30 nF. Compare with 4.3 data. Comment on
observed changes. Can you estimate Ron of switches?
4.5. Adjust the clocks so that they overlap significantly. Apply square wave input (1 Vpp and 1 kHz). Obtain
input and output waveforms on oscilloscope screen. Sketch the waveforms. Comment on observed changes.
4.6. Adjust clocks so they do not overlap and also so that there is significant time period when neither of clocks
is on. Obtain input and output waveforms on oscilloscope screen. Sketch the waveforms. Comment on observed
changes.
4.7. Obtain nonoverlaping clocks like in 4.3 again. Reduce clock frequency from 100 kHz down to 20 kHz.
Apply square wave input (1 Vpp and 1 kHz). Obtain input and output waveforms on oscilloscope screen. Sketch
the waveforms. Repeat for clock frequency equal to 5 kHz. Comment on observed difference from the case
when 100 kHz clock was used.
4. REPORT

The report should include the lab goals, short description of the work, the experimental and simulated data
presented in plots, the data analysis and comparison followed by conclusions. Please follow the steps in the
experimental part and clearly present all the results of measurements. Be creative; try to find something
interesting to comment on.