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ADMN 2014-17
4.1 Introduction
Registers are groups of flip-flops, where each flip-flop is capable of storing one bit of information.
An n-bit register is a group of n flip-flops. The basic function of a register is to hold information in a digital
system and make it available to the logic elements for the computing process. Registers consist of a finite
number of flip-flops. Since each flip-flop is capable of storing either a "0" or a "1", there is a finite number
of 0-1 combinations that can be stored into a register. Each of those combinations is known
as state or content of the register. With flip-flops we can store data bitwise but usually data does not appear
as single bits. Instead it is common to store data words of n bit with typical word lengths of 4, 8, 16, 32 or
64 bit. Thus, several flip-flops are combined to form a register to store whole data words. Registers are
synchronous circuits thus all flip-flops are controlled by a common clock line. As registers are often used
to collect serial data they are also called accumulators.
Shift Register
The Shift Register is another type of sequential logic circuit that can be used for the storage or the
transfer of data in the form of binary numbers. This sequential device loads the data present on its inputs
and then moves or shifts it to its output once every clock cycle, hence the name shift register.
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The data is shifted serially IN and OUT of the register, one bit at a time in either a left or
right direction under clock control.
It has only three connections, the serial input, which determines what enters the left hand flipflop, the serial output, which is taken from the output of the right hand flip-flop and the
sequencing clock signal. The logic circuit diagram below shows a generalized serial-in serial-out
shift register.
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The above figure illustrates entry of the four bits 1010 into the register. After imputing of datas, Four bits
(1010) being serially shifted out of the register and replaced by all zeros.
The parallel data is loaded into the register simultaneously and is shifted out of the register
serially one bit at a time under clock control.
The circuit shown below is a four bit parallel input serial output register.
Output of previous Flip Flop is connected to the input of the next one via a combinational circuit.
The binary input word B0, B1, B2, B3 is applied though the same combinational circuit.
There are two modes in which this circuit can work namely shift mode or load mode.
LOAD MODE
When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active. They will pass B 1, B2, and
B3bits to the corresponding flip-flops. On the low going edge of clock, the binary input B0, B1, B2, B3 will
get loaded into the corresponding flip-flops. Thus parallel loading takes place.
SHIFT MODE
When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become inactive. Hence the parallel
loading of the data becomes impossible. But the AND gate 1, 3 and 5 become active. Therefore the
Dept. of Computer Science And Applications, SJCET, Palai
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shifting of data from left to right bit by bit on application of clock pulses. Thus the parallel in serial out
operation take place.
The parallel data is loaded simultaneously into the register, and transferred together to their
respective outputs by the same clock pulse.
In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the data inputs D0, D1, D2, and
D3 respectively of the four flip-flops. As soon as a negative clock edge is applied, the input
binary bits will be loaded into the flip-flops simultaneously. The loaded bits will appear
simultaneously to the output side. Only clock pulse is essential to load all the bits.
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Here a set of NAND gates are configured as OR gates to select data inputs from the right or left adjacent
bistables, as selected by the LEFT/RIGHT control line.
With Right/Left = 1: Shift right operation
Then the AND gates 1, 3, 5 and 7 are enable whereas the remaining AND gates 2, 4, 6 and 8 will be
disabled.
The data is shifted to right bit by bit on the application of clock pulses. Thus we get the serial right
shift operation.
When the mode control M is connected to 0 then the AND gates 2, 4, 6 and 8 are enabled while 1,
3, 5 and 7 are disabled.
The data is shifted left bit by bit on the application of clock pulses. Thus we get the serial right shift
operation.
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Parallel loading
Lift shifting
Right shifting
The mode control input is connected to logic 1 for parallel loading operation whereas it is connected to 0
for serial shifting. With mode control pin connected to ground, the universal shift register acts as a bidirectional register. For serial left operation, the input is applied to the serial input which goes to AND
gate-1 shown in figure. Whereas for the shift right operation, the serial input is applied to D input.
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4.8 COUNTER
Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known counter.
Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied.
Counters are of two types.
Asynchronous or ripple counters: the first flip-flop is clocked by the external clock pulse, and then
each successive flip-flop is clocked by the Q or Q' output of the previous flip-flop.
Synchronous counters: all memory elements are simultaneously triggered by the same clock.
Synchronous counters are faster than asynchronous counter because in synchronous counter all flip flops
are clocked simultaneously.
For example, a Modulus-12 counter (Mod-12) would count from 0 (0000) to 11 (1011) and would
require four flip-flops (24 = 16 states; 12 are used)
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Once the counter counts to ten (1010), all the flip-flops are being cleared. Notice that only Q1 and Q3 are
used to decode the count of ten. This is called partial decoding, as none of the other states (zero to nine)
have both Q1 and Q3 HIGH at the same time. The sequence of the decade counter is shown in the table
below:
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When the control input UP is at 0 and DOWN is at 1, the inverted outputs of FF0 and FF1 are gated
into the clock inputs of FF1 and FF2 respectively. If the flip-flops are initially reset to 0's, then the counter
will go through the following sequence as input pulses are applied.
Synchronous Counters
In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by
the input pulses. Thus, all the flip-flops change state simultaneously (in parallel). The circuit below is a 3bit synchronous counter. The J and K inputs of FF0 are connected to HIGH. FF1 has its J and K inputs
connected to the output of FF0, and the J and K inputs of FF2 are connected to the output of an AND gate
that is fed by the outputs of FF0 and FF1.
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Cascaded counters
Cascading is a method of achieving higher-modulus counters. For synchronous IC counters, the next
counter is enabled only when the terminal count of the previous stage is reached. Larger counters can be
built by combining smaller counters together .The rollover signal is used to communicate when the upper
counters should roll over .
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Frequency counters
Digital clock
Time measurement
A to D converter
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