Fire sh2

FIRE Emulator for SH2
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TRACE32 Index
TRACE32 Documents ......................................................................................................................
FIRE In-Circuit Emulator ...............................................................................................................
FIRE Target Guides ....................................................................................................................
FIRE Emulator for SH2 ............................................................................................................
Warning .................................................................................................................................
Quick Start ............................................................................................................................
Troubleshooting ...................................................................................................................
10
Hang-Up
10
Dualport Errors
10
FAQ ........................................................................................................................................
11
Configuration ........................................................................................................................
13
Basics ....................................................................................................................................
14
Emulation Method
14
Emulation Modes
14
Dualport Access
15
General SYStem Settings and Restrictions .......................................................................

General Restrictions
18
18
SYStem.CPU
Processor type
18
SYStem.CPU
Operation mode
19
SYStem.Option V33
SYStem.Option IMASKASM
3.3 V power fail detection
19
Mask interrupts during assembler step
20
Mask interrupts during HLL step
20
SYStem.Option IMASKHLL
Continue with CPU specific Special Settings and Restrictions
20
Special Settings SH701x/704x and Restrictions ...............................................................

Restrictions for SH701x/704x
21
21
SYStem.Option PLL
Onchip PLL
21
SYStem.Option MTU
Control of multifunction timer pulse unit
21
SYStem.Option CMT
Control of compare match timer unit
22
Special Settings SH7050/51 and Restrictions ...................................................................
23
Restrictions for SH7050/51
23
SYStem.Option PLL
Onchip PLL
23
SYStem.Option ATU
Control of advanced timer unit
23
1989-2016 Lauterbach GmbH
Special Settings SH7055 and Restrictions ........................................................................

Restrictions for SH7055
24
24
SYStem.Option ATU
24
SYStem.Option CMT
25
On-chip Trigger Unit ............................................................................................................
26
General Description
26
Address Selectors
26
Sequential Mode
27
Examples
27
Specific TrOnchip Commands ............................................................................................

TrOnchip.view
View window
TrOnchip.RESet
29
29
Reset settings
29
TrOnchip.CONVert
Convert breakpoints
29
TrOnchip.A.Watch
Enable hardware output
30
TrOnchip.A.Break
Stop emulation
30
TrOnchip.A.CYcle
Select bus cycle type
31
TrOnchip.A.Type
Select bus master type
32
TrOnchip.A.Size
Select operand size
32
TrOnchip.A.Value
Set data selector value
33
TrOnchip.SEQ
Select sequential mode
33
TrOnchip.RPE
Enable reset pointer
34
Set repeat counter value
34
Exception Control ................................................................................................................
35
TrOnchip.A.Count
Reset
35
Manual Reset (SH701x/704x)
36
Hardware Standby (SH705x)
37
NMI
38
Exceptions during Break Mode
39
Breakpoints ...........................................................................................................................
Breakpoint Realization Modes
40
40
Memory Classes ...................................................................................................................

Overview
42
42
State Analyzer .......................................................................................................................
43
Keywords for the Display
43
Keywords for the Emulator Trigger Unit
44
General SH Keywords for the Emulator Trigger Unit
44
SH701x/704x Keywords for the Emulator Trigger Unit
44
SH705x Keywords for the Emulator Trigger Unit
44
Port Analyzer ........................................................................................................................
45
Port Signals SH7011
45
Port Signals SH7014
46
Port Signals SH7016/SH7017
47
Port Signals SH7040/SH7042/SH7044
49
50
52
Technical Data ......................................................................................................................
55
Mechanical Dimensions
55
Adaptions
61
Adapters
63
Operation Voltage
69
Operation Frequency
70
Support ..................................................................................................................................
71
Probes
71
Available Tools
72
Compiler Support
72
Realtime Operation Systems
73
3rd Party Tool Integrations
73
Products ................................................................................................................................
75
Product Information
75
Order Information
77

Version 24-May-2016
F::d.l
ddr/line
code
P:00010832 6303
545
P:00010834
P:00010836
546
P:00010838
P:0001083A
547
P:0001083C
P:0001083E
P:00010840
label
333C
7303
add
add
6203
323C
mov
add
3247
8D06
6743
cmp/gt
bt/s
mov
549
P:00010842 6123
F::r
T
_
S
_
I
F
Q
_
M
_
Tsk
R0
R1
R2
R3
R4
R5
R6
R7
GBR
VBR
MACH
MACL
mnemonic
mov
{
0
1
1
0
12
4006C0
0
12
0
0
1800000
2BCE
mov
R8
R9
R10
R11
R12
R13
R14
R15
PC
PR
SR
0
0
0
0
0
0
407FEC
407FEC
10834
107A2
0F0
r0,r3
comment
; return,primz
primz = i + i + 3;
r3,r3
; primz,primz
#3,r3
; #3,primz
k = i + primz;
r0,r2
; return,k
r3,r2
; primz,k
while ( k <= SIZE )
r4,r2
; r4,k
1084E
r4,r7
{
flags[ k ] = FALSE;
r2,r1
; k,r1
SP >00407FF4
+04 0001080C
+08 00010016
+0C 00000000
+10 00000000
+14 DEADDEAD
+18 00000000
+1C 00000000
+20 00000000
+24 00000000
+28 00000000
+2C 00000000
+30 00000000
F::v.w
flags = (1, 1, 1, 1, 1,
ast = (word = 0x0,
count = 12346,
left = 0x400710,
right = 0x0,
field1 = 1,
field2 = 2)
For general informations about the In-Circuit Debugger refer to the FIRE Users Guide (fire_user.pdf). All
general commands are described in IDE Reference Guide (ide_ref.pdf) and General Reference
Guide.
Warning
NOTE:
Do not connect or remove probe from target while target power is ON.
Power up:
Switch on emulator first, then target
Power down: Switch off target first, then emulator
Warning
Quick Start
Before debugging can be started, the emulator must be configured by software:
Ready to run setup files for most standard compilers can be found on the software CD in the directory ../
Demo/Sh7000/Compiler. All setup files are designed to run the emulator stand alone without target
hardware.
The following description should make the initial setup (to run the emulator together with the target
hardware) easier. It describes a typical setup with frequently used settings. It is recommended to use the
programming language PRACTICE to create a batch file, which includes all necessary setup commands.
PRACTICE files (*.cmm) can be created with the PRACTICE editor pedit (Command: PEDIT <file name>)
or with any other text editor.
A basic setup file includes the following parts:
1.
Set cpu-type and -mode
2.
Set system options
3.
Select dualport mode (optional)
4.
Set mapper (optional)
5.
Select frequency (optional)
6.
Activate the emulator
7.
Load application file (optional)
8.
Set breakpoints (optional)
9.
Start application
10.
Stop application (optional)
Quick Start
Here a typical example, how to setup the system:

1.
Set cpu-type and -mode options

The command sys.cpu is used to select one derivative within a cpu-family and to set its operation
mode.
system.down
system.cpu SH7044
system.cpu EXT16
2.
; switch the system down

; select derivative SH7044
; set the operation mode EXT16
Set system options

The system window controls the CPU specific setup. Please check this window very carefully and set
the appropriate options. Use the ? button in the main tool bar and click to the option check box
(Command: HELP.PICK) to get online help in a pop up window.
system.option v33 on
system.option pll 4
3.
; on: if a 3.3 V target board is used

; on-chip pll works with multiplication
; factor 4
Select dualport mode (optional)

Dualport allows access to emulation RAM, while emulation is running. This is necessary to display
variables, set breakpoints or display the flag listings while the emulation is running. System.Access
selects how dualport access is done.
system.access request
4.
; request: a dedicated bus request

; signal of the bondout cpu is used
; denied: dualport is disabled
Set mapper (optional)

The mapper controls the memory access of the CPU. This means the use of internal or external
memory, the protection of a memory bank etc. Address ranges must be defined by using memory
classes.
map.reset
map.ram c:0x0--0x07ffff
map.ram c:0x400000--0x43ffff
map.intern c:0x0--0x07ffff
map.extern c:0x400000-0x43ffff
;
;
;
;
;
;
;
reset mapper (all external)

emulation RAM: 512KB (e.g. for
program)
emulation RAM: 256KB (e.g. for
data)
map program memory internal
map data memory external
Quick Start
5.
Select frequency (optional)

The CPU can be clocked by an internal (emulator) or external (target) clock source. If the internal
clock is used, the clock is provides by the VCO of the emulator. The setting of the internal clock is
done by the vco command.
The current CPU frequency can be displayed in the counter window (Command: Count).
vco.clock 5.
6.
; input clock to the EXTAL pin of the

; cpu is set to 5 MHz (only necessary if
; internal clock is used)
Activate the emulator

When the emulator is activated a debug-monitor program is loaded into a hidden emulator memory.
Afterwards, a bondout reset-signal is inactivated and the monitor program starts. This program allows
access to user memory (data.dump, data.list) and cpu-registers, and gives control to start and stop
the emulation.
system.mode emulext
7.
; system works with external target

clock
Load application file (optional)

Application can be loaded by various file formats. COFF format is often used to load code and symbol
information. For information about the load command for your compiler see Compiler.
data.load.coff gnush7.x
8.
; load application file
Set breakpoints (optional)

There are several ways to set breakpoints (Command: Break.Set). Breakpoints can be displayed
using the Break.List command.
breakpoint.set main /program
breakpoint.set flags /write
9.
;
;
;
;
set program break on function

main
set write break on variable
flags
Start application
Application can be started with giving a break address. For example go main starts the application
and stops at symbol main.
go
; run application
Quick Start
10.
Stop application (optional)

Application can be breaked manually by using th BREAK command.
break
;break application manually
It is recommended to check the following chapters for all questions regarding the correct setup:
Configuration
General SYStem Settings and Restrictions
Special Settings SH701x/704x and Restrictions
Special Settings SH7050/51 and Restrictions
Special Settings SH7055 and Restrictions
Troubleshooting
Quick Start
Troubleshooting
Hang-Up
If you are not able to stop the emulation, there could be some typical reasons:
Active target-reset
The BREAK command wont stop the emulation if the target-reset

is active and the reset-line is enabled in the exception control.
Hardware Standby Mode

of SH705x
The hardware standby mode can only be cancelled by a new

activation (sys.up) of the emulator.
Dualport Errors
Dual-Port Busy
Request Mode: The bus is not released by the cpu within the
selected time with the sys.TimeReq option.
AUD Mode: This error occurs, if you try to dump a memory area
which cant be seen by the cpu (for example, any external memory
areas in single-chip mode).
10
Troubleshooting
FAQ
Debugging via
VPN
The debugger is accessed via Internet/VPN and the performance is very

slow. What can be done to improve debug performance?
The main cause for bad debug performance via Internet or VPN are low data
throughput and high latency. The ways to improve performance by the debugger
are limited:
in practice scripts, use "SCREEN.OFF" at the beginning of the script and
"SCREEN.ON" at the end. "SCREEN.OFF" will turn off screen updates.
Please note that if your program stops (e.g. on error) without executing
"SCREEN.OFF", some windows will not be updated.
"SYStem.POLLING SLOW" will set a lower frequency for target state
checks (e.g. power, reset, jtag state). It will take longer for the debugger to
recognize that the core stopped on a breakpoint.
"SETUP.URATE 1.s" will set the default update frequency of Data.List/
Data.dump/Variable windows to 1 second (the slowest possible setting).
prevent unneeded memory accesses using "MAP.UPDATEONCE
[address-range]" for RAM and "MAP.CONST [address--range]" for ROM/
FLASH. Address ranged with "MAP.UPDATEONCE" will read the specified
address range only once after the core stopped at a breakpoint or manual
break. "MAP.CONST" will read the specified address range only once per
SYStem.Mode command (e.g. SYStem.Up).
SH-2
Dualport
Access to Onchip RAM
SH-2
Dump of
External
Memory in
Mode ROM
I can not see the CPUs internal RAM via dualport!

There is no dualport access to the on-chip RAM of the cpu in request mode,
because this RAM is also physically internal at the bondout CPU. You can use
the AUD mode with SH7055 to access the on-chip RAM.
Contents of external memory can not be seen or changed in a data
window in the CPU mode ROM!
The emulator uses the user data-bus of the bodout cpu for the access to
external memorys. The initial value after a reset of the Pin-Function-Controller in
the cpu mode ROM is, that the data-bus pins are used as port-pins. So, the PinFunction-Controller must be changed to use this pins for the data-bus.
11
FAQ
SH-2
Illegal-SlotInstruction
Exception
An Illegal-Slot-Instruction Exception occurs at a line with a correct

opcode!
A Program-, Hll- or Spot-Breakpoint is set on this instruction and causes the
exception. Set the breakpoint on the branch instruction before.
12
FAQ
Configuration
There is no special hardware configuration necessary for the SH2. The configuration of the used derivative
and cpu-mode is done via the SYSTEM commands by software.
13
Configuration
Basics
Emulation Method
The FIRE Emulator uses a bondout versions of the SH2 CPUs.
NOTE: The bondout chip replaces the target cpu, i.e. the target cpu must be removed during emulation!
Emulation Modes
F::sys
system
Down
Up
RESet
Mode
RESet
AloneInt
AloneExt
EmulInt
EmulExt
Access
Request
Denied
TimeReq
1.000ms
CPU
SH7040
Option
V33
IMASKASM
IMASKHLL
PLL
1
2
4
Option
MTU0
MTU1
MTU2
MTU3
MTU4
CMT0
CMT1
CPU
EXT8
EXT16
EXT32
ROM
SINGLE
The emulator can operate in 5 modes. The modes are selected by the SYStem.Mode command.
Format:
SYStem.Mode <mode>
<mode>:
Reset
AloneInternal
AloneExternal
EmulInternal
EmulExternal
14
Basics
Reset
CPU is in reset.
Alone Internal
CPU is running with internal clock. Bus strobe signals (RD, WR, CS, RAS, CAS)
are disabled. This mode is used for 'standalone' operation.
Alone External
CPU is running with external clock. Bus strobe signals are disabled.
Emulation
Internal
CPU is running with internal clock. Bus strobe signals are enabled.
Emulation
External
CPU is running with external clock. Bus strobe signals are enabled.
In active mode, the power of the target is sensed and by switching down the target the emulator changes to
RESET mode. The probe is not supplied by the target power. When running without target, the target
voltage is simulated by an internal pull-up resistor.
Dualport Access
Format:
SYStem.MemAccess <option>
<option>:
Request
AUD
Denied
Request
The CPU bus access is stopped by a dedicated bondout bus-request signal for
performing a dualport access.
AUD
The AUD interface of the chip is used in monitor -mode for the dual-port
accesses. In this mode, you can even access target memories and onchip
peripherals while the application program is running.
If request or denied is selected, then the AUD interface can be used by the
target hardware.
Denied
Dualport access is not possible while the emulation is running.
Dualport allows access to emulation RAM and onchip ROM/FLASH, while emulation is running. This is
necessary to display variables, set breakpoints or display flag listings while the emulation is running.
Dualport access is only possible on the emulators internal RAM and not on target RAM.
NOTE:There is no dualport access to the onchip RAM of the cpu in request-mode, because this RAM is
physically internal at the bondout cpu.
15
Basics
Format:
SYStem.CpuAccess <option>
<option>:
Enable
Denied
Enable
If a dualport read/write access is requested to a non-mapped memory, a spot

point (emulation break and go) is used to access the memory.
Denied
Dualport access via spot point is not possible.
The emulator uses a two stage strategy to realize the best possible dualport access method:
If MemAccess is set to Request, the emulation controller tries a bus arbitration access as dualport cycle.
This is possible if memory is mapped to internal and on read cycles to shadow memory. Shadow memory
means, that memory is mapped in the emulator (map.ram), but the area is mapped external (map.extern).
On access to external mapped memory and write access to shadow memory the dualport is executed as a
spot point if CpuAccess is enabled. Dualport on access to external mapped memory and write access to
shadow memory is disabled if CpuAccess is disabled.
If MemAccess is set to AUD, the emulation controller uses the AUD interface of the CPU to realize the
dualport cycle. The advantage of this method is that all memories, independent on the mapping, can be
used. CpuAccess switch is ignored if MemAccess is set to AUD.
If MemAccess is set to Denied and CpuAccess is enabled, the emulation controller uses a spot point to
realize the dualport cycle. If MemAccess is set to Denied and CpuAccess is disabled, dualport access is not
possible.
The following table shows how the dualport is realized depending on the used system setting:
Mem
Access
Cpu
Access
Read
Map
Int.
Write
Map
Int.
Read
Shado
w
Write
Shado
w
Read
Map
Ext.
Write
Map
Ext.
Request
Enable
request
request
request
spot
spot
spot
Request
Denied
request
request
request
AUD
Enable
aud
aud
aud
aud
aud
aud
AUD
Denied
aud
aud
aud
aud
aud
aud
Denied
Enable
spot
spot
spot
spot
spot
spot
Denied
Denied
16
Basics
request: The bus arbitration interface of the CPU is used for dualport access. Application performance is
only slightly influenced.
aud: The AUD interface of the CPU is used for dualport access. Application performance is more
influenced than with request mode.
spot: The emulation is breaked, memory access is done via CPU, emulation is continued. Application
performance is most influenced with this method.
17
Basics
General Restrictions
Onchip RAM
The CPUs onchip RAM is physically internal at the bondout chip. This
means that there is no dualport access available to this RAM. Except
for SH7055 there is no Break- and Flag-RAM parallel to the onchip
RAM, so that there is no flag information available for it. The address
selectors for the emulator trigger-unit and the read and write
breakpoints are realized with the four channel onchip trigger-unit of the
bondout chip.
Interrupt requests
during the emulation
is stopped
Exceptions and interrupts are not handled during the emulation is

stopped. Some of them are stored and executed after starting the
emulation (see chapter Exception Control). If you will have problems
with either your target hardware or you application program because of
the blocked interrupts, then you have to use a foreground monitor.
Pending interrupts
during single-step
When executing an assembler step and external or internal interrupts

are pending, the emulator will not step into the interrupt handler and
stops at the next instruction. The execution of the interrupt program can
be avoided either by preventing the interrupt, e.g. stop the timer while
the emulation is stopped (see timer control) or by masking the interrupt
in the CPU (command SETUP.IMASKASM). For HLL steps the
problem can be solved in the same way (command
SETUP.IMASKHLL).
SYStem.CPU
Processor type
Format:
SYStem.CPU <type>
<type>:
SH7011|SH7016|SH7017
SH7014
SH7040|SH7042|SH7044
SH7041|SH7043|SH7045
SH7050
SH7051
SH7055
This selects the exact derivative within a CPU family.
18
SYStem.CPU
Operation mode
Format:
SYStem.CPU <mode>
<mode>:
EXT8
EXT16
EXT32
ROM
SINGLE
This option specifies operation mode of the cpu, which is normally defined with the MD0 and MD1 pins of
the cpu. But, the values of this pins in the target are not responsible for the operation mode, so that the pin
levels can differ from the emulator setting.
EXT8
CS0 is an external memory area with 8-bit bus width. The onchip ROM is
disabled.
EXT16
disabled.
EXT32
disabled.
ROM
The onchip ROM is enabled. External memory is accessible.
SINGLE
Single-Chip mode. No external memory accessible.
SYStem.Option V33
Format:
3.3 V power fail detection
SYStem.Option V33 [ON | OFF]
The emulator has a detection logic to detect a target power fail. This option must be set to on, if a 3.3 V
target is used.
19
SYStem.Option IMASKASM
Format:
Mask interrupts during assembler step
SYStem.Option IMASKASM [ON | OFF]
If enabled, the interrupt mask bits of the cpu will be set during assembler single-step operations. The
interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are
restored to the value before the step.
SYStem.Option IMASKHLL
Format:
Mask interrupts during HLL step
SYStem.Option IMASKHLL [ON | OFF]
If enabled, the interrupt mask bits of the cpu will be set during HLL single-step operations. The interrupt
routine is not executed during single-step operations. After single step the interrupt mask bits are restored to
the value before the step.
NOTE: By changing the status register through target software, this option can affect the flow of the
target program. Accesses to the interrupt-mask bits will see the wrong values.
Continue with CPU specific Special Settings and Restrictions

The following Special Settings and Restrictions are different for SH704x and SH705x:
20
Restrictions for SH701x/704x

Dual-purpose IO-Pins
The dual-purpose IO-Pins BREQ, IRQ0..7 and WAIT dont have a

pull-up resistor in the emulator.
This pins work as port pins after reset. If you change the pinfunction-controller so that this pins have bus control or interrupt
function, then the emulator will malfunction in stand-alone mode
because of the floating inputs.
SH7011
The Input-Pins IRQ0..7 and WAIT have 22K pull-up resistors in the
emulator to avoid that external interrupts are triggered or external
bus-cycles wont be terminated in stand-alone mode.
SYStem.Option PLL
Format:
Onchip PLL
SYStem.Option PLL 1 | 2 | 4
This option specifies the multiplication factor of the onchip PLL, which is normally defined with the MD2 and
MD3 pins of the cpu. But, the values of this pins in the target are not responsible for the multiplication factor,
so that the pin levels can differ from the emulator setting.
SYStem.Option MTU
Control of multifunction timer pulse unit
Format:
SYStem.Option MTU<channel> [ON | OFF]
<channel>:
0|1|2|3|4
This option controls the timers of the CPUs Multifunction Timer Pulse Unit for each channel independently.
Normally, the timers continue running if the emulation is stopped. If the option is now switched on, the
corresponding timer will stop after entering the break mode and will start running again before the emulation
is started. This is done by manipulating the timer start register by the emulators background monitor
program. Since there have to be done some important actions in the monitor before the timer control, the
starting and stopping cant be synchronous to the emulators go and break.
21
SYStem.Option CMT
Format:
SYStem.Option CMT<channel> [ON | OFF]
<channel>:
0|1
This option controls the timers of the CPUs Compare Match Timer Unit for each channel independently.
22
Restrictions for SH7050/51

The dual-purpose IO-Pins BREQ and IRQ0..7 dont have a pull-up

resistor in the emulator.
The dual-purpose IO-Pin WAIT can function as an external waitstate input in some cpu-modes immediately after reset. Therefore
this pin has a 22K pull-up resistor in the emulator to avoid that
external bus-cycles wont be terminated.
SYStem.Option PLL
Format:
Onchip PLL
SYStem.Option PLL 1 | 2 | 4
This option specifies the multiplication factor of the onchip PLL, which is normally defined with the MD2 and
MD3 pins of the cpu. But, the values of this pins in the target are not responsible for the multiplication factor,
so that the pin levels can differ from the emulator setting.
SYStem.Option ATU
Format:
SYStem.Option ATU<channel> [ON | OFF]
<channel>:
0|1|2|3|4|5|6|7|8|9
This option controls the timers of the CPUs Advanced Timer Unit for each channel independently.
23
Restrictions for SH7055

The dual-purpose IO-Pins BREQ and IRQ0..7 dont have a pull-up

resistor in the emulator.
The dual-purpose IO-Pin WAIT can function as an external waitstate input in some cpu-modes immediately after reset. Therefore
this pin has a 22K pull-up resistor in the emulator to avoid that
external bus-cycles wont be terminated.
SYStem.Option ATU
Format:
SYStem.Option ATU<channel> [ON | OFF]
<channel>:
0 | 1A | 1B | 2A | 2B | 3 | 4 | 5 | 6A | 6B | 6C | 6D | 7A | 7B | 7C | 7D | 10 | 11
This option controls the timers of the CPUs Advanced Timer Unit for each channel independently.
24
SYStem.Option CMT
Format:
SYStem.Option CMT<channel> [ON | OFF]
<channel>:
0|1
This option controls the timers of the CPUs Compare Match Timer Unit for each channel independently.
25
On-chip Trigger Unit
General Description
The onchip trigger-unit consists of four channels (A to D), which can work independently or can be
combined.The address and data values, and the bus cycle type, the bus master type and the operand
size can be set for each channel. There are two output events: A hardware signal can be generated and
the emulation can be stopped if a condition has matched. Furthermore is a sequential mode available.
Address Selectors
The address values for the trigger channels are set with the asynchronous breakpoints. There is a fixed
connection between the breakpoint types and the channels:
Alpha corresponds to channel A
Beta corresponds to channel B
Charly corresponds to channel C
Delta corresponds to channel D
Echo corresponds to the reset pointer
Example: Break.Set 400000 /Alpha /Onchip sets the address of channel A to 0x400000. You mustnt set
the option Onchip, if you have selected the Watch or Break option for the corresponing channel. If you
then open a Break.List window, then you can see the breakpoint marked as on-chip.
On-chip Breakpoints can also be set as a range. Then there are two channels used for one range: Channels
A or C are for the start address and channels B or D for the end address, e.g. Break.Set 1000--2000 /Charly
/Onchip sets an address range from 0x1000 to 0x2000 with the channels A and B. The output events must
be set in channel A for an AB-range and in channel C for a CD-range.
26
Sequential Mode
The onchip trigger-unit can also be used in a sequential mode. There are three possibilities:
Compare channels A and B sequentially (order: B > A)
Compare channels A to C sequentially (order: C > B > A)
Compare channels A to D sequentially (order: D > C > B > A)
If the conditions have matched sequentially, then the output event occurs, but this event must be set in all
participating channels (e.g. set A.Break, B.Break and C.Break if you want to stop the emulation after a C > B
> A sequence).
A reset pointer address can be defined with an Echo breakpoint to reset a sequence to the start event.
The reset is initialized when the pointer address is passed.
There is a repeat counter available. This value defines the number of times the sequence must be passed,
before the output event becomes active. This counter works also with channel A when it is used
independently.
Examples
Assume that there is a byte variable called 'flag', and you want to stop the emulation if the value 0x59 is
written to the variable.
TrOnchip.A.Break On
; The emulation stops on a compare match

; event
Break.Set flag /Alpha
; Set an alpha breakpoint to the address

; of the variable flag
TrOnchip.A Value 0xxxxxx59
; Specify data pattern
TrOnchip.A Cycle Write
; Specify that you want to trigger only on

; a write access
TrOnchip.A Size Byte

; byte access
27
Assume that there is a byte variable called 'flag' in the onchip RAM, and you want to mark only read cycles to
this variable.
TrOnchip.A.Watch On
;
;
;
;
The onchip trigger-unit generates a

signal on a compare match event. This
signal is fed into the emulator trigger
unit
Break.Set flag /Alpha
; Set an alpha breakpoint to the address

; of the variable flag
TrOnchip.A Cycle Read

; a read access
TrOnchip.A Size Byte

; byte access
mark.a if bta
s.e
;
;
;
;
;
addr ab flg /o /r /data.b 1

addr bb func /o /p
; Another example of using the onchip

; breakpoints with the advanced breakpoint
; options (data and access control)
This is a trigger program for the

emulator trigger-unit. It means, that
every cpu access is sampled and all
cycle matches of onchip trigger unit
channel A are marked in the listing.
start:
goto level1 if ab
level1:
s.e
goto start if bb
NOTE: Analyzer trigger signals (BTA, BTB, BTC, BTD) are delayed one or two bus cycles. This means in the
previous example, that the mark in the analyzer.list will be placed one or two bus cycles after the onchip
trigger-unit match. Therefore analyzer programming files should not use sample.enable if bta.
28
Specific TrOnchip Commands
TrOnchip.view
Format:
View window
TrOnchip.view
Opens a control panel to configure the on-chip breakpopint registers.
TrOnchip.RESet
Format:
Reset settings
TrOnchip.RESet
Resets the trigger system to the default state.
TrOnchip.CONVert
Format:
Convert breakpoints
TrOnchip.CONVert [ON | OFF]
The hardware breakpoints of the SH can only cover specific ranges. When enabled (default) the on-chip
breakpopints are automatically converted from a range to a single address if required. If the switch is off, the
system will only accept breakpoints which exactly fit to the on-chip breakpopint hardware.
29
TrOnchip.A.Watch
Format:
Enable hardware output
TrOnchip.A.Watch [ON | OFF]

TrOnchip.B.Watch [ON | OFF]
TrOnchip.C.Watch [ON | OFF]
TrOnchip.D.Watch [ON | OFF]
Activates a hardware output signal, if a condition has matched for the corresponding channel. It can be used
to program the emulator trigger unit with special keywords. Furthermore, a condition match can be seen in
the analyzer.list /all window under the corresponding keywords.
NOTE:
If the Watch option is on, then an asynchronous hardware breakpoint is automatically set as onchip.
The hardware output signal becomes active one or two bus cycles after the trigger condition has
matched, so you wont see the requested bus cycle at a selective trace. But if you use the
analyzer option PreTrace, then you can find the requested bus cycle in every traced block.
TrOnchip.A.Break
Format:
Stop emulation
TrOnchip.A.Break [ON | OFF]

TrOnchip.B.Break [ON | OFF]
TrOnchip.C.Break [ON | OFF]
TrOnchip.D.Break [ON | OFF]
Stops the emulation, if a condition has matched for the corresponding channel.
30
TrOnchip.A.CYcle
Select bus cycle type
Format:
TrOnchip.A.CYcle <cycle>
TrOnchip.B.CYcle <cycle>
TrOnchip.C.CYcle <cycle>
TrOnchip.D.CYcle <cycle>
<cycle>:
ANY
Read
Write
Access
Fetch
Defines the bus cycle type.

ANY
Trigger on any bus cycle
Read
Trigger on read cycles
Write
Trigger on write cycles
Access
Trigger on data access cycles
Fetch
Trigger on fetch cycles
31
TrOnchip.A.Type
Select bus master type
Format:
TrOnchip.A.Type <type>
TrOnchip.B.Type <type>
TrOnchip.C.Type <type>
TrOnchip.D.Type <type>
<type>:
ANY
CPU
DMA
Defines the bus master type.

ANY
Trigger on any bus master cycle
CPU
Trigger on CPU cycles
DMA
Trigger on DMA cycles
TrOnchip.A.Size
Select operand size
Format:
TrOnchip.A.Size <size>
TrOnchip.B.Size <size>
TrOnchip.C.Size <size>
TrOnchip.D.Size <size>
<size>:
ANY
Byte
Word
Long
Defines the operand size.

ANY
Trigger on any operand size
Byte
Trigger on byte accesses
Word
Trigger on word accesses
Long
Trigger on long accesses
32
TrOnchip.A.Value
Format:
Set data selector value
TrOnchip.A.Value <hexmask> | <bitmask>

TrOnchip.B.Value <hexmask> | <bitmask>
TrOnchip.C.Value <hexmask> | <bitmask>
TrOnchip.D.Value <hexmask> | <bitmask>
Defines the four data selectors as hex or binary mask (x means don't care).
NOTE: If you want to trigger on a certain byte access, the upper 24 bits must be set as dont care (e.g.
0xxxxxx55). If you want to trigger on a certain word access, the upper 16 bits must be set as dont care
(e.g. 0xxxxAA55). The placement of the data within the word depends on the bus width of the access. An
easier way to use data values is to supply the data and access width with the Break.Set command.
TrOnchip.SEQ
Select sequential mode
Format:
TrOnchip.SEQ <mode>
<mode>:
OFF
BA
CBA
DCBA
Defines a trigger sequence.

OFF
Trigger on channels A-D independently
BA
Trigger sequentially (B, then A)
CBA
Trigger sequentially (C, then B, then A)
DCBA
Trigger sequentially (D, then C, then B, then A)
33
TrOnchip.RPE
Format:
Enable reset pointer
TrOnchip.RPE [ON | OFF]
Sets a reset pointer for a sequential triggering. The Echo Breakpoint is used to set the address of the reset
pointer.
NOTE: If this option is on, the an Echo breakpoint is automatically set as the onchip reset pointer.
TrOnchip.A.Count
Format:
Set repeat counter value
TrOnchip.A.Count <value>
Sets a compare match counter for channel A or for a trigger sequence. This means, that the trigger result
becomes active, when the condition has matched for <value> times, e.g. the application stops after
repeating C > B > A for five times.
The maximum <value> is 65536 (216).
34
Exception Control
F::x
exception
OFF
ON
RESet
Delay
OFF
Activate
OFF
RESET
MRESET
NMI
Enable
OFF
ON
RESET
MRESET
NMI
BRQ
Pulse
OFF
RESET
MRESET
NMI
Pulse
Single
Width
1.000us
PERiod
OFF
ON
0.000
NMIPOL
+
The exception control system depends on the used cpu family (SH701x/704x or SH705x). The window
shown here is for the SH701x/704x.
Reset
Vcc
X.Enable
&
Run
22K
RESET
(Target)
RESET
(CPU)
22R
X.Activate
or
X.Pulse
Format:
eXception.Enable RESET [ON | OFF]
Enable or disable external RESET line.
Format:
eXception.Activate RESET [ON | OFF]
Set RESET line active or inactive.
35
Exception Control
Manual Reset (SH701x/704x)

Vcc
22K
X.Enable
MRESET
(Target)
MRESET
(CPU)
22R
X.Activate
or
X.Pulse
Format:
eXception.Enable MRESET [ON | OFF]
Enable or disable external MRESET line.

NOTE: If this pin is used as a port (PE13), then the exception mustnt be disabled.
Format:
eXception.Activate MRESET [ON | OFF]
Set MRESET line active or inactive.

NOTE:If this pin is used as an output port, then the exception mustnt be stimulated with X.Activate or
X.Pulse.
36
Exception Control
Hardware Standby (SH705x)

Vcc
22K
X.Enable
HSTBY
(Target)
HSTBY
(CPU)
22R
X.Activate
or
X.Pulse
Format:
eXception.Enable HSTBY [ON | OFF]
Enable or disable external HSTBY line.
Format:
eXception.Activate HSTBY [ON | OFF]
Set HSTBY line active or inactive.
37
Exception Control
NMI
Vcc
22K
X.Enable
X.NMIPOL
NMI
(Target)
NMI
(CPU)
22R
X.Activate
or
X.Pulse
10K
GND
Format:
eXception.Enable NMI [ON | OFF]
Enable or disable external NMI line.
Format:
eXception.Activate NMI [ON | OFF]
Set NMI line active or inactive.
Format:
eXception.NMIPOL [+ | -]
Selects the NMI edge. Set it corresponding to the bit NMIE in the Interrupt Control Register ICR of the CPU.
Selects the falling edge and the 22K pull-up resistor is active (see drawing above).
+
Selects the rising edge and the 10K pull-down resistor is active (see drawing above).
38
Exception Control
Exceptions during Break Mode

During break mode (application program not running), the hardware-caused exceptions are controlled by the
bondout CPU.
Manual Reset
If a manual reset occurs, then it is not stored in the CPU. So, exception processing will not occur if the /
MRES pin is not asserted until the emulation is started.
NMI
If a NMI occurs, then it is stored in the CPU. So, exception processing will occur after the first instruction of
the started emulation.
External level sensitive interrupts
If a level sensitive interrupt occurs, then it is not stored in the CPU. So, interrupt processing will not occur if
the /IRQ pin is not asserted until the emulation is started.
External edge sensitive interrupts
If an edge sensitive interrupt occurs, then it is stored in the CPU. So, interrupt processing will occur after the
first instruction of the started emulation.
Internal interrupts
If an internal interrupt occurs, then it is stored in the CPU. So, interrupt processing will occur after the first
instruction of the started emulation.
39
Exception Control
Breakpoints
For a basic description of the breakpoint system please refer to FIRE Users Guide.
Breakpoint Realization Modes

This chapter describes the different realization modes and shows their availability for the logical breakpoints
types.
Software
Breakpoints
Synchronous Breakpoints:
The user application code is patched with a special break-instruction of the
bondout CPU (opcode 0x0) before jumping into the user program. After
executing this instruction, the CPU stops the user program and jumps into the
emulator debug monitor.
Asynchronous Breakpoints:
These breakpoints are used as address selectors for the trigger unit (see FIRE
Users Guide).
Hardware
Breakpoints
The user application is stopped before the instruction is executed. For this, the
bondout break opcode is switched to the CPU data-bus instead of the user
application opcode via hardware. This type of breakpoint is useful if you would
like to set a breakpoint in a target memory where no code can be patched (e.g.
EPROM or Flash).
NOTE: This breakpoint type doesnt work in the onchip ROM and RAM area.
There are only synchronous software breakpoints available.
Asynchronous Breakpoints: See FIRE Users Guide).
Onchip
Breakpoints
The bondout CPU has an onchip trigger-unit with four independent channels.
They can be used if you would like to set a breakpoint in a target memory where
no code can be patched (e.g. EPROM or Flash).
Asynchronous Breakpoints:
The information, that a breakpoint has occurred is switched from the bondout
break controller to the trigger unit, so that the trigger unit for example can start
the analyzer.
NOTE: Since there is no breakpoint RAM in parallel to the CPUs onchip RAM
(except SH7055), the onchip trigger-unit is always used for asynchronous
breakpoints to the on-chip RAM.
40
Breakpoints
The following table shows realization of the logical breakpoint types in auto-mode.
Breakpoint
Type
Realization in Auto Mode
Program
Software
HLL
Software
Onchip (If the address is mapped as ReadOnly)
Stepmode (If HLL-Line is too complex)
Spot
Software
Onchip (If the address is mapped as ReadOnly)
Read, Write
Onchip
Alpha, Beta,
Charly, Delta,
Echo
Hardware
Onchip (CPUs onchip RAM area except SH7055)
Onchip (If option Watch, Break or RPE is set in the onchip trigger-unit)
41
Breakpoints
Memory Classes
Overview
Access Class
Description
CPU (Program and Data)
Data
Program
ED
Dualport Data
EP
Dualport Program
C:, E:, D:, P:, ED:, EP:

C:, P: and D:
This storage classes operate on the same physical memory. They are only used to be compatible with other
emulation probes.
E:, EP: and ED:
The E: prefix is used for accesses via dualport. The onchip I/O-registers and the onchip RAM area cant be
accessed via dualport.
42
Memory Classes
State Analyzer
Keywords for the Display

AREA
Access area
STATE
CPU status
ASEIF
Instruction fetch cycle
ASEHLIR
Pipeline execution status
ASELLIR
Pipeline execution status
ASEHEXP
Hardware exception processing
ASEBTA
Condition match signal of onchip trigger-unit channel A
ASEBTB
Condition match signal of onchip trigger-unit channel B
ASEBTC
Condition match signal of onchip trigger-unit channel C
ASEBTD
Condition match signal of onchip trigger-unit channel D
43
State Analyzer
Keywords for the Emulator Trigger Unit

General SH Keywords for the Emulator Trigger Unit
Input Event
Meaning
Analyzer
hardware
FEC
BTA
Condition match of onchip

trigger-unit channel A
BTB

trigger-unit channel B
BTC

trigger-unit channel C
BTD

trigger-unit channel D
DATA
Data access
FETCH
Prefetch cycle
Read
Read access
Write
Write access
SH701x/704x Keywords for the Emulator Trigger Unit

Input Event
Meaning
Analyzer
hardware
FEC
none
SH705x Keywords for the Emulator Trigger Unit

Input Event
Meaning
Analyzer
hardware
FEC
none
For not CPU-specific keywords, see non-declarable input variables in ICE/FIRE Analyzer Trigger Unit
Programming Guide (analyzer_prog.pdf).
44
State Analyzer
Port Analyzer
Port Signals SH7011

Name
Group
Description
A01 .. A21
ADDR
Address A01 .. A21
AN0 .. AN6
AN
Analog Input AN0 .. Input AN6
D00 .. D15
DATA
Data D00 .. D15
PA00 .. PA15
PA
Port PA00 .. PA15
2*SH7055
Signal 2*SH7055
PA18 .. PA19
PA
Port PA18 .. PA19
PB00 .. PB15
PB
Port PB00 .. PB15
PC00 .. PC04
PC
Port PC00 .. PC04
PD00 .. PD13
PD
Port PD00 .. PD13
PE00
PE
Port PE00
PE00 .. PE02
PE
Port PE00 .. PE02
PE02 .. PE04
PE
Port PE02 .. PE04
PE04 .. PE05
PE
Port PE04 .. PE05
PE05 .. PE06
PE
Port PE05 .. PE06
PE06 .. PE07
PE
Port PE06 .. PE07
PE07 .. PE12
PE
Port PE07 .. PE12
PE12 .. PE13
PE
Port PE12 .. PE13
PE13 .. PE14
PE
Port PE13 .. PE14
PE14 .. PE15
PE
Port PE14 .. PE15
PF00 .. PF15
PF
Port PF00 .. PF15
PG00 .. PG03
PG
Port PG00 .. PG03
PH00 .. PH15
PH
Port PH00 .. PH15
PJ00 .. PJ15
PJ
Port PJ00 .. PJ15
PK00 .. PK15
PK
Port PK00 .. PK15
PL00 .. PL13
PL
Port PL00 .. PL13
RXD
SCI
Receive Data
TXD
SCI
Transmit Data
CK
STROBES
System Clock
CS0-
STROBES
Chip Select 0
CS1-
STROBES
Chip Select 1
RD-
STROBES
Read
WAIT-
STROBES
Wait
WRH-
STROBES
Upper Write
WRL-
STROBES
Lower Write
45
Port Analyzer
Port Signals SH7014

Name
Group
Description
ADDR
Address A00 .. A17
2*SH7055
A00 .. A17
Signal 2*SH7055
D00 .. D15
DATA
Data D00 .. D15
PA00
PA
Port PA00
PA00 .. PA01
PA
Port PA00 .. PA01
PA01 .. PA02
PA
Port PA01 .. PA02
PA02 .. PA03
PA
Port PA02 .. PA03
PA03 .. PA04
PA
Port PA03 .. PA04
PA04 .. PA05
PA
Port PA04 .. PA05
PA05 .. PA06
PA
Port PA05 .. PA06
PA06 .. PA07
PA
Port PA06 .. PA07
PA07 .. PA08
PA
Port PA07 .. PA08
PA08 .. PA09
PA
Port PA08 .. PA09
PA09 .. PA15
PA
Port PA09 .. PA15
PA15
PA
Port PA15
PB00 .. PB02
PB
Port PB00 .. PB02
PB02 .. PB03
PB
Port PB02 .. PB03
PB03 .. PB04
PB
Port PB03 .. PB04
PB04 .. PB05
PB
Port PB04 .. PB05
PB05 .. PB06
PB
Port PB05 .. PB06
PB06 .. PB07
PB
Port PB06 .. PB07
PB07 .. PB08
PB
Port PB07 .. PB08
PB08 .. PB09
PB
Port PB08 .. PB09
PB09 .. PB15
PB
Port PB09 .. PB15
PC00 .. PC04
PC
Port PC00 .. PC04
PD00 .. PD13
PD
Port PD00 .. PD13
PE00
PE
Port PE00
PE00 .. PE01
PE
Port PE00 .. PE01
PE01 .. PE02
PE
Port PE01 .. PE02
PE02 .. PE03
PE
Port PE02 .. PE03
PE03 .. PE04
PE
Port PE03 .. PE04
PE04 .. PE05
PE
Port PE04 .. PE05
PE05 .. PE06
PE
Port PE05 .. PE06
PE06 .. PE07
PE
Port PE06 .. PE07
PE07 .. PE08
PE
Port PE07 .. PE08
PE08 .. PE09
PE
Port PE08 .. PE09
PE09 .. PE10
PE
Port PE09 .. PE10
PE10 .. PE11
PE
Port PE10 .. PE11
PE11 .. PE12
PE
Port PE11 .. PE12
PE12 .. PE13
PE
Port PE12 .. PE13
PE13 .. PE14
PE
Port PE13 .. PE14
PE14 .. PE15
PE
Port PE14 .. PE15
PE15
PE
Port PE15
PF0
PF
Port PF0
PF00 .. PF09
PF
Port PF00 .. PF09
PF1
PF
Port PF1
PF10 .. PF15
PF
Port PF10 .. PF15
PF2 .. PF7
PF
Port PF2 .. PF7
PG00 .. PG03
PG
Port PG00 .. PG03
46
Port Analyzer
Name
Group
Description
PH00 .. PH15
PH
Port PH00 .. PH15
PJ00 .. PJ15
PJ
Port PJ00 .. PJ15
PK00 .. PK15
PK
Port PK00 .. PK15
PL00 .. PL13
PL
Port PL00 .. PL13
CS0-
STROBES
Chip Select 0
CS1-
STROBES
Chip Select 1
RD-
STROBES
Read
WRH-
STROBES
Upper Write Enable
WRL-
STROBES
Lower Write Enable

Name
Group
Description
PA00
PA
Port PA00
PA00 .. PA01
PA
Port PA00 .. PA01
PA01 .. PA02
PA
Port PA01 .. PA02
PA02 .. PA03
PA
Port PA02 .. PA03
PA03 .. PA04
PA
Port PA03 .. PA04
PA04 .. PA05
PA
Port PA04 .. PA05
PA05 .. PA06
PA
Port PA05 .. PA06
PA06 .. PA07
PA
Port PA06 .. PA07
PA07 .. PA08
PA
Port PA07 .. PA08
PA08 .. PA09
PA
Port PA08 .. PA09
PA09 .. PA10
PA
Port PA09 .. PA10
PA10 .. PA11
PA
Port PA10 .. PA11
PA11 .. PA12
PA
Port PA11 .. PA12
PA12 .. PA13
PA
Port PA12 .. PA13
PA13 .. PA14
PA
Port PA13 .. PA14
PA14 .. PA15
PA
Port PA14 .. PA15
PA15
PA
Port PA15
2*SH7055
Signal 2*SH7055
PB00
PB
Port PB00
PB00 .. PB01
PB
Port PB00 .. PB01
PB01 .. PB02
PB
Port PB01 .. PB02
PB02 .. PB03
PB
Port PB02 .. PB03
PB03 .. PB04
PB
Port PB03 .. PB04
PB04 .. PB05
PB
Port PB04 .. PB05
PB05 .. PB06
PB
Port PB05 .. PB06
PB06 .. PB07
PB
Port PB06 .. PB07
PB07 .. PB08
PB
Port PB07 .. PB08
PB08 .. PB09
PB
Port PB08 .. PB09
PB09 .. PB15
PB
Port PB09 .. PB15
PC00
PC
Port PC00
PC00 .. PC01
PC
Port PC00 .. PC01
PC01 .. PC02
PC
Port PC01 .. PC02
PC02 .. PC03
PC
Port PC02 .. PC03
PC03 .. PC04
PC
Port PC03 .. PC04
47
Port Analyzer
Name
Group
Description
PC04 .. PC15
PC
Port PC04 .. PC15
PD00
PD
Port PD00
PD00 .. PD01
PD
Port PD00 .. PD01
PD01 .. PD02
PD
Port PD01 .. PD02
PD02 .. PD03
PD
Port PD02 .. PD03
PD03 .. PD04
PD
Port PD03 .. PD04
PD04 .. PD05
PD
Port PD04 .. PD05
PD05 .. PD06
PD
Port PD05 .. PD06
PD06 .. PD07
PD
Port PD06 .. PD07
PD07 .. PD08
PD
Port PD07 .. PD08
PD08 .. PD09
PD
Port PD08 .. PD09
PD09 .. PD10
PD
Port PD09 .. PD10
PD10 .. PD11
PD
Port PD10 .. PD11
PD11 .. PD12
PD
Port PD11 .. PD12
PD12 .. PD13
PD
Port PD12 .. PD13
PD13 .. PD15
PD
Port PD13 .. PD15
PE00
PE
Port PE00
PE00 .. PE01
PE
Port PE00 .. PE01
PE01 .. PE02
PE
Port PE01 .. PE02
PE02 .. PE03
PE
Port PE02 .. PE03
PE03 .. PE04
PE
Port PE03 .. PE04
PE04 .. PE05
PE
Port PE04 .. PE05
PE05 .. PE06
PE
Port PE05 .. PE06
PE06 .. PE07
PE
Port PE06 .. PE07
PE07 .. PE08
PE
Port PE07 .. PE08
PE08 .. PE09
PE
Port PE08 .. PE09
PE09 .. PE10
PE
Port PE09 .. PE10
PE10 .. PE11
PE
Port PE10 .. PE11
PE11 .. PE12
PE
Port PE11 .. PE12
PE12 .. PE13
PE
Port PE12 .. PE13
PE13 .. PE14
PE
Port PE13 .. PE14
PE14 .. PE15
PE
Port PE14 .. PE15
PE15
PE
Port PE15
PF0
PF
Port PF0
PF00 .. PF09
PF
Port PF00 .. PF09
PF1
PF
Port PF1
PF10 .. PF15
PF
Port PF10 .. PF15
PF2 .. PF7
PF
Port PF2 .. PF7
PG00 .. PG03
PG
Port PG00 .. PG03
PH00 .. PH15
PH
Port PH00 .. PH15
PJ00 .. PJ15
PJ
Port PJ00 .. PJ15
PK00 .. PK15
PK
Port PK00 .. PK15
PL00 .. PL13
PL
Port PL00 .. PL13
48
Port Analyzer

Name
Group
Description
PA00
PA
Port PA00
PA00 .. PA01
PA
Port PA00 .. PA01
PA01 .. PA02
PA
Port PA01 .. PA02
PA02 .. PA03
PA
Port PA02 .. PA03
PA03 .. PA04
PA
Port PA03 .. PA04
PA04 .. PA05
PA
Port PA04 .. PA05
PA05 .. PA06
PA
Port PA05 .. PA06
PA06 .. PA07
PA
Port PA06 .. PA07
PA07 .. PA08
PA
Port PA07 .. PA08
PA08 .. PA09
PA
Port PA08 .. PA09
PA09 .. PA10
PA
Port PA09 .. PA10
PA10 .. PA11
PA
Port PA10 .. PA11
PA11 .. PA12
PA
Port PA11 .. PA12
PA12 .. PA13
PA
Port PA12 .. PA13
PA13 .. PA14
PA
Port PA13 .. PA14
PA14 .. PA15
PA
Port PA14 .. PA15
PA15
PA
Port PA15
2*SH7055
Signal 2*SH7055
PB00
PB
Port PB00
PB00 .. PB01
PB
Port PB00 .. PB01
PB01 .. PB02
PB
Port PB01 .. PB02
PB02 .. PB03
PB
Port PB02 .. PB03
PB03 .. PB04
PB
Port PB03 .. PB04
PB04 .. PB05
PB
Port PB04 .. PB05
PB05 .. PB06
PB
Port PB05 .. PB06
PB06 .. PB07
PB
Port PB06 .. PB07
PB07 .. PB08
PB
Port PB07 .. PB08
PB08 .. PB09
PB
Port PB08 .. PB09
PB09 .. PB15
PB
Port PB09 .. PB15
PC00
PC
Port PC00
PC00 .. PC01
PC
Port PC00 .. PC01
PC01 .. PC02
PC
Port PC01 .. PC02
PC02 .. PC03
PC
Port PC02 .. PC03
PC03 .. PC04
PC
Port PC03 .. PC04
PC04 .. PC15
PC
Port PC04 .. PC15
PD00
PD
Port PD00
PD00 .. PD01
PD
Port PD00 .. PD01
PD01 .. PD02
PD
Port PD01 .. PD02
PD02 .. PD03
PD
Port PD02 .. PD03
PD03 .. PD04
PD
Port PD03 .. PD04
PD04 .. PD05
PD
Port PD04 .. PD05
PD05 .. PD06
PD
Port PD05 .. PD06
PD06 .. PD07
PD
Port PD06 .. PD07
PD07 .. PD08
PD
Port PD07 .. PD08
PD08 .. PD09
PD
Port PD08 .. PD09
PD09 .. PD10
PD
Port PD09 .. PD10
PD10 .. PD11
PD
Port PD10 .. PD11
PD11 .. PD12
PD
Port PD11 .. PD12
PD12 .. PD13
PD
Port PD12 .. PD13
49
Port Analyzer
Name
Group
Description
PD13 .. PD15
PD
Port PD13 .. PD15
PE00
PE
Port PE00
PE00 .. PE01
PE
Port PE00 .. PE01
PE01 .. PE02
PE
Port PE01 .. PE02
PE02 .. PE03
PE
Port PE02 .. PE03
PE03 .. PE04
PE
Port PE03 .. PE04
PE04 .. PE05
PE
Port PE04 .. PE05
PE05 .. PE06
PE
Port PE05 .. PE06
PE06 .. PE07
PE
Port PE06 .. PE07
PE07 .. PE08
PE
Port PE07 .. PE08
PE08 .. PE09
PE
Port PE08 .. PE09
PE09 .. PE10
PE
Port PE09 .. PE10
PE10 .. PE11
PE
Port PE10 .. PE11
PE11 .. PE12
PE
Port PE11 .. PE12
PE12 .. PE13
PE
Port PE12 .. PE13
PE13 .. PE14
PE
Port PE13 .. PE14
PE14 .. PE15
PE
Port PE14 .. PE15
PE15
PE
Port PE15
PF0
PF
Port PF0
PF00 .. PF09
PF
Port PF00 .. PF09
PF1
PF
Port PF1
PF10 .. PF15
PF
Port PF10 .. PF15
PF2 .. PF7
PF
Port PF2 .. PF7
PG00 .. PG03
PG
Port PG00 .. PG03
PH00 .. PH15
PH
Port PH00 .. PH15
PJ00 .. PJ15
PJ
Port PJ00 .. PJ15
PK00 .. PK15
PK
Port PK00 .. PK15
PL00 .. PL13
PL
Port PL00 .. PL13

Name
Group
Description
PA00
PA
Port PA00
PA00 .. PA01
PA
Port PA00 .. PA01
PA01 .. PA02
PA
Port PA01 .. PA02
PA02 .. PA03
PA
Port PA02 .. PA03
PA03 .. PA04
PA
Port PA03 .. PA04
PA04 .. PA05
PA
Port PA04 .. PA05
PA05 .. PA06
PA
Port PA05 .. PA06
PA06 .. PA07
PA
Port PA06 .. PA07
PA07 .. PA08
PA
Port PA07 .. PA08
PA08 .. PA09
PA
Port PA08 .. PA09
PA09 .. PA10
PA
Port PA09 .. PA10
PA10 .. PA11
PA
Port PA10 .. PA11
PA11 .. PA12
PA
Port PA11 .. PA12
PA12 .. PA13
PA
Port PA12 .. PA13
2*SH7055
Signal 2*SH7055
50
Port Analyzer
Name
Group
Description
PA13 .. PA14
PA
Port PA13 .. PA14
PA14 .. PA15
PA
Port PA14 .. PA15
PA15 .. PA23
PA
Port PA15 .. PA23
PB00
PB
Port PB00
PB00 .. PB01
PB
Port PB00 .. PB01
PB01 .. PB02
PB
Port PB01 .. PB02
PB02 .. PB03
PB
Port PB02 .. PB03
PB03 .. PB04
PB
Port PB03 .. PB04
PB04 .. PB05
PB
Port PB04 .. PB05
PB05 .. PB06
PB
Port PB05 .. PB06
PB06 .. PB07
PB
Port PB06 .. PB07
PB07 .. PB08
PB
Port PB07 .. PB08
PB08 .. PB09
PB
Port PB08 .. PB09
PB09 .. PB15
PB
Port PB09 .. PB15
PC00
PC
Port PC00
PC00 .. PC01
PC
Port PC00 .. PC01
PC01 .. PC02
PC
Port PC01 .. PC02
PC02 .. PC03
PC
Port PC02 .. PC03
PC03 .. PC04
PC
Port PC03 .. PC04
PC04 .. PC15
PC
Port PC04 .. PC15
PD00
PD
Port PD00
PD00 .. PD01
PD
Port PD00 .. PD01
PD01 .. PD02
PD
Port PD01 .. PD02
PD02 .. PD03
PD
Port PD02 .. PD03
PD03 .. PD04
PD
Port PD03 .. PD04
PD04 .. PD05
PD
Port PD04 .. PD05
PD05 .. PD06
PD
Port PD05 .. PD06
PD06 .. PD07
PD
Port PD06 .. PD07
PD07 .. PD08
PD
Port PD07 .. PD08
PD08 .. PD09
PD
Port PD08 .. PD09
PD09 .. PD10
PD
Port PD09 .. PD10
PD10 .. PD11
PD
Port PD10 .. PD11
PD11 .. PD12
PD
Port PD11 .. PD12
PD12 .. PD13
PD
Port PD12 .. PD13
PD13 .. PD31
PD
Port PD13 .. PD31
PE00
PE
Port PE00
PE00 .. PE01
PE
Port PE00 .. PE01
PE01 .. PE02
PE
Port PE01 .. PE02
PE02 .. PE03
PE
Port PE02 .. PE03
PE03 .. PE04
PE
Port PE03 .. PE04
PE04 .. PE05
PE
Port PE04 .. PE05
PE05 .. PE06
PE
Port PE05 .. PE06
PE06 .. PE07
PE
Port PE06 .. PE07
PE07 .. PE08
PE
Port PE07 .. PE08
PE08 .. PE09
PE
Port PE08 .. PE09
PE09 .. PE10
PE
Port PE09 .. PE10
PE10 .. PE11
PE
Port PE10 .. PE11
PE11 .. PE12
PE
Port PE11 .. PE12
PE12 .. PE13
PE
Port PE12 .. PE13
PE13 .. PE14
PE
Port PE13 .. PE14
PE14 .. PE15
PE
Port PE14 .. PE15
51
Port Analyzer
Name
Group
Description
PE15
PE
Port PE15
PF0
PF
Port PF0
PF00 .. PF09
PF
Port PF00 .. PF09
PF1
PF
Port PF1
PF10 .. PF15
PF
Port PF10 .. PF15
PF2 .. PF7
PF
Port PF2 .. PF7
PG00 .. PG03
PG
Port PG00 .. PG03
PH00 .. PH15
PH
Port PH00 .. PH15
PJ00 .. PJ15
PJ
Port PJ00 .. PJ15
PK00 .. PK15
PK
Port PK00 .. PK15
PL00 .. PL13
PL
Port PL00 .. PL13

Name
Group
Description
PA00
PA
Port PA00
PA00 .. PA01
PA
Port PA00 .. PA01
PA01 .. PA02
PA
Port PA01 .. PA02
PA02 .. PA03
PA
Port PA02 .. PA03
PA03 .. PA04
PA
Port PA03 .. PA04
PA04 .. PA05
PA
Port PA04 .. PA05
PA05 .. PA06
PA
Port PA05 .. PA06
PA06 .. PA07
PA
Port PA06 .. PA07
PA07 .. PA08
PA
Port PA07 .. PA08
PA08 .. PA09
PA
Port PA08 .. PA09
PA09 .. PA10
PA
Port PA09 .. PA10
PA10 .. PA11
PA
Port PA10 .. PA11
PA11 .. PA12
PA
Port PA11 .. PA12
PA12 .. PA13
PA
Port PA12 .. PA13
PA13 .. PA14
PA
Port PA13 .. PA14
PA14 .. PA15
PA
Port PA14 .. PA15
PA15
PA
Port PA15
2*SH7055
Signal 2*SH7055
PB00
PB
Port PB00
PB00 .. PB01
PB
Port PB00 .. PB01
PB01 .. PB02
PB
Port PB01 .. PB02
PB02 .. PB03
PB
Port PB02 .. PB03
PB03 .. PB04
PB
Port PB03 .. PB04
PB04 .. PB05
PB
Port PB04 .. PB05
PB05 .. PB06
PB
Port PB05 .. PB06
PB06 .. PB07
PB
Port PB06 .. PB07
PB07 .. PB08
PB
Port PB07 .. PB08
PB08 .. PB09
PB
Port PB08 .. PB09
PB09 .. PB10
PB
Port PB09 .. PB10
PB10 .. PB11
PB
Port PB10 .. PB11
PB11 .. PB15
PB
Port PB11 .. PB15
PC00
PC
Port PC00
52
Port Analyzer
Name
Group
Description
PC00 .. PC01
PC
Port PC00 .. PC01
PC01 .. PC02
PC
Port PC01 .. PC02
PC02 .. PC03
PC
Port PC02 .. PC03
PC03 .. PC04
PC
Port PC03 .. PC04
PC04 .. PC14
PC
Port PC04 .. PC14
PD00
PD
Port PD00
PD00 .. PD01
PD
Port PD00 .. PD01
PD01 .. PD02
PD
Port PD01 .. PD02
PD02 .. PD03
PD
Port PD02 .. PD03
PD03 .. PD04
PD
Port PD03 .. PD04
PD04 .. PD05
PD
Port PD04 .. PD05
PD05 .. PD06
PD
Port PD05 .. PD06
PD06 .. PD07
PD
Port PD06 .. PD07
PD07 .. PD08
PD
Port PD07 .. PD08
PD08 .. PD09
PD
Port PD08 .. PD09
PD09 .. PD10
PD
Port PD09 .. PD10
PD10 .. PD11
PD
Port PD10 .. PD11
PD11 .. PD12
PD
Port PD11 .. PD12
PD12 .. PD13
PD
Port PD12 .. PD13
PD13 .. PD15
PD
Port PD13 .. PD15
PE00
PE
Port PE00
PE00 .. PE01
PE
Port PE00 .. PE01
PE01 .. PE02
PE
Port PE01 .. PE02
PE02 .. PE03
PE
Port PE02 .. PE03
PE03 .. PE04
PE
Port PE03 .. PE04
PE04 .. PE05
PE
Port PE04 .. PE05
PE05 .. PE06
PE
Port PE05 .. PE06
PE06 .. PE07
PE
Port PE06 .. PE07
PE07 .. PE08
PE
Port PE07 .. PE08
PE08 .. PE09
PE
Port PE08 .. PE09
PE09 .. PE10
PE
Port PE09 .. PE10
PE10 .. PE11
PE
Port PE10 .. PE11
PE11 .. PE12
PE
Port PE11 .. PE12
PE12 .. PE13
PE
Port PE12 .. PE13
PE13 .. PE14
PE
Port PE13 .. PE14
PE14 .. PE15
PE
Port PE14 .. PE15
PF00
PF
Port PF00
PF00 .. PF01
PF
Port PF00 .. PF01
PF01 .. PF02
PF
Port PF01 .. PF02
PF02 .. PF03
PF
Port PF02 .. PF03
PF03 .. PF04
PF
Port PF03 .. PF04
PF04 .. PF05
PF
Port PF04 .. PF05
PF05 .. PF06
PF
Port PF05 .. PF06
PF06 .. PF07
PF
Port PF06 .. PF07
PF07 .. PF08
PF
Port PF07 .. PF08
PF08 .. PF09
PF
Port PF08 .. PF09
PF09 .. PF10
PF
Port PF09 .. PF10
PF10 .. PF11
PF
Port PF10 .. PF11
PF11 .. PF15
PF
Port PF11 .. PF15
PG00
PG
Port PG00
PG00 .. PG01
PG
Port PG00 .. PG01
53
Port Analyzer
Name
Group
Description
PG01 .. PG02
PG
Port PG01 .. PG02
PG02 .. PG03
PG
Port PG02 .. PG03
PG03 .. PG15
PG
Port PG03 .. PG15
PH00
PH
Port PH00
PH00 .. PH01
PH
Port PH00 .. PH01
PH01 .. PH02
PH
Port PH01 .. PH02
PH02 .. PH03
PH
Port PH02 .. PH03
PH03 .. PH04
PH
Port PH03 .. PH04
PH04 .. PH05
PH
Port PH04 .. PH05
PH05 .. PH06
PH
Port PH05 .. PH06
PH06 .. PH07
PH
Port PH06 .. PH07
PH07 .. PH08
PH
Port PH07 .. PH08
PH08 .. PH09
PH
Port PH08 .. PH09
PH09 .. PH10
PH
Port PH09 .. PH10
PH10 .. PH11
PH
Port PH10 .. PH11
PH11 .. PH12
PH
Port PH11 .. PH12
PH12 .. PH13
PH
Port PH12 .. PH13
PH13 .. PH14
PH
Port PH13 .. PH14
PH14 .. PH15
PH
Port PH14 .. PH15
PH15
PH
Port PH15
PJ00 .. PJ15
PJ
Port PJ00 .. PJ15
PK00 .. PK15
PK
Port PK00 .. PK15
PL00 .. PL13
PL
Port PL00 .. PL13
54
Port Analyzer
Technical Data
Mechanical Dimensions
Dimension
LA-9621
FIRE-M-SH7055
55
Technical Data
Dimension
LA-9562
FIRE-M-SH7040-32
LA-9565
FIRE-M-SH7014
56
Technical Data
Dimension
LA-9563
FIRE-M-SH7050
LA-9564
FIRE-M-SH7051
57
Technical Data
Dimension
LA-9566
FIRE-M-SH7017
58
Technical Data
Dimension
LA-9561
FIRE-M-SH7040-16
Front
14
6
160
SIDE VIEW
ET112QF36
105
52
Pin 1
80
TOP VIEW (all dimensions in mm)
59
Technical Data
Dimension
LA-9626
A-SH7055-S-BGA256
LA-9628
CPU-LASH7055-M
60
Technical Data
Adaptions
CPU
Adaption
SH7011
ET100-QF49
SH7014
SH7016
SH7017
SH7040
SH7042
SH7044
ET112-QF36
61
Technical Data
CPU
Adaption
SH7041
SH7043
SH7045
ET144-QF63
62
Technical Data
Adapters
Socket CPU
Adapter
ET100-QF49
YA-1091 ET100-EYA-QF49
Emul. Adapter for YAMAICHI socket ET100-QF49
SH7011
8
6
56
SIDE VIEW
66
18
14
63
Technical Data
Socket CPU
Adapter
ET112-QF36
SH7014
SH7016
SH7017
SH7040
SH7042
SH7044
8
6
56
SIDE VIEW
64
14
10
64
Technical Data
Socket CPU
Adapter
ET112-QF36
TO-1290 ET112-ETO-QF36
Emul. Adapter for TO socket ET112-QF36
SH7014
SH7016
SH7017
SH7040
SH7042
SH7044
2200
2500
PIN1
TOP VIEW
SIDE VIEW
600
ADAPTER
SOCKET
TARGET
ALL DIMENSIONS IN 1/1000 INCH
ET112-QF36
TO-1291 ET112-STO-QF36
Emul. Adapter TO-surface mount. ET112-QF36
SH7014
SH7016
SH7017
SH7040
SH7042
SH7044
2200
TOP VIEW
PIN1
2500
SIDE VIEW
400
SOLDER
BLOCK
TARGET
ALL DIMENSIONS IN 1/1000 INCH
65
Technical Data
Socket CPU
Adapter
ET120-QF56
SH7040
SH7042
ET120-QF56
Adapter/ Target Design
TOP VIEW
2400
2400
2050
2050
32
360
31
775
4 X SAMTEC:
TFM-115-22-S-LC
ICP-120-2
66
Technical Data
Socket CPU
Adapter
ET144-QF63
SH7041
SH7043
SH7045
8
6
69
SIDE VIEW
69
17
18
67
Technical Data
Socket CPU
Adapter
LASH7055
LA-9626 A-SH7055-S-BGA256
Emul. adapter for AI-BGA-socket for LASH7055
SH7052
SH7053
SH7054
SH7055
68
Technical Data
Operation Voltage
This list contains information on probes available for other voltage ranges. Probes not noted here supply an
operation voltage range of 4.5 5.5 V.
CPU
Module
Adapter
Voltage Range
SH7011
SH7014
SH7016
SH7017
SH7040
SH7041
SH7042
SH7043
SH7044
SH7045
SH7050
SH7051
SH7052
SH7053
SH7054
SH7055
LA-9566
LA-9565
LA-9566
LA-9566
LA-9561
LA-9562
LA-9561
LA-9562
LA-9561
LA-9562
LA-9563
LA-9564
LA-9621
LA-9621
LA-9621
LA-9621
LA-9629
LA-9629
LA-9629
-
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 3.5 V
3.0 .. 3.5 V
3.0 .. 3.5 V
3.0 .. 5.5 V
69
Technical Data
Operation Frequency
Module
CPU
F-W010
F-W110
S-W010
S-W110
CHIP
TRACE HEAD
RAM
LA-9566
LA-9565
LA-9566
LA-9566
LA-9561
LA-9562
LA-9561
LA-9562
LA-9561
LA-9562
LA-9563
LA-9564
LA-9621
LA-9621
LA-9621
LA-9621
SH7011
SH7014
SH7016
SH7017
SH7040
SH7041
SH7042
SH7043
SH7044
SH7045
SH7050
SH7051
SH7052
SH7053
SH7054
SH7055
20.0
28.7
28.7
28.7
33.0
33.0
33.0
33.0
33.0
33.0
20.0
20.0
40.0
40.0
40.0
40.0
20.0+
28.7+
28.7+
28.7+
33.0+
33.0+
33.0+
33.0+
33.0+
33.0+
20.0+
20.0+
40.0+
40.0+
40.0+
40.0+
17.3
23.5
23.5
23.5
26.3
26.3
26.3
26.3
26.3
26.3
17.3
17.3
30.6
30.6
30.6
30.6
20.0+
28.7+
28.7+
28.7+
33.0+
33.0+
33.0+
33.0+
33.0+
33.0+
20.0+
20.0+
40.0+
40.0+
40.0+
40.0+
20.0
28.7
28.7
28.7
33.0
33.0
33.0
33.0
33.0
33.0
20.0
20.0
40.0
40.0
40.0
40.0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
70
Technical Data
Support
Probes
LA-9560
LA-9566
SH7011
ET100-QF49 3.0..5.5V
LA-9565
SH7014
ET112-QF36 3.0..5.5V
SH7016
ET112-QF36 3.0..5.5V
SH7017
ET112-QF36 3.0..5.5V
LA-9561
SH7040
SH7040
ET112-QF36 3.0..5.5V
ET120-QF56 3.0..5.5V
LA-9562
SH7041
ET144-QF63 3.0..5.5V
LA-9561
SH7042
SH7042
ET112-QF36 3.0..5.5V
ET120-QF56 3.0..5.5V
LA-9562
SH7043
ET144-QF63 3.0..5.5V
LA-9561
SH7044
ET112-QF36 3.0..5.5V
LA-9562
SH7045
ET144-QF63 3.0..5.5V
LA-9563
SH7050
ET168-QF25 3.0..5.5V
LA-9564
SH7051
ET168-QF25 3.0..5.5V
LA-9566
LA-9621
LA-9620
LA-9629
LA-9621
SH7052
LASH7055
3.0..3.5V
SH7053
LASH7055
3.0..3.5V
SH7054
LASH7055
3.0..3.5V
SH7055
LASH7055
3.0..5.5V
71
Support
SH7011
SH7014
SH7016
SH7017
SH7040
SH7041
SH7042
SH7043
SH7044
SH7045
SH7050
SH7051
SH7052
SH7053
SH7054
SH7055
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
Available Tools
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Compiler Support
Language
Compiler
Company
Option
GCCSH
COFF
C
C
C
GREEN-HILLS-C
ICCSH
SHC
C++
SHC++
C++
D-CC
Free Software
Foundation, Inc.
Greenhills Software Inc.
IAR Systems AB
Renesas Technology,
Corp.
Renesas Technology,
Corp.
Wind River Systems
Comment
COFF
UBROF
SYSROF
ELF/DWARF2
ELF/DWARF
72
Support
Realtime Operation Systems

Name
Company
CMX-RTX
HI7000
Linux
Linux
Nucleus
OS21
OSEK
ProOSEK
QNX
SMX
ThreadX
uITRON
VxWorks
Windows CE
Windows Mobile
CMX Systems Inc.

Renesas Technology, Corp.
MontaVista Software, LLC
Mentor Graphics Corporation
ST Microelectronics N.V.
Elektrobit Automotive GmbH
QNX Software Systems
Micro Digital Inc.
Express Logic Inc.
Wind River Systems
Microsoft Corporation
Comment
Kernel Version 2.4 and 2.6, 3.x, 4.x

3.0, 3.1, 4.0, 5.0
via ORTI
via ORTI
6.0 to 6.5.0
3.4 to 4.0
3.0, 4.0, 5.x
HI7000, RX4000, NORTi,PrKernel
5.x and 6.x
4.0 to 6.0
4.0 to 6.0
3rd Party Tool Integrations

CPU
Tool
Company
ALL
ALL
ALL
ADENEO
X-TOOLS / X32
CODEWRIGHT
ALL
CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER
Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ATTOL TOOLS
VISUAL BASIC
INTERFACE
Host
Windows
Windows
Windows
Code Confidence Ltd
Linux
EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
73
Support
CPU
Tool
Company
Host
ALL
LABVIEW
Windows
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER
NATIONAL
INSTRUMENTS
Corporation
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software
Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows
Vector Software
Windows
Windows
Windows
ALL
ALL
74
Support
Products
Product Information
OrderNo Code
Text
LA-9560
FIRE Family Module for SH2
FIRE-SH2-1
supports SH7040/7042/7044
with FIRE CPU Module for SH7040 (16-bit bus)
supports SH7041/7043/7045
with FIRE CPU Module for SH7040 (32-bit bus)
supports SH7014
with FIRE CPU Module for SH7014
supports SH7050
supports SH7051
requires FIRE-SRAM
LA-9561
FIRE CPU Module for SH7040 (16-bit bus)
FIRE-M-SH7040-16
QFP112 Adapter for SH7040/7042/7044

TQFP120 Adapter for SH7040/7042
QFP112 requires ET112-QF36
TQFP120 requires ET120-QF56
LA-9562
FIRE-M-SH7040-32
QFP144 Adapter for SH7041/7043/7045

LA-9563
FIRE CPU Module for SH7050
FIRE-M-SH7050
QFP168 Adapter for SH7050

LA-9564
FIRE-M-SH7051

LA-9565
FIRE-M-SH7014

LA-9566
FIRE CPU Module for SH7011/7016/7017
FIRE-M-SH7017
QFP112 Adapter for SH7016/7017

TQFP100 Adapter for SH7011
TQFP100 requires ET100-QF49
LA-9620
FIRE Family Module for SH2E
FIRE-SH2-2
supports SH7055
requires FIRE-SRAM
LA-9621
FIRE CPU Module for SH7055/52/53/54
FIRE-M-SH7055
LASH7055 Adapter (TCON320)

QFP256 requires LA-9625 (SH7055)
BGA256 requires LA-9626 and
Mirror-Adapter LA-2036
QFP208 requires LA-9629 (SH7052/53/45)
LA-9625
Surface Mount. Adapter for LASH7055 to QFP256
A-SH7055-S-QFP256
Adapter for SH7055 to QFP256

solder on connection
(solder on block included)
Testadapter for usage of cpu in QFP256 (LA-9627)
TO-1395
TO-256RD Adapter Extension
TO-256RD-EXTENSION
Extension for TET Adapter LA-9625

(Extents vertical clearance of 28 mm)
75
Products
OrderNo Code
Text
LA-9626
A-SH7055-S-BGA256
Adapter for SH7055 to BGA256-Socket

Advanced Interconnect socket part number (AI-9634):
MGS256-636GG (20 20 rows)
Testadapter for usage of cpu in BGA256 (LA-9628)
AI-9634
Advanced Interconnect socket for SH7055
BGA256-AI-SOCKET(SH)
Advanced Interconnect socket

BGA256 for SH7055
(20 x 20 rows)
LA-9629
Surface Mount. Adapter for LASH7052/53/54
A-SH7055-S-QFP208
Adapter for SH7055 to QFP208 (SH7052/53/54)

solder on connection
(solder on block included)
LA-9627
CPU Test Adapter for LASH7055
CPU-LASH7055
Testadapter for LA-9625

allows the use of the original
CPU in QFP256 package
LA-9628
CPU Test Adapter for LASH7055-M
CPU-LASH7055-M
Testadapter for LA-9626

allows the use of the original
CPU in BGA256 package
76
Products
Order Information
Order No.
Code
Text
LA-9560
LA-9561
LA-9562
LA-9563
LA-9564
LA-9565
LA-9566
LA-9620
LA-9621
LA-9625
TO-1395
LA-9626
AI-9634
LA-9629
LA-9627
LA-9628
FIRE-SH2-1
FIRE-M-SH7040-16
FIRE-M-SH7040-32
FIRE-M-SH7050
FIRE-M-SH7051
FIRE-M-SH7014
FIRE-M-SH7017
FIRE-SH2-2
FIRE-M-SH7055
A-SH7055-S-QFP256
TO-256RD-EXTENSION
A-SH7055-S-BGA256
BGA256-AI-SOCKET(SH)
A-SH7055-S-QFP208
CPU-LASH7055
CPU-LASH7055-M
FIRE Family Module for SH2

FIRE CPU Module for SH7011/7016/7017
FIRE Family Module for SH2E
FIRE CPU Module for SH7055/52/53/54
Surface Mount. Adapter for LASH7055 to QFP256
TO-256RD Adapter Extension
Advanced Interconnect socket for SH7055
Surface Mount. Adapter for LASH7052/53/54
CPU Test Adapter for LASH7055
CPU Test Adapter for LASH7055-M
Additional Options
LA-9547
BGA256-CPU-ADAPTER
LA-7216
BGA357-CPU-ADAPTER
YA-1142
ET120-EYA-QF56
LA-2036
MCON320
LA-7526
MON-SH
CPU Test Adapter for BGA256 (MPC850)

CPU Test Adapter for BGA357 (MPC860)
Mirror Adapter for T-CON320 (M-CON320)
ROM Monitor for SH family on ESI
77
Products

Fire sh2

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FIRE Emulator for SH2

TRACE32 Online Help

FIRE In-Circuit Emulator ...............................................................................................................

FIRE Target Guides ....................................................................................................................

FIRE Emulator for SH2 ............................................................................................................

Quick Start ............................................................................................................................

General SYStem Settings and Restrictions .......................................................................

3.3 V power fail detection

Mask interrupts during assembler step

Mask interrupts during HLL step

Continue with CPU specific Special Settings and Restrictions

Special Settings SH701x/704x and Restrictions ...............................................................

Control of multifunction timer pulse unit

Control of compare match timer unit

Special Settings SH7050/51 and Restrictions ...................................................................

Restrictions for SH7050/51

Control of advanced timer unit

1989-2016 Lauterbach GmbH

FIRE Emulator for SH2

Special Settings SH7055 and Restrictions ........................................................................

Control of advanced timer unit

Control of compare match timer unit

On-chip Trigger Unit ............................................................................................................

Specific TrOnchip Commands ............................................................................................

Enable hardware output

Select bus cycle type

Select bus master type

Select operand size

Set data selector value

Select sequential mode

Enable reset pointer

Set repeat counter value

Exception Control ................................................................................................................

Manual Reset (SH701x/704x)

Hardware Standby (SH705x)

Exceptions during Break Mode

Memory Classes ...................................................................................................................

State Analyzer .......................................................................................................................

Keywords for the Display

Keywords for the Emulator Trigger Unit

General SH Keywords for the Emulator Trigger Unit

SH701x/704x Keywords for the Emulator Trigger Unit

SH705x Keywords for the Emulator Trigger Unit

Port Analyzer ........................................................................................................................

Port Signals SH7011

Port Signals SH7014

FIRE Emulator for SH2

Port Signals SH7016/SH7017

Port Signals SH7040/SH7042/SH7044

Port Signals SH7041/SH7043/SH7045

Port Signals SH7050/SH7051

Technical Data ......................................................................................................................

Realtime Operation Systems

3rd Party Tool Integrations

1989-2016 Lauterbach GmbH

FIRE Emulator for SH2

FIRE Emulator for SH2

1989-2016 Lauterbach GmbH

FIRE Emulator for SH2

1989-2016 Lauterbach GmbH

FIRE Emulator for SH2

Set cpu-type and -mode

Set system options