Professional Documents
Culture Documents
Concept ....................................................................................................................................
Modules
Host Interface
Power Supply
11
12
14
Modularity
14
Buffered Probes
14
Memories
15
Dual-Port Technology
15
16
16
Basic Function
16
Set-up
17
Function
18
Dual-port Access
19
Access Procedures
19
Memory Classes
20
Breakpoint System
21
Breakpoint Definition
21
Breakpoint Selection
21
Breakpoint Types
22
Realization Modes
23
Breakpoint Example
24
Trigger System
26
Function
26
Trigger Events
27
State Display
27
1989-2016 Lauterbach GmbH
Set-up
27
Analyzer
28
Function
28
Modes
29
Commands
29
30
30
Display Commands
30
31
Performance Analyzer
31
Analyzer Structure
31
Commands
32
Display Results
33
33
Flag System
34
Function
34
Set-up
34
Applications
34
Restrictions
34
35
Function
35
Set-Up
36
Exception Control
37
Function
37
Set-up
37
Frequency Generator
38
Function
38
Set-up
38
Universal Counter
39
Function
39
Level Display
40
Display Window
40
Set-up
40
Pulse Generator
41
Function
41
Set-up
41
42
43
Concept
TRACE32-FIRE is a modular, universal microprocessor development system, working with a PC or a
workstation. The modular concept allows memory size and analyzer performance to be customized to the
developer's needs.
Modules
The FIRE-Probe for Non-bondout CPUs
Host Interface
Power Supply
FSC
FEC
Trigger, Trace
Clock Generator
Dual-Port Controller
FR
Up to 4M + 4M Emulation
and Break Memory or
up to 4M + 4M Emulation
and Flag Memory
Target System
Concept
Host Interface
Power Supply
FSC
FEC
Trigger, Trace
Clock Generator
Dual-Port Controller
FR
FF-XX
Up to 4M + 4M Emulation
and Break Memory or
up to 4M + 4M Emulation
and Flag Memory
Target System
Concept
Host Interface
The Host Interface is mounted on top of the FIRE System Controller. It links the host hardware with the FIRE
probe. There are two different types available:
PODBUS Interface
Parallel Interface
Power Supply
The FIRE Power Supply is mounted on top of the FIRE System Controller. It is necessary to transform the
6-12V input supply of the FIRE Probe to the different voltages that are used.
The 110V or 220V detection is done automatically in the power pack.
The description of the LEDs that are physically mounted on the PowerSupply is in the description of the Fire
System Controller
Concept
Status LED
The FSC has an array of LEDs to show some status information to the user.
AUX
ERROR
EMULATE
ACTIVE
TRANSFER
SELECT
POWER
During the bootig sequence of the subcontroller the LEDs show the boot progress. The following
combinations will apear:
AUX
ERROR
EMULATE
ACTIVE
TRANSFER
SELECT
POWER
BOOT PROGRESS
Concept
Function
AUX
Not Used
ERROR
Internal error
EMULATE
ACTIVE
System up
TRANSFER
SELECT
Podbus device select. This LED is bright all the time if the T32Fire is the only
podbus device
POWER
Trace Connector
The FSC has a connector for tracing external port lines if a port analyzer is available, and show some status
information of the running emulation.
Pin39
Pin1
Pin40
Pin2
Pin
I/O
Function
1 - 32
Input
External Port 0 - 31
33
Output
34
Output
35
Output
36
Output
37 - 38
Output
39 - 40
Output
GND
Concept
This module contains all emulation components which are not CPU
specific. These include the VCO generator, the trace and trigger unit,
the runtime counter, the universal counter and the pulse generator.
Trigger
The trigger system can combine all trigger sources and therefore generate the emulator break and analyzer
control signals.
Event
Break
Break
External
CPU
Trigger
Unit
Trace
External
...
Trace
The trace unit samples address, data and status lines of the CPU plus additional analyzer control signals.
Address
Data
Status
Timestamp
Trace
Unit
...
Control
Concept
Dualport Controller
The dualport controller enables direct access to the overlay emulation memory.
DualPort
Access
Dual
Port
CTRL
Memory
CPU
Performance Analyzer
The performance analyzer allows the continuous display and measurement of the program execution time.
The analysis can be done on function base, predefined areas or fixed address spaces.
Runtime Counter
The runtime counter counts the time the CPU runs in user program.
Run/Stop
Time Reference
...
Runtime
Counter
Counter
The universal counter is an utility system for measuring clock frequencies or events.
Clock
Cycle
...
...
...
...
...
...
...
Input
multiplexer
Universal
Counter
Concept
Pulse Generator
The pulse generator is able to supply the target system with short single or periodic pulses.
Rate
generator
Pulse Connector
Puls
generator
Single Puls
Emulation Adapter
Analyzer
VCO
The VCO (voltage controlled oscillator) can be used to generate a system clock, when the internal clock is
selected.
Driver
on
Emulation
Adapter
VCO
1 150 MHz
CLOCK
CPU
Trigger Connector
The FEC has a connector for trigger/pulse out and trigger input (EXTA, EXTB)
Version for FCA_3 (HELP->VERSION->HARDWARE):
Trigger
Pulse
N/C
EXTB
EXTA
N/C
GND
GND
GND
GND
GND
10
Concept
GND
GND
GND
EXTB
EXTA
GND
GND
Usage
The usage of this memory is different:
32bit CPUs
64bit CPU
Configurations
Up to 4 FR modules can be used in one TRACE32Fire system.
Sizes
Every FR module has 8 + 8 memory blocks. There are different sizes available.
Module Size
Block Size
1M + 1M
128K
2M + 2M
256K
4M + 4M
512K
11
Concept
FIRE - Emulation
Adapter
Onchip/Monitor Interface
The access to the CPU is done by a on-chip debug interface if the CPU contains such an interface. If not, the
access is realized through a monitor program that runs on an extra monitor memory.
Mapper
The mapper is the interface between the complete address space of the CPU and the mapped overlay
memory. It translates the address information of each CPU cycle to the chipselect lines of the overlay
memory.
CPU
...
...
...
...
...
address
...............
....
....
....
....
map bussize
select internal memory
protect internal memory
enable break memory
enable data memory
12
Concept
Exception Unit
The exception unit can separate exception lines of the CPU from the target, and activate exceptions
manually or by trigger.
Pulse
Generator
Pulse
Activate
Exception
Activation
Enable
Switch
CPU
Target
For the very specific options that your FIRE Emulation Adapter offers, refer to the emulation probe manual.
13
Concept
Modularity
TRACE32 FIRE is a modular emulation system that uses multi-step modular technology to support as many
CPU and socket types as possible. Designed as an open system, it offers connections to many workstations
and host operating systems and most compiler systems on the market.
The basic system is designed for 8, 16, 32 and 64-bit CPUs.
Buffered Probes
The address and data lines are isolated. To bring-up the emulator system the target power must be valid
only. This concept allows debugging target systems with hardware failures. The debug monitor is allocated in
a separate memory and needs no space within the target memory (monitor versions) or the debug interface
is made by an on-chip debug interface. The target software neednt to be changed for TRACE32 FIRE.
CPU
BUFFER
TARGET
14
Memories
Emulation
CPU
Emulation
Memory
Dual Port
Controller
Emulation
Controller
TRACE32 FIRE has an emulation memory that consists of two 32bit memory blocks. The usage of the two
blocks can differ. For 32-bit CPUs, the lower half is always used as overlay memory, the upper half can be
used as overlay memory or as flag memory. For 64-bit CPUs the memory is always used as overlay
memory.
Dual-Port Technology
All memories can be accessed by the CPU and the system controller. The dual-port technology enables fast
down-load of the program and data. On a running system static variables and system set-ups may be
displayed and manipulated. Setting of breakpoints and analyzing flag memory is possible, while the target
program is running in realtime.
The emulation memory is no real dual-ported memory. The dual ported access is done while the CPU does
not use the emulation memory. Different access modes are implemented inside the FIRE adapter. See your
emulation probe manual for the dual port modes that are implemented for your CPU.
Debug
Interface
CPU Access
Fire
System
Controller
DualPort
Access
DualPort
Logic
Memory
CPU
Target
15
Emulator Functions
The different functions of the Trace32 FIRE are implemented in different modules (e.g. FIRE Emulation
Controller, FIRE Adapter). The description of these functions is not organized by the modules but by the
functionality.
Mapper
Basic Function
The mapper is the basic system for controlling all signals depending on the address of the emulation CPU.
The basic functions are to set-up the overlay memory and write protect certain address areas. An additional
function of the mapper is to generate stimulation signals like acknowledge signals. The mapper consists of a
64K * 32 bit high-speed memory. The address input is connected to the CPU address bus, while the data
outputs control the system or enable the chip selects of the emulation memory.
CPU
...
...
...
...
...
address
...............
....
....
....
....
map bussize
select internal memory
protect internal memory
enable break memory
enable data memory
When mapping overlay, break or flag memory, the minimum blocksize of the mapper is caused by the size of
the RAM chips on the TRACE32 FIRE RAM modules. Each RAM module is organized as 16 blocks, 8
blocks for the lower 32 bit and 8 blocks for the higher 32 bit. The resulting blocksizes are:
Module
Blocksize
1M + 1M
128K
2M + 2M
256K
4M + 4M
512K
16
Emulator Functions
Set-up
The DATA memory can store code and data from the user program. To simulate EPROM structures, a writeprotect definition can be made for this type of memory. The allocation of memory and the control of the data
bus (internal/external mapping) are two different functions. To replace a target memory by the emulator
memory, the MAP.Data as well as the MAP.Intern function must be activated.
map.data
0x0--0x0fffff
map.intern 0x0--0x0fffff
Parallel to the DATA memory, the BREAK or FLAG memory can be mapped in a similar way.
map.break 0x0--0x0fffff
map.flag 0x0--0x0fffff
It is only possible to map break or flag memory when using 32-bit CPUs. Usually the BREAK memory will
not be mapped by the user. It is allocated dynamically when setting breakpoints.
MAP.RESet
Reset Mapper
MAP.state
MAP.List
MAP.Ram
MAP.NoRam
MAP.Data
MAP.NoData
MAP.Flag
MAP.NoFlag
MAP.Protect
MAP.NoProtect
Attributes for memory protection and CPU specific settings like bus size can be set additionally:
map.protect 0x0--0x0fffff
map.bus8 0x0--0x0fffff
17
Emulator Functions
Function
DATA memory is used for program and data storage during the development phase. Usually it replaces the
EPROM on the target system. If no target system is available, the data and stack area must be supplied by
the emulator system.
DATA memory is assigned to the user program and data space by the command MAP.Data. When
assigning memory, emulation memory is accessed parallel to target memory. On write cycles both
memories are updated. The wait-state generation results from the logic on the target system. On read
cycles, both memories are accessed, the data stream used by the CPU is defined by the MAP.Intern or
MAP.Extern command.
CPU
Emulation
Target
Memory
Memory
CPU
Map
Intern
Map
Extreme
Emulation
Target
Memory
Memory
18
Emulator Functions
Dual-port Access
The TRACE32 FIRE development system features dual-ported emulation memory, accessible by both the
emulation CPU and the system control CPU. The emulation CPU always reads data from memory assigned
to it via the MAP.Intern or MAP.Extern command (internal or external memory). However, the dual-port
function allows access to emulation memory only. Memory access to external memory or to I/O areas must
always be handled via the emulation CPU.
Debug
Logic
Dual-port access
Emulation
CPU
Dual Port
Controller
Emulation
Memory
Intern/Extern
Mapping
Target
Access Procedures
Access procedures are selected by entering a memory class in the address field. For example, if the
command
D
D:0x1000
is used to display memory in the DATA address space, starting from address 1000, then the command
D
ED:0x1000
will be used to display the same address space, except that it will be accessed only directly via dual port
access, thus ensuring that memory contents are also visible during realtime emulation.
On emulation probes, which support CPUs with segmentation or MMU, access to memory can be made on
logical or physical level:
D
AD:0x0
D:0x0
; logical access
19
Emulator Functions
Memory Classes
The available memory access classes depend on the target processor. Following classes are available:
Code
Description
Program Space
Data Space
EP
ED
AD
Absolute Data
AP
Absolute Program
USR
EEPROM
20
Emulator Functions
Breakpoint System
Breakpoint Definition
A breakpoint is an event that happens when the CPU is accessing a specific address of code or data space.
The address event can be combined with CPU status lines (e.g. Read/Write, Data/Code ...). Breakpoints
that lead to a break of the user program can react synchronously or asynchronously.
Synchronous breakpoints: The break is executed before the instruction that is marked with the breakpoint
is performed. This happens if the CPU reads a break instruction instead of the instruction which is marked
with the breakpoint. For example program breakpoints.
Asynchronous breakpoints: The break is executed one or more instructions after the memory location
that is marked with the breakpoint is accessed. This happens if the trigger logic activates a break signal or
sends a break command to the CPU after it has noticed a bus access on the location with the breakpoint.
For example read breakpoints.
Breakpoint Selection
Up to 10 different logical breakpoint types in three different realization modes can be used.
Each logical breakpoint type can contain an unnumbered amount of single breakpoints, but depending on
the mode of realization, the software will make a limitation on the amount of breakpoints.
The selection, which breakpoint type is used with which realization mode, is done in the break.select menu.
Not every breakpoint realization is available with every CPU. For more information about breakpoint
realization refer to the emulation probe manual.
21
Emulator Functions
Breakpoint Types
This chapter describes the 10 different logical breakpoint types. These breakpoint types are available on
every CPU. The realization modes are not always available.
Refer to your emulation probe manual for an exact definition, which realization mode is possible with which
logical breakpoint.
Breakpoint Type
Description
Program
Hll
Spot
Spot breakpoints are temporary and used solely for saving the
register state. The program execution is then continued. Spot
breakpoints can be set in program space. For code areas,
breakpoints can be set at the beginning of an instruction only.
Read, Write
22
Emulator Functions
Realization Modes
This chapter describes the different realization modes. The realization modes are not available on every
CPU.
Refer to your emulation probe manual for an exact definition, which realization mode is possible with which
logical breakpoint
Software
Breakpoints
2.
On-chip
Breakpoints
Normally, modern CPUs have a debug logic on the CPU itself with own
breakpoint registers to perform breakpoints on different locations. These
breakpoints can include program and data breakpoints.
WARNING: Some CPU break logic perform also asynchronous (read/write)
breakpoints before the instruction is executed completely.
Hardware
Breakpoints
Auto
This is the default configuration for all logical breakpoint types. It is CPU specific
which of the 3 realization modes (Soft, Hard, Onchip) is chosen, by default, two
models can be separated:
23
Emulator Functions
1.
2.
Program
Hardware
Hll
Hardware
Stepmode
Spot
Hardware
Read, Write
Onchip
Hardware
The CPU speed is too high for the usage of synchronous hardware breakpoints
Breakpoint Type
Program
Software
Onchip (If the address is marked as ReadOnly or a range of
program breakpoints is used)
Hll
Software
Onchip (If the Address is marked as ReadOnly)
Stepmode
Spot
Software
Onchip (If the Address is marked as ReadOnly)
Read, Write
Onchip
Hardware
Breakpoint Example
Following application:
ROM
FFFFF
RAM
100000
1FFFFF
24
Emulator Functions
Code
Variables
1EFFFF
1F0000
1FFFFF
All breakpoint selections are default (auto), the CPU has no synchronous hardware breakpoints, the ROM
area is marked as read only (MAP.ReadOnly 0--0FFFFF)
Breakpoint settings:
Breakpoint Type
Address
Realization Mode
Program
500
OnChip
100100
Soft
Spot
100200
Soft
Read
1FFF00
OnChip
Alpha
10
Hardware
20
Hardware
30
Hardware
100
Hardware
100300
Hardware
Charly
100400
Hardware
Delta
100500
Hardware
Beta
Now, only the realization mode soft is left: Alpha - Delta breakpoints use the 4 available hardware
breakpoints, program and read breakpoint use the 2 available on-chip breakpoints. (The number of available
on-chip breakpoints is CPU specific). If an additional write breakpoint is set, the message <no such
hardware breakpoint available> shows that another realization mode has to become unused before.
25
Emulator Functions
Trigger System
Function
The trigger system is used for reacting to any event that occurs while the CPU is running in user program.
The trigger output controlls the analyzer and the emulation controller, but can also trigger different emulator
probes or external devices like oscilloscopes. When activated, the trigger runs all the time, entering up to 8
different states (trigger level) with different event outputs. The trigger input has a double multiplexer logic to
enlarge the amount of input events.
1. MUX
Input
Events
2. MUX
Trigger
Logic
Output Events
Recursive Events
26
Emulator Functions
Trigger Events
Input Events
Output Events
Recursive Events
Data Selector
Load Counter/Timer
Count Counter/Timer
Sample Analyzer
Activate Exception
Counter/Timer = 0
Level Switch
State Display
<Under Construction>
Set-up
<Under Construction>
27
Emulator Functions
Analyzer
Function
The Analyzer is a device to trace the activity of the target CPU. It consists of a real time trace and time stamp
unit with 64K trace depth.
The trace memory unit stores all specified lines in real-time. The speed is limited to 10ns per trace record. It
is possible to switch between bus mode with a trace record every bus cycle or clock mode with a trace
record every clock cycle.
All important processor signal lines, such as address, data and status lines, are connected to the trace
memory via the trace bus. The width depends on the processor type and the configuration. If required, the
trace can be extended on the emulation adapter, the default width on the FEC is 192 bits. The trace can only
be read and displayed when the analyzer is stopped. Real-time emulation can be continued, while the
analyzer is stopped.
The trace unit can be controlled by the trigger system.
The following signals are traced on the FEC
32
Bit
Addresses
64
Bit
Data
14
Bit
Status signals
Bit
48
Bit
Time Stamp
Bit
Trigger Level
Bit
Trace Marker
Bit
Bank Enable
Bit
Bit
Bit
Analyzer Control
Each record in the trace memory is marked with a time stamp, allowing the measurement of timing
relationships between recorded events. They are also used for detailed statistic and performance analysis
functions. The time stamp unit has a resolution of 20ns and a maximum of 64 days till overflow.
28
Emulator Functions
Modes
There are several modes how to use the analyzer:
Mode:
Description:
Fifo
FIFO operation mode, analyzer records the last cycles before recording
is stopped.
Stack
STACK operation mode, analyzer stops recording, when the trace buffer
is full.
Bus
BUS operation mode, analyzer traces one record every bus cycle.
Clock
CLOCK operation mode, analyzer traces one record every clock cycle.
Prestore
PreTrace
Slave (On/Off)
When active, the analyzer samples only cycles while the user program is
running. Background program and emulation monitor cycles are not
sampled.
Commands
There are several commands to set the analyzer:
Analyzer.Arm
Analyzer.Init
Clear the trace buffer and restart the trigger unit and it's counters.
Analyzer.OFF
Analyzer.RESet
Analyzer.SIZE
Analyzer.state
Analyzer.TEST
29
Emulator Functions
Arm the analyzer before starting the user program, switch off after stopping
Analyzer.AutoInit
Analyzer.AutoStart
Clear the trigger unit before starting, when it has reached the 'break' state
Analyzer.AutoTEST
Automatically arm the analyzer after all windows have been updated
Display Commands
The trace buffer can be displayed in tabular form, as mnemonics, with source code or in graphical form.
Analyzer.List
Analyzer.Timing
Analyzer.View
30
Emulator Functions
Analyzer.LOAD
Performance Analyzer
The real-time performance analyzer can display the percentage of time spent by a program in different
functions or modules of a program.
Analyzer Structure
The performance analyzer of the Trace32 FIRE is implemented as a software function of the FIRE
Controller. Therefore, the performance analysis functions check the value of the PC randomly, while the
target CPU is running. To get propper result, your software must run for some seconds - minutes. There are
two different methods implemented:
1.
2.
BusSnoop: The PC fetch of the target CPU is latched while the CPU is running. This fetch
address is used to count the corresponding address range counter. If the fetch was taken from an
address where no range is defined, one counter for all other addresses is incremented. The FIRE
Controller checks the fetches approximately every 100us.
-
Disadvantage: If the instruction cache of the CPU is enabled, it is not possible to latch the last
fetched address. This will cause wrong results.
PCSnoop: The target CPU is stopped, the actual PC is read out and the CPU is started again.
This PC address is used to count the corresponding address range counter. If the PC address is
an address where no range is defined, one counter for all other addresses is incremented. The
FIRE Controller stops the CPU for checking approximately every 10ms.
-
The measurement is made in intervals, after each the results in the display windows are refreshed. The
default interval is one second. All results can be displayed for the complete measurement, or for the last
interval (dynamic display). As the counters are stopped when the program stops, it is also possible to
interrupt the user program and restart it again.
The address ranges can be defined either by entering the function names or address ranges in a definition
window, or by an automatic programming system, which can be based on the symbol tables of the program
or in a fixed address raster (screening). The address range of this functions can be limited by
PERF.Address.
31
Emulator Functions
Commands
The following commands define the operation mode of the performance analyzer.
PERF.state
PERF.Mode
PERF.PreFetch
PERF.AnyAccess
PERF.Entry
PERF.Init
PERF.Address
PERF.Gate
PERF.Sort
PERF.METHOD
PERF.RESet
All functions of the performance analyzer can be controlled by the performance analyzer state window:
E::PERF.state
Mode
commands
OFF
Init
Program
RESet
LINE
Function
options
Modul
AnyAccess
LABEL
PreFetch
S10
Entry
S100
S1000
Gate
LeVel
1.000s
FLAGs
Sort
OFF
Address
sYmbol
Ratio
METHOD
Hardware
BusSnoop
PCSnoop
Address
SP:000000--FFFFFF
scans done
2.
curr.scan
77.828%
cov.time
67.854%
For most applications it is sufficient to select one the of predefined modes and display the results by an
performance list window. The Function mode will analyses the time spent in different functions. The
covered address range can be limited to one module by the PERF.Address command. The PERF.Sort will
determine the display of the results.
32
Emulator Functions
Display Results
The results can be displayed in different formats.
PERF.List
PERF.View
PERF.Sort
E::PERF.List
1
symbolname
(other)
func0
func1
func2
func3
func4
func5
func6
func7
func8
func9
func10
10
20
50
100
ratio
43.001%
0.000%
1.056%
4.357%
0.044%
0.968%
0.396%
1.584%
2.068%
9.991%
2.772%
20.158%
PERF.ReProgram
33
Emulator Functions
Flag System
Function
The flag system is an excellent tool for the analysis of complex software systems.
If the TRACE32 FIRE development system is used with a 8-, 16-, or 32-bit CPU, the upper 32 bit memory
can be used for the flag system. It can be activated separately from emulation memory and can be used for
marking read or write access to different RAM locations.
Flag memory can be mapped into the CPU's entire external bus address range. The memory can be used
as read-flag or as write-flag memory. The read-flag is set at memory read and OP-FETCH cycles (prefetch
too), whereas the write-flag is set for all write-to memory operations. After power-up, or execution of the
MAP.RESet command, no flag memory is mapped.
Flag
Memory
(32Bit High)
Overlay
Memory
(32Bit Low)
CPU
Target
Set-up
<Under Construction>
Applications
1.
Stack depth
2.
3.
4.
Restrictions
The flag system is not able to decide if the prefetch is executed or not. Therefore short skips are not detected
as not executed code and prefetches at function ends set some flag bits in the next function. Data flags are
not set correctly, if the CPUs cache function is activated (it should be disabled for data analysis).
34
Emulator Functions
refA
total execution time
refB
last
time of last program execution
actual
rt.res
; reset timer
r.s pc main
g func1
; run to func1
rt.refb
g func2
; run to func2
; single step
35
Emulator Functions
Total time, as well as the previous emulation command execution time, is automatically recorded. The
differences between the individual reference points are displayed in tabular form.
E68::w.rt
ref A
zero
+ 0.000
ref A
ref B
laststart
ref B
laststart
+ 48.700 s + 82.300 s
+ 48.700 s + 82.300 s
+ 33.600 s
actual
+ 87.600
+ 87.600
+ 38.900
+ 5.300
s
s
s
s
Set-Up
RunTime.Init
Reset timers
RunTime.RESet
Reset timers
RunTime.refA
RunTime.refB
RunTime.state
36
Emulator Functions
Exception Control
Function
Exception commands are used to control and stimulate special CPU lines like RESET or interrupt inputs.
This is especially useful during the development phase, allowing disabling of CPU input lines, or to simulate
certain events. All signals are enabled during real-time emulation only. The exception generator works only
while foreground emulation is running (i.e. the CPU must generate bus cycles). The exception system
cannot control interrupts generated by internal peripherals in microcontrollers.
Pulse
Generator
Pulse
Activate
Exception
Activation
Enable
Switch
CPU
Target
Set-up
eXception.Enable
eXception.Activate
eXception.Puls
eXception.Width
eXception.PERiod
eXception.Single
eXception.ON
eXception.OFF
eXception.RESet
For more detailed information on special probe functions refer to the emulation probe manual.
37
Emulator Functions
Frequency Generator
Function
The VCO may be used as a clock generator for the emulation CPU. The frequency range of the VCO is up to
150 MHz but is limited by the individual CPU adapter software. The frequency control is made on CPU input
pin frequency level. This can be different to the CPU clock.
The VCO has a grid of possible values. The VCO software uses a frequency that is as close to the
requested frequency as possible. The true value is displayed in the VCO window.
E68::w.vco
Freq
1 6 .0 0 0 .0 0 0 . Hz
control
RESet
Up
Down
Set-up
VCO.state
VCO.Clock
VCO.Up
Increment frequency
VCO.Down
Decrement frequency
VCO.RESet
38
Emulator Functions
Universal Counter
Function
The universal counter is the logic measurement system for sampling of pulses and frequencies. The input
multiplexer enables the counter to measure important CPU lines and external probe inputs. Together with
the trigger system, complex events can be counted.
Clock
Cycle
...
...
...
...
...
...
...
Input
multiplexer
Universal
counter
0 100 MHz
CPU clock:
0 100 MHz
VCO:
0 .. 100 MHz
Puls width:
Period:
Events:
2.8 * 10E+14
The input signal is selected with the function Count.Select. The function Count.Mode is used to change the
counter mode and the Count.Gate function defines the gate time. Frequency and event analyzing may be
qualified by the foreground running signal.
39
Emulator Functions
Level Display
If there is no signal (frequency is zero), the level of the input signal will be displayed (high or low level).
Display Window
Gate
7 .9 9 9 .9 2 0 . Hz
Value
Type
Clock
(*80)
Channel Resolution
Set-up
Count.state
Count.RESet
Count.Init
Initialize counter
Count.Mode
Count.Select
Count.Gate
Count.Enable
Count.Glitch
Count.PROfile
Display profile
40
Emulator Functions
Pulse Generator
Function
The pulse generator is an independent system for generating short pulses or static signals, and can be used
for stimulation of the target system. The output pin of the generator is placed on the output connector of the
FEC module. The triggering can be done periodically, manually from the keyboard or by the trigger unit of
the analyzer.
Rate
generator
0...200s
Pulse
generator
Polarity
switch
Puls output
Single
0..6.4ms
Trigger
Set-up
PULSE.RESet
PULSE.Width
PULSE.Pulse
PULSE.PERiod
Define period
PULSE.Single
PULSE.state
Display set-up
41
Emulator Functions
Getting Started
The sys-up procedure for a specific probe is described in the quick start of the FIRE Target Guides.
42
Getting Started
Index (local)
Absolute:Address ...........................................................................................................................................FIRE User's Guide
19
19
14
12
22
19
33
19
27
22
31
12
26
22
22
22
22
22
22
21
22
22
22
22
26
22
20
10
32
37
39
40
40
40
27
17
33
27
40
40
36
33
36
27
19
12
37
43
Index (local)
12
37
37
36
35
11
34
38
10
12
37
38
10
10
41
12
12
40
22
10
40
17
26
16
17
17
17
17
40
35
15
17
21
20
17
18
18
18
19
40
14
33
31
32
33
31
19
41
44
Index (local)
12
22
37
10
41
41
41
41
11
41
34
22
34
18
12
36
35
40
27
22
17
26
31
14
18
35
26
27
26
26
27
27
27
37
34
27
26
26
26
38
10
17
12
41
22
34
18
45
Index (local)