module cic3r32 //----> Interface

(input clk, reset,

input signed [7:0] x_in,
output signed [9:0] y_out,
output reg clk2);
parameter hold=0, sample=1;
reg [1:0] state;
reg [4:0] count;
reg signed [7:0] x; // Registered input
reg signed [25:0] i0, i1 , i2; // I section 0, 1, and 2
reg signed [25:0] i2d1, i2d2, c1, c0; // I + COMB 0
reg signed [25:0] c1d1, c1d2, c2; // COMB section 1
reg signed [25:0] c2d1, c2d2, c3; // COMB section 2
always @(posedge clk or posedge reset)
begin : FSM
if (reset) begin // Asynchronous reset
count <= 0;
state <= hold;
clk2 <= 0;
end else begin
if (count == 31) begin
count <= 0;
state <= sample;
clk2 <= 1;
end else begin
count <= count + 1;
state <= hold;
clk2 <= 0;
end
end
end
always @(posedge clk) // 3 integrator sections
begin : Int
x <= x_in;

i0 <= i0 + x;
i1 <= i1 + i0 ;
i2 <= i2 + i1 ;
end
always @(posedge clk) // 3 comb sections
begin : Comb
if (state == sample) begin
c0 <= i2;
i2d1 <= c0;
i2d2 <= i2d1;
c1 <= c0 - i2d2;
c1d1 <= c1;
c1d2 <= c1d1;
c2 <= c1 - c1d2;
c2d1 <= c2;
c2d2 <= c2d1;
c3 <= c2 - c2d2;
end
end
assign y_out = c3[25:16];
endmodule

2.
module cic3s32 //----> Interface
(input clk, reset,
output reg clk2,
input signed [7:0] x_in,
output signed [9:0] y_out);
parameter hold=0, sample=1;
reg [1:0] state;
reg [4:0] count;
reg signed [7:0] x; // Registered input

reg signed [25:0] i0; // I section 0

reg signed [20:0] i1; // I section 1
reg signed [15:0] i2; // I section 2
reg signed [13:0] i2d1, i2d2, c1, c0; //
I+C0
reg signed [12:0] c1d1, c1d2, c2; //
COMB 1
reg signed [11:0] c2d1, c2d2, c3; //
COMB 2

always @(posedge clk or posedge

reset)
begin : FSM
if (reset) begin // Asynchronous reset
count <= 0;
state <= hold;
clk2 <= 0;
end else begin
if (count == 31) begin
count <= 0;
state <= sample;
clk2 <= 1;
end
else begin
count <= count + 1;
state <= hold;
clk2 <= 0;
end
end
end
always @(posedge clk) // 3 integrator
sections
begin : Int
x <= x_in;
i0 <= i0 + x;
i1 <= i1 + i0[25:5];
i2 <= i2 + i1[20:5];

end
always @(posedge clk) // 3 comb
sections
begin : Comb
if (state == sample) begin
c0 <= i2[15:2];
i2d1 <= c0;
i2d2 <= i2d1;
c1 <= c0 - i2d2;
c1d1 <= c1[13:1];
c1d2 <= c1d1;
c2 <= c1[13:1] - c1d2;
c2d1 <= c2[12:1];
c2d2 <= c2d1;
c3 <= c2[12:1] - c2d2;
end
end
assign y_out = c3[11:2];
endmodule

3. VHDL:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY cic3r32 IS
PORT ( clk, reset : IN STD_LOGIC;
x_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clk2 : OUT STD_LOGIC;
y_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
END cic3r32;
ARCHITECTURE fpga OF cic3r32 IS
SUBTYPE word26 IS STD_LOGIC_VECTOR(25 DOWNTO 0);
TYPE STATE_TYPE IS (hold, sample);
SIGNAL state : STATE_TYPE ;
SIGNAL count : INTEGER RANGE 0 TO 31;
SIGNAL x : STD_LOGIC_VECTOR(7 DOWNTO 0) :=
(OTHERS => 0); -- Registered input
SIGNAL sxtx : STD_LOGIC_VECTOR(25 DOWNTO 0);
-- Sign extended input
SIGNAL i0, i1 , i2 : word26 := (OTHERS=>0);
-- I section 0, 1, and 2
SIGNAL i2d1, i2d2, c1, c0 : word26 := (OTHERS=>0);
-- I and COMB section 0
SIGNAL c1d1, c1d2, c2 : word26 := (OTHERS=>0);-- COMB1
SIGNAL c2d1, c2d2, c3 : word26 := (OTHERS=>0);-- COMB2
BEGIN
FSM: PROCESS (reset, clk)
BEGIN
IF reset = 1 THEN -- Asynchronous reset
state <= hold;
count <= 0;
clk2 <= 0;
ELSIF rising_edge(clk) THEN
IF count = 31 THEN
count <= 0;

state <= sample;

clk2 <= 1;
ELSE
count <= count + 1;
state <= hold;
clk2 <= 0;
END IF;
END IF;
END PROCESS FSM;
sxt: PROCESS (x)
BEGIN
sxtx(7 DOWNTO 0) <= x;
FOR k IN 25 DOWNTO 8 LOOP
sxtx(k) <= x(xhigh);
END LOOP;
END PROCESS sxt;
Int: PROCESS -- 3 integrator sections
BEGIN
WAIT UNTIL clk = 1;
x <= x_in;
i0 <= i0 + sxtx;
i1 <= i1 + i0 ;
i2 <= i2 + i1 ;
END PROCESS Int;
Comb: PROCESS -- 3 comb sections
BEGIN
WAIT UNTIL clk = 1;
IF state = sample THEN
c0 <= i2;
i2d1 <= c0;
i2d2 <= i2d1;
c1 <= c0 - i2d2;
c1d1 <= c1;
c1d2 <= c1d1;
c2 <= c1 - c1d2;
c2d1 <= c2;
c2d2 <= c2d1;

c3 <= c2 - c2d2;
END IF;
END PROCESS Comb;
y_out <= c3(25 DOWNTO 16); -- i.e., c3 / 2**16
END fpga;