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Current mirrors are important blocks in electronics. They are widely used in
several applications and chips, the operational amplifier being one of them.
Current mirrors consist of two branches that are parallel to each other and
create two approximately equal currents. This is why these circuits are called
current mirrors. These currents are used to load other stages in circuits and
they are designed in such a way so that current is constant and independent
of loading.
Current mirrors come in different varieties:
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Vo
3.600V
1.472mA
R1
VCC
IREF
Vo
Io
2k
3.600V
V1
3.6Vdc
Q1
Q2
1.425mA
23.47uA
23.47uA 655.3mV
Q2N3642
650.0mV
V2
1.425mA
I
Q2N3642
-1.449mA
-1.449mA
0.65Vdc
1.425mA
0V
1.472mA
0V
0V
1.0mA
0.5mA
0A
-0.5mA
0V
IC(Q2)
50mV
-I(R1)
100mV
150mV
200mV
250mV
300mV
350mV
400mV
450mV
500mV
V_V2
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VCC VBE1
I REF
VA
From KCL analysis at the collector of Q1, the reference current is defined as
I REF I C 2 I B I C 2
I C 1
o
o
IC
VVBE
V
I o I C I S e T 11 CE
VA
When VCB=0V the Early effect is eliminated and it does not affect the
equation. As the value of VCB increases, values for both transistors no
longer match and the output current is no longer flat but its tilted with a slope
of 1/ro.
The output resistance is
R0 r0
V A VCE
Io
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MOSFET
The MOSFET implementation of the simple current mirror is as follows:
VDD
Vo
3.600V
537.8uA
R1
IREF
VDD
Vo
Io
2k
3.600V
V1
3.6Vdc
2.524V
M2
537.8uA
M1
0A
M2N6760
2.500V
V2
537.8uA
0A
M2N6760
2.5Vdc
537.8uA
0V
537.8uA
0V
0V
400uA
200uA
0A
0V
-I(R1)
0.4V
ID(M2)
0.8V
1.2V
1.6V
2.0V
2.4V
2.8V
3.2V
3.6V
V_V2
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V DD VGS 1
I REF
Both transistors work in the active/saturation region and their drain current is
given by
I D K n VGS VTN 1 V DS VGS VTN
2
Since no current enters the gates, reference and output currents match.
When VDS-VGS+VTN=0V the channel-length modulation is eliminated and it
does not have affect the equation. If the value of VDS-VGS+VTN0V, the output
current is no longer flat but its tilted with a slope of 1/ro.
Currents are related by the following expression:
Io
I REF
W2 / L2
W1 / L1
1 V DS 2
1 V DS1
The above relationship says that current in the two branches of the current
mirror depends on the aspect ratio of the two transistors.
The output resistance is
R0 r0
1
I o
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Vo
3.600V
1.194mA
VCC
R1
3.600V
IREF
VCC
2k
Q3
1.211V
913.6nA
Q1
1.193mA
Q2N3642
Vo
Io
3.600V
38.73uA
V1
Q2N3642
-39.64uA
650.5mV
19.82uA
1.200V
V2
3.6Vdc
Q2
19.82uA
-1.213mA
1.193mA
1.2Vdc
1.193mA
0V
1.233mA
0V
Q2N3642
-1.213mA
0V
0.8mA
0.4mA
0A
-0.4mA
0V
-I(R1)
50mV
IC(Q2)
100mV
150mV
200mV
250mV
300mV
350mV
400mV
450mV
500mV
V_V2
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VA
From KCL analysis at the collector of Q1, the reference current is defined as
I REF I C1 I B 3 I C
2I C
V V BE 3 V BE1
CC
1
R
VA
R0 r0
V A VCE
Io
Note: the MOSFET implementation of this circuit does not exist since current
does not enter the gate of a MOSFET.
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Vo
3.600V
1.019mA
R1
VCC
IREF
Vo
Io
2.9k
3.600V
700.0mV
V1
V2
3.6Vdc
Q1
Q2
992.6uA
Q2N3642
9.188uA
16.88uA 645.9mV
-1.010mA
R2
506.7uA
0.7Vdc
506.7uA
0V
1.019mA
0V
Q2N3642
515.9uA
-515.9uA
17.54mV
34
0V
0.8mA
0.4mA
0A
-0.4mA
0V
-I(R1)
50mV
IC(Q2)
100mV
150mV
200mV
250mV
300mV
350mV
400mV
450mV
500mV
V_V2
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R1
VCC V BE1
I REF
and
I
VBE 2 VT ln o
IS
I
I
VT ln o VT ln REF
IS
Io
so that
I
VBE1 V BE 2 I o R2 VT ln REF
Io
VT I REF
ln
I o I o
Note that if the condition IREF=Io is forced, the argument of the logarithm is 1
which produces 0 and therefore a 0 resistance (simple current mirror
configuration). This is why reference and output currents do not match.
The output resistance is higher than the one for the simple current mirror:
Ro ro 1 g m R2 || r
Note: the MOSFET implementation of the Widlar current source is not used
and if it were, it would behave similarly to the simple current mirrors.
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VCC
Vo
3.600V
2.266mA
R1
IREF
Io
VCC
1k
Q3
35.55uA
1.334V
3.600V
Q2
666.9mV
35.07uA
35.07uA
-2.265mA
V2
3.6Vdc
666.9mV
2.230mA
1.400V
V1
Q2N3642
-2.281mA
Q1
Q2N3642
2.245mA
Vo
1.4Vdc
2.245mA
0V
2.266mA
0V
2.210mA
Q2N3642
-2.246mA
0V
0V
2.0mA
0A
-2.0mA
-4.0mA
0V
-I(R1)
0.2V
IC(Q3)
0.4V
0.6V
0.8V
1.0V
1.2V
1.4V
1.6V
1.8V
2.0V
V_V2
10
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ro 3
2
VCC
Vo
3.600V
2.265mA
R1
I
1k
IREF
Io
1.335V
Q4
2.195mA
Q2N3642
667.9mV
34.84uA
Q3
35.83uA
-2.230mA
Q2
-2.265mA
1.400V
V1
Q1
667.1mV
35.35uA
35.35uA
Vo
3.600V
Q2N3642
-2.300mA
2.230mA
Q2N3642
VCC
2.264mA
V2
3.6Vdc
667.1mV
2.230mA
1.4Vdc
2.264mA
0V
2.265mA
0V
Q2N3642
-2.265mA
0V
0V
2.0mA
0A
-2.0mA
-4.0mA
0V
-I(R1)
0.2V
IC(Q3)
0.4V
0.6V
0.8V
1.0V
1.2V
1.4V
1.6V
1.8V
2.0V
V_V2
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MOSFET
The MOSFET implementation of the Wilson current mirror looks like the
following:
Ro
VDD
Vo
3.600V
319.5uA
R1
IREF
Io
VDD
2k
2.961V
M3
318.8uA
0A
3.600V
V1
IRF830
M1
319.5uA
M2
0A
0A
IRF830
IRF830
2.700V
V2
3.6Vdc
1.480V
1.480V
Vo
2.7Vdc
318.8uA
0V
319.5uA
0V
318.8uA
0V
0V
300uA
200uA
100uA
0A
0V
-I(R1)
0.4V
ID(M3)
0.8V
1.2V
1.6V
2.0V
2.4V
2.8V
3.2V
3.6V
V_V2
12
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W2 / L2
W1 / L1
1 V DS 2
1 V DS1
VDD
Vo
3.600V
319.0uA
R1
I
IREF
Io
2k
VDD
2.962V
M4
319.0uA
M3
319.0uA
0A
0A
IRF830
IRF830
1.481V
M1
319.0uA
0A
IRF830
3.600V
V1
M2
V2
2.7Vdc
319.0uA
0V
319.0uA
0V
319.0uA
0A
IRF830
2.700V
3.6Vdc
1.481V
1.481V
Vo
0V
0V
300uA
200uA
100uA
0A
0V
-I(R1)
0.4V
ID(M3)
0.8V
1.2V
1.6V
2.0V
2.4V
2.8V
3.2V
3.6V
V_V2
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VCC
Vo
3.600V
2.267mA
R1
I
1k
IREF
Io
1.333V
Q4
2.198mA
Q2N3642
Q3
2.131mA
33.87uA
VCC
3.600V
Q2N3642
-2.164mA
-2.233mA
Q2N3642
Q1
2.164mA
Q2
666.3mV
34.40uA
34.40uA
-2.199mA
1.400V
V1
667.2mV
666.3mV
Vo
34.89uA
V2
3.6Vdc
2.164mA
1.4Vdc
2.131mA
0V
2.267mA
0V
Q2N3642
-2.199mA
0V
0V
2.0mA
0A
-2.0mA
-4.0mA
0V
-I(R1)
0.2V
IC(Q3)
0.4V
0.6V
0.8V
1.0V
1.2V
1.4V
1.6V
1.8V
2.0V
V_V2
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Note: VBE4 and VBE3 cancel each other so the base and collector voltages of
Q2 are the same.
The collector resistor is given by
R
15
ro 3
2
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MOSFET
The MOSFET implementation of the cascoded current mirror is as follows:
Ro
VDD
Vo
3.600V
231.1uA
R1
I
1k
IREF
Io
3.369V
M4
231.1uA
M3
0A
230.9uA
IRFJ132
VDD
3.600V
IRFJ132
1.685V
V1
1.609V
M1
231.1uA
0A
M2
1.685V
IRFJ132
2.700V
V2
3.6Vdc
230.9uA
2.7Vdc
230.9uA
0V
231.1uA
0V
0A
IRFJ132
Vo
0A
0V
0V
200uA
100uA
0A
0V
-I(R1)
0.4V
ID(M3)
0.8V
1.2V
1.6V
2.0V
2.4V
2.8V
3.2V
3.6V
V_V2
16
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V DD VGS 4 VGS 1
I REF
W 2 / L2
W1 / L1
Note: the channel-length modulation factor is not present here since for this
circuit there is no Early effect.
The output resistance is very high and its given by
Ro ro 2 ro 3 1 g m 3 ro 2
17
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