SELECTIVE HARMONIC ELIMINATION OF

SINGLE PHASE AND THREE PHASE 11 LEVEL

CASCADED INVERTER
WITH MINIMUM TOTAL HARMONIC DISTORTION
AND UNIFORM DISCHARGE OF BATTERIES

A thesis submitted in partial fulfillment of the requirements for

the award of the degree of

M.Tech. (Phase 1)
in
Power Systems

By

SHEFEEN M

DEPARTMENT OF ELECTRICAL AND ELECTRONICS

ENGINEERING
NATIONAL INSTITUTE OF TECHNOLOGY
TIRUCHIRAPPALLI - 620015
DECEMBER 2014

BONAFIDE CERTIFICATE
This is to certify that the project titled SELECTIVE HARMONIC ELIMINATION
OF SINGLE PHASE AND THREE PHASE 11 LEVEL CASCADED INVERTER
WITH MINIMUM TOTAL HARMONIC DISTORTION AND UNIFORM
DISCHARGE OF BATTERIES is a bonafide record of the work done by

SHEFEEN M (207113025)

in partial fulfillment of the requirements for the award of the degree of Master of
Technology

in

Power

Systems

of

the

NATIONAL

INSTITUTE

OF

TECHNOLOGY, TIRUCHIRAPPALLI, during the year 2014-2015.

Dr. M.P. SELVAN

Guide

Head of the Department

Project Viva-voce held on _____________________________

Internal Examiner

External Examiner

ABSTRACT

A new method is proposed for selective harmonic elimination of 11 level cascaded inverter.
Cascaded multilevel inverter needs separate DC sources, hence it is well suited for
renewable sources like fuel cells and solar photovoltaics. It consists of a series of H-Bridges
to produce desired voltage levels. By selecting appropriate switching angles desired
harmonics can be eliminated. The switching angles are found by solving simultaneous nonlinear equations. For simultaneous non-linear equations where there exists multiple roots,
conventionally used Newton Raphson method gives only one solution(root).Hence, the
switching angles obtained as solution for selective harmonic elimination may not
correspond to minimum total harmonic distortion, since there may exist another solution
for which total harmonic distortion is less than previously found. By adopting modified
Newton Raphson method multiple solutions for simultaneous nonlinear equations can be
obtained and the solution corresponding to least total harmonic distortion for each
modulation index can be selected. Modulation index is the ratio of peak fundamental phase
voltage to its maximum-value. Here 5th, 7th, 11th and 13th harmonics of 11 level cascaded
inverter are eliminated using modified Newton Raphson Method. A graph between
minimum possible total harmonic distortion and modulation index is plotted. The lowest
point on the curve gives the modulation index at which total harmonic distortion is the least
and corresponding switching angles are selected. Moreover, in conventional multilevel
inverter, batteries discharge at a different rate since the duty cycle for each voltage level
(H-Bridge) is different. Uniform discharge of batteries for 11 level inverter is achieved in
this work by swapping gate pulses for H-bridges. There are five batteries and period of

each gate signal is 10ms. By swapping the gate signals the state of charge remains same
for all five batteries by the end of every 50ms. Finally, results obtained from simulation
carried out in MATLAB/SIMULINK for 11 level cascaded inverter (both single phase and
three phase) are included to validate the proposed theory.

ii

ACKNOWLEDGMENT

I express my profound gratitude to my project guide, Dr. M.P. SELVAN, Assistant

professor, Department of Electrical and Electronics engineering for his guidance and
Encouragement throughout the tenure of the project.
I am grateful to Dr. N. KUMARESAN, Associate professor and Head, Department
of Electrical and electronics engineering for his kind support and encouragement for my
project work.
I extend my gratitude to Mr. B. DASTAGIRI REDDY, Research scholar,
Department of Electrical and Electronics engineering for his support and aid for this
project.
Finally, I wish to thank other staff members and my friends for their help and
encouragement during execution of this project work.

SHEFEEN M

iii

TABLE OF CONTENTS

Title

Page No

ABSTRACT

ACKNOWLEDGEMENT

iii

TABLE OF CONTENTS

iv

LIST OF FIGURES

vi

LIST OF ABBREVIATIONS

viii

CHAPTER 1

INTRODUCTION

1.1

Harmonics in Electrical Systems. .1

1.2

Multilevel Inverter.2

1.3

Objective........................................................3

1.4

Thesis outline.....3

CHAPTER 2
MULTILEVEL VOLTAGE SOURCE INVERTER USING
a
CASCADED-INVERTERS WITH SEPARATED DC SOURCES
2.1

2.2

2.3

Full bridge or H-Bridge Voltage Source Inverter. ..4

2.1.1

Introduction4

2.1.2

Gate signal and Inverter operation.....4

2.1.3

Blanking time.....5

Cascaded Inverter Configuration....6

2.2.1

Single Phase Structure....6

2.2.2

Three Phase Structure.....8

2.2.3

Separated DC Sources (SDCSs)11

Summary................................13

iv

CHAPTER 3
s

SELECTIVE HARMONIC ELIMINATION (IN MULTILEVEL)

CASCADED INVERTER

3.1

Introduction.....15

3.2

Selective Harmonic Elimination Pulse Width Modulation.....16

3.2.1

Fourier series..16

3.2.2

Modified Newton Raphson Method...17

3.2.2.1 Flow chart for Modified Newton Raphson
Method.....19

a
3.2.3

Total harmonic Distortion vs. Modulation Index..20

3.2.4

Voltage and Current waveform of single phase and

three phase 11 level inverter......22

3.2.5

Simulink Model of 11 level single phase cascaded

Inverter..24

3.2.6

Simulink Model of 11 level single phase cascaded

Inverter..26

3.2.7

Minimum and maximum modulation index for

single phase 11 level cascaded inverter..27

a
a
a
a
3. 3

Summary...27

CHAPTER 4

CHARGE BALANCE CONTROL

4.1

Introduction.....28

4.2

Charge balance using swapping algorithm .....30

4.3

Summary 32

CHAPTER 5
7.1

CONCLUSION
Conclusions.33

REFERENCES

34

LIST OF FIGURES
Fig. No.

Title

Page No.

2.1

H-bridge cell .

2.2

Apply blanking time to the gate signal .

2.3

Single-phase configuration of an m-level cascaded inverter.. 7

2.4
a

Waveform showing a nine-level output phase voltage and each

H-bridge output voltage. 8

2.5
a

Three-phase seven-level inverter using cascaded-inverters with

SDCSs 9

2.6
a

Phase and line voltages of three-phase seven-level

cascaded inverter 11

2.7

Two possible dc source connection. 12

2.8

Short circuit possibility in the topology shown in fig. 2.7.. 13

3.1

Flow Chart for Modified Newton Raphson Method 19

3.2

Total harmonic Distortion vs. Modulation Index. 20

3.3

Total harmonic Distortion vs. Modulation Index 20

3.4

Total harmonic Distortion vs. Modulation Index 21

3.5

Total harmonic Distortion vs. Modulation Index 21

3.6

Voltage waveform of single phase 11 level cascaded inverter 22

3.7

Current waveform of single phase 11 level cascaded inverter 23

3.8

Voltage waveform (line to line (RB)) of 3-phase 11-level

inverter (RYB sequence) 23

3.9

Current waveform of three phase 11 level cascaded inverter 24

3.10

Simulink model of gating signal of single phase 11 level cascaded

inverter. 24
vi

3.11

Simulink model of single phase 11 level cascaded inverter

25

3.12

Simulink model of three phase 11 level cascaded inverter.

26

3.13

Simulink model of gating signal of three phase 11 level cascaded

inverter.

4.1

Single-phase structure of a cascade inverter with SDCSs 28

4.2

Typical voltage waveform of 11 level cascaded inverter... 29

4.3

Switching pattern swapping of the 11 level cascade inverter

for balancing battery charge . 30

4.4

State of Charge vs. time with battery balancing control .. 31

4.5

State of Charge vs. time without battery balancing control

4.6

State of Charge vs. time with battery balancing control

(zoomed view).... 32

vii

26

31

LIST OF ABBREVIATIONS

EMI

Electromagnetic Interference

THD

Total Harmonics Distortion

CM

Common Mode

SDCSs

Separated Direct Current Sources

SHE

Selective Harmonic Elimination

SHEPWM

: Selective Harmonic Elimination Pulse Width Modulation

SOC

State of Charge

viii

CHAPTER 1
INTRODUCTION

1.1 HARMONICS IN ELECTRICAL SYSTEMS

One of the biggest problems in power quality aspects is the harmonic contents in the
electrical system. Generally, harmonics may be divided into two types: 1) voltage
harmonics, and 2) current harmonics. Both harmonics can be generated at either the source
or the load side. Harmonics generated by load are caused by nonlinear operation of devices,
including power converters, arc-furnaces, gas discharge lighting devices, etc. Load
harmonics can cause the overheating of the magnetic core of transformers and motors. On
the other hand, source harmonics are mainly generated by power supply with nonsinusoidal voltage waveform. Voltage and current harmonics imply power losses,
Electromagnetic Interference (EMI) and pulsating torque in AC motor drives. Any periodic
waveform can be shown to be the superposition of a fundamental and a set of harmonic
components. By applying Fourier transformation, these components can be extracted. The
frequency of each harmonic component is an integral multiple of its fundamental. There
are several methods to indicate the quantity of harmonic contents. The most widely used
measure is the Total Harmonics Distortion (THD), which is defined in terms of the
amplitude of the harmonics, Hn, at frequency n0, where 0 is frequency of the
fundamental component whose amplitude is H1 and n is an integer. The THD is
mathematically given by

THD =

=2

(1.1)

1.2 MULTILEVEL INVERTER

Demand for high-voltage, high power converters capable of producing high-quality
waveforms while utilizing low voltage devices and reduced switching frequencies have led
to the multilevel inverter development with regard to semiconductor power switch voltage
limits. Multilevel inverters include an array of power semiconductors and capacitor voltage
sources, the output of which generate voltages with stepped waveforms. The commutation
of the switches permits the addition of the capacitor voltages, which reach high voltage at
the output, while the power semiconductors must withstand only reduced voltages. The
most attractive features of multilevel inverters are as follows:1)

They can generate output voltages with extremely low distortion and lower dv/dt.

2)

They draw input current with very low distortion.

3)

They generate smaller common mode (CM) voltage, thus reducing the stress in the

motor bearings. In addition, using sophisticated modulation methods, CM voltages can

be eliminated.
4)

They can operate with a lower switching frequency.

The multilevel inverter has been implemented in various applications ranging from
medium to high-power levels, such as motor drives, power conditioning devices, also
conventional or renewable energy generation and distribution. The different multilevel
inverter structures are cascaded H-bridge, diode clamped and flying capacitor multilevel
inverter. Among the three topologies, the cascaded multilevel inverter has the potential to
be the most reliable and achieve the best fault tolerance owing to its modularity, a feature
that enables the inverter to continue operating at lower power levels after cell failure.
Modularity also permits the cascaded multilevel inverter to be stacked easily for high
power and high-voltage applications. The cascaded multilevel inverter typically comprises
several identical single phase H-bridge cells cascaded in series at its output side. This
configuration is commonly referred to as a cascaded H-bridge, which can be classified as
symmetrical if the dc bus voltages are equal in all the series power cells, or as asymmetrical
if otherwise.
2

1.3 OBJECTIVE
To find set of all switching angles to eliminate desired harmonics and to select switching
angles corresponding to minimum Total Harmonic Distortion (T.H.D.) for an 11 level
cascaded inverter.
To plot graph between minimum possible T.H.D. and modulation index.
To achieve uniform discharge of batteries.

1.4 THESIS OUTLINE

This thesis consists of this introductory chapter and four other chapters arranged as below:
Chapter 2 presents the basics about multilevel cascaded inverter
Chapter 3 describes selective harmonic elimination using Modified Newton Raphson
method
Chapter 4 describes the methodology used for uniform discharge of batteries
Chapter 5 concludes the thesis.

CHAPTER 2
MULTILEVEL VOLTAGE SOURCE INVERTER USING
CASCADED-INVERTERS WITH SEPARATED DC SOURCES

The structure and switching pattern of the multilevel inverter using cascaded-inverters with
separated dc sources will be introduced in this chapter.
2.1 FULL-BRIDGE or H-BRIDGE VOLTAGE SOURCE INVERTER
2.1.1 INTRODUCTION
The smallest number of voltage levels for a multilevel inverter using cascaded inverter with
SDCSs is three. To achieve a three-level waveform, a single full-bridge inverter is
employed. Basically, a full-bridge inverter is known as an H-bridge cell, which is
illustrated in Fig. 2.1. The inverter circuit consists of four main switches and four
freewheeling diodes.
Is

S1

S2
Io

Vs

Load

S3

S4

Fig. 2.1 H-bridge cell.

2.1.2 GATE SIGNAL AND INVERTER OPERATION
According to four-switch combination, three output voltage levels, +V, -V, and 0, can be
synthesized for the voltage across A and B. During inverter operation shown in Fig. 2.1,
switches S1 and S4 are closed at the same time to provide VAB a positive value and a current
path for Io. Switches S2 and S3 are turned on to provide VAB a negative value with a path for
4

Io. Depending on the load current angle, the current may flow through the main switch or
the freewheeling diodes. When all switches are turned off, the current will flow through
the freewheeling diodes.
In case of zero level, there are two possible switching patterns to synthesize zero level, for
example, 1) S1 and S2 on, S3 and S4 off, and 2) S1 and S2 off and S3 and S4 on. Here zero
level is generated by turning off S1 and S2 and turning on S3 and S4.
2.1.3 BLANKING TIME
Another issue that has to be concerned is providing blanking time for gate signal. In section
2.1.2, the switches were assumed to be ideal, which allowed the state of the two switches
in an inverter leg to change simultaneously from on to off and vice versa. In practice,
switching devices are not ideal. To completely turn-off the devices, a short period, which
depends on the type of the device, is needed. Usually, because of the finite turn-off and
turn-on times associated with any types of switch, a switch is turned off at the switching
time instant. However, the turn-on of the other switching in that inverter leg is delayed by
a blanking time, t, which is conservatively chosen to avoid cross conduction current
through the leg. The blanking time concept is illustrated in Fig 2.2 by selecting the leg of

Voltage (V)

S1 and S3 as an example.

Time

Fig. 2.2 Apply blanking time to the gate signal.

2.2 CASCADED INVERTER CONFIGURATION

2.2.1 SINGLE-PHASE STRUCTURE
To synthesize a multilevel waveform, the ac output of each of the different level H-bridge
cells is connected in series. The synthesized voltage waveform is, therefore, the sum of the
inverter outputs. The number of output phase voltage levels in a cascaded inverter is
defined by
m =2s +1

(2.1)

where s is the number of dc sources.

For example, a nine-level output phase voltage waveform can be obtained with fourseparated dc sources and four H-bridge cells. Fig 2.3 shows a general single-phase m- level
cascaded inverter.
From Fig. 2.3, the phase voltage is the sum of each H-bridge output and is given as
VAN =Vdc1 +Vdc2 + ...+Vdc(S-1) +VdcS

(2.2)

Because zero voltage is common for all inverter outputs, the total level of output voltage
waveform becomes 2s+1. An example phase voltage waveform for a nine-level cascaded
inverter and all H-bridge cell output waveforms are shown in Fig. 2.4. In this thesis, all dc
voltage are assumed to be equal, i.e., Vdc1 =Vdc2 =...=Vdc(S-1) =VdcS =Vdc.
According to sinusoidal-liked waveform, each H-bridge output waveform must be quartersymmetric as illustrated by V1 waveform in Fig. 2.4. Obviously, no even harmonic
components are available in such a waveform. To minimize THD, all switching angles will
be numerically calculated, which will be proposed in chapter 3.

Fig. 2.3 Single-phase configuration of an m-level cascaded inverter.

Voltage (V)

Angle (Radian)

Fig. 2.4 Waveform showing a nine-level output phase voltage and each H-bridge output
voltage.
2.2.2 THREE-PHASE STRUCTURE
For a three-phase system, the output of three identical structure of single-phase cascaded
inverter can be connected in either wye or delta configuration. Fig 2.5 illustrates the
schematic diagram of wye-connected seven-level inverter using three H-bridge cells and
three SDCSs per phase, which will be used to verify the concept of the optimized harmonic
stepped-waveform technique in chapter 3.

Fig. 2.5 Three-phase seven-level inverter using cascaded-inverters with SDCSs.

From Fig 2.5, VAN is voltage of phase A, which is the sum of Va1, Va2, and Va3. The same
idea is applied to phase B and phase C. To synthesize seven-level phase voltage, three
firing angles are required. The same three switching angles can be used in all three phases
with delaying 0, 120, and 240 electrical degree for phase A, B, and C, respectively.
According to three-phase theory, line voltage can be expressed in term of two phase
voltages. For example, the potential between phase A and B is so-called VAB, which can
be written as follows:
VAB =VAN VBN

(2.3)

where VAB is line voltage

VAN is voltage of phase A with respect to point N and VBN is voltage of phase B with respect
to point N
Theoretically, the maximum number of line voltage levels is 2m-1, where m is the number
of phase voltage levels. The seven-level cascaded inverter, for example, can synthesize up
to thirteen-level line voltage.

The advantage of three-phase system is that all triplen harmonic components in the line
voltage will be eliminated by one-third cycle phase shift feature. Therefore, only nontriplen harmonic components need to be eliminated from phase voltage. In single phase
nine-level waveform, for example, the 3rd, 5th, and 7th harmonics will be eliminated from
output phase voltage. Compared to single-phase inverter, in three-phase nine-level inverter,
the 5th, 7th, and 11th harmonics will be eliminated from output phase voltage. Thus, the 9th
harmonic is the lowest harmonic component in phase voltage in single phase system, while
the 13th harmonic is the lowest harmonic component appearing in line voltage of threephase system.
Fig 2.6 shows output voltage of phase A, VAN, and output voltage of phase B, VBN, line
voltage waveform, VAB of seven-level cascaded inverter shown in Fig 2.5.

10

Voltage (V)

Angle (Radian)

Fig. 2.6 Phase and line voltages of three-phase seven-level cascaded inverter

11

From Fig. 2.6, assuming the positive sequence three-phase system, output voltage of phase
B lags output voltage of phase A by 120 electrical degree. The line voltage, VAB, therefore,
leads voltage of phase A by 30 electrical degree, which is according to the three-phase
theory.
2.2.3 SEPERATED DC SOURCES (SDCSs)
To avoid short circuit of dc sources, the separated dc source configuration is applied to the
multilevel inverter using cascaded-inverter. This section will discuss about why cascaded
inverter has to employ separated dc sources (SDCSs). To explain this, two possible dc
sources connections are assumed. In the first case, all H-bridge cells in the same leg share
the same dc source. Another connection is that the same dc source is shared in the same
level of each phase. Fig. 2.8(a) and 2.8(b) illustrate the first connection and the second
connection of five-level cascaded inverter, respectively.
S11

S12

S13

S14

S 21

S 22

S 23

S 24

V AN

Vdc

(a)

S A1

S A2

S B1

SB2

VBN

V AN

Vdc
S A3

S A4

S B3

SB4

(b)
Fig. 2.7 Two possible dc source connections
12

To avoid confusing, both cases will be assumed that no self-shoot-through is possible.

However, there are many combinations, which make short circuit happen. Therefore, one
possibility of each case will be presented. In the first case, short circuit across the dc source
exists when switches S11 and S24 are turned on simultaneously, which is illustrated in Fig.
2.8(a). Likewise, in the second connection, when switch SA1 and SB3 are on at the same
time, which is shown in Fig. 2.8(b), short circuit will be happened.

(a)

(b)
Fig. 2.8 Short circuit possibility in the topology shown in fig. 2.7.
2.3

SUMMARY

A full-bridge inverter or so-called H-bridge cell is introduced. Basically, an H-bridge cell

can generate up to three output voltage levels. Multilevel inverter using cascaded-inverter
with SDCSs are introduced in both single-phase and three-phase structure. The output
voltage is the sum of the output voltage of each H-bridge cell. In three-phase system, the
voltage THD can be improved in line voltage. Finally, the reason to use SDCSs is
explained.
13

In the next chapter, the concept of the optimized harmonic stepped-waveform technique
will be presented. Also, the procedure to find the switching angles for such a waveform
will be proposed.

14

CHAPTER 3
SELECTIVE HARMONIC ELIMINATION
(IN MULTILEVEL) CASCADED INVERTER

3.1 INTRODUCTION
To produce multilevel output ac voltage using different levels of dc inputs, the
semiconductor devices must be switched on and off in such a way that the fundamental
voltage is obtained as desired along with the elimination of certain number of higher order
harmonics in order to have least harmonic distortion in the ac output voltage. For switching
the semiconductor devices, proper selection of switching angles is a must. The switching
angles at fundamental frequency, in general, are obtained from the solution of nonlinear
transcendental equations characterizing harmonics contents in the output ac voltage; these
equations are known as selective harmonic elimination (SHE) equations. As the SHE
equations are nonlinear transcendental in nature, their solutions may have simple,
multiple and even no roots for a particular value of modulation index (m), moreover, it is
difficult to solve these equations.
A big challenge is how to get all possible solution sets where they exist using simple and
less computationally complex method. Once these solution sets are obtained, the switching
angles producing minimum total harmonic distortion (THD) in the output ac voltage are
selected for switching of the power electronics devices. The key issue in designing an
effective multilevel inverter is to ensure that the total harmonic distortion of the output
voltage waveform is within acceptable limits. In general sinusoidal pulse width modulation
and space vector pulse width modulation are suggested in literatures for eliminating
harmonics. Conversely both the methods do not eliminate lower order harmonics
completely and in the process Selective harmonic elimination (SHE) has been reported in
previous works, which involves choosing the switching angles so that specific harmonics
such as the 5th, 7th, 11th, and 13th are suppressed in the output voltage of the inverter, to
minimize lower order harmonics & THD.

15

The primary hold-up associated with SHE is to achieve the arithmetic solution of nonlinear
transcendental equations, so obtained by Fourier theory of output voltage waveform,
depicting trigonometric terms and as expected present multiple solutions. Thus this
problem was overcome using conventional analytical route involving iterative procedure
such as Newton-Raphson technique. This method is derivative-dependent and may end in
local optima, and a judicious choice of the initial values alone can guarantee conversion.
Another approach available in literatures based on conversion, in which resultant theory is
applied to determine the switching angles to eliminate specific harmonics, however, it
appears to be unattractive because as the number of inverter levels increases, so does the
degree of the polynomials of the mathematical model which lead to numerical complexity
and substantial computational burden.

3.2 SELECTIVE HARMONIC ELIMINATION PULSE-WIDTH MODULATION

(SHEPWM)

3.2.1 FOURIER SERIES

Traditionally, the Fourier series expansion for any output of the system can be expressed
as in (3.1):

V(t) = () = 0 + =1( cos( t) + sin( t))

(3.1)

As it is an odd symmetric function, the value of a0 = an = 0. Amplitude of the even harmonic

component of bn is zero. The Fourier series expansion of the waveform obtained from DC
sources having same magnitude can be expressed as in (3.2):

V(t) = =1( sin( t))

(3.2)

where, is the amplitude of the harmonics. The magnitude of becomes zero for evenorder harmonics because of an odd quarter-wave symmetric characteristic:

16

 = { 4

( ( )) ;

(3. 3)

=1

where is the voltage of DC sources which are of the same magnitude and p is number
of switching instant before 90 degrees. Subsequently, V becomes
V(t) =

( ( 1 ) + ( 2 )+. . . ( )) sin( t)

=1,3,5

(3. 4)

where j is the number of switching angles and n is the harmonic order. Ideally, in the
multilevel inverters, there can be k number of switching angles, in which one switching
angle can be used for fundamental voltage selection and the remaining (k-1) switching
angles can be used to eliminate few prime low-order harmonics. Moreover, the modulation
index is defined as the ratio of fundamental output voltage V to the maximum obtainable
voltage Vmax as shown in (3.5):
M=

V1

(3.5)

Vmax

For the eleven-level cascade inverter ,k value is 5 or five degrees of freedom are available;
one degree of freedom can be used to control the magnitude of the fundamental voltage
and the remaining can be used to eliminate fifth, seventh, eleventh and thirteenth order
harmonic components. The following equations (3.6)(3.10) can be obtained from the
above-stated conditions to manipulate the switching angle for performing selective
harmonic elimination:
cos(x(1)) + cos(x(2)) + cos(x(3)) + cos(x(4)) + cos(x(5)) = 5*M

(3.6)

cos(5*x(1)) + cos(5*x(2)) + cos(5*x(3)) + cos(5*x(4)) + cos(5*x(5)) = 0

(3.7)

cos(7*x(1)) + cos(7*x(2)) + cos(7*x(3)) + cos(7*x(4)) + cos(7*x(5)) = 0

(3.8)

cos(11*x(1)) + cos(11*x(2)) + cos(11*x(3)) + cos(11*x(4)) + cos(11*x(5)) = 0

(3.9)

cos(13*x(1)) + cos(13*x(2)) + cos(13*x(3)) + cos(13*x(4)) + cos(13*x(5)) = 0

(3.10)

where x(1), x(2), x(3) ,x(4) and x(5) corresponds to switching angles.
17

3.2.2 MODIFIED NEWTON RAPHSON METHOD

These nonlinear polynomial equations can be solved by the iterative Modified NewtonRaphson method to determine the switching angles x(1), x(2), x(3), x(4) and x(5). The
initial for switching angles lies in between 0 and /2. The flow chart for the Modified
Newton-Raphson method can be used to compute all possible solutions without any
computational complexity as shown in Fig. 3.1.The Modified Newton Raphson method
approach is capable of finding analytical solutions for limited ranges.
Instead of guessing initial angles which is done in Newton Raphson method, here we divide
switching intervals into many subintervals. Initial values for switching angles will take all
possible combinations of subintervals.
By solving (3.6) (3.10), the above mentioned harmonics can be eliminated. M is a
variable in (3.6). For each value of M there are multiple solutions, which leads to different
THD and the solution (switching angles) corresponding to minimum THD should be
selected. Finally, value of M which has the lowest value of THD and corresponding
switching angles are selected.
MIN and MAX given in Fig. 3.1 represents minimum and maximum modulation index
for which at least one solution exists and NC5 represents number of combination.
By the proposed method it possible to find optimized switching angles for a multilevel
cascaded inverter to eliminate specific harmonics as well as to have minimum THD for
any modulation index (MINMMAX).

18

3.2.2.1 FLOW-CHART FOR MODIFIED NEWTON RAPHSON METHOD

Input a set of N numbers between zero and /2
From N numbers, take all combinations of five numbers & sort it in ascending order: A[i]

Set
count=0
M=MIN

M=M + count

YES

M>MAX

i=1
Increment
count

Solve equations using N.R Method

with initial values A[i] (1 i NC5)

NO
Convergence?

YES
Note THD and corresponding M

Stop

Fig. 3.1

19

Increment i

NO

YES
i>NC5

3.2.3 THD Vs. MODULATION INDEX

Graphs plotted below show the relationship between minimum possible THD verses

THD%

modulation index

Modulation Index

THD%

Fig. 3.2 %THD vs. Modulation Index

Modulation Index

Fig. 3.3 %THD vs. Modulation Index

20

THD%

Modulation Index

THD%

Fig. 3.4 %THD vs. Modulation Index

Modulation Index

Fig. 3.5 %THD vs. Modulation Index

21

It is required to find modulation index for which THD is minimum. From Fig 3.5 we get
to know minimum T.H.D as 7.8910 and corresponding modulation index as 0.8028.
With the found out modulation index, we solve non-linear simultaneous equations using
modified newton Raphson method.
Finally switching angles (in degrees) obtained using Modified Newton Raphson method
for minimum THD are 6.3297, 18.8913, 26.7091, 44.6450 and 62.0184

3.2.4 VOLTAGE AND CURRENT WAVEFORM OF SINGLE PHASE AND

THREE PHASE 11 LEVEL CASCADED INVERTER

Voltage(V)

Graphs were plotted for an active load of 10 kW and reactive load of 5 kVAR for single
phase inverter and thrice the load for three phase inverter (star configuration).

Time (s)

Fig. 3.6 Voltage waveform of single phase 11 level cascaded inverter

Fig. 3.6 shows 11 level voltage waveform of single phase cascaded inverter with switching
angles selected to eliminate 5th, 7th, 11th and 13th harmonics.

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Current(A)

Time (s)

Voltage(V)

Fig. 3.7 Current waveform of single phase 11 level cascaded inverter

Time (s)

Fig. 3.8 Voltage waveform (line to line (RB)) of 3-phase 11-level inverter (RYB sequence)

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Current(A)

Time (s)

Fig. 3.9 Current waveform of three phase 11 level cascaded inverter

3.2.5 SIMULINK MODEL OF 11 LEVEL SINGLE PHASE CASCADED
INVERTER

Fig. 3.10 Simulink model of gating signal of single phase 11 level cascaded inverter

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Fig. 3.11 Simulink model of single phase 11 level cascaded inverter

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3.2.6 SIMULINK MODEL OF 11 LEVEL THREE PHASE CASCADED

INVERTER

Fig. 3.12 Simulink model of three phase 11 level cascaded inverter

Fig. 3.13 Simulink model of gating signal of three phase 11 level cascaded inverter

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3.2.7 MINIMUM AND MAXIMUM MODULATION INDEX FOR SINGLE PHASE

11 LEVEL CASCADED MULTILEVEL INVERTER
To find minimum and modulation index M is set to zero and one respectively. By using
Modified Newton Raphson method it is possible to find minimum as well as maximum
modulation index by forward and backward iteration of modulation index (M) respectively.
It have been found that minimum and maximum modulation index are 0.4460 and 0.8460
respectively with a tolerance of 0.001.The Modified Newton Raphson can be generalized
to find minimum and maximum of n-level cascaded inverter, where n is a positive integer.

3.3 SUMMARY
In this chapter, the concept of selective harmonic elimination using modified Newton
Raphson is introduced. Modulation index for which THD is minimum is found. Maximum
and minimum modulation index are also found.
In the next chapter, the concept of uniform battery discharge will be presented. Also, the
procedure to swap the gate signals will be discussed.

27

CHAPTER 4
CHARGE BALANCE CONTROL
4.1 INTRODUCTION
A cascaded multilevel inverter consists of series of H-bridge (single-phase full-bridge)
inverter units. The general function of this multilevel inverter is to synthesize a desired
voltage from separate dc sources (SDCSs), which may be obtained from batteries, fuel
cells, or ultra-capacitors. Each SDCS is connected to a single-phase full-bridge inverter as
shown in fig 4.1

Fig4.1 Single-phase structure of a cascaded inverter with SDCSs

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Each inverter level can generate three different voltage outputs, + , 0 and - by
connecting the dc source to the ac output side by different combination of four
switches, 1 , 2 , 3 and 4 .
The ac output of each levels full-bridge inverter is connected in series such that the
synthesized voltage waveform is the sum of the inverter outputs. The number of output
phase voltage levels in a cascaded inverter is defined by m = 2s + 1, where s is the number
of dc sources. A typical phase voltage waveform for an 11-level cascaded inverter with
five SDSCs and five full bridges is shown in Fig. 4.2. The phase voltage = 1 +

Voltage (V) (V)

2 + 3 + 4 + 5 .

Angle (Radian)

Fig. 4.2 Typical voltage waveform of 11 level cascaded inverter

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From Fig. 4.2, note that the duty cycle for each of the voltage levels is different. If this
same pattern of duty cycles is used on an electrical load continuously, then the level-1
battery (or any other SDCS) is cycled on for a much longer duration than the level-5
battery. This means that level-1 battery will discharge much sooner than the level-5 battery.

4.2 CHARGE BALANCE USING SWAPPING ALGORITHM

Uniform discharge of batteries for 11 level inverter is achieved by swapping of gate pulses
for H-bridges as shown in Fig. 4.3 .The period of each gate pulse is 10ms. Since there are
five bridges, by the end of every 50ms (5*10ms=50ms) state of charge (SOC) remains
same for all five batteries. Fig. 4.4 shows a plot between state of charge and time for a load
of 0.5 MW when swapping of gate pulses are done while Fig.4.5 shows the relationship

Voltage (V) (V)

among the same when swapping is not done.

Angle (Radian)

Fig 4.3 Switching pattern swapping of the 11 level cascade inverter for balancing battery
charge

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Fig 4.4 State of Charge vs. time with battery balancing control

Fig 4.5 State of Charge vs. time without battery balancing control

31

Fig 4.6 State of Charge vs. time with battery balancing control (zoomed view)

From Fig 4.6 it is evident that state of charge of five batteries are not same at each and
every instant but remain same at the end of every 50 ms. For instance, state of charge for
all five batteries at 0.35s and 0.40s are same.
4.3 SUMMARY
Uniform discharge of batteries for 11 level inverter is achieved by swapping of gate pulses
for H-bridges. It is found that SOC of five batteries are made same at end of every 50 ms
by using battery balancing control.

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CHAPTER 5
CONCLUSION

MATLAB (Simulink) model of 11 level cascaded inverter (both single phase & three
phase) are simulated and following conclusions are drawn
1. Percentage harmonic content of 5th, 7th, 11th & 13th harmonics with respect to
fundamental are 4.5604*103, 6.111*104 , 3.0469*103 & 1.8928*103
respectively obtained using Modified Newton Raphson Method. Lowest THD for
single phase and three phase inverter are found to be 7.89 % and 5.57% (line to
line) respectively, and corresponding modulation index is 0.8028.
2. Uniform discharge of batteries are achieved by appropriately swapping the gate
signals to H-bridges.
3. Minimum possible THD for each modulation index is also obtained.
4. The minimum and maximum modulation index of 11 level cascaded inverter are
0.4460 and 0.8460 respectively.

33

REFERENCES

1. D. Ahmadi, K. Zou, C. Li, Y. Huang, and J. Wang, (2011) A universal selective

harmonic elimination method for high-power inverters, IEEE Transactions on
Power Electronics, vol. 26, no. 10, pp. 27432752.
2. N. Yousefpoor, S. H. Fathi, N. Farokhnia, and H. A. Abyaneh, (2012) THD
minimization applied directly on the line-to-line voltage of multilevel inverters,
IEEE Transactions on Industrial Electronics, vol. 59, no. 1, pp. 373380.

3. L. M. Tolbert, F. Z. Peng, and T. G. Habetler, (1999) Multilevel converters for

large electric drives, IEEE Transactions on Industry Applications, vol. 35, no. 1,
pp. 3644.

4.

John N. Chiasson, Leon M. Tolbert, Keith McKenzie, Zhong Du, (2003)"A

Complete Solution to the Harmonic Elimination Problem," IEEE Applied Power
Electronics Conference (APEC 2003), February 9-13, Miami, Florida, pp. 596-602.

34