Simulation and Characterization

of SOI MOSFETs
Dual Degree Project Presentation
Aatish Kumar
(96D07039)
Department of Electrical Engineering,
IIT Bombay, India

Outline of the presentation

Introduction to SOI Devices

SOI Vs Bulk Devices

Characterization and Simulation Results
Gate Induced Drain Leakage (GIDL) Current Studies
Multi-Frequency Transconductance Technique
Conclusions
2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

Why SOI??

An SOI nMOSFET
2:30 pm 26/6/2001

Active region in bulk MOSFET is

limited to top 0.1% of the device.
Remaining 99.9% of the wafer is
inactive and interaction between
device and substrate gives rise to a
range of parasitic effects like
latchup.
In SOI devices, the active device
overlay is isolated from the
detrimental influence of silicon
substrate by a buried oxide layer,
preventing the occurrence of many
parasitic effects.
Simulation and Characterization of
SOI MOSFETs

SOI Technology (SIMOX)

Buried Oxide synthesized by internal
oxidation during the deep implantation of
oxygen ions into silicon.
Postimplantation annealing is necessary to
recover the crystalline quality of the Si
overlay.
In regular quality SIMOX wafers, the
buried-oxide interfaces are found to be
SIMOX Process
sharp and uniform.
11 cm-2eV-1, which is more

D
~
0.5-2x10
it2
* Acronym for Separation by IMplantation
10 cm-2eV-1, but, small
than
D
~
10
it1
of Oxygen Process
enough not to adversely affect device
* Most promising among SOI Technologies
performance.
2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

Classification of SOI Devices

Done on the basis of doping
concentration and silicon
film thickness
Maximum depletion width

xd max =

Band diagram in a
(A) Bulk device,
(B) Thick film SOI device,
(C) Thin film SOI device.

2:30 pm 26/6/2001

4 Si F
qN A

For thick film SOI device,

tSi > xdmax
For thin film SOI device,
tSi < xdmax

Simulation and Characterization of

SOI MOSFETs

SOI Vs Bulk Devices

Schematic
Configuration of
CMOS Transistors
on bulk and SOI
wafers

Advantages:

Disadvantages:

Dielectric Isolation
Vertical Junctions
Lesser Short Channel Effects

Self Heating Effects

Floating Body Effects
Parasitic Bipolar Effects

2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

Floating Body and Parasitic Bipolar Effects

Parasitic Bipolar Transistor

of SOI nMOSFET
2:30 pm 26/6/2001

Presence of floating volume of silicon

beneath the gate gives rise to several
effects unique to SOI generically referred
to as floating body effects.
In an n-channel transistor, n+ source, ptype body and n+ drain form the emitter,
base and collector of an NPN bipolar
transistor.
In bulk MOSFETs, base is grounded by
substrate contact. But, in SOI MOSFETs,
base of the bipolar transistor is floating.
This parasitic bipolar transistor is source
of many undesirable effects.

Simulation and Characterization of

SOI MOSFETs

Kink Effect

Ids (Amps/m)

0.0008
0.0006

Black squares - LAC

Cont Line - conv
L = 0.1 m
TSOI = 35 nm

1.5 V
1.25 V

0.0004

1.00 V
0.75 V

0.0002

0.50 V

0.0000

Vgt = 0V

-0.5 0.0 0.5 1.0 1.5 2.0 2.5

Vds (Volts)

2:30 pm 26/6/2001

Refers to the appearance of kink in output

characteristics of an SOI MOSFET
operating in strong inversion
Kink very strong in nMOSFETs as
compared to pMOSFETs
Thin film fully depleted SOI MOSFETs
dont exhibit kink effect. Its only seen
for thick film partially depleted SOI
MOSFETs
Kink effect can be eliminated from
partially depleted SOI MOSFETs by
providing a body contact and by other
channel engineering and source
engineering methods

Simulation and Characterization of

SOI MOSFETs

Kink Effect (contd.)

Potential in neutral region
from source to drain in
PD and FD SOI Devices

At high enough drain voltage, energetic channel electrons produce electron-hole pairs

by impact ionization mechanism. Electrons move into the channel and drain, whereas
holes move to the place of lowest potential i.e. the floating body.
Injection of holes in the floating body leads to increase in body potential, lowering

source-body potential barrier and threshold voltage.

More carriers flow from source to channel, causing a positive feedback mechanism,

which leads to sudden increase in drain current causing kink in the output characteristics.
2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

Anomalous Subthreshold Slope and Latchup

(a) Normal subthreshold Slope at

low drain voltage,
(b) Device latch up at higher drain
voltage

2:30 pm 26/6/2001

At high enough drain voltage, impact

ionization can occur even in the subthreshold region
When gate voltage is increased slightly, the
weak inversion current can lead to impact
ionization in the high electric field region
near the drain.
Threshold voltage shifts and currents can
increase with gate voltage with a slope lower
than 60 mV/decade.
Parasitic BJT turns on causing sudden
increase in drain current and device cant be
turned off leading to latchup of the device.

Simulation and Characterization of

SOI MOSFETs

10

Process flow for SOI MOSFETs

Boron

Field
Oxide

poly
S

Field
Oxide

Buried Oxide
(A)
Ge
A mor phous Si
Field
Oxide

Oxide
Spacer

poly
S

Field
Oxide

Buried O xide
(B)
TiSi2
Field
Oxide

poly
S
D
Buried Oxide

Oxide
Spacer

Field
Oxide

Starting Material

A Large Angle Tilt Implant for VTH

Adjustment (for LAC MOSFET)

SOI Wafers Si Film Thinning Down

RTA Anneal (1020 oC, 15 seconds)
(35 nm, 50 nm, and 80 nm)
Active Area Definition
Oxide Spacer
and LOCOS
Threshold Voltage Adjustment
B Ge Implantation, 12, 20, and
(For Conventional MOSFET)
40 Kev, 1 1015 cm-2
Gate Oxidation (4 nm)
and Poly Deposition (200 nm)
C Ti Deposition (20~35 nm)
Two Step RTA Silicidation
E-beam Poly Gate Lithography
and Poly Etch
Contact Hole
Source/Drain Extension Implant
Metallization and Forming Gas

(C)

2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

11

VTh Roll-off and DIBL Results

250

0.75

200

Vth (Volts)

LAC SOI MOSFET

0.60
Conv SOI MOSFET

0.45
0.30

DIBL (mV/V)

0.90

LAC SOI
CONV SOI

150
100

W= 10 m
TSOI = 35 nm

50

VTh Roll off and DIBL for

LAC and conventional SOI
nMOSFETS

0.00 0.25 0.50 0.75 1.00

L (m)

0.00 0.25 0.50 0.75 1.00

L (m)

VTH roll off not appreciable for devices less than 0.5 m devices. VTH roll-up observed in

LAC devices. Can be explained by higher effective doping in the channel for smaller
channel lengths.

LAC devices show lesser DIBL than conventional devices due to higher doping near the

source end causing the barrier to be higher there, rendering it less prone to drain bias
variations.
2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

12

Transfer and Output Characteristics

0.0004

0.0008
0.5 V

L = 0.5 m
W = 10 m
TSOI = 35 nm
0.25 V

0.0002

0.0006

Conv SOI
L = 0.25 m
W = 10 m

0.75 V

0.0004
0.0002

0.5 V

0.0000
-1.0 -0.5

Vds = 0.05 V

0.0

0.5

1.0

1.5

Vgt (Volts)

Transfer Characteristics

0.0000

0.0008

1.00 V

Ids (Amps)

0.0006

0.0010
Cont line: LAC SOI
Open Square: Conv SOI

Ids (Amps)

Ids (Amps)

0.0008

LAC SOI
L = 0.25 m
W = 10 m

0.0006

1.25 V

1.00 V

0.0004
0.75 V

0.0002

0.5 V

Vgs = 0.25 V

0.0 0.2 0.4 0.6 0.8 1.0

Vds (Volts)

0.0000

Vg = 0.25 V

0.0

0.5 1.0 1.5

Vds (Volts)

2.0

Output Characteristics of Conv and LAC SOI Devices

LAC SOI MOSFETs show marginal increase in transconductance values as compared to

conventional SOI MOSFETs. Can be attributed to reduction in scattering centers near the
drain end and also due to early velocity overshoot near the source region.
LAC devices exhibit kink effect whereas conventional devices dont show kink, implying
that LAC device is operating in partial depletion mode whereas conventional is in full
depletion mode under the given biasing conditions.
2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

13

Simulations Performed
Final Mesh Structure

Final Device Structure

Two dimensional process simulator, TSUPREM-4 used to simulate the devices. LAC
as well as conventional devices were simulated.
The process simulated devices were extracted into Medici, a two dimensional device
simulator and characteristics were obtained under different biasing conditions.
2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

14

Simulation Results
0.20 V

0.0008

line - conventional

0.00006

Transfer Characteristics

L = 0.1 m
TSOI = 35 nm

0.00004

0.15 V

0.00002

Ids (Amps/m)

Ids (Amps/m)

0.00008 squares - LAC

0.0006

Black squares - LAC

Cont Line - conv
L = 0.1 m
TSOI = 35 nm

1.5 V
1.25 V

0.0004

1.00 V
0.75 V

0.0002

0.50 V

Vds = 0.1 V

0.00000
-0.3

0.0 0.3 0.6

Vgt (Volts)

0.9

Output Characteristics

0.0000

Vgt = 0V

-0.5 0.0 0.5 1.0 1.5 2.0 2.5

Vds (Volts)

LAC devices show higher transconductance than conventional devices, and can be
attributed to reasons as discussed previously
Simulations also show kink in output characteristics for LAC devices, as obtained
from experiments.
2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

15

Gate Induced Drain Leakage (GIDL) Studies

Depletion Regions in the gate drain
overlap region under GIDL bias
Band Diagram in the gate drain
overlap region under GIDL bias

GIDL current is due to tunneling current, which flows from drain to substrate, when
the channel is off or in accumulation and a high drain bias is applied.
The tunneling of valence band electrons into the conduction band generates electronhole pairs due to high vertical electric field in the gate-drain overlap region.
Due to vertical electric field present, the electrons and holes are collected by the drain
and substrate respectively.
2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

16

GIDL Currents in SOI Devices

I D = I GIDL + I GIDL = ( + 1)I GIDL

Schematic of current flow in an
SOI nMOSFET under GIDL bias
2:30 pm 26/6/2001

Origin of GIDL currents same as that in bulk.

The front channel of device is kept in off state or
in accumulation.
The electrons produced are collected by the drain
terminal.
The holes, however, cant be collected by the
substrate due to the buried oxide present.
The GIDL current serves as the base current for
the lateral parasitic bipolar transistor.
The GIDL current which is independent of
channel length is amplified by the parasitic BJT.
This amplification is more pronounced in short
channel MOSFETs.

Simulation and Characterization of

SOI MOSFETs

17

1E-8

1E-5

1E-9
W = 20 m
Tox = 3.9 nm

1E-10

1.0

1.5

2.0

2.5

Drain Voltage (Volts)

Bulk MOSFET

3.0

1E-6

L = 0.25 m
L = 1 m
L = 5 m
L = 10 m

1E-5

1E-7
1E-8
1E-9
1E-10
1.0

W = 20 m
Tox = 3.9 nm
TSi = 35 nm
1.5
2.0
2.5
Drain Voltage (Volts)

3.0

Conv SOI MOSFET

Drain Current (Amps)

L = 0.25 m
L = 1 m
L = 5m
L = 10m

Drain Current (Amps)

Drain Current(Amps)

Results obtained from GIDL Studies

1E-6

L = 0.25 m
L = 1 m
L = 5 m
L = 10 m

1E-7
1E-8
1E-9
1E-10
1.0

W = 20 m
Tox = 3.9 nm
TSi = 35 nm
1.5
2.0
2.5
Drain Voltage (Volts)

3.0

LAC SOI MOSFET

GIDL currents independent of channel lengths for bulk MOSFET as band to band
tunneling depends on gate drain overlap region and VDG only.
The base width of parasitic BJT in SOI decreases, with decrease in channel length,
causing the current gain, to increase.
2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

18

Results from GIDL (cont.)

The current gain, is small for lower collector current levels. This explains identical
currents for small drain biases.
In conventional SOI MOSFET, GIDL current enhancement takes place for channel
length of 0.25 m for higher drain (collector) current levels. The value of is estimated
to be around 30.
In LAC SOI MOSFET, there is no enhancement in GIDL currents showing suppression
of parasitic bipolar action. The increase in GIDL currents is marginal and the value of
obtained is around 3, which is an order of magnitude lower than that for conventional
SOI MOSFETs.
Thus, LAC SOI MOSFETs show immense promise for alleviation of floating body
effects, by reduction of parasitic bipolar gain, .
2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

19

Possible Reasons

Electric Field Variation for LAC

and conventional SOI MOSFETs

2:30 pm 26/6/2001

Lower peak electric field in LAC SOI

MOSFET due to lower doping near the
drain side, which leads to lower impact
ionization and hence, lower hole generation.
Wider depletion region and lower field
across the junction in LAC MOSFETs lead
to reduced band-to-band tunneling giving
rise to a lower hole current.
LAC SOI MOSFETs have larger effective
channel length as compared to conventional
SOI MOSFETs, causing the base width of
parasitic BJT to be more in LAC and thus,
lower current gain, .

Simulation and Characterization of

SOI MOSFETs

20

Interface Characterization in SOI MOSFETs

Techniques developed for bulk-Si technology not directly applicable, due to
Lack of substrate contact
Complex multi-interface nature of SOI devices (especially effects of the back gate)
Multi-frequency transconductance technique using a multi-frequency impedance
analyzer had been used for large geometry bulk and SOI MOSFETs.
The above technique cant be extended for small channel length devices as it is
difficult to eliminate the effects of parasitics.
A multi-frequency transconductance technique using lock-in-amplifier has been
implemented for small geometry SOI devices and used to study hot-carrier degradation
in JVD SOI MNSFETs.
2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

21

Details of the Technique

Set up schematic

Adder used to superpose AC and DC gate signals

Transistor biased in weak inversion

Small signal sinusoidal gate excitation superimposed on DC gate bias
Lock-in-amplifier measures AC component of drain current
2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

22

Details of the Technique (cont..)

At low frequencies, interface traps respond; whereas at high frequencies, they
dont; and from these measurements interface state density can be obtained as:
Dit =

I D Cox
kT

1
1

Re
Re
m
m
g
g HF
LF

Scanning the frequency from a suitable low value to a large value could help
profile trap response distribution.
This small signal measurement essentially probes average Dit along the channel.
Method useful for characterizing high K dielectrics as gate leakage currents are
high in these devices due to poor interface between the gate dielectric and silicon.

2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

23

Initial Measurements

-8

Re{gm}x 10 (Amp/V)

10

1000

N it : 7.2x10 cm
JVD SOI

100 T Si = 35 nm

Frequency of sinusoidal gate excitation

swept from 10 Hz to 100 kHz

-2

n-SOI
W = 20 m
L = 200 nm

10
10

N it : 4.3x10 cm
Oxide-SOI

10

100

1k

10k

-2

100k

Freq (Hz)

Pre-stress interface state densities

obtained by multi-frequency
transconductance technique on SOI
MOSFETs
2:30 pm 26/6/2001

At low frequencies, interface traps respond

whereas at high frequencies, they stop
following gate excitation, giving rise to the
double plateau curve.
Though Re{gm} at lower frequencies is
more for JVD SOI MNSFETs, the interface
state density turns out to be more than that
of conventional SOI MOSFET after taking
into account the IDCox factor.

Simulation and Characterization of

SOI MOSFETs

24

M ulti F req g m m ethod

C harge P um ping

10
-2

W = 10 m
L = 100 nm

V g = V d/2
S tress T im e = 500 sec

1.8 2.0 2.2 2.4 2.6 2.8 3.0

M ulti F req g m m ethod

C harge P um ping

12

10

11
10
9
8
7
6
5
4
3

Nit x 10 cm

10

Nit x 10 cm

-2

Validation of the Technique

V g = V d/2 = 1.5 V

8
6
4

W = 10 m
L = 100 nm

2
10

100

1000

S tress T im e (sec)

V d (V )

Hot carrier experiments were performed on small geometry bulk MOSFETs and the
evolution of interface state density with stress bias and stress time was measured by
charge pumping and the multi-frequency technique.
An excellent match is obtained between the two methods.
2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

25

Hot carrier studies on JVD SOI MNSFETs

SOI MNSFET

Vg = Vd/2
Stress Time = 500 sec

1.8 2.0 2.2 2.4 2.6 2.8 3.0

Vd (V)

W =10 m
L = 100 nm

10

T Si = 35 nm

12

-2

12

8
Nit x 10 (cm )

10
9

cm

11

14
10

12

W = 10 m
L = 100 nm
TSi = 35 nm

L=100 nm

SOI-MNSFET

Nit x 10

10

Nit x 10 cm

-2

13

10

16

14

Vg = Vd/2 = 1.6 V

stress
V G=V D /2
ISUB=41 A

2
0

8
10

100
Stress Time (sec)

0.085

1000

t=1000s

Oxide
JVD Nitride

0.090

0.095

0.100

DISTANCE ALONG THE CHANNEL ( m)

In JVD SOI MNSFET, Nit after 1000 seconds of stress is found to be 7 x 1010 cm-2,
obtained by assuming that interface states are generated uniformly in the channel.
Interface state generation is confined to high field region, which is ~5% of channel
region. Scaling up the interface state density, Nit works out to be 1.4 x 1012 cm-2.
2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

26

Hot carrier studies on JVD (cont.)

This is less than Nit (~ 3 x 1010 cm-2) obtained in identically processed bulk JVD
MNSFETs, for similar stress bias conditions and time.
The SOI JVD MNSFET is working in full depletion mode at the given biasing
conditions. Therefore, lower substrate initiated carrier damage in these devices.
Also, fully depleted SOI MOSFETs have lower electric fields in drain region as
compared to identically processed partially depleted SOI or bulk devices.
Therefore, less electron-hole pair generation takes place in these devices, leading
to lesser hot-carrier degradation.

2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

27

Conclusions
Superiority of LAC SOI MOSFETs over conventional SOI MOSFETs
established by means of experiments and simulations.
Gate Induced Drain Leakage (GIDL) current studies show that LAC
structure alleviates the floating body effects by suppressing the current
gain of parasitic bipolar transistor.
Multi-frequency transconductance technique used to study hot-carrier
degradation effects in JVD SOI MNSFETs. Degradation found to be
less severe than identically processed bulk MNSFETs due to lower
peak electric fields in FD device as well as absence of substrate
initiated hot carrier degradation.
2:30 pm 26/6/2001

Simulation and Characterization of

SOI MOSFETs

28