Implementation of Vedic Multiplier

RAKSHITH
NO:58(A2)
ABSTRACT

ROLL
ECE( 5 TH SEM

REG NO: 140907730

Vedic mathematics is the ancient techniques of

mathematics, based on 16 simple sutras (formulae).
Decimal number system multiplication technique
based on such ancient mathematics is reported in this
paper. Improvement in speed was achieved through
stage reduction. Which was adopted from Vedas,
during multiplication. Binary coded decimal (BCD)
methodology was incorporated with Vedic
mathematics, to implement such multiplier for
practical VLSI applications. The functionality of these
circuits was checked and performance parameters
such as propagation delay, dynamic switching power
consumptions were calculated by spice spectre using
90nm CMOS technology. BCD implementation of
Vedic multiplier ensures the stage reduction for
decimal number, hence substantial reduction in
propagation delay compared with earlier reported
one, has been investigated. Implementation result
offered propagation delay of the resulting (55) digit
decimal multiplier was only ~5.798ns while the power
consumption of the same was ~23.487W. Almost
~26% improvement in speed from earlier reported
decimal multiplier, e.g. parallel implementation
methodology, the best architecture reported so far,
has been achieved.
INTRODUCTION

PROCEDUE
2X2 multiplier:
Design:

Figure illustrates the steps to multiply two 2 bit

numbers. Converting the above figure to a hardware
equivalent we have 3 and gates which will act as 2 bit
multipliers and two half adders to add the products to
get the final product. Here is the hardware detail of
the multiplier

DESIGN:

Hello guys, I have recently worked on Vedic

multipliers and have referred few papers too to
implement it. I want to make this project open to
everyone so that you can build your own Vedic
multipliers and compare the results. Previously i have
written about 2x2 bit Vedic multiplier which you can
refer back again. We will start by designing a 2x2
multipliers and will develop a 16x16 multipliers.

Where "a" and "b" are two numbers to be multiplied

and "q" is the product. With this design we are now
ready to code this in Verilog easily using and gates
and HA (half adders). To make the design more
modular we try to write code for HA first and then
instantiate it to have the final product.

BLOCK DIAGRAM:

//code for Half adder

module ha(a, b, sum, carry);
// a and b are inputs
input a;
input b;
output sum;
output carry;
assign carry=a & b;
assign sum=a^b;

SOURCE CODE:

endmodule

module vedic_2_x_2( a,b,c);

input [1:0]a;
input [1:0]b;
output [3:0]c;
wire [3:0]c;
wire [3:0]temp;
//stage 1
// four multiplication operation of bits accourding to
vedic logic done using and gates
assign c[0]=a[0]&b[0];
assign temp[0]=a[1]&b[0];
assign temp[1]=a[0]&b[1];
assign temp[2]=a[1]&b[1];
//stage two
// using two half adders
ha z1(temp[0],temp[1],c[1],temp[3]);
ha z2(temp[2],temp[3],c[2],c[3]);
endmodule

RESULT: