Professional Documents
Culture Documents
ASIC Design Engineer at SSR Labs| Actively Seeking Full Time opportunities in ASIC Design,
Verification, FPGA Design
Summary
Make goals, dream big, live with passion- Tony Newton
Born and brought up in Mumbai; an incredibly fast city; the city of dreams. The fast paced life kept me on my
toes to work hard and efficiently as well as it gave me the courage to dream.
Always interested in technological advances seen in Consumer Electronics, I completed my undergrads in
Electronics from University of Mumbai. To strengthen my knowledge and become proficient I set out to pursue
my dreams at University of Illinois at Chicago. I successfully completed my Masters in VLSI Design and
Computer Architecture.
UIC gave me a chance to sharpen my skills, through the different logic design projects I got introduced to
various softwares and hardware languages used in semiconductor industry. Apart from technical knowledge
I was elected in the board committee of Indian graduate Association (IGSA). IGSA helped me improve my
communication and management skills.
All work and no play makes Jack a dull boy. Being a firm believer in this old adage, I have always been a
huge fan of outdoor sports. I am passionate about cricket, winning the intramural cricket championship at UIC.
Also I started liking basketball and being in Chicago, a city where Michael Jordan and the Bulls created a
dynasty; I was attracted towards it.
Currently residing in San Jose, bringing to the table a strong 10 months internship experience, I am actively
looking for a full time opportunity in semiconductor industry. My areas of interests include:
-Digital/Analog Design
-ASIC Design and Verification
-Layout Design/RTL Synthesis
-VHDL and Verilog Programming
-Computer Architecture
Experience
ASIC Design Engineer at Scalable Systems Research Labs Inc.
August 2015 - Present (1 year 4 months)
SSR Labs Inc. is a global leader in instruction and energy efficient massively parallel co-processors and
adjunct memories.
- Designing a parser and command interpreter of a Very Large Capacity RAM based on Hybrid Memory
Cube technology using Verilog.
Page1
-The parser and command interpreter receives and interprets commands from HMC Host Adapter and sends
the data to the internal switches.
- Designed FSM for controller of HMC Interface and memory management for HMC. Also designed
asynchronous FIFO and dual port SRAM to handle issues of CDC for different reads and writes.
Graduate Assistant at University of Illinois at Chicago
June 2014 - May 2015 (1 year)
Graduate Assistant in Systems Department.
-Extensively manage Active Directories by controlling staff access and privileges
-Setting up Proxy servers
-Hardware Trouble shooting of Windows and Macintosh Operating Systems
-Troubleshooting and Maintenance of all staff computers and other electronic devices
-Assisting staff in setting up webinars and meetings
-Documenting established solutions and procedures on Wiki
-Keeping track of the inventory
Associate Software Engineer at Accenture
January 2013 - July 2013 (7 months)
-Worked as a Java Developer at Accenture Services Pvt Ltd
-Was a part of a team doing project for JP Morgan Chase bank.
-Involved active Java coding on Thunderhead software.
-Underwent training on Java concepts like AJAX, Servlets, XML
-Also learnt database management and SQL.
-Learned Test Scripting
Education
University of Illinois at Chicago
Master of Science (M.S.), Electrical and Computer Engineering, 2013 - 2015
Grade: 3.62/4.0
Activities and Societies: Indian Graduate Student Association Coordinator, UIC Intramural Cricket Spring
Champions, 2015
University of Mumbai
Bachelor of Engineering (BEng), Electrical and Electronics Engineering, 2008 - 2012
Activities and Societies: Indian Society for Technical Education, Member of Institute of Electrical and
Electronics Engineers(IEEE) (VESIT Chapter)
Projects
Multiple Interacting FSM's
November 2013 to Present
Members:Gaurav Sahasrabudhe, Shafagh Kamkar
Page2
- Designed Schematic of multiple interacting FSMs to determine n-mod-3 (modulus operation) where n
ranges from a 16 bit number to 128 bit number.
- A 128 bit shift register was designed to take 16, 32 ,64 or 128 bit numbers in a parallel load.
-Multiple FSMs were used to reduce computation time from n cycles to n/4 cycles by maintaining constant
hardware cost.
-A 5 bit counter was used to indicate to the FSM that the last bit of the sequence had arrived.
-The entire designing was done using one hot design technique.
-All the designing was done in Altera Quartus II and the programming was done in Verilog.
4-bit Synchronous ALU Design
September 2013 to Present
Members:Gaurav Sahasrabudhe, Abhishek Shendre, Kapil Majumder
-Designed the complete Schematic and Layout of a 4-bit Synchronous ALU with 6 operations using 250nm
SOI technology in Cadence Virtuoso.
- ALU can do multiple jobs depending on the select lines of a 6:1 MUX like Addition of two 4-bit numbers,
1's Complement, Add-traction, NAND operation, NOR operation, 2's Complement
- Involved building of various gates using the hierarchical approach.
- Created schematics and layouts of multiple gates such as inverter, 4-Input NAND, 4-Input NOR, 4-bit Carry
Select Adder based on Mirror design.
-Since a synchronous ALU was needed we designed a 4-bit output register using a D flip-flop Design.
-Designed for clock frequency of 1 GHz and simulated. Parasitics were extracted from doing LVS check and
performance was observed.
Novel Adder Design using FA5 adder
November 2013 to Present
Members:Gaurav Sahasrabudhe, Shafagh Kamkar
-The adder was designed to add three 16-bit numbers to produce an 18-bit output.
-The basic block of the project was an FA5 adder. The adder was designed to take 3 inputs and produce 2 bit
output
-Designed using Wait strategy and Design-for-all-cases (DAC).
-A comprehensive comparison was in terms of hardware cost, static time and dynamic time required for both.
-It was observed that DAC method minimizes delay at the expense of chip area.
-To optimize using DAC method customized multiplexer blocks were deigned.
Parallelization of Minimum cost network using Push and Relabel Technique
September 2014 to Present
Members:Gaurav Sahasrabudhe, Abhishek Shendre
Developed an efficient algorithm for solving the Min-Cost-Network-Flow formulation of Circuit Sizing
Problem using Push-Relabel technique.
-Parallelization of the algorithm was done and project was tested on multi core processors.
-Both static and dynamic load balancing technique was employed to get efficient parallelism.
-A significant reduction of 25% was obtained for 8 cores compared to a single core at higher fanout.
Page3
Page4
Courses
Bachelor of Engineering (BEng), Electrical and
Electronics Engineering
University of Mumbai
Microprocessors and Microcontrollers -I
Microprocessors and Microcontrollers -II
Computer Organization
Microcomputer System Design
DSP Processors
Basics of VLSI
Embedded Systems
Robotics
Continuous Time Signals and Systems
Linear Integrated Circuit Design
Electronic Circuit Design and Analysis
Basics Electronic Circuit Design and Analysis
Master of Science (M.S.), Electrical and Computer
Engineering
University of Illinois at Chicago
Computer Algorithms
Physical Design Automation
Computer System Design
High Performance Processors
Digital System Design
Introduction to VLSI
CS 401
ECE 565
ECE 469
ECE 569
ECE 465
ECE 467
Page5
ECE 466
ECE 468
ECE 567
ECE 541
Organizations
Indian Graduate Student Association
Pick up and Accommodation Co-ordinator
March 2014 to Present
Languages
German
(Elementary proficiency)
English
Hindi
Marathi
Sanskrit
Page6
Computer Architecture
Microcontrollers
C++
ATPG
Static Timing Analysis
TCP/IP
UDP
DHCP
Semiconductors
Electronics
Xilinx ISE
Interests
VLSI Design, Cricket, Trekking, Music
Volunteer Experience
Coordinator at Indian Graduate Student Association at University of Illinois at Chicago
March 2014 - May 2015
Committee member for Indian Graduate Student Association.
-Provided free of cost temporary accommodation for 300+ graduate students of UIC.
-Work also included providing transport and pick ups for graduate students from airport every 3 hours.
-Helped in promoting IGSA and bringing sponsorship for the Association.
-Arranged and actively involved various cultural events as a part of IGSA committee.
Certifications
VLSI Design and Tools
Test Scores
GPA-Master of Science
May 2015 Score:3.62/4.0
Page7
Page8
Gaurav Sahasrabudhe
ASIC Design Engineer at SSR Labs| Actively Seeking Full Time opportunities in ASIC Design,
Verification, FPGA Design
Page9