A Simple Lumped Port S-Parameter De-Embedding Method for On-Package-Interconnect and

Packaging Component High-Frequency Modeling

Zhaoqing Chen
IBM Corporation
2455 South Road, P37 1, Poughkeepsie, NY 12601
email: /lliaoir jau.i
tni, Phone: (845)435-5595
Abstract
The negative capacitance de-embedding method Is shown
to be simple, fast, and accurate for some electronic packaging
component electromagnetic modeling. The lumped port gap
accuracy ofr the simulated S-parameters
capacitance affects the rr
especially at higher frequencies. For removing this effect of
the parasitic lumped port capacitance, we proposed a simple
and accurate de-embedding method. By adding a negative
capacitance with an absolute value of the estimated lumped
port parasitic capacitance at each port of the S-parameter
model, we just need to run a circuit AC simulation to generate
the de-embedded S-parameters. For 3D transmission line
applications like the pin area wire modeling, we developed a
simple method for optimizing the negative capacitance by
getting mimimum reflection from the junction of two
cascaded sections in TDR simulation.
1. Introduction
Lumped port (or discrete port by another name, Fig.1) is
widely supported in commercial electromagnetic simulation
tools [1][2] and in many research activities[4]-[6]. It is very
easy to define a lumped port in these tools by defining two
points. However, lumped port introduces parasitic such as the
gap capacitance in the port area which reduces the accuracy of
the model especially at higher frequencies. This parasitic gap
capacitance shuts the transmitted signal and makes the Sparameter model unusable at higher frequencies.

Another effective solution is by de-embedding the lumped

There are several methods already available [3]-[7]
port.
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We are trying to invent a simple, fast, and accurate lumped
port de-embedding method for the engineering applications of
electronic packaging component modeling.

2. The Lumped Port Parasitic Capacitance Be-Embedding

Method by Negative Capacitance
Fig.2 shows the principle of the proposed method. The Nport S-matrix [SO] is the original S-matrix from the
electromagnetic simulation by using lumped ports. The Smatrix [SO] includes the effect of the lumped port parasitic
which is mainly the parasitic capacitance C>.
N-Port S-P3rameters After Deenihbedna
PlIp

012

itJ

N-Poil S-Paramiieters
by EM

Sdi,ali-e

sig L-mPed Ports

GI0apC ippacitne Inclded)

_~~~~~~~~~~~~~~~~~~~~~~

Fig.2. De-Embedding Lumped Port Parasitic Capacitance

Fig. 1 Lumped Ports for Electromagnetic Simulation

To avoid this shortcoming of the lumped port in the
electromagnetic simulation, we can use the "waveguide port",
or "wave port" by another name, supported in most
electromagnetic simulation tools [1][2]. However, the
waveguide port is accurate only if the cross section of the port
can be extended outwards as a uniform 2D transmission line.
For many applications, the condition of the extension is not
satisfied such as in the case of the pin area wire modeling.

978-1-4244-2318-7/08/$25.00 2008 IEEE

By adding a negative capacitance -Ci with an absolute

alue of the lumped port parasitic capacitance C, at each port,
we can cancel the effect of the lumped port parasitic
capacitance adget a de-embedded S-parameter matrix [S] by
circuit AC simulaton on the schematic shown in Fig.2. Most
commercial circuit simulation tools support negative
capacitance at least in the AC simulation, some even support
it in the transient simulation. For the circuit simulation tool
not supporting the S-parameter model, we have to use an Sparameter-to-circuit-model converter like Broadband SPICE
[8] or IdEM [9] to get a SPICE circuit model from the Smatrix before the circuit simulation(Fig.3).

SPI 2008

modeled which is impossible by traditional 2D transmission

line modeling.

0SPIClfiEX
SPiCE

fBroiadbDand!i
Broadband

SPICE Model from [Sol

SPICE Model
With -qw Added to Each Port

HSPICE

Fig.3 Flow Chart by Using Circuit Model for [SO]

Another method is by the S-matrix operation as described
in [10] to combine the original NxN S-matrix [SO] and the N
2x2 S-matrix [Si] (i=1,2,...,N) of each negative capacitance
which is given by
[534 = ry-j / (yQ+2)
isgi

2 /(y,q+2}

2 / (y6F2)
t: 1 (YeA2)

-yc (yc,+2)

W2here y~~JwC -1 4=50i2

The gap capacitance can be estimated by plate capacitance

formula plus an estimated fringe capacitance. A more accurate
method is to use an electromagnetic tool such as Q3D[1] to
compute the port parasitic capacitance.

For the "3D" transmission line such as the pin area card
wire modeling, a TDR simulation on two cascaded periodical
sections is helpful for optimizing the lumped port parasitic
capacitance. We can adjust the value of the negative
capacitance in the simulation input until the simulated
reflection from the junction becomes minimum.

2. An Application Example
We applied this method to an 18-line pin area wire modeling
(Fig.4) by using CST Microwave Studio [2]. The wire width
is 3mils with thickness of 1.3mils. The dielectric constant f
the board material is 3.4 with a loss tangent of 0.003. To make
the electromagnetic simulation faster, we used PEC for all
conductors. The signal-to-ground ratio of the pins is 2:1 as
shown in Fig.4. The pitch of the pins is lmm. The wire length
is 6mm which is a multiple of 3mm, the x-direction period of
this structure.
The 3D electromagnetic simulation can take into account the
non-TEM properties of the wire structure which result in
stronger far end crosstalk. In addition, the crosstalk from
adjacent signal layers through the via holes can also be

In the 3D electromagnetic simulations, we define each lumped

port by a d=0.02mm gap in +x or -x direction between the
end of signal wire and adjacent electrical wall. By the plate
capacitance equation, we get the plate capacitance
C,p,a,t0.0036pF which is the lower limit of the lumped port
parasitic capacitance. The lumped port parasitic capacitance
should be the plate capacitance plus the fringe capacitance.
Usually numerical methods or simulation tools, like Ansoft's
Q3D, are needed to calculate the port capacitance including
fringe capacitance.

For this 3D transmission line example, we use a simpler

method to estimate the lumped port capacitance by TDR
simulation on two cascaded sections of transmission line each
of them including a negative capacitance at each port to
cancel the parasitic capacitance. We can optimize the value of
the negative capacitance by an objective minimum of the
reflection at the junction of the two sections. Fig. 5 shows the
TDR simulation of two cascaded 6mm sections. We can see
the negative capacitance of -0.008lpF is the one with the

minimum junction reflection. By using this value of the

negative capacitance, we can remove the lumped port parasitic
capacitance and get the S-matrix [S] as shown in Fig.2.
Fig. 6 compares the TDR simulation by using two cascaded
6mm section model to that by one 12mm section model which
is by another electromagnetic simulation. The difference
between the two curves is very small which means the Smatrix of the 6mm section model has been de-embedded quiet
accurately from the original S-Matrix [SO] by a negative
capacitance -0.0081pF at each lumped port.
Fig.7 and Fig.8 show simulated crosstalk results of a
12mm wire structure based on one 12mm de-embedded
model, two cascaded 6mm de-embedded models, and two
cascaded raw (without de-embedding) models, respectively.
The error by cascading is smaller by using de-embedded
models.
Fig.9 shows good correlation between single and cascaded
de-embedded models in active wire near end voltage transient
simulations. Not shown in this figure, the timing error of the
far end voltage is 0.33ps by two cascaded 6mm de-embedded
models, and 1.1 lps by two cascaded 6mm raw models.

Fig.4 (a)

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Fig.6. TDR Simulations by Two Cascaded 6mm Models

Odd Number Port i Coneeflna t Een Nuimbeir Port 0+1)

and One 12mm Model.

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Fig.7. Transient Simulation Results of the Far-End

Crosstalk at Port 2 Caused by Aggressor Signal at All Other
17 Lines.

Fig.4. 18-Line Pin Area Wire Modeling

44 *o)

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Fig.5. TDR Simulation Results by Different Values

25 oo

30D40.05.0SOO0
Fig.8 Transient Simulation Results of the Near End

Crosstalk at Port 1 Caused by Aggressor Signal at All Other

17 Lines.

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Fig.9 Transient Simulation Results of the Near End

Aggressor Voltage at Port 3.

3. Conclusions
A simple and fast lumped port S-parameter de-embedding
method by using negative capacitance to cancel the lumped
port parasitic capacitance is proposed and tested. It is very
accurate and easy to use the proposed method in practical
high-frequency interconnect and packaging component
modeling.
References
[1] Ansoft, HFSS, Q3D, www,ansoft.com
[2] CST, Microwave Studio, wwvAwcst.com
[3] B.Rubin and S.Daijavad, "Calculation of multi-port
parameters of electric packages using a general purpose
electromagnetic code, " in Proc. IEEE 2nd Topical Meeting
on Electrical Performance of Electronic Packaging,
Monterey, CA, Oct. 1993, pp.37-39.
[4] L.Zhu and K.Wu, "Unified eqivalent-circuit model of
planar discontinuities suitable for field theory-based CAD
and optimization of M(H)MIC 's," IEEE Trans. on
Microwave Theory and Tech., vol.47, no.9, 1999,
pp.1589-1602.
[5] M.Farina and T.Rozzi, "A short-open deembedding
technique for Method-of-Moments-based electromagnetic
analysis," IEEE Trans. on Microwave Theory and Tech.,
vol.49, no.4, 2001, pp.624-628.
[6] V.Okhmatocski, J.Morsey, and A.C.Cangellaris, "On
deembedding of port discontinuities in full-wave CAD
models of multiport circuits," IEEE Trans. on Microwave
Theory and Tech., vol.51, no.12, 2003, pp.2355-2365.
[7] Z.Chen and S.Chun, "Per-unit-length RLGC extraction
using a lumped port de-embedding method for application
on periodically loaded transmission lines," in Proc. 56h
Electronic Components & Technology Conference, San
Diego, CA, 2006, pp.1770-1775.
[8] Sigrity, Broadband SPICE, www.sigrity.corn
I
[9] Polito, IdEM, RE

[10] K.C.Gupta, et al., Computer-Aided Design

Circuit, Artech House (Dedham MA, 1981)

of Microwave