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A 2.4 GHz All-Digital PLL With a 1 ps

Resolution, 0.9 mW Edge-interchanging Based
Stochastic TDC
Jianhui. Wu, Member, IEEE, Zixuan. Wang, Chao. Chen, Cheng. Huang and, Meng. Zhang

AbstractA 2.4GHz all-digital phase-locked loop (ADPLL) for

Zigbee application is presented. A stochastic time-to-digital
converter (STDC) with an edge-interchange circuit (EIC) is
proposed. The rising edges of the two input clocks of STDC are
interchanged cyclically by EIC, which achieves dynamic element
matching and doubles the equivalent number of arbiters in STDC.
The frequency resolution of the LC-based digitally controlled
oscillator (DCO) is improved by the tiny unit capacitor and the
high-speed dithering. The proposed ADPLL has been
implemented in a 0.13-m CMOS technology. The measurement
results show a 9-mW total power consumption, in which the
proposed 1-ps-resolution STDC only consumes 0.9 mW. The
in-band and out-band phase noise are -83.0127dBc/Hz @10kHz
and -118.95dBc/Hz @1MHz. The RMS jitter and peak-to-peak
jitter are 4.6ps and 25.7ps, respectively.
Index TermsAll-digital phase-locked loop (ADPLL),
stochastic time-to-digital (STDC), edge-interchange circuit (EIC),
zero-phase error starting.

I. INTRODUCTION

the key components of transceivers, phase-locked loops

(PLLs) are experiencing a transition from analog
implementations to digital implementations [1-2]. All-digital
PLLs (ADPLLs) have better scalability, higher noise immunity
and greater adaptability to deep-submicron technology. A
classical integer-N ADPLL comprises a time-to-digital
converter (TDC), a digital loop filter (DLF), a digitally
controlled oscillator (DCO) and a feedback divider. The TDC
senses the time difference between reference clock and
feedback signal, and converts it to a digital format. The DCO
outputs a high-frequency signal that is tuned by oscillator
tuning words (OTW) instead of control voltage in a VCO. The
loop filter and divider in an ADPLL perform the same functions
with the analog counterparts in a traditional analog PLL.
Although ADPLLs have many advantages compared to
analog counterparts, the quantization noise caused by TDC and
S

The authors are with the National ASIC System Engineering Research Center,
Southeast University, Nanjing 210096, China (e-mail: wjh@seu.edu.cn;
wzx.asic@gmail.com).
Copyright (c) 2015 IEEE. Personal use of this material is permitted. However,
permission to use this material for any other purposes must be obtained from
the IEEE by sending an email to pubs-permissions@ieee.org.

Fig. 1. Block diagram of the proposed ADPLL.

DCO deteriorates the ADPLL performance. Unlike a voltage

controlled oscillator (VCO) can achieve continuous frequency
tuning, a DCOs frequency is discrete. The frequency
resolution of DCO determined by unit capacitor is generally
limited to kilo Hertz class for the present technology. Because
the frequency resolution of DCO dominates the out-band phase
noise of ADPLL, in order to achieve comparable performance
to analog PLLs, many efforts have been made to improve the
frequency resolution, such as a modulator (DSM) is used to
process the OTW through high-speed dithering [3], a
digital-to-analog converter (DAC) is employed to convert
digital code to control voltage to drive a VCO [4], and so on.
On the other hand, the performance of TDCs lags some
distance from that of phase detectors (PDs) and charge pumps
(CPs) in analog PLLs. Among the state-of-art TDCs, a flash
TDC [3, 5] has the simplest architecture, but its resolution is
limit to gate class. A pipeline TDC [6-7] has higher resolution,
but the time amplifier circuit is susceptible to process, voltage
and temperature (PVT) variations. A TDC [8-9] can achieve
noise shaping, but the circuit is complex and the power
dissipation is high. A stochastic TDC (STDC) [4, 10] has high
resolution, good PVT immunity and simple architecture, but
suffers from higher power consumption and larger area because
the resolution depends on the number of arbiters used in the
STDC. In order to implement a high-performance ADPLL for
Zigbee application, a TDC that simultaneously exhibits high
resolution, good PVT immunity and low power is necessary.
This brief presents a 2.4 GHz integer-N ADPLL used in
Zigbee transceiver, as shown in Fig. 1. An edge-interchange
circuit (EIC) is proposed to save power and keep high
resolution of the STDC. In order to assist the operation of
STDC, a divider with zero-phase error starting is used. The
divider, EIC and STDC (DEST) form a block placed in the
feedback path, whose function is similar to the TDC circuit in

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where N is the number of arbiters used in STDC, and T is the

standard deviation of time offsets TOSi (i=1, 2, ... , N). The
resolution is usually improved by using more arbiters at the cost
of higher power and larger area. We herein present an EIC to
solve the contradiction between improving resolution and
reducing power consumption. As shown in Fig. 2(a), the EIC
comprises a D flip-flop based on true-single-phase-clock
structure and four NAND gates. As shown in Fig. 2(b), the
rising edges of Fref and Fdiv are output through clk1 and clk2
commutatively. A signal SC is generated by the falling edge of
START and passed to the encoder as a sampling clock. The
arbiters that are implemented in differential structures detect
which input signal is the first to arrive. The encoder sums the
outputs of the arbiters and converts the summation to binary
code.
In a traditional STDC, the offsets of the arbiters can be
defined as an array T: {TOS1, TOS2, , TOSN}. The standard
deviation of T is given by

(a)

1 N
1 N
2
(2)
(TOSi ET )

TOSi 2
N i =1
N i =1
where ET means the expectation of T, which is close to zero
because the offsets approximately follow a standard Gaussian
distribution.
In the proposed STDC, the rising edges of Fdiv and Fref are
interchanged cyclically due to the EIC. The encoder receives
2N outputs from arbiters in a cycle of SC (i.e., two adjacent
cycles of Fref). Therefore, the offsets can be redefined as T:
{TOS1, TOS2, , TOSN, -TOS1, -TOS2, , -TOSN}. The expectation
of the array T vanishes identically due to its symmetry, and the
standard deviation can be determined by

T =

(b)
Fig. 2. The proposed STDC with EIC. (a) Circuit. (b) Key waveform.

[3]. On power up, only the auto frequency calibration (AFC),

DCO and 1/8 divider are active. AFC counts the number of
cycle of FDCO/8 in one Fref cycle, compares it with |Ndiv/8| and
changes OTWI according to the comparative results. The AFC
operation is based on frequency estimation algorithm [11].
Once AFC finishes detection, it freezes OTWI and activates
digital loop filter (DLF), DSM and DEST by setting Enable
low-voltage. The DEST block divides FDCO by the ratio of Ndiv,
senses and quantizes the phase difference between Fref and Fdiv.
The DEST output Dout is then processed by DLF and DSM, and
controls DCO as the fractional part of OTW. The paper is
organized as follows. The proposed DEST block is described
and analyzed in Section II, the architecture and the DCO
circuits are presented in Section III. In Section IV, experimental
results are discussed, followed by conclusions in Section V.
II. DEST BLOCK
The proposed DEST block is composed of a programmable
divider, an EIC and an STDC. The EIC cyclically interchanges
the rising edges of Fref and Fdiv generated by the divider, and
sends clk1 and clk2 to the STDC that senses the time difference
between them and converts the time difference to a digital code
Dout, as shown in Fig. 1.
A. STDC and EIC
An STDC employs a set of identical arbiters that exhibit
random mismatches following a Gaussian distribution. The
mismatches have a dithering effect on outputs, which is
equivalent to adding a random time offset TOSi to one input of
each ideal arbiter. As analyzed in [4], the resolution of an
STDC is given by
TLSB =

2 T
N

(1)

T' =

N
1 N 2
2
TOSi + (TOSi ) =
2 N i =1
i =1

1
N

2
OSi

(3)

i =1

Due to the switching operation in EIC, the offset of each

arbiter exhibits opposite polarities between adjacent cycles of
input clocks, which resembles the operation of dynamic
element matching [12]. The dynamic behavior can be
represented as
E ( ) = F sgn ( cos o t ) V ( )
4
4
4

= F ( cos o t
cos 3o t +
cos 5o t K) V ( )
3
5

(4)

where o is 2Fref herein and V() represents the power

spectral density (PSD) of mismatch along with flick noise. The
signals remain while the mismatch and flick noise are spread
into higher harmonic, and can be easily filtered by DLF because
the loop bandwidth is much narrower than o generally.
The EIC spreads the mismatch and flick noise into higher
frequency by periodically averaging the quantization error.
Therefore, the quantization accuracy is improved, and the
STDC with EIC achieves a similar quantization effect with a
traditional STDC that contains 2N arbiters. So the resolution
can be rewritten as
T
'
(5)
TLSB
LSB
2
The circuits have been designed using a 0.13-m CMOS

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Fig. 3. Power reduction and resolution versus number of arbiters.

technology with a 1.2-V supply. The number of arbiters is 32 to

reach a balance between power and performance. The EIC and
arbiters consume about 0.2 mW and 0.6 mW respectively while
the digital circuit consumes 0.1 mW. Fig. 3 shows the power
reduction and resolution versus the number of arbiters. In this
work, the power reduction is over 30% and the resolution is
about 1ps. It should be noted that such an advantage of
low-power will become greater when more arbiters are used.

(a)

B. STDC Quantization Effect on Phase Noise

TDC quantization mainly affects the in-band phase noise of
the ADPLL. As analyzed in [3], the phase noise spectrum at the
ADPLL RF output due to the TDC quantization effect is

( 2 TLSB )

N div FDCO
(6)
12
where TLSB is the resolution of TDC, Ndiv is the dividing ratio.
Eq. (5) and (6) reveal that the proposed STDC can achieve a
phase noise improvement of about 6dBc/Hz, comparing with
the traditional STDC with the same amount of arbiters.
Substituting (5) in (6), the phase noise due to the proposed
STDC quantization can be written as
3 T2 N div FDCO
(7)
L
3N 2
In this work, a 2-MHz reference clock and 32 arbiters are used.
Substituting T=25ps, FDCO=2.4GHz, Ndiv=1200, N=32, we
obtain L-110.4dBc/Hz.
L=

C. Divider
In the arbiter circuit, there is an undesirable case when a very
narrow pulse width results at the OR gate output VG, as shown
in Fig. 2(b). Thus, M5 and M6 have insufficient time to charge
their drain terminals prior to the next detection. This probably
results in abnormal situations of STDC operation. Therefore, a
mechanism is necessary to limit the phase difference when the
STDC starts to work.
A divider with zero-phase error starting is used in the DEST
block, as shown in Fig. 4. Ndiv is the dividing ratio. 10-stage D
flip-flops based on current-mode logic structure are cascaded to
achieve a 10-bit down counter. When the count value is down
to zero, |Ndiv/2| and Ndiv-|Ndiv/2| are alternately selected to be the
load value of D flip-flops. Once AFC circuit finishes frequency
locking, FDCO approximates Fref times Ndiv, and the signal
Enable triggered by the falling edge of Fref becomes
low-voltage, which will be seen in Section III. Then the divider

(b)
Fig. 4. The proposed divider with zero-phase error starting. (a) Architecture.
(b) Key waveform.

Fig. 5. DCO core.

starts to work and the first rising edge of Fdiv aligns with that of
Fref when the divider finishes the first down-counting, as shown
in Fig. 4(b). The zero-phase error starting is achieved and the
locking time is reduced, although there is still a tiny phase
difference that is much less than .
III. DCO
A. DCO core
The LC-based DCO, shown in Fig. 5, consists of three tuning
stages: a 5-bit binary-coded coarse array, a 7-bit binary-coded
medium array and a 7-bit thermometer-coded fine array. An

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Fig. 6. C-V curve.

Fig. 8. Linearity measurement.

0.98mm

Fig. 7. Chip micrograph.

18-fF MIM capacitor is used as the unit of the coarse array,

achieving a tuning range of 2.39 to 2.55GHz.
A MOS capacitor, comprising two PMOS pairs that are
inversely connected in parallel, is used as the unit of the
medium and fine array. When the control voltage OTW is high,
pair1 works in inversion region while pair2 works in depletion
region. When OTW is low, pair1 works in depletion region
while pair2 works in inversion region. The unit capacitance
equals (C1I+C2D)-(C2I+C1D), which is much smaller than that of
the conventional MOS cap [3] that is C1I C1D, as shown in Fig.
6. The size of the transistors in pair1 and pair2 are 80/13 and
40/13 respectively, resulting in a high resolution up to 200
kHz/LSB. In order to eliminate a possible gap between adjacent
frequency bands due to PVT variations, the unit capacitance of
the medium array is slightly smaller than that of the fine array.
B. DSM
The DSM is based on MASH 1-1-1 structure, which is
clocked by FDCO/8. The frequency resolution of DCO is 200 kHz
with a 2-MHz reference clock. After the 300-MHz dithering
with 8 sub-LSB bits, the effective time-averaged resolution is
up to 200 kHz / 28 780 Hz. The DSM is designed with Verilog
HDL and synthesized from a standard logic library.
IV. EXPERIMENTAL RESULTS
The proposed ADPLL has been fabricated using a 0.13-m
1P8M CMOS technology. The chip occupies 0.92mm2,
including a bandgap reference circuit occupying 0.23 mm2, as
shown in Fig. 7. The ADPLL has a maximum power
consumption of 9mW from a 1.2-V supply. The DEST block
consumes 4.5mW, in which the divider, EIC and STDC
consume 3.6mW, 0.2mW and 0.7mW respectively.

(a)
(b)
Fig. 9. Single shot measurement. (a) With EIC. (b) Without EIC.

A. STDC Measurement
To measure the performance of STDC, a replica circuit has
been designed in the chip. The resolution of the proposed
STDC is about 0.98ps, which means T25ps and the range of
STDC is about 75ps. To measure the linearity, two inputs with
0.05Hz difference in frequency at 2MHz are applied to generate
a ramp input. Differential nonlinearity (DNL) and integral
nonlinearity (INL) within linear region are measured from code
density analysis with 105 hits. As shown in Fig. 8, the DNL is
-0.7 to 0.5 LSB and the INL is -1.7 to 0.5 LSB.
Fig. 9 shows the comparison of single-shot measurement
between STDC with and without EIC for a constant input of
20ps repeated 105 times. Thanks to the dynamic element
matching of EIC, the proposed STDC exhibits a more
centralized code distribution (standard deviation = 0.48LSB)
than the STDC without EIC (standard deviation = 0.81LSB).
B. ADPLL Measurement
The phase-noise plots of the ADPLL with and without EIC
are shown in Fig. 10. The in-band phase noise is about
-83.0127dBc/Hz @10kHz when EIC is on while the measured
result is about -77.0726dBc/Hz @10kHz when EIC is off. A
5.9401dBc/Hz improvement is achieved by using EIC, which
corresponds to the analysis in Section II. A -118.9556dBc/Hz
@1MHz out-band phase noise with EIC is achieved thanks to
the high-resolution DCO while the out-band phase noise
without EIC is -119.9772dBc/Hz@1MHz.
Fig. 11 shows the jitter performance of the ADPLL. When
operating at 2.4GHz output, the RMS jitter is 4.6ps and the
peak-to-peak jitter is 25.7ps. Table I summarizes the
performance comparison among similar works. This work has
the best out-band phase noise performance, and better jitter
performance and lower power except [2]. However, on in-band
phase noise performance, this work lags some distance from
some other excellent works, such as [2] and [4], which mainly
results from the slowest reference clock used in the ADPLL.

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TABLE I
Performance Comparison with Prior Works

130

40

130

180

This
work
130

20

26

75

60

1.93.1

2.4

1.2

0.91.25

2.392.55

-75.49
@10kHz

-90.3
@10kHz

-96.9
@1MHz

N/A

-83
@10kHz

-104.6
@10MHz

-109.3
@10MHz

-109
@10MHz

N/A

-118.9
@1MHz

4.01

3.29

6.9

5.03

4.6

60

N/A

56

35.6

25.7

2MHz

200kHz

4MHz

N/A

100kHz

14.4

6.4

17

12.24

[1]
tech. (nm)
ref clock
(MHz)
output
(GHz)
in-band
phase noise
(dBc/Hz)
(a)

out-band
phase noise
(dBc/Hz)
RMS jitter
(ps)
pk-pk jitter
(ps)
Bandwidth
power
(mW)

[2]

[4]

[7]

Science Foundation of China under no. 61176031.

REFERENCES
(b)
Fig. 10. ADPLL Phase noise at 2.48GHz. (a) With EIC. (b) Without EIC.

Fig. 11. ADPLL jitter performance at 2.4 GHz.

V. CONCLUSION
This brief presented a 2.4G ADPLL for Zigbee application.
An EIC was proposed to solve the contradiction between
resolution and power in traditional STDC. A 1-ps resolution
was achieved using only 32 arbiters, which means a 30% power
reduction was achieved, comparing with a traditional STDC
that has the same resolution. In addition, a good linearity and a
more centralized code distribution was also achieved due to the
usage of EIC. A divider with zero-phase error staring was used
to assist the operation of STDC. The frequency resolution of
DCO and out-band phase noise of ADPLL was improved due to
the DSM. The chip was fabricated in a 0.13-m CMOS
technology and the measured results showed that the ADPLL
featured a 4.6-ps RMS jitter and a -118.95dBc/Hz out-band
phase noise and consumed 9mW under a 1.2-V supply.
ACKNOWLEDGMENT

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This work was financially supported by the National Natural

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