Introduction

We were instructed to design a 4-bit PC. We used SAP-1, 2 and 3s concepts and cumulatively
tried to design a PC which consists of data bus of 4 bits. Bidirectional transmission and stack
pointer are implemented in our PC. We were given instruction sheet for each groups. We
designed, simulated the PC on Proteus and finished report regarding this. There were some
additional specifications that we had to implement here. Those are:

Address bus will be of 8-bit and data bus will be of 4-bit

There will be two independent units in the system Fetch unit and Execution unit. So
two stage pipe lines will be preferable.
Program has to be written on a normal PC and then sent the appropriate machine codes
through communication ports to the microcomputer implemented.

Instruction Set
LDA address; STA address; MOV Acc, B; MOV B, Acc; MOV Acc, immediate; IN; OUT; ADD B; ADC B; SUB
B; SBB B; ADC [address]; SBB [address]; CMP B; DEC; JNO address; JG address; PUSH; POP; CALL address;
RET; JMP; HLT; NOP; RCL; RCR; AND B; XOR B

Instruction
LDA address
STA address

MOV Acc, B
MOV B, Acc
MOV Acc, immediate
IN
OUT
ADD B
ADC B
SUB B
SBB B
ADD [address]
ADC [address]
SUB [address]
SBB [address]
ADD immediate
ADC immediate

Description
Acc <- Memory [address]

Memory [address] <- Acc

Acc <- B
B <- Acc

Acc <- immediate

Acc <- input port
Output port <- Acc
Acc <- Acc + B
Acc <- Acc + B + C (Contents of Carry Flag)
Acc <- Acc B
Acc <- AccBBo (Contents of Carry Flag)
Acc <- Acc + Memory [address]
Acc <- Acc + Memory [address] + C (Contents of
Carry Flag)

Acc <- AccMemory [address]

Acc <- Acc -Memory[address]Bo(Contents of
Carry Flag)
Acc <- Acc+immediate
Acc <- Acc + immediate + C (Contents of Carry
Flag)

SUB immediate
SBB immediate
PUSH
POP
CALL address
RET
JMP address
HLT
AND B
OR B
XOR B

Acc <- Acc immediate

Acc <- Acc immediateBo(Contents of Carry
Flag)
Pushes the content of Accumulator to the
stack
Pops off stack to Accumulator
Calls a subroutine (at the specified address)
unconditionally
Returns from current subroutine to the caller
unconditionally
Jumps unconditionally to the address
Halts execution
Acc <- Acc . B
Acc <- Acc | B
Acc <- Acc B

AND [address]
OR [address]
XOR [address]

Acc <- Acc . Memory [address]

Acc <- Acc | Memory [address]
Acc <- Acc Memory [address]

AND immediate
OR immediate
XOR immediate

Acc <- Acc . immediate

Acc <- Acc | immediate
Acc <- Acc immediate

NOT
NEG
XCHG
SHL
SHR
ROL
ROR

Acc <- !Acc

Acc <- -Acc
Acc B (Exchanges contents of
Accumulator and B)
Acc <- Acc << 1, C (Carry) <- Acc [MSB], Acc
[LSB] <- 0
Acc <- Acc >> 1, C (Carry) <- Acc [LSB], Acc
[MSB] <-0
Acc <- Acc << 1, Acc [LSB] <- Acc [MSB], C
(Carry) <- Acc [MSB]
Acc <- Acc >> 1, Acc [MSB] <- Acc [LSB], C

RCL
RCR
INC
DEC
CMP B
TEST B
CMC
CLC
STC
CLS
STS
CLZ
STZ
JC address
JNC address
JZ address
JNZ address
JO address
JNO address
JE address
JNE address
JG address
JL address
NOP

(Carry) <- Acc [LSB]

Acc <- Acc << 1, Acc [LSB] <-C (Carry), C
(Carry) <- Acc [MSB]
Acc <- Acc >> 1, Acc [MSB] <- C (Carry) , C
(Carry) <-Acc [LSB]
Acc <- Acc + 1
Acc <- Acc 1
Accumulator will be unchanged. Set flags
according to (AccB).
Accumulator will be unchanged. Set flags
according to (Acc . B)
Complements the Carry flag
Clears the carry flag
Sets the carry flag
Clears the sign flag
Sets the sign flag
Clears the zero flag
Sets the zero flag
Jumps to the address if carry flag is set
Jumps to the address if carry flag is not set
Jumps to the address if zero flag is set
Jumps to the address if zero flag is not set
Jump if overflow
Jump if no overflow
Jump if equal
Jump if not equal
Jump if greater
Jump if less
No Operation

Description of major components

1. Fetch and Decode Unit
This unit supplies instructions in program order to the execution unit. It performs the
following functions:

Fetches instructions that will be executed next.

Decodes instructions into micro-instructions.
Generates micro-codes to execute micro-instructions.

a) Program Counter Register (PC)

The program Counter Register holds the address of the next instruction that is to
be executed. It is incremented automatically at each clock cycle to contain the
next instruction address or operand address. Sometimes it is directly loaded with
address values by JMP, CALL, RET, JC and JE instructions. The output is fed to the
input of Instruction Memory.

b) Instruction Memory
Instruction memory is 256x8 RAM. It has 8 output and address pins separately.
Thus byte addressable. Each byte contains the desired instructions. The read
signal is always activated. Since address inputs are directly connected to the PC,
hence the memory output is always available without requiring any extra clock
cycle. There is no need to write instruction memory. Because we used separate
memory for data and instruction. Data writes and stack writes take place in the
data memory. Only at the start of the simulation program code needs to be
loaded in the instruction ROM.

c) Instruction Register (IR)

The instruction register holds the opcode of the instruction that is being
executed in the execution unit. Its 8 bits long. Its contents are directly fed to the
instruction decoder unit to generate the micro-operations for each instructions.
d) Instruction Memory Buffer Register
This register is used to hold the 2nd for all 2 byte instructions. The 1st opcode byte
is stored in the instruction register. During the 1st clock cycle the opcode is
fetched into the IR. During the 2nd clock cycle the 2nd byte is fetched and kept in
this buffer. IR is not loaded during this clock cycle.
e) MUX1, Data Memory Address Selector
This MUX controls the input in Data Memory Address. The possible inputs can be:
SP value, required in PUSH instruction.
SP value + 1, required in POP instruction.

Instruction memory buffer register output, required in indirect data

memory access where data address value is given as 2nd byte.

f) Adder for computing PC+1 and output buffer

This adder computes the current PC value +1. It is required in CALL where we
need to store the next address to the stack. The 3 state buffer in front of the
adder for PC + 1 output is necessary so that the adder does not load the data
memory output bus while it is busy.
g) Bidirectional Transceiver

In some instructions we need the data memory output is to be passed to

the shared data bus.
In some other instructions we may need that shared bus output is to be
loaded to the data memory output bus.
In other cases, data memory must not load the shared bus while its busy.
To meet all the purposes mentioned above we need a 3-state buffer. The
bus transceiver does the same. It has a chip select pin. If it is active, it
does not load the bus on both sides. Otherwise, depending on other pin it
transfers data one side to another side.

h) Instruction Decoder Unit

This unit decodes each instructions according to their types. This is a ROM that
generates the appropriate micro-operation depending on the value in IR. This
ROM address is found to be generated control signals for handling the execution
of the instruction. An important feature of it is that it stores many program
codes initial sections in same address, thus reducing the ROM size.

2. Execution Unit
It performs arithmetic and logical operations, transfers values between registers and
data memory.

a) Arithmetic and Logical Unit (ALU)

This is a 4-bit ALU which performs following operations:
Arithmetic operations addition, subtraction, increment, decrement and
transfer operation.
Logical operation logical or, xor, and, compliment operations.
The two selector pins S1, S0 of MUX2 selects 2nd operand as follows:
S1
0
0
1
1

S0
0
1
0
1

Operand
B Register
1
Data memory output
Instruction memory buffer register output

b) Register
The entire register set consists of:
2 general purpose registers Accumulator and B.
1 program status register or flags register.
1 temporary register.
1 input port register.
1 output port register.
c) Functions of Registers

Accumulator: For any arithmetic or logical operation this is the default

register for operand and result.

B register: We can move values in and out of this general purpose

register to accumulator. It can be selected as 2nd operand for some
operations too.

Temp Register: This is used for stack or call instructions. Used for
swapping contents to and from accumulator and B.

Input Port Register: Used for interfacing with outside world. It receives
data from external devices.

Output Port Register: Used for interfacing with outside world. It sends
data to external devices.

Flags Register: Stores status of recent operations.

d) The Status Flags Register

CF

Carry Flag Set if any arithmetic operation results in a carry or borrow,

cleared otherwise.
Zero Flag Set if result is zero, cleared otherwise.
Overflow Flag Set if the result is too large of positive integer or too
small a negative integer.

ZF
OF

Functionalities of the flags are given below:

Arithmetic operations set all flags.

CF and VF do not change during logic operations.
The status flags allow a single operation to have multiple data types:
signed and unsigned.
The conditional branching instructions (e.g. JC, JZ) use one or more of the
status flags as condition codes and test them for branching.

How to load a program and run it:

1.Set BOOT=1
2.for i=1 to number of lines in code bin file:
#prepare address & data for ram to write
MARL=0 //prepare MAR to load the address
BMDRL_BUS=0 //prepare MDR to load data from bus
BOOT_CLK=0 //1-->0 transition,half cycle
BOOT_CLK=1 //0->1 transition,half cycle
MARL=1 ///load disable for MAR
BMDRL_BUS=1 //load disable for MDR
//data+address prepared,now write on RAM
BOOT_CAR_EN=1 //increment prog counter for next iteration
BW=1 //boot write enable
BMDRE_RAM=1 //enable RAM to read from MDR
BOOT_CLK=0 //1-->0 transition ,half cycle,writes data on RAM
BOOT_CAR_EN=0 // disable prog counter increment
BOOT_CLK=1 //0-->1 transition,half cycle
BW=0 //write disable
BMDRE_RAM=0 //disable MDR enable
//boot over,now work on stack pointer
BDEC=1
BOOT_CLK=0 //1-->0
BOOT_CLK=1 //0--1
BOOT=0
BDEC=0

PC_RESET= do something so that it has an 1->0 transition,if pc_reset initially 0,do

0-->1-->0;otherwise,1-->0
now,to run,you need to go through several CLK:1-->0 transitions.every transition will
change the value of T0T1T2T3.10(not sure) transitions like this will take T0T1T2T3 from
0000 to again 0000
If u do so,u have successfully executed 1 instruction.
Now do this for each instrutions

Control Words Description:

Control bits:

SL.

Control Containing

On Active State

No

bit

Register

INL

Input Port

Loads data on input po

EIP

Input Port

Enables to write data on BUS

PC_AC
TIVE

Program
Counter

Loads address to program counter

L/I

Program
Counter

Increments the counter

EP

Program
Counter

Writes current program address to the bus

MARL

Memory
Address

Loads the MAR with input data from BUS

Register
6

EMA

Memory

Gives input address to RAM

Address
Register
7

~LR

RAM

Loads RAM data on the given address by MAR

ER

RAM

Writes the Data to MDR

~LMD

Memory
Data

Loads MDR with the data supplied by RAM

Register
10

EMD

Memory
Data
Register

Writes data from MDR to the BUS

11

~LIR

Instruction
Register

12

EIR

Instruction
Register

Loads instruction register with opcode of the

current instruction
Supplies the controller sequencer with the
opcode of current instruction

13

~LA

Accumulat
or

Loads the accumulator

14

EA

Accumulat
or

Writes to data bus from Accumulator

15

S2

Arithmetic

Selector bit for ALU

Logic Unit

000=Add/Adc

100=AND

Arithmetic

001=Sub/SBB

101=XOR

Logic Unit

010=CMP

110=RCL

Arithmetic

011=NOT

111=RCR

16

17

S1

S0

Logic Unit
18

EC

Arithmetic

Carry flag content takes part in operation

Logic Unit
19

EALU

Arithmetic

Performs the selected operation

Logic Unit
20

~LB

Load data into B register

21

EB

Write data from B register

22

~LT

Temporary

Load address to the Temporary Address Register

Address
Register
23

ET

Temporary
Address

Write address from the Temporary Address

Register

Register
24

~LSP

Stack

Loads the stack pointer

Pointer
25

ISP

Stack
Pointer

Increment stack pointer

26

ESP

Stack
Pointer

Writes current stack pointer address to the data

bus

27

DSP

Stack
Pointer

Decrement stack pointer

28

~LO

Output
Register

Loads output Register

29

~NOP

Do nothing,but no return to fetch cycle

IC USed with count:

Quantity
6
8
2
3
1
2
2
1
2
1
1
3
15
7
6
5
1
2
1
3
2
1
1
6
1
1

References
U1, U5, U26, U41, U46, U65
U2, U7, U21, U28, U43, U50, U57,
U3, U51
U4, U6, U18
U8
U9, U79
U10-U11
U12
U13, U55
U14
U15
U16, U59-U60
U17, U23, U32, U38-U39, U47U48, U52, U68, U75, U80, U83-U86
U19, U54, U56, U61-U64
U20, U29, U31, U33, U36-U37
U22, U24-U25, U34-U35
U27
U30, U44
U40
U42, U45, U77
U49, U76
U53
U58
U66, U69-U73
U67
U74

Value
74LS193
U78 74LS04
74LS08
74LS244
74LS10
74LS11
FUNCTION_4_8
74HC139
7404
4030
7432
4019
74LS157
74126
74LS126
74LS173
74LS20
74LS32
74LS02
74HC4002
74LS21
6116
74LS86
2732
7408
74173

Discussion

We used Proteus for the simulation, hence we were able to make the design flexible.
We designed this with easy to handle wireless terminal method by giving label the
important components.

We have separated data and instruction memory. This reduced number of average clock
cycles for those instructions to be nearly one.

The design contains 4-bit data bus, there is no address bus in our design as we
implemented two stage pipe lining.

Average CPI is calculated 1.5368 and total ICs used is 55 only which fulfills the
requirements of this assignment.

We faced some preliminary difficulties regarding Proteus usage. Critical sections and
operations on the simulation software were handled carefully for the experiment.

CSE 404:Digital Design System Sessional

4-Bit PC Design Report Submission

Lab Group: A1
Group : 2
Submitted By:
1105002
1105004
1105021
1105022
Submission date:
9.5.16