IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO.

12, DECEMBER 2012

4831

Design Methodology for Dual-Band Doherty Power

Amplifier With Performance Enhancement
Using Dual-Band Offset Lines
Karun Rawat, Student Member, IEEE, and Fadhel M. Ghannouchi, Fellow, IEEE

AbstractThis paper proposes a design methodology for

dual-band Doherty power amplifier (DPA) with performance enhancement using dual-band phase offset lines. In the proposed
architecture, 50- dual-band offset lines with arbitrary electric
lengths at two frequencies are key components, and a novel analytical design solution has been proposed for their design and
implementation. The methodology is validated with the design and
fabrication of a 10-W GaN-based DPA for code division multiple access and Worldwide Interoperability for Microwave Access
applications at 1960 and 3500 MHz, respectively. The dual-band
Doherty amplifier using the proposed design methodology has
better performance than the current state of the art. The peak
drain efficiency of the amplifier is 59.5% at the first frequency
and 49.6% at the second frequency of operation. Compared to balanced mode operation, there is an improvement of more than 10%
in drain efficiencies, around 6.5-dB back-off, at both frequencies.
Index TermsDispersive structure, Doherty power amplifier
(DPA), dual band, phase offset lines.

I. I NTRODUCTION

UAL-BAND/WIDEBAND applications are recently getting attention and encouragement in the communications
research area due to the modern and upcoming communication
standards [1][3]. These components can be used in developing multistandard/multimode and reconfigurable transmitter
architecture, capable of operating on a number of different air
interface standards at different carriers [4], [5]. Such transmitter
is intended to be used in a software-defined radio (SDR) terminal [4]. Hence, there is a keen motivation toward developing
various passive or active radio frequency (RF) circuits [6][11]
with multiband/wideband operation capability [12][16]. The
SDR terminals are also proposed as smart devices for energy
saving in a high-traffic communication network [17], [18]. Due
to their reconfigurability, such radios can optimally choose
among appropriate connectivity options with minimized path
Manuscript received June 30, 2011; revised September 9, 2011 and
October 23, 2011; accepted November 8, 2011. Date of publication
November 21, 2011; date of current version July 2, 2012. This work was
supported in part by the Alberta Innovates Technology Future, by the Natural Sciences and Engineering Research Council of Canada, by the Canada
Research Chair Program, and by TRLabs.
The authors are with the Department of Electrical and Computer
Engineering, Schulich School of Engineering, University of Calgary, Calgary,
AB T2N1N4, Canada (e-mail: krawat@ucalgary.ca; fadhel.ghannouchi@
ucalgary.ca).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2011.2176695

loss/shadowing. Thus, in consideration of predicted traffic

loads and channel characteristics, the transmitted power can
be optimized. This results into energy-efficient communication
systems, where the transmitter is the main energy consuming
subsystem due to the presence of power amplifier (PA).
Apart from being a power-hungry component, PA is also
the most nonlinear component [19][23] in the entire communication link, which contributes to adjacent channel power
leakage, reducing the spectral efficiency [20]. Thus, linearity
and efficiency are the two main benchmarks for any transmitter
topology [19][23]; hence, an optimal solution is being sought.
In order to achieve high linearity, digital predistortion (DPD)
is highly appreciated among several linearization schemes due
to its accuracy and its implementation in digital domain, resulting into reconfigurable capability [19][23]. However, utilizing predistortion as a linearization tool results in efficiency
reduction as the PA is operated at average power back-off,
which depends on the peak-to-average power ratio (PAPR) of
the predistorted signal [19][23]. To enhance the efficiency in
this back-off region, Doherty PA (DPA) is studied extensively,
where theoretically the same efficiency as at saturation can be
obtained at a certain back-off, which is decided by the load
modulation factor [24][27]. Thus, for the dual-band transmitter architecture, a dual-band DPA design in conjunction with
DPD is of great interest.
In the literature, some attempts to design a dual-band DPA
[28][31] have been reported, which discuss architectural
overview without any proper design methodology.
Since, in a single-band design, phase offset lines are commonly used to optimize the performance of Doherty [26], [32],
such optimization in a dual-band design needs dual-band phase
offset lines with arbitrary electric lengths at the two frequencies.
Implementing such lines is the main challenge in the design
of dual-band DPA as two arbitrary phases are required at
the two frequencies which should be controlled using design
parameters.
This paper presents a novel analytical design methodology
for the design of dual-band phase offset lines which have 50-
characteristic impedances but two arbitrary electric lengths at
the two frequencies. These offset lines are used in the performance optimization of dual-band DPA, which is validated with
simulation, hardware design, and measurements.
A 10-W dual-band DPA has been designed using the proposed architecture, which operates for code division multiple
access (CDMA) and Worldwide Interoperability for Microwave

0278-0046/$26.00 2011 IEEE

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012

Fig. 1. Proposed architecture for dual-band DPA.

Access (WiMAX) applications at 1960 and 3500 MHz, respectively. The results of the prototype are compared with the state
of the art in the dual-band DPA design to report the performance
improvement.
Section II describes the utilization of dual-band phase offset
lines for optimizing DPA performance. Section III briefs the
design methodology of these dual-band phase offset lines.
Section IV provides the design summary of dual-band DPA,
with EM simulated results illustrating the performance enhancement using dual-band phase offset lines. The performance
is validated experimentally in Section V, with the results and
discussion provided in Section VI.
II. D UAL -BAND D OHERTY A RCHITECTURE W ITH
D UAL -BAND P HASE O FFSET L INE
The proposed architecture is based on replacing each component of a conventional single-band DPA with corresponding
dual-band components. Hence, the specifications and performance requirements of each circuit component are similar
to its respective single-band configuration, which are readily
available in the literature [24], [26]. Fig. 1 shows the schematic
of the proposed dual-band DPA. The carrier amplifier is a dualband PA biased at class AB operation. This involves a dualband matching topology in order to match a 50- load to
two arbitrary complex impedances seen by the device at two
desired frequencies of operation. Such complex impedances
are obtained by load-pull analysis of a stable GaN-based high
electron mobility transistor biased for class AB operation in
order to obtain optimum power added efficiency (PAE) at
saturation.
Once the carrier amplifier is designed, the peaking amplifier
can be developed: the peaking amplifier is similar to the
carrier amplifier circuit but biased at class C operation. After
this, a load modulation combiner is designed using Pi-type
transformers which are well known for dual-band quarter-wave
applications [33]. For a load modulation factor of 0.5, an
impedance transformer with a characteristic impedance of 50
is required and represented as transformer 1 in Fig. 1. Accordingly, transformer 2 in Fig. 1 has a characteristic impedance of
35.35 , which transforms a 50- load to 25 at junction A,
as per standard DPA architecture. A corresponding input splitter

Fig. 2. Dual-band phase offset line operation. (a) Peaking path. (b) Carrier
path.

will be designed as dual-band branch-line hybrid using Pi-type

transformers, as shown in Fig. 1.
The 50- dual-band phase offset lines in the carrier and
peaking paths, as shown in Fig. 1, are used to optimize the
overall performance of the dual-band DPA. The phase offset
line at the output of the peaking amplifier adjusts the impedance
ZP in Fig. 1 to a high value in order to avoid any power
leakage from the carrier to the peaking path. This operation is
shown in Fig. 2(a), where the 50- line shifts the corresponding
ZP to effectively open circuit points. Since, for dual-band
applications, ZP can be different, the phase shift provided by
this line at the two frequencies of the operation is different
[represented as P (f1 ) and P (f2 ) in Fig. 2(a)].
Therefore, the design requires a 50- dual-band phase offset line with arbitrary phases at the two frequencies. If the
impedance ZP is effectively open in the back-off (low-power
region), then the carrier amplifier will see 100 , which appears
due to the 50- load transformation by the two quarter-wave
transformers of 50 and 35.35 in the load-modulation circuit.
When this 100- load appears at the output of the carrier
amplifier matching network, the offset line in the carrier path
ensures that the optimum Zopt corresponding to the optimum
PAE will be seen by the device in the carrier amplifier at backoff. The operation of such offset line in the carrier path is shown

RAWAT AND GHANNOUCHI: DESIGN METHODOLOGY FOR DUAL-BAND DPA

4833

line of characteristic impedance ZS and electrical length S ,

as shown in Fig. 3(a) can be written as [33], [35]



cos
S BS ZS sin S
jZS sin S


.
j Z1S sinS 1ZS2 BS2 +2ZS BS cot S cos S BS ZS sinS
(1)
The overall effective electrical length and characteristic
impedance of the loaded structure can be derived from (1) as
A+D
= cos S BS ZS sin S
2


B
1
ZT =
= ZS
.
C
1 ZS2 BS2 + 2ZS BS cot S

cos(T ) =

Fig. 3.

Proposed schematic of the dual-band phase offset line.

in Fig. 2(b), where a 100- load is shifted to the optimum power

aided efficiency (PAE) points (A and B).
Since the optimum load condition also varies with the output
power back-off [34], a separate load-pull simulation for a carrier amplifier along with its matching networks (at the reference
plane of the output matching network) is required for back-off
power region (6-dB back-off in case of conventional Doherty
with load-modulation factor of 0.5), and various PAE contours
are plotted as shown in Fig. 2(b). Each phase offset line adds
corresponding phases in their paths; hence, an additional 50-
dual-band phase offset line is added at the input to compensate
for the phase difference in the two paths.
It is worth mentioning that these offset lines have a characteristic impedance of 50 ; hence, at saturation, the load seen
by the carrier and peaking amplifiers is 50 . Thus, the offset
will be effective only at back-off, and these offset lines do
not have any effect at saturation, thereby keeping the overall
matching conditions intact at saturation. Moreover, it is also
evident from Fig. 2(b) that it is not always possible to achieve
optimum load [represented as P AEOPT in Fig. 2(b)] with
such phase offset lines, which depends on the position of PAE
contours in the Smith chart. However, the closest point can be
achieved as shown in Fig. 2(b) for the case of frequency f2 .
This arrangement also provides an opportunity to use the same
line in the carrier path as used in the peaking path, provided that
a reasonable PAE contour can be reached in the carrier path at
back-off. Therefore, one can avoid additional phase offset line
at the input if the two similar lines are used in both carrier and
peaking paths, as shown in Fig. 1.

III. T HEORY AND D ESIGN OF D UAL -BAND O FFSET L INE

It has been demonstrated in [10], [15], and [33] that the
dispersive property of stub-loaded structure can be used to
modify its nonlinear phase response to obtain different electric
lengths (phase shifts) at different frequencies. Fig. 3 shows
the structure of the stub-loaded line proposed for dual-band
operation. The proposed structure will imitate a dual-band
line with arbitrary electric lengths T 1 and T 2 at f1 and f2 ,
respectively, while the characteristic impedance is 50 in both
frequencies. If an arbitrary stub value BS loads a transmission

(2)
(3)

If n is the frequency ratio between f1 and f2 , (3) can be

rearranged as
ZS2
= 1 K 2 (f1 ) + 2K(f1 ) cot S
ZT2
ZS2
= 1 K 2 (f2 ) + 2K(f2 ) cot nS
ZT2

@f1
@f2

(4a)
(4b)

where ZT is the effective characteristic impedance at two

frequencies and K is defined as
K(f1 ) = ZS BS (f1 )
K(f2 ) = ZS BS (f2 )

@f1
@f2 .

(5a)
(5b)

Similarly, (2) can be rearranged as

K(f1 ) sin S = cos S cos T 1
K(f2 ) sin nS = cos nS cos T 2

@f1
@f2 .

(6a)
(6b)

By substituting the corresponding values of K at f1 and f2

from (6) in (4), one can obtain
ZS = ZT

| sin T 1 |
| sin S |

@f1

ZS = ZT

| sin T 2 |
| sin nS |

@f2 . (7)

Thus, from (7), following condition can be obtained:

| sin nS |
| sin T 2 |
=
.
| sin S |
| sin T 1 |

(8)

For given values of T 1 , T 2 , and n, (8) can be solved

analytically to obtain electrical length S of the loaded line,
as given in Appendix A. Once obtaining the value of S , ZS
can be calculated from (7) for a desired value of ZT , which is
50 in the present case. Similarly, the value of K at the two
frequencies can be obtained using (6) once ZS is known. The
design parameter BS at the two frequencies is then calculated
using (5) once ZS and K are known.
Fig. 4 shows the dependence of the ratio in the right-hand
side of (8) over the values of S for different values of n
corresponding to various wireless commercial standards. It is
shown in Fig. 4 that the maximum value that can be achieved for
the ratio in (8) is decided by the frequency ratio n. The physical
length corresponding to the electrical length S is calculated at
frequency f1 .
The final step in the design is to realize BS (f1 ) and BS (f2 )
using dual-band multisection stub [35], [36] of Fig. 3(b). Such

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012

Since YA (f2 ) can also be expressed as a parallel combination

of YB (f2 ) and YC (f2 ) at node A in Fig. 3(b), the following
relation holds:
YA (f2 ) = YC (f2 ) + YB (f2 )

(11)

where YC (f2 ) is the admittance at the input of the 90 transformer in Fig. 3(b) at f2 and is given as


f2
1
YC (f2 ) = j
tan
.
(12)
ZC,OC
2 f1

Fig. 4. Range of T 1 and T 2 obtained from the proposed methodology for

different frequency ratios.

multisection stub design can be divided in two sections, as

shown in Fig. 3(b), where the first step is the realization
of the required susceptance BS (f1 ) at the input, which is
accomplished as in section 1 of Fig. 3(b). Here, f1 is the
lower frequency between f1 and f2 . In Fig. 3(b), section 1
can be depicted as a transmission line short circuit at node A.
This short circuit is realized by a 90 open-circuit stub at f1 ,
as shown in Fig. 3(b), and ensures that adding any further
section beyond this point will not affect the input admittance
at frequency f1 .
Once section 1 is realized, section 2 is designed as an
admittance which terminates section 1 at node A and emulates
susceptance BS (f2 ) at the input of section 1. This terminating
admittance is referred to as section 2 in Fig. 3(b) and can be
realized by either an open or short stub. In order to realize the
desired input admittance value of jBS (f1 ) with section 1 in
Fig. 3(b), the designer can choose a short-circuit transmission
line (short circuit at node A) with certain realizable value of
characteristic impedance ZC1 which has electric length C1
calculated as


1
C1 (f1 ) = tan1
(9)
ZC1 BS (f1 )
where BS (f1 ) can be positive or negative, depending on the
required susceptance value calculated from (5a). The value
obtained for C1 is considered at f1 in order to calculate the
physical length.
Once the design parameters for section 1 are finalized, the
value of susceptance YB is synthesized for frequency f2 . This
requires the synthesis of admittances YA (f2 ), YB (f2 ), and
YC (f2 ), as shown in Fig. 3(b).
YA (f2 ) can be obtained by de-embedding section 1 with
a known value of BS (f2 ) using a standard transmission line
impedance equation as follows:



f2
Z
B
(f
)

tan

(f
)
C1
S
2
C1
1
f1
j
 (10)

YA (f2 ) =
ZC1 1 + Z B (f ) tan (f ) f2
C1

C1

1 f1

where BS (f2 ) can be positive or negative, depending on the

required value calculated from (5b).

Thus, by using (12) in (11), one can find the required value
of YB (f2 ) as follows:


f2
1
YB (f2 ) = YA (f2 ) j
tan
(13)
ZC,OC
2 f1
where YA (f2 ) can be obtained from (10).
This synthesized value of YB (f2 ) can be realized by an open
or short stub of characteristic impedance ZC2 and electrical
length C2 , which is represented as section 2 in Fig. 3(b). If the
designer chooses a certain realizable value for the characteristic
impedance of ZC2 for this stub, its electrical length can be
given by

tan1 (Z
 C2 imag (YB (f
2 ))) , for open stub
C2 (f2 ) =
1
,
for short stub.
tan1 ZC2 imag(Y
B (f2 ))
(14)
The choice of using an open or short stub and ZC2 in (14)
depends on the realizability of YB (f2 ) with a minimum stub
length. The imaginary value of YB (f2 ) in (14) can be positive
or negative, depending on the calculated results in (13).
IV. D ESIGN OF D UAL -BAND D OHERTY A MPLIFIER AND
I TS O PTIMIZATION U SING D UAL -BAND O FFSET L INE
The dual-band DPA architecture consists of various dualband active and passive components replacing their corresponding single-band components in a conventional DPA design. The
following sections brief the design of each of these components.
A. Input Splitter and Load Combiner
A dual-band branch-line hybrid can be used as input splitter
in dual-band DPA design. Such coupler is designed with stubloading at the edges of the line, with a design methodology
reported in [33]. Since the input splitter consists of 50- and
35.35- dual-band quarter-wave transformers which are also
required in dual-band load-combiner, hence a similar methodology can be used in the design of dual-band load combiner
circuit, as shown in Fig. 1.
B. Carrier and Peaking Amplifier Designs
Similar to any conventional single-band PA design, the transistor is first biased and stabilized in the present dual-band
design using conventional methodology, as in [37]. A simple
biasing circuit for an RF PA includes an inductor that feeds dc to
the transistor but blocks ac leakage from the RF path. However,

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4835

Fig. 6. Pi-type structure as dual-band/dual-impedance quarter-wave transformer with shunt stub realized using the following: (a) open- and (b) shortcircuit transmission lines.
Fig. 5.

Dual-band matching topology.

these inductors suffer great losses due to their low-Q factors

that are further lowered when high power handling capacity is
required; therefore, the most conventional approach is to use
a transmission line based 90 transformer, short circuit at one
of its ends, realizing an effective open circuit at the other end,
connected to the RF path [37]. This behaves as a lossless path
for dc; however, effectively, no ac leaks through it. For a dualband PA design, such a 90 transformer should be dual band
with high characteristic impedance. This dual-band transformer
is designed by using a T-type structure, which is a transmission
line loaded by a stub at the center [15]. Once the transistor is
biased using this dual-band 90 transformer, a stability circuit
is designed at the input.
After stabilization, a dual-band matching network is designed to present optimum load and source impedances, which
are different at two frequencies, when terminated by a 50-
load. Several useful techniques have been proposed for such
dual-band matching [35], [36], [38][40].
Fig. 5 shows the dual-band matching topology. In the present
design, a non-50- matching technique which utilizes a dualband/dual-impedance quarter-wave transformer of two different
characteristic impedances at two frequencies has been used, as
shown in Fig. 5. According to this topology, these characteristic
impedances of the transformer are synthesized in such a manner
that, when it is terminated by certain admittances (YJ (f1 ) and
YJ (f2 ) in Fig. 5) with the real conductive part as 1/50
(represented by G0 in Fig. 5) at both frequencies, it will realize
the desired input admittances (known from load-pull analysis)
Y (f1 ) and Y (f2 ) at the two frequencies. In this technique,
the first step involves the synthesis of the required values of
the characteristic impedances ZT 1 and ZT 2 at two frequencies f1 and f2 , respectively, and the corresponding values of
the susceptances jBJ (f1 ) and jBJ (f2 ) at the reference JJ 
(in Fig. 5). Then, the values of these characteristic impedances
and susceptances are realized as given in [35]. The value of
junction admittance YJ (f ) and the required input admittance
Y (f ) are related with simple impedance inversion relationship
of a quarter-wave transformer given by

1
ZT 1 , @f1
YJ (f ) =
, where ZT (f ) =
(15)
2
ZT 2 , @f2 .
(ZT (f )) Y (f )
By putting Y (f ) and YJ (f ) in their complex forms in (15)
and by individually comparing the real and imaginary parts,
the susceptance values BJ (f ) of the junction admittances

(at reference JJ  in Fig. 5) and the required characteristic

impedances ZT (f ) of the 90 transformer (impedance inverter)
can be synthesized as follows:
B(f )
50G(f )


1

ZT (f ) = 
.

50G(f ) (GJ (f ))2 + (BJ (f ))2

BJ (f ) =

(16a)
(16b)

Once the required values of BJ (f ) are known from

(16a), these susceptance values are realized using a similar
dual-band/dual-susceptance stub as described in Section III
with design equations (9)(14). However, the dual-band/dualimpedance quarter-wave transformer is designed using the Pitype stub-loaded structure, as described in Appendix B and as
shown in Fig. 6.
Fig. 7 shows the circuit topology of the carrier and peaking
amplifiers with dual-band dc-feeds. Fig. 8 shows the performance of the carrier and peaking amplifiers at the two frequencies. Since the carrier and peaking amplifiers both have
the same architecture except the bias conditions, thus the
transconductance of the device is lower in the class C bias,
resulting into less gain and less output power as compared to
the carrier amplifier biased in a class AB mode. The carrier
amplifier is biased at drain voltage and current of 28 V and
200 mA, respectively. The gate bias of the peaking amplifier is
5.1 V in order to operate in class C operation. The peak drain
efficiencies of the carrier and peaking amplifiers are 66.1%
and 67.0%, respectively, at 1960 MHz, as shown in Fig. 8(a).
Similarly, in Fig. 8(b), the peak drain efficiencies of the peaking
and carrier amplifiers can be obtained as 61.1% and 62.2%,
respectively, at 3500 MHz. From these figures, the PAEs of
the carrier amplifier can be calculated as 54% and 49.7% at
1960 and 3500 MHz, respectively. Similarly, the PAEs of the
peaking amplifier are reported as 49.7% and 48.2% at 1960 and
3500 MHz, respectively.
C. Dual-Band Phase Offset Line Design
In order to find the design specifications for the dual-band
offset lines, the graphs similar to Figs. 2 and 3 are obtained
from the simulation of the carrier and peaking amplifiers. Fig. 9
shows the output return loss of the designed peaking amplifier
(without any offset line), which is represented as (f1 ) and
(f2 ) at the two frequencies.

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Fig. 7. Overall architecture of dual-band carrier and peaking amplifiers.

Fig. 9. Design specifications and performance of phase offset line in the

peaking path in terms of output return losses of the peaking amplifier.

Fig. 8. Performance of the carrier and peaking amplifiers. (a) At 1960 MHz.
(b) At 3500 MHz.

It can be seen from this figure that the approximate value

of phase offsets required to bring these impedances to higher
values are 55.84 and 159.68 at frequencies f1 and f2 , respectively. Fig. 10 shows the measured phase response of the dualband phase offset line.
Phase shifts of 58.87 and 163.2 at 1960 and 3500 MHz,
respectively, are reported with this phase offset line.
In the presence of this offset line, the required high impedance is achieved at the output of the peaking amplifier at

Fig. 10.

Measured phase response of the dual-band phase offset line.

back-off. This fact can also be observed in Fig. 9, where the

output impedance of the peaking amplifier is also measured in
the presence of this offset line.
Fig. 11 shows the S-parameter response of this dual-band
phase offset line. The insertion loss is less that 0.12 dB, and the
return loss is better than 38 dB at both frequencies, confirming
the characteristic impedance of 50 for these lines.

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4837

Fig. 11. Performance of dual-band phase offset line in terms of S-parameters.

Fig. 13. Effect of phase offset lines over the performance of the dual-band
Doherty amplifier. (a) At 1960 MHz. (b) At 3500 MHz.
Fig. 12. Performance of the carrier amplifier in terms of PAE at 6-dB back-off
in the presence of phase offset lines in the carrier path.

Similarly, in order to obtain the required value of phase

offset in the carrier path, a load-pull simulation of the carrier
amplifier including the matching network is done at 6-dB output
power back-off. These load-pull contours for PAE are shown in
Fig. 12. Thus, in order to bring 100 to these optimum PAE
points, dual-band offset lines with arbitrary phases are needed.
In our particular case, when a phase offset line that is the
same as the peaking path is inserted at the output of the carrier,
it shifts 100- load at back-off to the impedances corresponding to reasonable PAEs, i.e., 47.3% and 39.3% for frequencies
of 1960 and 3500 MHz, as shown in Fig. 12. However, in the
absence of this offset line, the 100- load lies on the 32%
and 36% PAE contours at frequencies of 1960 and 3500 MHz,
respectively.
Fig. 13 shows the effect of these offset lines in the electromagnetic simulation (EM) based performance of integrated
dual-band DPA at 1960 and 3500 MHz. From these figures, it
can be inferred that the absence of the offset lines at 1960 MHz
reduces the efficiency by approximately 9% at 6-dB backoff. Moreover, at 3500 MHz, the absence of offset line in
the peaking path reduces efficiency by approximately 7.8%,
whereas the absence of phase offset line in the carrier path
reduces the efficiency by 3.4% at 6-dB back-off. The reduction
of efficiency at back-off in the absence of carrier offset line is

more prominent at 1960 MHz as compared to the operation at

3500 MHz as the PAE contours are much closer to 100 in the
later case, as shown in Fig. 12.
Fig. 13 also shows the performance improvements in terms
of gain in the presence of these offset lines at 1960 and
3500 MHz, respectively.
V. E XPERIMENT AND D ESIGN C ONSIDERATIONS
In order to validate the proposed design architecture and
design methodology, each component of the dual-band DPA
is fabricated in Rogers RT 5870 board with dielectric constant
of 2.33 and loss tangent of 0.0012. The substrate thickness is
20 mil.
The photograph of the integrated DPA is shown in Fig. 14.
Table I gives the physical design parameters of the carrier
and peaking amplifiers corresponding to the topology shown
in Fig. 7. Table II lists various electrical and physical design
parameters of the 50- dual-band offset line calculated from the
design equations. The physical design parameters are obtained
corresponding to the electrical design parameters shown in
Fig. 3 using Agilent ADS Linecalc.
VI. R ESULTS AND D ISCUSSION
The fabricated dual-band DPA is measured for obtaining
various specifications at different modes of operations.

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012

Fig. 14. Photograph of the fabricated dual-band Doherty amplifier.

TABLE I
D ESIGN PARAMETERS FOR THE D UAL -BAND PA E LEMENTS

Fig. 15. Measured performance of dual-band Doherty amplifier. (a) At

1960 MHz. (b) At 3500 MHz.

TABLE II
D ESIGN PARAMETERS FOR THE D UAL -BAND P HASE O FFSET L INES

A. CW Single-Tone Operation
The fabricated dual-band DPA is measured in the presence
of continuous wave (CW) single tones at 1960 and 3500 MHz
fed at its input individually. Fig. 15 shows the performance
of dual-band DPA in comparison with class AB balanced
mode operation at 1960 and 3500 MHz. For the operation at
1960 MHz, as shown in Fig. 15(a), there was an approximately

15.3% improvement in the drain efficiency compared to the

class AB balanced mode operation at 6.6-dB back-off. The
corresponding PAE improvement is 10.7%. Fig. 15(b) shows
the measured performance of dual-band DPA in comparison
with class AB balanced mode operation at 3500 MHz. At
this frequency, the drain efficiency improvement was around
10.2%, compared to class AB balanced mode operation at
6.7-dB back-off, as shown in Fig. 15(b). The corresponding
PAE improvement is 7.1% at this back-off.
Although the proposed dual-band DPA design is optimized
for individual frequency operation, there is no theoretical limit
on the concurrent operation of such a dual-band DPA.
However, it is worth discussing here that, due to the simultaneous power fed at two carrier frequencies, the PA was
saturated faster; hence, it appears that PA performs at each
frequency as it operates nominally at a 3-dB back-off (assuming
that both driving signals have equal power levels and that the PA
has the same gain at both frequencies), in comparison with its
operation when driven by a single frequency signal. This backoff will be further enhanced if the PA has different gains at the
two different frequencies.
Fig. 16 shows the concurrent operation of the fabricated dualband Doherty amplifier. The peak drain efficiencies at saturation are 22.5% and 23.4% at 1960 and 3500 MHz, respectively,
whereas the PAE is reported as 15.8% and 17.7% at 1960 and
3500 MHz, respectively.

RAWAT AND GHANNOUCHI: DESIGN METHODOLOGY FOR DUAL-BAND DPA

Fig. 16.
mode.

4839

Measured performance of dual-band Doherty amplifier in concurrent

B. Modulated Signal Measurement

In order to test the designed dual-band DPA in the presence
of complex modulated signals, the output of the designed DPA
is measured in the presence of a single-carrier WCDMA at
1960 MHz and a 5-MHz WiMax signal at 3500 MHz, both
having a PAPR of 7 dB. Fig. 17 shows the average drain
efficiency and adjacent channel power ratio (ACPR) measured
at 5- and 10-MHz offset and plotted with respect to the average
power of complex modulated signals. This figure also shows
a slight difference between the ACPR in lower frequencies
and at higher frequencies which corresponds to memory effect
in the PA. Since the average efficiency depends on the probability density function of the modulated signal [41], it has
slightly different values from the efficiency achieved at backoff in the CW excitation. The ACPRs are better than 34 and
31 dBc at 1960 and 3500 MHz, respectively. The average
efficiencies are 42.1% and 36.8% at 1960 and 3500 MHz,
respectively. Fig. 18 shows the average efficiency and ACPR
performance in concurrent mode. It is clearly evident from
this figure that, in a concurrent mode, the average efficiency
and ACPR performance is poor as compared to individual
operation at respective frequencies. This is due to the fact
that the DPA saturates faster in simultaneous excitation by
the two signals, which also interact and result into lower
ACPR performance. The average efficiencies are 16.9% and
16.7% at 1960 and 3500 MHz, respectively, whereas the ACPR
is better than 24.7 dBc at corresponding frequencies of
operation.
In order to validate the use of the designed DPA in conjunction to DPD, the designed DPA is linearized using memory
polynomial based DPD model.
Fig. 19 shows the linearized output of DPA in the presence
and absence of DPD.
These figures show that linearized output satisfies the
spectral-mask requirements for WCDMA and WiMax signals.
With the DPD linearization, there are corresponding 25- and
20-dB improvements in terms of ACPR at 1960 and 3500 MHz,
respectively.
Table III shows the comparison of the proposed dual-band
DPA design with the current state of the art. From this table,
it can be seen that the proposed design architecture shows

Fig. 17. Measured average drain efficiency and ACPR with complex modulated signals. (a) One-carrier WCDMA signal at 1960 MHz. (b) 5-MHz WiMax
signal at 3500 MHz.

Fig. 18. Measured average drain efficiency and ACPR in concurrent operation
with one-carrier WCDMA signal at 1960 MHz and 5-MHz WiMax signal at
3500 MHz.

performance improvement in terms of efficiency as well as operating frequency range in comparison to some of the previous
works.
VII. C ONCLUSION
An architectural solution for a dual-band DPA has been proposed using dual-band offset line for efficiency improvement.

4840

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 12, DECEMBER 2012

A PPENDIX
A. Polynomial Expansion of the Ratio of Two Sinusoidals
The ratio of two sinusoidals for a range of S can be
expressed in a polynomial form as
sin(nS )
= A0 +A1 S2 +A2 S4 +A3 S6 +A4 S8 +. . . . . . Ak S2k
sin(S )
(A1)
.
where 0 < S < 2
n
Expanding sine series in each numerator and denominator of
(A1) and rearranging
(nS )5
(nS )7
(nS )3
+

+ ...
3!
5!
7!




S5
S7
S3
2
4
+

... .
= A0 + A1 S + A2 S + . . . S
3!
5!
7!
nS

(A2)
Comparing each term of S with the same order in (A2), the
value of the coefficients can be obtained as
Ak =

k1

Am
(1)k n2k+1
+ (1)k+1
;
(1)m
(2k + 1)!
(2k 2m + 1)!
m=0

where k 0 m < k. (A3)

Since these coefficients in (A3) tend to be very small for
a higher value of k, hence approximation up to five terms in
(A1) is taken, which gives sufficient accuracy in calculating S .
Thus, if the ratio in (A1) is given, then S can be obtained
by solving the polynomial expansion given in (A1) with the
coefficient values retrieved in (A3).
Fig. 19. Output power spectral density of dual-band DPA measured in the
presence and absence of DPD. (a) WCDMA signal at 1960 MHz. (b) WiMax
signal at 3500 MHz.
TABLE III
C OMPARISON W ITH S TATE OF THE A RT OF
D UAL -BAND D OHERTY A MPLIFIER

B. Dual-Band/Dual-Impedance Quarter-Wave
Transformer Design
For a Pi-type structures with stub-loading at the edges as
shown in Fig. 6, the following conditions together guarantee
that the structure will emulate 90 transmission line of characteristic impedance ZT [33], [35]:
1
ZS tan S

(B1)

ZT (f ) = ZS sin S .

(B2)

BStub (f ) =

If ZT 1 and ZT 2 are the two required characteristic impedances of a dual-band/dual-impedance quarter-wave transformer at two frequencies and n is the frequency ratio greater
than 1, then using (B2), these characteristic impedances can be
expressed as
In addition to this architecture, a novel design methodology
for the dual-band phase offset line has also been described.
Such dual-band DPA along with DPD is highly useful for SDR
transmitters in energy-efficient cognitive networks. The effect
of utilizing the dual-band phase offset lines in the dual-band
DPA architecture is validated through the design, simulation,
and measurement of a prototype.

ZT 1 = ZS sin S
ZT 2 = ZS sin nS

@f1
@f2 .

(B3)
(B4)

Equations (B3) and (B4) can be solved simultaneously to

obtain design parameters ZS and S , as shown in Fig. 6 [35].
These values are considered at frequency f1 while calculating
the corresponding physical design parameters ws,m and ls,m ,

RAWAT AND GHANNOUCHI: DESIGN METHODOLOGY FOR DUAL-BAND DPA

respectively, as shown in Fig. 7. Once these values are found,

they are used to determine the design parameters for the shunt
stub loading, depending on whether the stub is realized by an
open- or short-circuit transmission line. If ZP and P are the
characteristic impedances of the open-circuit transmission line
realizing the stub as shown in Fig. 6(a), these design parameters
can be obtained as [35]
Zp = 
Zp = 

ZT 1 ZS
ZS2 ZT2 1
ZT 2 ZS
ZS2 ZT2 2

tan P
tan(nP )

@f1
@f2 .

(B5)
(B6)

The values of ZP and P are obtained by simultaneously

solving (B5) and (B6). Similarly, for the designers choice of
using a short-circuit transmission line as stub, the electrical
design parameters ZP and P in Fig. 6(b) can be related for
the two frequencies of operation as [35]
1
ZT 1 ZS
Zp =  2
ZS ZT2 1 tan P
1
ZT 2 ZS
Zp =  2
ZS ZT2 2 tan(nP )

@f1
@f2 .

(B7)
(B8)

Equations (B7) and (B8) can be solved simultaneously to

obtain the design parameters ZP and P for the shunt stub to
be realized by a short-circuit transmission line.
The design parameters ZP and P for the shunt stub are
considered at frequency f1 while calculating the corresponding
physical design parameters wp,m and lp,m , respectively, in
Fig. 7. The input matching network in Fig. 7 utilizes the stubloaded structure of Fig. 6(b), while the output matching network
of Fig. 7 is realized using the stub-loaded structure of Fig. 6(a).
ACKNOWLEDGMENT
The authors would like to thank J. Shelley and T. Bata for
their technical assistance in manufacturing the prototypes; the
reviewers and the associate editor for their suggestions and
comments, making this paper more technically informative and
enhancing its readiness; and the members of iRadio Laboratory,
University of Calgary, particularly R. Darraji, for the technical
discussions.
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Karun Rawat (M08S09) received the B.E. degree in electronics and communication engineering
from Meerut University, Meerut, India, in 2002. He
is currently working toward the Ph.D. degree in the
Department of Electrical and Computer Engineering, Schulich School of Engineering, University of
Calgary, Calgary, AB, Canada.
He worked for the Indian Space Research Organization from 2003 to 2007. After that, he joined
the iRadio Laboratory, Schulich School of Engineering, University of Calgary, where he is a Student
Research Assistant. He is also a Reviewer of several reputed journals in the
field of electrical engineering. His current research interests are in the areas
of microwave active and passive circuit design, and advanced transmitter and
receiver architecture for software-defined radio applications.

Fadhel M. Ghannouchi (S84M88SM93F07)

received the B.Eng. degree in engineering physics
and the M.S. and Ph.D. degrees in electrical engineering from the Ecole Polytechnique de Montreal,
Montreal, QC, Canada, in 1983, 1984, and 1987,
respectively.
He is currently a Professor and iCORE/CRC Chair
with the Department of Electrical and Computer
Engineering, Schulich School of Engineering, University of Calgary, Calgary, AB, Canada, and the
Director of the Intelligent RF Radio Laboratory. He
has held numerous invited positions at several academic and research institutions in Europe, North America, and Japan. He has provided consulting
services to a number of microwave and wireless communications companies.
He has authored or coauthored over 400 publications. He is the holder of ten
U.S. patents, with three pending. His research interests are in the areas of microwave instrumentation and measurements, nonlinear modeling of microwave
devices and communications systems, design of power- and spectrum-efficient
microwave amplification systems, and design of intelligent RF transceivers and
SDR radio systems for wireless and satellite communications.