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machine
design
inst. set design (Ch 3)
Arithmetic (Ch 4)
technology
R-type
I-type
J-type
26
21
op
6 bits
31
26
11
rt
5 bits
21
op
6 bits
31
16
rs
5 bits
rd
5 bits
shamt
5 bits
funct
6 bits
16
rs
5 bits
0
immediate
rt
5 bits
16 bits
26
op
6 bits
target address
26 bits
26
21
16
11
5 bits
5 bits
0
funct
6 bits
16 bits
= MEM[ PC ]
inst
Register Transfers
ADD
PC < PC + 4
SUB
PC < PC + 4
OR
PC < PC + 4
LOAD
STORE
BEQ
Combinational Elements
Storage Elements
Clocking methodology
Data
PC
Address
Instruction
memory
Instruction
Register #
Registers
Register #
ALU
Address
Data
memory
Register #
Data
Adder
32
Adder
B
Sum
Carry
32
Selec
t
A
32
MUX
MUX
32
32
32
O
P
32
ALU
ALU
32
Result
32
cycle time
rising edge
_
Q
D-latch
Two inputs:
the data value to be stored (D)
the clock signal (C) indicating when to read & store D
Two outputs:
the value of the internal state (Q) and its complement
C
D
_
Q
Q
D flip-flop
Output changes only on the clock edge
D
C
D
latch
Q
D
latch _
C
Q
Q
_
Q
Our Implementation
An edge triggered methodology
Typical execution:
read contents of some state elements,
send values through some combinational logic
write results to one or more state elements
State
element
1
Combinational logic
State
element
2
Clock cycle
State
element
Combinational logic
Register File
Built using D flip-flops
Read register
number 1
Read register
number 1
Register 0
Register 1
M
u
x
Register n 1
Register file
Read data 1
Write
register
Read
data 2
Register n
Write
data
Read register
number 2
M
u
x
Read
data 1
Read register
number 2
Write
Read data 2
Register File
Note: we still use the clock to determine when to write
Write
0
R egister n u mber
C
R e gi ster 0
n-to-1
deco der
n 1
R e gi ster 1
D
C
Register n 1
D
C
R e gi ster n
R e gi st er d at a
10
RWRARB
Write Enable 5 5 5
11
Clocking Methodology
Clk
Setup
Hold
Setup
Hold
.
.
.
.
.
.
Dont Care
.
.
.
.
.
.
Step 3
12
Instruction
address
PC
Instruction
Add Sum
Instruction
memory
a. Instruction memory
b. Program counter
c. Adder
13
Add
4
Read
address
PC
Instruction
Instruction
memory
26
op
6 bits
5
Register
numbers
5
5
Data
21
16
rs
5 bits
Read
register 1
rt
5 bits
11
rd
5 bits
6
shamt
5 bits
0
funct
6 bits
ALU control
Read
data 1
Read
register 2
Registers
Write
register
Read
data 2
Write
data
Data
Zero
ALU ALU
result
RegWrite
a. Registers
b. ALU
14
Read
register 1
Read
data 1
Read
register 2
Registers
Write
register
Read
data 2
Write
data
Instruction
ALU operation
Zero
ALU ALU
result
RegWrite
Register-Register Timing
Clk
PC
Old Value
Clk-to-Q
New Value
Old Value
ALUctr
Old Value
RegWr
Old Value
busA, B
Old Value
busW
Old Value
Rd Rs Rt
RegWr 5 5
5
Rw Ra Rb
32 32-bit
Registers
Register Write
Occurs Here
busA
32
busB
32
ALU
busW
32
Clk
ALUctr
Result
32
15
26
op
6 bits
21
rs
5 bits
16
rt
5 bits
0
immediate
16 bits
MemWrite
Read
data
Address
Write
data
16
Data
memory
Sign
extend
32
MemRead
a. Data memory unit
b. Sign-extension unit
Read
register 1
Instruction
ALU operation
MemWrite
Read
data 1
Read
register 2
Registers
Write
register
Read
data 2
Write
data
Zero
ALU ALU
result
Address
Write
data
RegWrite
16
Sign
extend
32
Read
data
Data
memory
MemRead
16
26
op
6 bits
21
rs
5 bits
16
rt
5 bits
0
immediate
16 bits
if (COND eq 0)
Calculate the next instructions address
PC <- PC + 4 + ( SignExt(imm16) x 4 )
else
PC <- PC + 4
Branch target
Shift
left 2
Instruction
Read
register 1
Read
register 2
Registers
Write
register
Write
data
ALU operation
Read
data 1
ALU Zero
To branch
control logic
Read
data 2
RegWrite
16
Sign
extend
32
17
Add
4
PC
Read
register 1
Read
address
Instruction
Instruction
memory
Registers
3
Read
register 2
Read
data 1
Write
register
Read
data 2
ALU operation
MemtoReg
ALUSrc
M
u
x
Write
data
Zero
ALU ALU
result
Address
Sign 32
extend
Read
data
M
u
x
Data
memory
Write
data
RegWrite
16
MemWrite
MemRead
Add
Add ALU
result
4
Shift
left 2
PC
Read
address
Instruction
Instruction
memory
Registers
Read
register 1
Read
Read
data 1
register 2
Write
register
Write
data
RegWrite
16
ALUSrc
Read
data 2
Sign
extend
M
u
x
ALU operation
Zero
ALU ALU
result
MemWrite
MemtoReg
Address
Read
data
Data
Write memory
data
M
u
x
32
MemRead
18
contd
PCSrc
Add
ALU
Add result
4
Shift
left 2
RegWrite
Instruction [25 21]
Read
address
Instruction
[31 0]
PC
Instruction
memory
Read
register 1
Read
register 2
Read
data 1
MemWrite
ALUSrc
Read
Write
data 2
register
Write
Registers
data
1
M
u
Instruction [15 11] x
0
RegDst
Instruction [15 0]
16
1
M
u
x
0
1
M
u
x
0
Sign 32
extend
Zero
ALU ALU
result
MemtoReg
Address
Read
data
Data
Write
data memory
ALU
control
1
M
u
x
0
MemRead
Instruction [5 0]
ALUOp
Control
Read
address
Instruction
memory
PCSrc
Read
register 1
Shift
left 2
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
ALU ALU
result
Address
Write
data
Instruction [15 0]
16
Sign
extend
Read
data
Data
memory
1
M
u
x
0
32
ALU
control
Instruction [5 0]
19
Ideal
Instruction
Memory
Instruction
Rd Rs
5
5
Instruction
Address
Rt
5
Imm
16
A
32
Rw Ra Rb
32 32-bit
Registers
PC
32
32
ALU
Next Address
Clk
Data
In
Ideal
Data
Memory
Clk
32
Clk
Data
Address
Rd
<0:15>
Rs
<11:15>
Rt
<16:20>
Op Fun
<21:25>
Adr
<21:25>
Inst
Memory
Imm16
Control
Zero
DATA PATH
20
Control
Selecting the operations to perform (ALU, read/write, etc.)
Design the ALU Control Unit
Controlling the flow of data (multiplexor inputs)
Design the Main Control Unit
Information comes from the 32 bits of the instruction
Example:
add $8, $17, $18
Instruction Format:
rs
rt
01000
rd
00000 100000
shamt
funct
ALU Control
e.g., what should the ALU do with this instruction
Example: lw $1, 100($2)
35
op
rs
rt
100
16 bit offset
AND
OR
add
subtract
set-on-less-than
21
ALUOp
Instruction
operation
Funct field
Desired
ALU action
ALU control
input
LW
00
Load word
xxxxxx
Add
010
SW
00
Store word
xxxxxx
Add
010
BEQ
01
Branch eq
xxxxxx
Subtract
110
R-type
10
Add
100000
Add
010
R-type
10
Subtract
100010
Subtract
110
R-type
10
AND
100100
And
000
R-type
10
OR
1000101
Or
001
R-type
10
Set on less
than
101010
Set on less
than
111
Control
Must describe hardware to compute 3-bit ALU control input
given instruction type
00 = lw, sw
ALUOp
01 = beq
computed from instruction type
10 = arithmetic
function code for arithmetic
Describe it using a truth table (can turn into gates):
ALUOp
ALUOp1 ALUOp0
0
0
X
1
1
X
1
X
1
X
1
X
1
X
F5
X
X
X
X
X
X
X
Funct field
F4 F3 F2 F1
X X X X
X X X X
X 0 0 0
X 0 0 1
X 0 1 0
X 0 1 0
X 1 0 1
Operation
F0
X
X
0
0
0
1
0
010
110
010
110
000
001
111
22
Control Signals
1. RegDst = 0 => Register destination number for the Write register
comes from the rt field (bits 20-16)
RegDst = 1 => Register destination number for the Write register
comes from the rd field (bits 15-11)
2. RegWrite = 1 => The register on the Write register input is written with
the data on the Write data input (at the next clock edge)
3. ALUSrc = 0 => The second ALU operand comes from Read data 2
ALUSrc = 1 => The second ALU operand comes from the signextension unit
4. PCSrc = 0 => The PC is replaced with PC+4
PCSrc = 1 => The PC is replaced with the branch target address
5. MemtoReg = 0 => The value fed to the register write data input comes
from the ALU
MemtoReg = 1 => The value fed to the register write data input comes
from the data memory
6. MemRead = 1 => Read data memory
7. MemWrite = 1 => Write data memory
23
R-format instructions
RegDst = 1
RegWrite = 1
ALUSrc = 0
Branch = 0
MemtoReg = 0
MemRead = 0
MemWrite = 0
ALUOp = 10
Load word
RegDst = 0
Store Word
RegDst = X
RegWrite = 1
RegWrite = 0
ALUSrc = 1
ALUSrc = 1
Branch = 0
Branch = 0
MemtoReg = 1
MemtoReg = X
MemRead = 1
MemRead = 0
MemWrite = 0
MemWrite = 1
ALUOp = 00
ALUOp = 00
24
Branch Equal
RegDst = X
RegWrite = 0
ALUSrc = 0
Branch = 1
MemtoReg = X
MemRead = 0
MemWrite = 0
ALUOp = 01
Control
0
M
u
x
Add
Add
4
Instruction [31 26]
Control
Read
address
Instruction
memory
Shift
left 2
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite
Read
register 1
ALU
result
0
M
u
x
1
Read
data 1
Read
register 2
Registers Read
Write
data 2
register
0
M
u
x
1
Write
data
Zero
ALU ALU
result
Address
Write
data
Instruction [15 0]
16
Sign
extend
Read
data
Data
memory
1
M
u
x
0
32
ALU
control
Instruction [5 0]
25
Inputs
Op5
Op4
Op3
Op2
Op1
Op0
ALUOp
ALU control block
ALUOp0
Outputs
ALUOp1
R-format
F3
F2
Iw
sw
beq
Operation2
RegDst
ALUSrc
MemtoReg
Operation
Operation1
RegWrite
F (5 0)
F1
MemRead
Operation0
MemWrite
F0
Branch
ALUOp1
ALUOpO
State
element
1
Combinational logic
State
element
2
Clock cycle
26
Ideal
Instruction
Memory
Instruction
Rd Rs
5
5
Instruction
Address
Rt
5
Imm
16
A
Rw Ra Rb
32 32-bit
Registers
PC
32
32
32
ALU
Next Address
Data
Address
Data
In
Clk
Clk
32
Clk
Ideal
Data
Memory
Add
ALU
Add result
4
RegWrite
Instruction [25 21]
PC
Read
address
Instruction
[31 0]
Instruction
memory
Read
register 1
Read
register 2
Read
data 1
Read
data 2
Write
register
Write
data Registers
16
Sign 32
extend
1
M
u
x
0
Shift
left 2
MemWrite
ALUSrc
1
M
u
x
0
ALU
control
Zero
ALU ALU
result
MemtoReg
Address
Read
data
Data
Write
data memory
1
M
u
x
0
MemRead
Instruction [5 0]
ALUOp
27
Summary
5 steps to design a processor
Single cycle datapath => CPI=1, Clock Cycle Time => long
28