UCC28070

Application Report
SLUA479B August 2008 Revised July 2010
UCC28070 300-W Interleaved PFC Pre-Regulator Design

Review
MIchael O'Loughlin ........................................................................ PMP - Power Supply Control Products
ABSTRACT
In higher power applications to utilize the full line power and reduce line current harmonics PFC
Pre-regulators are generally required. In these high power applications interleaving PFC stages can
reduce inductor volume and reduce input and output capacitor ripple current. This results in smaller overall
magnetic volume and filter capacitor volume increasing the converters overall power density. This is made
possible through distributing the power over two interleaved boost converters and the inductor ripple
current cancellation that occurs with interleaving, reference [5]. This application note will review the design
of a 300W two-phase interleaved power factor corrected (PFC) pre-regulator. This power converter
achieves PFC with the use of the UCC28070 interleaved PFC controller, reference [7].
Design Goals
The specifications for this design were chosen based on the power requirements of a medium power LCD
TV.
Table 1. Design Specifications
PARAMETER
VIN
RMS input voltage
VOUT
Output voltage
MIN
85
(VIN_MIN)
MAX
UNITS
265
(VIN_MAX)
63
Hz
300
390
47 Hz
(fLINE)
Line frequency
PF
Power factor at maximum load
POUT
Output power
Full load efficiency
fs
Individual phase switching frequency
TYP
0.90
90%
200
UCC28070 300-W Interleaved PFC Pre-Regulator Design Review

Copyright 20082010, Texas Instruments Incorporated
kHz
Schematic
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Schematic
UCC28070 PFC controller in a two-phase average current mode control interleaved PFC pre-regulator.
DB
Vin
IIN
L1
IL1
DPA2
VOUT
D1
DRA
RFA
COUT
T1
1k
CFA
GDA
RTA
RFB
VCC=13V
DPA1
CTA
GDB
CCDR
RB1
UCC28070
DMAX 20
CDR
RDM
VAO
T2
L2
VINAC
GND 16
IMO
VCC 15
RSYNTH
CSB
CSA
PKLMT
IL2
T2
RA2
GDB 17
12V to 21V
Q2
CB4
RB2
GDA 14
CAOA
12
CAOB
11
RZCB
RSYN
RPK2
1.2nF
VREF 13
RIMO
RRDM
RZV
RR
SS 18
VSENSE
RPK1
CPV
CRR
RT 19
10
CB1
RSB
Q1
D2
DPB1
1.2nF
DRB
4.7pF
RTB
CZV
T1
220pF
DPB2
CTB
RR
CRR
4.7pF
1k
CFB
ROB
RA1
RSA
220pF
ROA
CB2
0.1uF
CB3
CSS
RRT
RDMX
0.1uF
CPCB
RZCA
CPCA
CZCB
CZCA
Figure 1. Typical Average Current Mode Interleaved PFC Pre-Regulator

Inductor Selection
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Inductor Selection
One of the benefits of interleaved PFC boost pre-regulators is inductor ripple current reduction that is seen
at the input of the converter. The following equations and Figure 2 show the ratio of input ripple current
(IIN) to individual inductor ripple current (IL1) in a two-phase interleaved PFC as a function of duty cycle
(D). Because of this inductor ripple current cancellation, the designer can allow each inductor to have
more inductor ripple current than in a single stage design.
K(D) =
DIIN
DIL1
(1)
K(D) =
1- 2D
if D is < 05 = 0.5
1- D
(2)
K(D) =
2D - 1
if D is > 0.5
D
K(D)=DIIN/DIL1
(3)
D - Duty Cycle
Figure 2. Input Inductor Ripple Current Cancellation

The boost inductors (L1 and L2) are selected based on the maximum allowable input ripple current. In
universal applications (e.g., 85 V to 265 V RMS input) the maximum input ripple current occurs at the
peak of low line and for this design the maximum input ripple current was set to 30% of the peak nominal
input current at low line.

Inductor Selection
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The following calculations are used to select the appropriate inductance for L1 and L2. Where, variable
DPLL is the converters duty cycle at the peak of low line operation. Variable K(DPLL) is the ratio of input
current to inductor ripple current at the peak of low line operation. IL is the boost inductor ripple current
at the peak of low line based on the converters input ripple current requirements.
DPLL =
VOUT - VIN_MIN 2
VOUT
390V - 85V 2
0.69
390 V
(4)
K(DPLL ) =
DIL =
2 0.69 - 1
= 0.55
0.69
POUT 2 0.3
300W 2 0.3
3.0 A
=
VIN_MIN h K(DPLL )
85V 0.90 0.55
L1 = L2 =
VIN_MIN
2 DPLL
DIL f s
85V 2 0.69
140 uH
2.96A 200 kHz
(5)
The following equation can be used to calculate total inductor RMS current (IL1_RMS and IL2_RMS).
IL1_RMS = IL2_RMS
POUT
2
VIN_MIN h
VIN_MIN 2sin(q ) VOUT - VIN_MIN 2sin(q )
1p
L1 f s
VOUT
+
12
p 0
(6)
IL1_RMS = IL2_RMS
2
85V 2sin(q )
390V - 85V 2sin(q )
300W
1
140uH 200kHz
390V
2
=
+
12
85V 0.90 p 0
2A
(7)
A 140-mH boost inductor from Cooper Electronic Technologies part number CTX16-18060 was chosen for
the design. The inductance during normal operation will swing from 140mH to 350mH.
L1MIN = L2MIN = 140 uH
(8)
L1MAX = L2MAX = 350 uH

(9)
The average inductance is calculated for current loop compensation purposes. This will be used in the
current loop compensation section of the application note:
L1AVG = L2AVG =
L1MIN + L1MAX
140 uH + 350 uH
=
= 245 uH
2
2
(10)

Output Capacitor Selection
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Output Capacitor Selection

The output capacitor (COUT) is selected based on holdup requirements.
COUT
2 POUT
fLINE
VOUT 2 - (VOUT 0.75)2
2 300W
47 Hz
=
192 uF
2
2
(390V) - (292.5V )
(11)
Two 100-mF capacitors were used in parallel for the output capacitor.
COUT = 200 F
(12)
For this size capacitor the output peak to peak voltage ripple (VRIPPLE) is:
VRIPPLE
2 300W
2 POUT
1
0.90
=
=
14.5V
h
VOUT 2p 2fLINE COUT
390V 2 2 47Hz 200 F
(13)
In addition to holdup requirements, a capacitor must be selected so that it can withstand both the
low-frequency RMS current (ICOUT_LF) and the high-frequency RMS current (ICOUT_HF). High-voltage
electrolytic capacitors generally have both low frequency (100 Hz to 120 Hz) and high frequency RMS
current ratings on their data sheets.
ICOUT_LF =
POUT
h VOUT 2
300W
0.90 390V
0.604A
(14)
ICOUT_HF
P
= OUT
h VOUT
16 VOUT
6p VIN_MIN
- h - ICOUT_LF
(15)
300W
ICOUT_HF =
0.90 390V
2
- (0.90)2 - (0.604 ) 1.0A
6p 85V 2
16 390V
(16)

Power Semiconductor Selection (Q1, Q2, D1, D2)
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Power Semiconductor Selection (Q1, Q2, D1, D2)

The selection of Q1, Q2, D1, and D2 are based on the power requirements of the design. Application note
(SLUA369), UCC28528 350-W Two Phase Interleaved PFC Pre-regulator, explains how to select power
semiconductor components for interleaved PFC pre-regulators using average current mode control
techniques, reference [4]. To meet the power requirements of this design IRFB11N50A N channel FETs
from IR were chosen for Q1 and Q2. To reduce reverse recovery losses SiC diodes CSD10060G from
CREE were chosen for the design.
Boost Diode (D1, D2) and FET (Q1, Q2) peak current (IPEAK) calculation:
A factor of 1.2 was added to the equation for added design margin.
POUT 2
DI
IPEAK =
+ L1 1.2 =
2 VIN_MIN h
2
300W 2
2.97A
+
1.2 5.1A
2
2 85V 0.90
(17)
Q1 and Q2 RMS current (IDS) calculation:
IDS =
POUT
2 VIN_MIN 2
2 -
16 VIN_MIN 2
3 p VOUT
300W
16 85V 2
0.90
=
2 1.685A
3 p 390V
2 85V 2
(18)
D1 and D2s average current calculation (ID):

ID =
POUT
300W
=
0.39A
VOUT
2 390V
(19)

Current Sense Transformers Setup and Selection (T1, T2, DRA, DRB)
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The current sense transformer is selected to handle IPEAK and have a peak current sense signal (IRS) of
roughly 100 mA.
NCT =
NS
I
5.1A
PEAK =
= 51
NP
IRS
0.1A
(20)
For this design a current sense transformer with a turns ratio (NCT) of 50 was chosen for the design.
NCT = 50
(21)
The magnetizing inductance (LM) of the current sense transformer should be selected or designed so the
magnetizing current is less than 2% of the maximum current sense signal. The following equation
calculates the minimum LM where VS is the maximum current sense signal voltage. For this design a
current sense transformer was designed by Cooper Electronic Technologies (CTX16-18294) with a
magnetizing inductance of 8.25 mH.
LM
VOUT - VIN_MIN 2
VS
3.7V
390V - 85V 2
6.24mH
=
IPEAK
5.1A
VOUT
390V
0.02 200kHz
0.02 f s
50
NCT
(22)
LM = 8.25 mH
(23)
Selection of the current sense resistors (RSA and RSB ) is based on the peak current limit signal (VS) and
the peak current on the secondary side of the current sense transformer. A factor of 0.9 was multiplied by
the current sense signal to leave room for the 10% PWM ramp that is used to make this design more
noise immune at lighter loads.
RSA = RSB =
0.9 VS
0.9 3.7V 50
=
32.5 W
IPEAK
0.102A
NCT
(24)
Select a standard resistor for the design:

RS = 33.2 W
(25)
Resistor RR is used to reset the current sense transformer:

RR
RS DMAX
33.2 W 0.97
=
; 1 kW
1 - DMAX
1 - 0.97
(26)
Current sense transformers rectifying diodes (DR) need to be designed to withstand the current sense
transformers reset voltage (VR):
VR = IPEAK
NP
5.1A 1 kW
RR =
103V
NS
50
(27)

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To improve noise immunity at extremely light loads, a PWM ramp with a dc offset is recommended to be
added to the current sense signals. Electrical components RTA, RTB, CTA, CTB, DPA1, DPA2, DPB1, and DPB2
form a PWM ramp that is activated and deactivated by the gate drive outputs of the UCC28070. Resistor
ROA and ROB add a DC offset to the CS resistors (RSA and RSB).
When the inductor current becomes discontinuous the boost inductors ring with the parasitic capacitances
in the boost stages. This inductor current rings through the CTs causing a false current sense signal.
Refer to the following graphical representation of what the current sense signal looks like when the
inductor current goes discontinuous. Note that the inductor current and VRSA may vary from this graphical
representation depending on how much inductor ringing is in the design when the unit goes discontinuous.
GDA
IL1
0A
VRSA
VOFF
0V
Discontinues Current Causes False Current Sense Signal
Figure
3. False Current Sense Signal

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To properly select the offset (VOFF) just requires adjusting resistors ROA and ROB to add a dc offset to the
current sense resistors, that is high enough to block DRA and DRB from conducting when a false current
sense signals is present. This occurs when the inductors are operating with discontinuous inductor current
and was described above in detail. Setting the offset to 200 mV is a good starting point and may need to
be adjusted based on individual design criteria and the amount of noise and parasitic elements present in
the system.
VOFF = 0.2 V
(28)
ROA = ROB =
(VVCC
- VOFF )RSA
VOFF
(13V
- 0.2V ) 33.2
0.2V
2.1 kW
(29)

ROA = 2.05 kW
(30)
RTA =RTB =
(VVCC - (Vs 0.1- VOFF +VDPA2 )RSA (13V - (3.7V 0.1- 0.2V)+0.6V ) 33.2
Vs 0.1- VOFF
3.7V 0.1- 0.2V
2.62 kW
(31)
Chose a standard resistor for the design:

RTA = RTB = 2.49 kW
(32)
CTA = CTB =
RSA
1
50 nF
fS 3
(33)
A standard capacitor needs to be chosen for the design:

CTA = 47 nF
(34)

Setting Up Peak Current Limiting (RPK1, RPK2)
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Setting Up Peak Current Limiting (RPK1, RPK2)

The UCC28070 has an adjustable peak current limit comparator that can be set up by selecting RPK1 and
calculating the required RPK2. For this design to keep the reset voltage of the current sense transformer
manageable the peak current sense signal (VS) was set to 3.7 V.
RPK2 =
VS RPK1
3.7V 3.65 k
=
5.9 kW
VREF - VS
6V - 3.7V
(35)
Converter Timing and Maximum Duty Cycle Clamp

Resistor RRT and RDMX set up converter timing and the maximum PWM duty cycle clamp:
RRT =
7.5 109 W Hz
7.5 109 W Hz
=
= 37.5 kW
fs
200 kHz
(36)
A standard resistor was selected for the design:

RRT = 37.4 kW
(37)
Resistor RDMX was selected to set the maximum duty cycle clamp (DMAX) to 0.97:
RDMX = RRT (2 DMAX - 1) = 37.4 k (2 0.97 - 1) = 35 k W
(38)
Chose a standard resistor for the design:

RDMX = 34.8 kW
(39)
Programming VOUT
Resistor RA is selected to minimize the error due to VSENSE input bias current and to minimize loading on
the power line when the PFC is disabled. Construct resistor RA from two or more resistors in series to
meet high voltage requirements. Resistor RB is sized to program the converters output voltage (VOUT).
RA = 3M W
(40)
VREF
RA
3V 3M
2
RB =
=
23.3 kW
VREF
390V
3V
VOUT 2
(41)
A standard resistor was chosen for the design.

RB = 23.2 kW
(42)
The resistor divider formed by RA and RB from the output voltage to the VSENSE pin also sets the over
voltage protection threshold (VOVP).
VOVP = 3.18V
R A + RB
3MW + 23.2 kW
= 3.18V
414V
RB
23.2 kW
(43)
10

VINAC Divider Setup
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VINAC Divider Setup

The UCC28070 also requires sensing the line input for proper operation. This requires a divider from the
rectified line voltage to the VINAC pin of the UCC28070. For simplicity the UCC28070 was designed to
use the same resistor divider values as the VSENSE pin. Resistors RA and RB need to be the same ratio
for the VINAC voltage divider as thouse in the VSENSE voltage divider to ensure the UCC28070 controller
operates correctly. Please refer to the applications schematic for proper component placement.
10
Voltage Loop Configuration

The methodology used to compensate the voltage loop is based on the compensation methodology
developed by Lloyd Dixon. A detailed explanation of this compensation scheme written by Mr. Dixon can
be found in the 1990 Unitrode Power Supply Design SEM700, High Power Factor Switching Pre-regulator
Design Optimization, Topic 7, reference [2].
Capacitor CPV is sized to attenuate low frequency ripple to less than 3% of the voltage amplifier output
range. This will ensure good power factor and low input current harmonic distortion.
Voltage Amplifier Transconductance Amplifier gain:
gmV = 70 m S
(44)
Voltage Divider Feedback Gain:

H=
VVREF
3V
=
0.0077
VOUT
390V
(45)
Output impedance (ZO) is required to attenuate the low frequency boost capacitor output ripple (VRIPPLE) to
less than 3% of the effective voltage amplifier output range (VAO). This impedance is set by properly
selecting feedback capacitor CPV:
ZO =
3.2V 0.03
DVAO 0.03
=
12.3 kW
VRIPPLE H gmV
14.5V 0.0077 70 m S
(46)
CPV =
1
1
=
138nF
2p 2 fLINE Zo 2p 2 47Hz 12.3kW
(47)
Choose as standard capacitor for the design:

CPV = 150 nF
(48)

11
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For the highest possible power factor the voltage loop crossover frequency (fCV) needs to be set based on
the following equation:
DVAO = 3.2 V
(49)
fCV = H gmV
1
POUT
j 2p COUT
1
VOUT
2 p CPV
DVAO
(50)
fCV
300W
1
1
= 0.0077 70m S 0.90
11Hz
3.2V 2 p 200mF 390V 2 p 150nF
(51)
Voltage compensation resistor RZV is then sized to put a pole at the converters voltage loop crossover
frequency:
R ZV =
1
1
=
96.4 kW
2p fCV CPV
2p 10.6Hz 150nF
(52)

R ZV = 100 kW
(53)
Voltage compensation capacitor CZV is used to increase the dc gain of the voltage loop and gives some
added phase margin before crossover. The zero added to the voltage loop needs to be set at 1/10th the
crossover frequency.
CZV =
1
1
1.5 mF
=
11Hz
fCV
2p
100 kW
2p
R ZV
10
10
(54)
12

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The following equations can be used to estimate voltage compensation network gain, voltage loop power
stage gain and voltage loop gain. These equations can also be used to graphically check loop stability.
Voltage Compensation Network Gain (GCV(f)) as function of frequency:
GCV (f ) =
DVVAO
= H gmV
DVOUT
j 2p f R ZV CZV +1
CZV CPV
+1
(j 2p f (CZV + CPV )) j 2p f C RZV
ZV +CPV
(55)
Voltage Loop Power Stage Gain (GPSV(f)) as function of frequency:
GPSV (f ) =
DVOUT
DVVAO
1
POUT
j 2p f COUT
VOUT
DVAO
(56)
Voltage Loop Gain in dB (TvdB(f)) as function of frequency:

TvdB( f ) = 20log (GPSV ( f ) GCV ( f ) )
(57)
Figure 4 shows the theoretical loop gain (TvdB(f)) as a function of frequency and Figure 5 shows the
theoretical loop phase (qv(f)) as a function of frequency. From these figures it can be observed that the
voltage loop crossed over at roughly 9 Hz with a phase margin of 60 degrees. Compensating the voltage
loop is not an exact science and should be checked with a network analyzer and adjusted if necessary.
90
90
90
90
60
75
30
TvdB ( f)
60
qv( f)45
30
30
60
15
- 90
90
1
1
10
100
f
3
1 .10
110
0
0
1
1
Figure 4. Theoretical Voltage Loop Gain (TvdB(f))
10
1 .10
100
f
110
Figure 5. Theoretical Voltage Loop Phase (qv(f))

13
Current Loop Compensation
11
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Setting up the current synthesizer is accomplished by correctly selecting RSYN:
The inductor used in this design example swings from 350 mH to 140 mH from no load to maximum load.
When calculating RSYN the highest inductance value (L1MAX) should be used.
RB
23.2 kW
50 350 mH
R A + RB
3
M
+ 23.2 kW 40.5 kW
W
=
33.2W 0.1nF
0.1 nF
NCT L1MAX
RSYN =
RS
(58)
Chose a standard resistor:

RSYN = 38.3 kW
(59)
The IMO resistor needs to be set with the following equation to center the digitized multiplier for universal
line applications:
IMO =
17 10-6 A VINAC (VVAOMAX - 1V )

K VFF
17 10-6 A 0.76V (5V - 1V )

0.398V 2
130 m A
(60)
VI =
0.76V (R A + RB )
RB
0.76V (3MW + 23.2kW)

23.2kW
70V
(61)
V2 =
1.1 POUT 2
1
1.1 300W 2
1
RS =
33.2W 2.458V
NCT
2 h V 1
2 0.92 72V 50
(62)
RIMO =
V2
2.458 V
=
18.9kW
IMO
130 m A
(63)
Choose a standard resistor close to the calculated value:

RIMO = 19.6 kW
(64)
th
th
The current loop in a PFC converter is generally designed to crossover at between 1/10 and 1/6 the
converters switching frequency. The current loop in this design example is going to be designed to
crossover at 1/10th of the single stages switching frequency. In order to properly compensate the current
loop it is required to calculate the current loop's power stage gain (GPS) at the current loop's crossover and
properly select passive components RZC1/2, CZC1/2 and CPC1/2:
VOUT RS
GPSC =
2p
1
NCT
fs
L1AVG VRAMP
10
390 V 33.2W
=
2p
1
50
200 kHz
245 mH 4.0V
10
2.1
(65)
14

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Variable gmC is the current amplifier Transconductance Current Amplifier Gain.

gmC = 100 m S
(66)
R ZC1 = R ZC2 =
gmC
1
1
=
= 4.8 kW
GPSC
100 m S 2.1
(67)
CZC1 = CZC2 =
1
1
1.7nF
=
fs
200 kHz
4.8 kW
2p
2p
R ZC
10
10
(68)
CPC1 = CPC2 =
1
1
333 pF
=
fs
200 kHz
2p
R ZC
2p
4.8 kW
2
2
(69)
Standard components close to the calculated values are chosen for the current loop compensation:
R ZC1 = 4.02 kW, CZC1 = 2.2 nF, CPC1 = 330 pF
(70)
Graphically Check Theoretical Current Loop Gain (TcdB(f)) and loop phase (qc(f)): From the plots in
Figure 6 and Figure 7 it can be observed that the theoretical loop gain crossed over at roughly 20 kHz
with a phase margin of roughly 39 degrees.
VOUT Rs P
NS
j 2p f R ZC CZC +1
TcdB(f ) = 20log
gmC
j 2p f L1 DVRAMP
j
2
R
C
C
p
f
ZC
ZC
PC
j 2p f (CZC +CPC ))
+1
(
CZC +CPC
(71)
200
180
200
180
133.33
150
66.67
120
TcdB( f)
qc( f) 90
66.67
60
133.33
- 200
30
200
1
10
100
1 .10
1 .10
1 .10
1 .10
6
110
0
0
1
10
Figure 6. Current Loop Gain (TdB(f))
100
1 .10
1 .10
1 .10
1 .10
6
110
Figure 7. Current Loop Phase (qc(f))

15
Soft Start
12
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Soft Start
To have a controlled soft start the CSS capacitor needs to be set to at least the same value as the CZV
capacitor or larger. This means the design has a minimum soft start time based on the CZV capacitor
t SSMIN =
2.25 V CZV
2.25V 1.5 mF
338 ms
=
10 m A
10 m A
(72)
CSS CZV
(73)
The soft-start timing can be set with timing capacitor CSS once the amount of soft start time (tSS) has been
determined. Our original design requirement was to have 200 ms of soft-start time. The calculated
capacitance needed for this soft-start time is less than the minimum required capacitance.
Css =
10 m A t ss
10 m A 200 ms
0.889 mF
=
2.25V
2.25 V
(74)
A CSS capacitor value equal to the CZV capacitor was chosen for the design.
Css = 1.5 mF
(75)
13
Spread Spectrum Reduces EMI

It has been shown that dithering the converters switching frequency can reduce EMI. Resistor RRDM and
CCDR program the frequency dithering magnitude and rate. For this design the frequency dither magnitude
(fDM) was set to 30 kHz and the frequency dither rate (fDR) was set to 10 kHz. The frequency will dither
around the typical frequency programmed by resistor RRT. In this example the frequency will dither from
roughly 185 kHz to 215 kHz at a 10 kHz rate.
fDM = 30 kHz
(76)
fDR = 10kHz
(77)
6
RRDM =
937.5 10 W
937.5 10 W
=
= 31.13 kW
fDM
30 kHz
(78)
CCDR =
0.0667 10-9F RRDM

0.0667 10-9F 31.13 kW
=
= 208 pF
10 kHz
fRD
(79)
A standard resistor and capacitor are chosen for the design:

RRDM = 31.6 kW
(80)
CCDR = 220 pF
(81)
16

Recommended PCB Device Layout
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14

Interleaved PFC techniques dramatically reduce input and output ripple current caused by the PFC boost
inductor, which allows the circuit to use smaller and less expensive filters. To maximize the benefits of
interleaving, the output filter capacitor should be located after the two phases allowing the current of each
phase to be combined together before entering the boost capacitor. Similar to other power management
devices, when laying out the PCB it is important to use star grounding techniques and to keep filter and
high frequency bypass capacitors as close to the device pins and ground pin as possible. To minimize the
interference caused by magnetic coupling from the boost inductor, the device should be located at least
one inch away from the boost inductor. It is also recommended that the device not be placed underneath
magnetic elements. To verify the application a 300-W interleaved prototype was constructed and
evaluated. This prototype consisted of mother board that was the power stage and a daughter board that
consisted of the control circuitry. Refer to Figure 8 through Figure 13 for schematics and a recommended
layout. The daughter board controller has two jumpers JP1 and JP2. If these jumpers are open the
evaluation module is running with frequency dithering. If these jumpers are shorted frequency dither is
disabled and the EVM can be synchronized through the sync input.
Figure 8. 300-W Prototype Daughter Board Controller Schematic

17
www.ti.com
U1
UCC27324D
Figure 9. 300-W Prototype Mother Board Power Stage
18

www.ti.com
Figure 10. Daughter Board Layout Front
Figure 11. Daughter Board Layout Back

19
www.ti.com
VOUT
RETURN
C5
HS1
C2
L1
L2
C6
D5
T1
C7
T2
D6
J1
RT1
C2
Q1
VAR1
Q1
F1
HS3
HS2
C11
AC LINE
VCC
AC NEUTRAL
J2
SYNC
GND
Figure 12. Mother Board Layout Front
VOUT
RETURN
JP2
D1
JP2
D3
R5
D13
R3
C3
D4
R2
R4
C8
C12
R13 R1
R11
C9
D10
R8
U1
D7 R6
C4 D8
R18
J1 R12 R7
R17
R9 R10
D2
R14 C10 D12

D11 R16
R15
R19
D9
AC NEUTRAL
AC LINE
Figure 13. Mother Board Bottom
20

Efficiency Curves
www.ti.com
15
Efficiency Curves
A 300-W prototype was built based on the design information presented in this application note. The
following graphs show the performance of this EVM.
15.1 Prototype Efficiency

Efficiency
100%
100%
98%
98%
96%
96%
94%
94%
% Efficiency
% Efficiency
Efficiency
92%
90%
92%
90%
88%
88%
86%
86%
84%
82%
80%
10%
20%
30%
40%
50%
Efficency at Vin 85V RMS
84%
Efficency at Vin = 265V RMS
82%
60%
70%
80%
90%
Efficiency at VIN = 115V

Efficiency at VIN = 230V
80%
10%
100%
20%
30%
40%
50%
60%
70%
80%
90%
100%
% Output Power
% Output Power
Figure 14.
Figure 15.
Current Harmonics V IN = 230V, POUT = 300W
1.41473
1.17894
0.94316
Amplitude (A)
EN61000-3-2 Class D Specifications
0.70737
0.47159
0.23580
0.00001
1
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
Harmonic
Figure 16. Prototype Harmonic Content at VIN = 230 V, POUT = 300 W

21
Efficiency Curves
www.ti.com
15.2 Prototype Power Factor

Pow er Factor
1.000
0.990
0.990
0.980
0.980
0.970
0.970
0.960
0.960
PF
PF
Pow er Factor
1.000
0.950
0.950
PF VIN = 230V
PF VIN = 265V
0.930
0.930
0.920
0.920
0.910
0.910
0.900
20%
30%
40%
50%
60%
70%
80%
90%
PF VIN = 115V
0.940
PF VIN = 85V
0.940
0.900
20%
100%
30%
22
40%
50%
60%
70%
80%
90%
100%
% Output Pow er
% Output Pow er
Figure 17.
Figure 18. Input Current and Output Ripple Voltage at

Maximum Output Power
Ch2 = IIN, CH2 = VOUT
Figure 19. VIN = 85 V RMS
Figure 20. VIN = 265 V RMS

Efficiency Curves
www.ti.com
15.3 Inductor Ripple Current Cancellation, CH2=IL1, CH3=IL2, M1=IL1+IL2
Figure 21. VIN = 85 V RMS, Peak of Line
Figure 22. VIN = 265V RMS, Peak of Line
Figure 23. VIN = 265V RMS, Line Voltage at Half the

Output Voltage
Figure 24. VIN = 85 V, POUT = 300 W

23
Efficiency Curves
www.ti.com
24

Efficiency Curves
www.ti.com
15.4 Recovery from Line Dropout, CH1= Rectified Line Voltage, CH2=IL1, CH3=IL2, CH4 =
VOUT
Figure 26. Brownout at VIN = 115V, POUT = 300 W
15.5 Startup, CH2 = IL1, CH3 = IL2, CH4 = VOUT

25
References
www.ti.com
15.6 EMI Measurements

When dithering was applied to the EVM a 4.35dBuV reduction in the Quasi Peak (QP) measurement was
observed. Note a filter was added to the front end of the EVM to clean up some of the noise to take EMI
data. Depending on the filter the amount of EMI will vary. Also, this filter was not setup to pass EMI
requirements but to show frequency dither reduced EMI.
Figure 29. EMI Quasi Peak (QP) Measurement with out Frequency Dithering, No EMI Filter Present
Figure 30. EMI Quasi Peak (QP) Measurement with Frequency Dithering, No EMI filter Present
16
References
1. Lazlo Balogh and Richard Redi, Power Factor Correction with Interleaved Boost, APEC 1993, pp.
168-174
2. Lloyd Dixon, High Power Factor Switching Pre-regulator Design Optimization, Unitrode Power Supply
Design Seminar SEM-700, 1990, Topic 7
3. Brett Miwa, David Otten, Martin F. Schlecht, High Efficiency Power Factor Correction Using Interleaved
Techniques IEEE 1992, pp. 557 to 568
4. Michael OLoughlin, 350W, Two Phase Interleaved PFC Pre-regulator Design Review, Texas
Instrument Literature Number SLUA369, 2006
5. Michael OLouglin, An Interleaving PFC Pre-Regulator for High-Power Converters Unitrode/TI Power
Supply Design Seminar SEM-1700, Topic 5
6. P. Zumel, O. Garcia, J. A. Cobos, J. Uceda, EMI Reduction by Interleaving of Power Converters
Presentation, APEC 2004
7. UCC28070 Data Sheet, Texas Instruments Literature Number SLUS794,
http://focus.ti.com/lit/ds/symlink/ucc28070.pdf
26

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Application Report

SLUA479B August 2008 Revised July 2010

UCC28070 300-W Interleaved PFC Pre-Regulator Design

RMS input voltage

Power factor at maximum load

Full load efficiency

Individual phase switching frequency

SLUA479B August 2008 Revised July 2010

UCC28070 300-W Interleaved PFC Pre-Regulator Design Review

Figure 1. Typical Average Current Mode Interleaved PFC Pre-Regulator

UCC28070 300-W Interleaved PFC Pre-Regulator Design Review

SLUA479B August 2008 Revised July 2010

Figure 2. Input Inductor Ripple Current Cancellation

SLUA479B August 2008 Revised July 2010

UCC28070 300-W Interleaved PFC Pre-Regulator Design Review

VIN_MIN 2sin(q ) VOUT - VIN_MIN 2sin(q )

L1MAX = L2MAX = 350 uH

UCC28070 300-W Interleaved PFC Pre-Regulator Design Review

SLUA479B August 2008 Revised July 2010

Output Capacitor Selection

Output Capacitor Selection

SLUA479B August 2008 Revised July 2010

UCC28070 300-W Interleaved PFC Pre-Regulator Design Review

Power Semiconductor Selection (Q1, Q2, D1, D2)

Power Semiconductor Selection (Q1, Q2, D1, D2)

Q1 and Q2 RMS current (IDS) calculation:

D1 and D2s average current calculation (ID):

UCC28070 300-W Interleaved PFC Pre-Regulator Design Review

SLUA479B August 2008 Revised July 2010

Select a standard resistor for the design:

Resistor RR is used to reset the current sense transformer:

SLUA479B August 2008 Revised July 2010

UCC28070 300-W Interleaved PFC Pre-Regulator Design Review

UCC28070 300-W Interleaved PFC Pre-Regulator Design Review

SLUA479B August 2008 Revised July 2010

Select a standard resistor for the design:

3.7V 0.1- 0.2V

Chose a standard resistor for the design:

A standard capacitor needs to be chosen for the design:

SLUA479B August 2008 Revised July 2010

UCC28070 300-W Interleaved PFC Pre-Regulator Design Review

Setting Up Peak Current Limiting (RPK1, RPK2)

Setting Up Peak Current Limiting (RPK1, RPK2)

Converter Timing and Maximum Duty Cycle Clamp

A standard resistor was selected for the design:

Chose a standard resistor for the design:

A standard resistor was chosen for the design.

UCC28070 300-W Interleaved PFC Pre-Regulator Design Review

SLUA479B August 2008 Revised July 2010

VINAC Divider Setup

VINAC Divider Setup

Voltage Loop Configuration

Voltage Divider Feedback Gain:

Choose as standard capacitor for the design:

SLUA479B August 2008 Revised July 2010

UCC28070 300-W Interleaved PFC Pre-Regulator Design Review

Voltage Loop Configuration

Select a standard resistor for the design:

UCC28070 300-W Interleaved PFC Pre-Regulator Design Review

SLUA479B August 2008 Revised July 2010

Voltage Loop Configuration

Voltage Loop Power Stage Gain (GPSV(f)) as function of frequency:

Voltage Loop Gain in dB (TvdB(f)) as function of frequency:

Figure 4. Theoretical Voltage Loop Gain (TvdB(f))