Date

Group No.
Group Members

:
:
:

EXPERIMENT

SHIFT REGISTER
2016/17

OBJECTIVES

build and understand the operation of ring

shift register, Johnson shift register and
To
ring shift register with error correction circuit.

To design and verify a Johnson shift register with error correction circuit.

COMPONENTS

EQUIPMENTS

74LS76

(2)

Breadboard

(1)

7420

(2)

Power supply

(1)

7404

(1)

7400

(1)

PREPARATION
Prepare a complete design of a MOD 5 cross ring counter with error correction circuit before
entering this lab session. Experiment 4 is to test and verify the circuit designed. The binary
sequences for this counter are as shown in Figure D.1.
0
000

00 1

011

6
100

110

Figure D.1

D1

Module I: Experiment D (2016/17)

INTRODUCTION
Two common circuits that we use to produce a controllable sequence waveform for digital
system are ring shift register and Johnson shift register. A shift register is similar to a
synchronous counter as it has similar clock input timing to every flip-flops. The outputs from
shift register do not count in usual binary order, but it creates a repetitive sequence of digital
outputs. Shift register is used in controlling a sequence of a digital system (digital sequences).
Figure D.2 shows a basic ring counter with corresponding binary sequences output.
RESET

FF1(LSB)
J

FF2
J

CL Q
CLK

CLOCK
K

PR

FF3
J

CL Q
CLK

_
Q

CLK
_
Q

PR

PR

FF4
J

CL Q

CL Q

CLK
_
Q

PR

_
Q

SET

(a) Basic ring counter

0
Lock Up

0000

0001

0010

1000

0100

1001

Loop 1 Valid

0011

14

0110

0111

1110

1100

1011

1101

1010

11

13

10
Loop 4 Invalid

12

Loop 2 Invalid

Loop 3 Invalid

5
0101

(b) The corresponding binary outputs

Figure D.2

The Johnson shift counter is not much different to ring shift counter except the last output is
crossed (that is why we call it cross ring counter) before being fed back to first flip-flop input.
D2

Module I: Experiment D (2016/17)

Initially, all flip-flops are in reset position. Figure D.3 shows a cross ring counter with
corresponding binary sequences.
RESET

FF1(LSB)
CL Q

CLK
K

PR

FF2

CLK

_
Q

FF3

CL Q

PR

CL Q

CLK

_
Q

PR

CL Q

CLK

_
Q

PR

_
Q

CLOCK
SET

(a) Basic cross shift counter

0
0000

1
0001

1000

3
0011

0111

1100

1110

12

14

0010

1111

15

1001

0101

1011

0100

1010

10

Loop 1 Valid

11

0110

1101

13

Loop 2 Invalid

(b) The corresponding binary outputs

Figure D.3

EXPERIMENT 1: BASIC RING COUNTER

1.

Build the circuit shown in Figure D.2(a). The input clock is the output from
debounced switch. Remember that 74LS76 is negative-edge trigger FF.

2.

Connect LED to each of Q for all FF. Use CL to reset each of FF. Set FF1 to 1
(Q1 = 1) by connecting P R FF1 to GND. Let P R = 1 again.

3.

Record each of FF outputs when clock input is 0 (Table D.1.a). Give 4 steps of
clock input for all FF. Record your result for each of clock input.

4.

Again, use CL to reset all FF. Set FF1 and FF2 to 1 (Q1=1, Q2 = 1). What is the
binary shown at output? Is this a valid condition?

5.

Repeat step 3 and record in Table D.1.b

D3

FF4

Module I: Experiment D (2016/17)

6.

Reset all FF again. Set FF1, FF2 and FF3 to 1 (Q1 = Q2 = Q3=1). What is the
binary number shown? Is this a valid condition?

7.

Repeat step 3 and record in Table D.1.c

EXPERIMENT 2: CROSS RING COUNTER

1. Repeat step 1 of Experiment 1, by using Figure D.3(a).
2. Reset all FF. Record all the outputs for each FF when input clock is 0 (refer Table
D.2).
3. Give 8 steps of clock input for all FF. Record your result for each of clock input in
Table D.2.a.
4. Again, use CL to reset all FF. Set FF2 to 1 (Q2 = 1). What is the binary shown at
output? Is this a valid condition?
5. Repeat step 3 of Experiment 2 and record in Table D.2.b.

EXPERIMENT 3: ERROR CORRECTION RING COUNTER

A ring counter with error correction circuit is shown in Figure D.4.
1. Build the circuit in Figure D.4.
2. Reset all FF. Record all the outputs for each FF when input clock is 0 (refer Table
D.3).
3. Give 5 steps of clock input for all FF. Record your result for each of clock input
as in Table D.3.a.
4. Reset all FF. Set FF1 and FF2 to 1 (Q1 = Q2 = 1). What is the number displayed?
Is this a valid condition?
5. Repeat step 3 of Experiment 3. Record the results in Table D.3.b.

D4

Module I: Experiment D (2016/17)

Figure D.4 Ring counter with error correction circuit

D5

Module I: Experiment D (2016/17)

RESULTS:
EXPERIMENT 1: BASIC RING COUNTER

Table D.1.a (Only Flip-Flop 1 is set to HIGH)

FF State
Clock
Input
0

FF1

FF2

FF3

FF4

1
2
3
4

Table D.1.b (Flip-Flop 1 and 2 set to HIGH)

FF State
Clock
Input
0

FF1

FF2

FF3

FF4

1
2
3
4

Table D.1.c (Flip-Flop 1, 2 and 3 is set to HIGH)

FF State
Clock
Input
0

FF1

FF2

1
2
3
4

D6

FF3

FF4

Module I: Experiment D (2016/17)

DISCUSSIONS AND CONCLUSION:

D7

Module I: Experiment D (2016/17)

EXPERIMENT 2: CROSS RING COUNTER

Table D.2

Step 2:

FF State
Clock Input
0
1
2
3
4
5
6

FF1

FF2

FF3

FF4

FF3

FF4

7
8

Step 3:

Table D.2.a
FF State
Clock Input
0
1

FF1

FF2

2
3
4
5
6
7
8
Answer for step 4:

D8

Module I: Experiment D (2016/17)

Step 5:

Table D.2.b
FF State
Clock Input
0
1
2
3
4
5
6
7

FF1

FF2

8
DISCUSSIONS AND CONCLUSION:

D9

FF3

FF4

Module I: Experiment D (2016/17)

EXPERIMENT 3: ERROR CORRECTION RING COUNTER

Table D.3

Step 2:

FF State

Clock Input
0
1
2
3
4
5

FF1

FF2

FF3

FF4

Step 3:

Table D.3.a
FF State

Clock Input
FF1

FF2

0
1
2
3
4
5

Answer for step 4:

D10

FF3

FF4

Module I: Experiment D (2016/17)

Step 5:

Table D.3.b
FF State

Clock Input

FF1

FF2

0
1
2
3
4
5
DISCUSSIONS AND CONCLUSION:

D11

FF3

FF4