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ECE357: Introduction to VLSI CAD
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Prof. Hai Zhou
Electrical Engineering & Computer Science

Northwestern University
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Logistics
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Time & Location: MWF 11-11:50 TECH L160
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Instructor: Hai Zhou haizhou@ece.northwestern.edu
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Office: L461
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Office Hours: W 3-5P
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Teaching Assistant: Chuan Lin
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Texts:
VLSI Physical Design Automation: Theory & Practice, Sait
& Youssef, World Scientific, 1999.
Reference:
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An Introduction to VLSI Physical Design, Sarrafzadeh &

Wong, McGraw Hill, 1996.
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Grading: Participation-10% Project-30% Midterm-30%

Homework-30%
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Homework must be turned in before class on each due date,

late: -40% per day
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Course homepage:
www.ece.northwestern.edu/~haizhou/ece357
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What can you expect from the course
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Understand modern VLSI design flows (but not the details

of tools)
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Understand the physical design problem
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Familiar with the stages and basic algorithms in physical

design
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Improve your capability to design algorithms to solve

problems
Improve your capability to think and reason
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What do I expect from you
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Active and critical participation
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speed me up or slow me down if my pace mismatches

yours
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Your role is not one of sponges, but one of whetstones;

only then the spark of intellectual excitement can
continue to jump over
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Read the textbook
Do your homeworks
You can discuss homework with your classmates, but
need to write down solutions independently
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VLSI (Very Large Scale Integrated) chips
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VLSI chips are everywhere
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computers
commercial electronics: TV sets, DVD, VCR, ...
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voice and data communication networks

automobiles
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VLSI chips are artifacts

they are produced according to our will ...
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Design: the most challenging human activity
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Design is a process of creating a structure to fulfill a

requirement
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Brain power is the scarcest resource
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Delegate as much as possible to computersCAD
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Avoid two extreme views:
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Everything manual: impossiblemillions of gates

Everything computer: impossible either
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Design is always difficult
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A main task of a designer is to manage complexity
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Silicon complexity: physical effects no longer be ignored

resistive and cross-coupled interconnects; signal
integrity; weak and faster gates
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reliability; manufacturability
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System complexity: more functionality in less time

gap between design and fabrication capabilities
desire for system-on-chip (SOC)
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CAD: A tale of two designs
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Targethardware design
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How to create a structure on silicon to implement a

function
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Aidsoftware design (programming)
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How to create an algorithm to solve a design problem

Be conscious of their similarities and differences
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Emphasis of the course

Design flow
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Understand how design process is decomposed into

many stages
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What are the problems need to be solved in each stage
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Algorithms
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Understand how an algorithm solves a design problem

Consider the possibility to extend it
Be conscious and try to improve problem solving skills
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Basics of MOS Devices

The most popular VLSI technology: MOS
(Metal-Oxide-Semiconductor).
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CMOS (Complementary MOS) dominates nMOS and

pMOS, due to CMOSs lower power dissipation, high
regularity, etc.
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Physical structure of MOS transistors and their schematic

icons: nMOS, pMOS.
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Layout of basic devices:

CMOS inverter
CMOS NAND gate
CMOS NOR gate
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MOS Transistors gate

drain
source
conductor (polysilicon)
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drain
n
source
substrate
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diffusion
psubstrate
ntransistor
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gate
insulator (SiO2)
schematic icon
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The nMOS switch passes "0" well.

gate
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drain
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source
conductor (polysilicon)
gate
insulator (SiO2)
drain
substrate
nsubstrate
source
diffusion
schematic icon
ptransistor
The pMOS switch passes "1" well.

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A CMOS Inverter
Metal
Metaldiffusion contact
pMOS transistor
VDD
A
1
0
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nMOS transistor
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Polysilicon
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Diffusion
B
0
1
VDD
pchannel (pMOS)
B
nchannel (nMOS)
GND
GND
layout
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A CMOS NAND Gate

Metal
VDD
or
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GND
B C
0 1
1 1
0 1
1 0
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Diffusion
Polysilicon
A
0
0
1
1
VDD
C
B
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GND
layout
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A CMOS NOR Gate

Metal
VDD
Polysilicon
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GND
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B C
0 1
1 0
0 0
1 0
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or
A
0
0
1
1
VDD
Diffusion
GND
layout
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Current VLSI design phases
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Synthesis (i.e. specification implementation)
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1. High level synthesis (459 VLSI Algorithmics)
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2. Logic synthesis (459 VLSI Algorithmics)
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3. Physical design (This course)
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Analysis (implementation semantics)

Verification (design verification, implementation
verification)
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Analysis (timing, function, noise, etc.)

Design rule checking, LVS (Layout Vs. Schematic)
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Physical Design
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Physical design converts a structural description into a

geometric description.
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Physical design cycle:
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1. Circuit partitioning
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2. Floorplanning
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3. placement, and pin assignment

4. Routing (global and detailed)
5. Compaction
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Design Styles
Issues of
VLSI circuits
Performance
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Cost
Timetomarket
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Full custom
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Area
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Standard cell
Different design styles
Gate array
FPGA
CPLD
SPLD
SSI
Performance, Area efficiency, Cost, Flexibility
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Full Custom Design Style
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Data path
or
PLA
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ROM/RAM
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overthecell
routing
I/O
via
(contact)
Controller
Random logic
A/D converter
pins
I/O pads
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Standard Cell Design Style

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A
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library cells
Cell A
Cell C
Cell B
Cell D
Feedthrough Cell
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Gate Array Design Style
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I/O pads
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pins
prefabricated
transistor
array
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customized
wiring
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FPGA Design Style
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logic
blocks
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routing
tracks
switches
Prefabricated all chip components
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SSI/SPLD Design Style

x2 y2
x1 y1
x3 y3
x4 y4
74LS02
74LS86
x1
Vcc
Vcc
y1
Vcc
x3
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y3
x2
y2
x4
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y4
GND
GND
F=
4
i=1
xi
yi
(a) 4bit comparator.
x1
y1
x2
y2
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y4
GND
(b) SSI implementation.
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x3
y3
x4
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74LS00
AND array
x1 y1 x2 y2
x3
y3
x4
y4
OR array
(c) SPLD (PLA) implementation.
(d) Gate array implementation.
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Comparisons of Design Styles

Cell size
Cell type
Cell placement
Interconnections
Full
custom
variable
variable
variable
variable
Standard
cell
fixed height
variable
in row
variable
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Gate
array
fixed
fixed
fixed
variable
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FPGA
fixed
programmable
fixed
programmable
SPLD
fixed
programmable
fixed
programmable
* Uneven height cells are also used.
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Comparisons of Design Styles

Fabrication time
Packing density
Unit cost in large quantity
Unit cost in small quantity
Easy design and simulation
Easy design change
Accuracy of timing simulation
Chip speed
+ desirable
not desirable
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Standard
cell

++
++

++
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Full
custom

+++
+++

+++
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Gate
array
+
+
+
+
FPGA
+++

+++
++
++
+
SPLD
++

+
+
++
+
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Design-Style Trade-offs
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Full
custom
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10
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Turnaround
Time
(Days)
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10
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CPLDs
SPLDs
semi
custom
FPGAs
optimal
solution
SSIs
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10
10
10
10
10
10
Logic Capacity (Gates)
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Algorithms 101
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Algorithm: a finite step-by-step procedure to solve a

problem
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Requirements:
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Unambiguity: can even be followed by a machine
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Basic: each step is among a given primitives

Finite: it will terminate for every possible input
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A game
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An ECE major is sitting on the Northwestern beach and

gets thirsty, she knows that there is an ice-cream booth
along the shore of Lake Michigan but does not know
wherenot even north or south. How can she find the
booth in the shortest distance?
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Primitives: walking a distance, turning around, etc.
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A first solution
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Select a direction, say north, and keep going until find the
booth
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Suppose the booth is to the south, she will never stop... of

course, with the assumption she follows a straight line, not
lake shore or on earth
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Another solution
Set the place she is sitting as the origin
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Search to south 1 yard, if not find, turn to north
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Search to north 1 yard, if not find, turn to south
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Search to south 2 yard, if not find, turn to north
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Search to north 2 yard, if not find, turn to south
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... (follow the above pattern in geometric sequence 1, 2, 4,

8, ...)
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OR
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n = 1;
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While (not find) do
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n = n + 1;
Search to south 2n, and turn;
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Search to north 2n, and turn;
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Correctness proof
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Each time when the while loop is finished, the range from
south 2n to north 2n is searched. Based on the fact that
the booth is at a constant distance x from the origin, it will
be within a range from south 2N to north 2N for some N .
With n to increment in each loop, we will find the booth in
finite time.
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Is this the fastest (or shortest) way to find the booth?
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Analysis of algorithm
Observation: the traveled distance depends on where is the
booth
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Suppose the distance between the booth and the origin is x

When the algorithm stops, we should have 2n x but
2n1 < x
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The distance traveled is
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3 2n + 2(2 2n1 + 2 2n2 + + 2) 7 2n
which is smaller than 14x

We know that the lower bound is x, can we do better?
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Complexity of an algorithm
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Two resources: running time and storage
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They are dependent on inputs: expressed as functions of

input size
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Why input size: lower bound (at least read it once)
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Big-Oh notation: f (n) = O(g(n)) if there exist constants n0

and c such that for all n > n0, f (n) c g(n).
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Make our life easy: is it 13x instead of 14x in our game

The solution is asymptotically optimal for our game
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Time complexity of an algorithm
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Run-time comparison: 1000 MIPS (Yr: 200x), 1 instr. /op.

Time
500
3n
n log n
n2
n3
2n
n!
Big-Oh
O(1)
O(n)
O(n log n)
O(n2 )
O(n3 )
O(2n )
O(n!)
n = 10
5 107 sec
3 108 sec
3 108 sec
1 107 sec
1 106 sec
1 106 sec
0.003 sec
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n = 100
5 107 sec
3 107 sec
2 107 sec
1 105 sec
0.001 sec
3 1017 cent.
-
n = 103
5 107 sec
3 106 sec
3 106 sec
0.001 sec
1 sec
-
n = 106
5 107 sec
0.003 sec
0.006 sec
16.7 min
3 105 cent.
-
Polynomial-time complexity: O(p(n)), where n is the input

size and p(n) is a polynomial function of n.
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Complexity of a problem
Given a problem, what is the running time of the fastest
algorithm for it?
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Upper bound: easyfind an algorithm with less time
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Lower bound: hardevery algorithm requires more time
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P: set of problems solvable in polynomial time
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NP(Nondeterministic P): set of problems whose solution

can be proved in polynomial time
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Millennium open problem: NP 6= P?

Fact: there are a set of problems in NP resisting any
polynomial solution for a long time (40 years)
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NP-complete and NP-hard
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Cook 1970: If the problem of boolean satisfiability can be

solved in poly. time, so can all problems in NP.
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Such a problem with this property is called NP-hard.
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If a NP-hard problem is in NP, it is called NP-complete.
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Karp 1971: Many other problems resisting poly. solutions

are NP-complete.
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How to deal with a hard problem

Prove the problem is NP-complete:
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1. The problem is in NP (i.e. solution can be proved in

poly. time)
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2. It is NP-hard (by polynomial reducing a NP-complete

problem to it)
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Solve NP-hard problems:
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Exponential algorithm (feasible only when the problem

size is small)
Pseudo-polynomial time algorithms
Restriction: work on a subset of the input space
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Approximation algorithms: get a provable

close-to-optimal solution
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Heuristics: get a as good as possible solution
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Randomized algorithm: get the solution with high

probability
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Algorithmic Paradigms
Divide and conquer: divide a problem into sub-problems,
solve sub-problems, and combine them to construct a
solution.
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Greedy algorithm: optimal solutions to sub-problems will

give optimal solution to the whole problem.
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Dynamic programming: solutions to a larger problem are

constructed from a set of solutions to its sub-problems.
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Mathematical programming: a system of optimizing an

objective function under constraints functions.
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Simulated annealing: an adaptive, iterative,

non-deterministic algorithm that allows uphill moves to
escape from local optima.
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Branch and bound: a search technique with pruning.
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Exhaustive search: search the entire solution space.
.
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ECE357: Introduction to VLSI CAD

Prof. Hai Zhou

Electrical Engineering & Computer Science

Time & Location: MWF 11-11:50 TECH L160

Instructor: Hai Zhou haizhou@ece.northwestern.edu

Office Hours: W 3-5P

Teaching Assistant: Chuan Lin

An Introduction to VLSI Physical Design, Sarrafzadeh &

Grading: Participation-10% Project-30% Midterm-30%

Homework must be turned in before class on each due date,

What can you expect from the course

Understand modern VLSI design flows (but not the details

Understand the physical design problem

Familiar with the stages and basic algorithms in physical

Improve your capability to design algorithms to solve

What do I expect from you

Active and critical participation

speed me up or slow me down if my pace mismatches

Your role is not one of sponges, but one of whetstones;

Read the textbook

VLSI (Very Large Scale Integrated) chips

VLSI chips are everywhere

commercial electronics: TV sets, DVD, VCR, ...

voice and data communication networks

VLSI chips are artifacts

Design: the most challenging human activity

Design is a process of creating a structure to fulfill a

Brain power is the scarcest resource

Delegate as much as possible to computersCAD

Avoid two extreme views:

Everything manual: impossiblemillions of gates

Design is always difficult

A main task of a designer is to manage complexity

Silicon complexity: physical effects no longer be ignored

System complexity: more functionality in less time

CAD: A tale of two designs

How to create a structure on silicon to implement a

Aidsoftware design (programming)

How to create an algorithm to solve a design problem

Emphasis of the course

Understand how design process is decomposed into

What are the problems need to be solved in each stage

Understand how an algorithm solves a design problem

Basics of MOS Devices

CMOS (Complementary MOS) dominates nMOS and

Physical structure of MOS transistors and their schematic

Layout of basic devices:

MOS Transistors gate

The nMOS switch passes "0" well.

The pMOS switch passes "1" well.

A CMOS NAND Gate

A CMOS NOR Gate

Current VLSI design phases

Synthesis (i.e. specification implementation)

1. High level synthesis (459 VLSI Algorithmics)

2. Logic synthesis (459 VLSI Algorithmics)

3. Physical design (This course)

Analysis (implementation semantics)

Analysis (timing, function, noise, etc.)

Physical design converts a structural description into a

Physical design cycle:

3. placement, and pin assignment