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Published in IET Power Electronics
Received on 31st March 2010
Revised on 31st March 2011
doi: 10.1049/iet-pel.2010.0332

ISSN 1755-4535

Analysis of THD and output voltage performance for

cascaded multilevel inverter using carrier pulse width
modulation techniques
P. Palanivel S.S. Dash
SRM University, EEE, Kattankulathur, Chennai 603203, Tamilnadu, India
E-mail: palanidash@gmail.com

Abstract: Multilevel inverter is used in applications that need high voltage and high current. The topologies of multilevel inverter
have several advantages such as lower total harmonic distortion (THD), lower electro magnetic interference (EMI) generation, high
output voltage. The main feature of multilevel inverter is the ability to reduce the voltage stress on each power device due to the
utilisation of multilevel on the DC bus. The advent of multilevel inverter topologies has caused variety of pulse width
modulation strategies. In this paper, various carrier pulse width modulation techniques are proposed, which can minimise the
total harmonic distortion and enhances the output voltages from ve level inverter. Three methodologies adopting the constant
switching frequency (CSF), variable switching frequency (VSF), and phase shifted pulse width modulation (PSPWM) concepts
are proposed in this paper. The above methodologies divided into two techniques like subharmonic pulse width modulation
which minimises total harmonic distortion and switching frequency optimal pulse width modulation which enhances the output
voltages. Field programmable gate array (FPGA) has been chosen to implement the pulse width modulation due its fast proto
typing, simple hardware and software design. The simulation and experimental results are presented.

Introduction

Nowadays, multilevel inverters have achieved increasing

contribution in high-performance applications. Recently, for
high-performance power application, multilevel converters
are widely used such as static var compensators, drives and
active power lters. The advantages of multilevel inverters
are good power quality, low switching losses and highvoltage capability [1 3]. The topologies of multilevel
inverters are classied into three types, that is, the ying
capacitor, diode clamped and cascaded multilevel inverters
[4 9]. In this paper, constant switching frequency, variable
switching frequency and phase-shifted carrier pulse width
modulation methods are presented. These techniques take
advantage of special properties available in multilevel
inverter to minimise total harmonic distortion and increase
output voltage. The total harmonic distortion values are
high for subharmonic pulse-width modulation and
switched frequency optimal pulse width modulation and
corresponding output voltages below the actual value
[10 14]. Illustrative examples are given to demonstrate the
feasibility of the proposed methods.

Three-phase cascaded multilevel inverter

The three-phase cascaded multilevel inverter is shown in

Fig. 1. The circuit is designed for a ve-level inverter
consisting of 12 switches. Each dc source connected with
their respective H-bridges generates three different output
voltages, +Vdc , 0 and Vdc using various combinations of
IET Power Electron., 2011, Vol. 4, Iss. 8, pp. 951958
doi: 10.1049/iet-pel.2010.0332

switching with the four switches. The output of multilevel

inverter is synthesised by H-bridges connected in series.
The number of output phase voltage levels in a cascaded
inverter is given as m 2s + 1, where s is the number of
separate dc sources and m is the inverter level.

3 Constant switching frequency pulse-width

modulation
3.1

Subharmonic pulse-width modulation

The constant switching frequency pulse-width modulation

technique is most popular and very simple switching
schemes. For m-level inverter, m 2 1 carriers with the same
frequency fc and the same amplitude Ac are disposed such
that the bands they occupy are contiguous. The reference
waveform has peak-to-peak amplitude Am , the frequency fm
and it is zero centred in the middle of the carrier set. The
reference is continuously compared with each of the carrier
signals. If the reference is greater than s carrier signal, then
the active device corresponding to that carrier is switched off.
In multilevel inverters, the amplitude modulation index Ma
and the frequency ratio Mf are dened as
Ma =

Am
(m 1)Ac

(1)

fc
fm

(2)

Mf =

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In the subharmonic method, related to the way the carrier
waves are placed in relation to the reference signal, three
cases can be distinguished.
Fig. 2a shows a phase disposition pulse-width modulation
(PDPWM), where all the carriers are in phase. Fig. 2c shows
a phase opposition disposition pulse-width modulation
(PODPWM), where the carriers above the zero reference are
in phase, but shifted by 1808 from those carriers below the
zero reference. Fig. 2e shows an alternative phase
opposition disposition (APODPWM), where each carrier
band is shifted by 1808 from the adjacent bands.
3.2 Switching frequency optimal pulse-width
modulation

Fig. 1 FPGA-based three-phase cascaded ve-level inverter

The switching frequency optimal pulse width modulation

(SFOPWM), which triples harmonic voltage, is added to
each of the carrier waveforms. The method takes the
instantaneous average of the maximum and minimum of the

Fig. 2 Constant switching frequency pulse-width modulation

a
b
c
d
e
f

PD-SH PWM
PD-SFO PWM
POD-SH PWM
POD-SFO PWM
APOD-SH PWM
APOD-SFO PWM

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three reference voltages (Va , Vb , Vc) and subtracts the value
from each of the individual reference voltages to obtain the
modulation waveforms
Voff



max(Va , Vb , Vc ) + min(Va , Vb , Vc )
=
2

(3)

Va SFO = Va Voffset

(4)

Vb SFO = Vb Voffset

(5)

Vc SFO = Vc Voffset

(6)

The zero-sequence modication made by the SFO PWM

technique restricts its use to a three-phase three-wire
system; however, it enables the modulation index to be
increased by 15% before over-modulation or pulse dropping
occurs.
In the switching frequency optimal method, related to the
way the carrier waves are placed in relation to the reference
signal, three cases can be distinguished:
Fig. 2b shows a phase disposition pulse-width modulation
(PDPWM), where all the carriers are in phase. Fig. 2d shows a
phase opposition disposition pulse-width modulation
(PODPWM), where the carriers above the zero reference are
in phase, but shifted by 1808 from those carriers below the
zero reference. Fig. 2f shows an APODPWM, where each
carrier band is shifted by 1808 from the adjacent bands.

4 Variable switching frequency pulse-width

modulation
4.1

Subharmonic pulse-width modulation

For a multilevel inverter, four carrier signals and one

sinusoidal reference signal are consider based on the
equation (m 2 1), where m represents the level of the
inverter. The carriers are in phase across all the bands. In
this technique, signicant harmonic energy is concentrated
at the carrier frequency. Since, it is a co-phasal component,
the line-to-line voltage does not appear. In this proposed
method, the carrier frequency of a ve-level inverter, whose
levels are 0, +V/2 and +V, is assigned to have variable
switching frequency of 2000 and 4000 Hz as shown in
Fig. 3a.

4.2 Switching frequency optimal pulse-width

modulation
For a multilevel inverter, if the level is m there will be m 2 1
carrier sets with variable switching frequency carrier pulsewidth modulation when compared with third harmonic
injection reference. The third harmonic injection is given
as [10]
Y = 1.15 sin u + 1.15/6 sin u

(7)

The resulting at-topped waveform allows over modulation

while maintaining excellent ac term and dc term spectra.
This is an alternative to improve the output voltage without
entering the over-modulation range. So any carriers
employed for this reference will enhance the output voltage
by 15% without increasing the harmonics.
In this paper, a ve-level inverter is proposed whose levels
are 0, +V/2 and +V, and its carrier sets are assigned to have
variable switching frequency of 2000 and 4000 Hz as shown
in Fig. 3b.

5
5.1

Phase-shifted pulse-width modulation

Subharmonic pulse-width modulation

Fig. 4a shows the phase-shifted subharmonic pulse-width

modulation. Each cell is modulated independently using
sinusoidal unipolar pulse-width modulation and bipolar
pulse-width modulation, respectively, which provides an
even power distribution among the cells. A carrier phase
shift of 1808/m for cascaded inverter is introduced across
the cells to generate the stepped multilevel output waveform
with lower distortion.
The modulating signal generator for the PSC PWM
optimum harmonic cancellation is achieved in PSC PWM.
Phase shifting for the carrier is given by
(K 1)
n


(8)

where K is the Kth bridge. n is the number of series-connected

single-phase inverters
N=

(L 1)
2

(9)

where L is the number of switched dc levels that can be

Fig. 3 Variable switching frequency pulse-width modulation

a SH PWM
b SFO PWM
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doi: 10.1049/iet-pel.2010.0332

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Fig. 4 Phase-shifted pulse-width modulation

a SH PWM
b PSC-SFO PWM

achieved in each phase leg. The average output voltage of a

phase-shifted pulse-width modulation to a particular power
cell i is given by

1
Voi =
(10)
Voi (t) dt
Tcr
Voi =

Ton
V
Tcr dc

(11)

Voi = V

(12)

where Voi is the output voltage of cell i and Ton is the

time interval, determined by the comparison between the
reference and the carrier signals.
5.2 Switching frequency optimal pulse-width
modulation
The method takes the instantaneous average of the maximum
and minimum of the three reference voltages (Va , Vb , Vc) and
subtracts the value from each of the individual reference
voltages to obtain the modulation waveforms, which is
shown in Fig. 4b. From the above criteria we obtain the
following equation

Voff =

max(Va , Vb , Vc ) + min(Va , Vb , Vc )
2


(13)

Va SFO = Va Vcarrier

(14)

Vb SFO = Vb Vcarrier

(15)

Vc SFO = Vc Vcarrier

(16)

The carrier voltage is the average of maximum and minimum

value of Va , Vb , Vc . The phase voltage using SFO is the

difference between reference voltage and carrier voltage.
The zero-sequence modication made by the SFO PWM
technique restricts its use to three-phase three-wire system;
however, it enables the modulation index to be increased by
15% before over-modulation or pulse dropping occurs.

Results

The THD and output voltage values for CSF PWM, VSF
PWM and PSC PWM are as shown in Table 1. The THD
value and output voltage values are small in the SH PWM
technique, whereas the values are high in the SFO PWM
technique. It is analysed that to minimise THD and output
voltage the SH PWM method gives better results and to
increase the output voltage the SFO PWM technique is
most suitable.
6.1

Simulation results

To verify the proposed schemes, a simulation model for

a three-phase ve-level cascaded H-bridge inverter is
implemented. The simulation parameters for constant
switching frequency pulse-width modulation are as follows:
inverter rating 5 kW, three-phase load R 100 V,
L 20 mH, each source Vdc 100 V and switching
frequency 2 kHz. Phase leg voltages have been calculated
and drawn for the PD PWM method in Figs. 5a and b.
Phase leg voltages have been calculated and drawn for the
POD PWM method in Figs. 5c and d. Phase leg voltages
have been calculated and drawn for the APOD PWM
method in Figs. 5e and f.
The simulation parameters for variable switching
frequency pulse-width modulation are as follows: inverter
rating 5 kW, three-phase load R 100 V, L 20 mH, each

Table 1

Output voltage and THD for constant switching frequency, variable switching frequency and phase-shifted pulse-width
modulation
PWM method

constant switching frequency PWM

Subharmonic PWM

PD PWM
POD PWM
APOD PWM

variable switching frequency PWM

phase-shifted carrier PWM

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Switching frequency
optimal PWM

THD%

VAC

THD%

VAC

6.70
14.60
14.61
10.10
0.35

180.0
199.9
200.0
180.1
200.1

21.40
24.67
24.34
22.45
20.65

200.1
220.2
220.2
200.0
220.2

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Fig. 5 Constant switching frequency pulse-width modulation output voltage and harmonic spectrum
a
b
c
d
e
f

PD-SH PWM
PD-SFO PWM
POD-SH PWM
POD-SFO PWM
APOD-SH PWM
APOD-SFO PWM

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doi: 10.1049/iet-pel.2010.0332

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Fig. 6 Variable switching frequency pulse-width modulation output voltage and harmonic spectrum
a SH PWM
b SFO PWM

source Vdc 100 V and switching frequency 2 and 4 kHz.

Phase leg voltages have been calculated and drawn for the
SH PWM method in Figs. 6a and b.

The simulation parameters for phase-shifted pulse-width

modulation are as follows: inverter rating 5 kW, three-phase
load R 100 V, L 20 mH, each source Vdc 100 V and

Fig. 7 Phase-shifted pulse-width modulation output voltage and harmonic spectrum

a SH PWM
b SFO PWM
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Fig. 8 Constant switching frequency pulse-width modulation output voltage

a
b
c
d
e
f

PD-SH PWM
PD-SFO PWM
POD-SH PWM
POD-SFO PWM
APOD-SH PWM
APOD-SFO PWM

switching frequency 5 kHz. Phase leg voltages have been

calculated and drawn for SH PWM method in Figs. 7a and b.
6.2

Hardware results

A 5 kW hardware set-up of three-phase ve-level cascaded

inverter has been built to validate the theoretical analysis.
The hardware parameters for CSF PWM are as follows:
three-phase load R 100 V, L 20 mH, each source
Vdc 100 V, fundamental frequency 50 Hz, switching
frequency 2 kHz and Xilinx Spartan DSP controller

(FPGA). The three-phase output voltage waveform for PD

PWM method is shown in Figs. 8a and b. The waveform
for POD PWM method is shown in Figs. 8c and d. The
output voltage waveform for APOD PWM method is shown
in Figs. 8e and f.
The hardware parameters for VSF PWM are as follows:
inverter rating 5 kW, three-phase load R 100 V,
L 20 mH, each source Vdc 100 V, fundamental
frequency 50 Hz, switching frequency 2 kHz, 4 kHz and
Xilinx Spartan DSP controller (FPGA). The three-phase
output voltage waveform for VSFMC-SH PWM method is

Fig. 9 Variable switching frequency pulse-width modulation

a SH PWM
b SFO PWM
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Fig. 10 Phase-shifted pulse-width modulation output voltage

a SH PWM
b SFO PWM

shown in Fig. 9a and VSFMC-SFO PWM method is shown

in Fig. 9b.
The hardware parameters for PSC PWM are as follows:
inverter rating 5 kW, three-phase load R 100 V,
L 20 mH, each source Vdc 100 V, fundamental
frequency 50 Hz, switching frequency 5 kHz and Xilinx
Spartan DSP controller (FPGA). The three-phase output
voltage waveform for PSC-SH PWM method is shown in
Fig. 10a and PSC-SFO PWM method is shown in Fig. 10b.

Conclusion

In this paper, three different schemes adopting the constant

switching frequency, variable switching frequency and
phase-shifted pulse-width modulation concepts are
incorporated. The subharmonic pulse-width modulation
and switching frequency optimal pulse-width modulation
techniques analysed by means of all the three methods. It
is observed that, the subharmonic pulse-width modulation
and switching frequency optimal pulse-width modulation
in phase-shifted pulse-width modulation gives better
results when compared to the other two methods. Here,
the subharmonic pulse-width modulation strategy reduces
the total harmonic distortion and switching frequency
optimal pulse width modulation strategies enhances the
output voltage. The multilevel inverter improves output
voltage, reduces output total harmonic distortion and
voltage stress on semiconductors switches and hence the
schemes are conrmed by simulation and experimental
results.

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References

1 Corzine, K.A., Familiant, Y.L.: A new cascaded multi-level H-bridge

drive, IEEE Trans. Power Electron., 2002, 17, pp. 125 131
2 Teodorescu, R., Blaabjerg, F., Pedersen, J.K., Cengelci, E., Enjeti, P.N.:
Multilevel inverter by cascading industrial VSI, IEEE Trans. Ind.
Electron., 2002, 49, pp. 832 838
3 Lai, J.S., Peng, F.Z.: Multilevel converters a new bread of
converters, IEEE Trans. Ind. Appl., 1996, 32, pp. 509 517
4 Maynard, T.A., Fadel, M., Aouda, N.: Modelling of multilevel
converter, IEEE Trans. Ind. Electron., 1997, 44, pp. 356364
5 Bhagwat, P., Stefanovic, V.R.: Generallized structure of a multilevel
PWM inverter, IEEE Trans. Ind. Appl., 1983, 1A-19, pp. 1057 1069
6 Rodriguez, J., Lai, J.-S., Zheng Peng, F.: Multilevel inverters; a survey
of topologies, controls, and applications, IEEE Trans. Ind. Electron.,
2002, 49, pp. 724738
7 Carrara, G., Gardella, S., Marchesoni, M., Salutari, R., Sciutto, G.: A
new multilevel PWM method: a theoretical analysis, IEEE Trans.
Power Electron., 1992, 7, pp. 497 505
8 Tolber, L.M., Habetler, T.G.: Novel multilevel inverter carrier based
PWM method, IEEE Ind. Appl., 1999, 35, pp. 1098 1107
9 McGrath, B.P., Holmes, D.G.: Multicarrier PWM strategies for
multilevel inverter, IEEE Trans. Ind. Electron., 2002, 49, pp. 858 867
10 Koaro, S., Lezana, P., Anguio, M., Rodriguez, J.: Multicarrier PWM
DC-link ripple forward compensation for multilevel inverters, IEEE
Trans. Power. Electron., 2008, 123, pp. 5256
11 Palanivel, P., Dash, S.S.: A FPGA based variable switching frequency
multicarrier pulse width modulation for three phase cascaded multilevel
inverter. Proc. Int. Conf. on INCACEC-2009, Erode, India, June 2009,
pp. 811815
12 McGrath, B.P., Holmes, D.G., Meynard, T.: Reduced PWM harmonic
distortion for multilevel inverter operating over a wide modulation
range, IEEE Trans. Power Electron., 2006, 21, pp. 941949
13 Sirisukpraserl, S., Lai, J.S., Liu, T.H.: Optimum harmonic reduction
with a wide range of modulation indices for multilevel converters,
IEEE Trans. Ind. Electron., 2002, 49, pp. 875 881
14 Naderi, R., Rahmati, A.: Phase-shifted carrier PWM technique for
general cascaded inverters, IEEE Trans. Power Electron., 2008, 23,
pp. 1257 1269

IET Power Electron., 2011, Vol. 4, Iss. 8, pp. 951 958

doi: 10.1049/iet-pel.2010.0332