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CMPE 640
pMOS
CMOS Basics
CMPE 640
Source
Source
Gate
p substrate
Drain
Polysilicon
Thin
Oxide
SiO2
Drain
L
n+
Gate
nMOS
n+
n+
p
n+
Source
Gate
bulk Si
Drain
Polysilicon
SiO2
pMOS
p+
p+
n
bulk Si
CMOS Basics
CMPE 640
VDD
GND
(pactive)
layer #3
layer #2
p+
n+
p+
n+
(drains)
p+
n+
layer #1
n-well (nwell)
(nactive)
p-transistor
3
CMOS Basics
CMPE 640
CMOS Basics
CMPE 640
d
nMOS
pMOS
g=0
g=1
d
OFF
ON
OFF
ON
s
CMOS Basics
CMPE 640
Signal Strengths
Signals such as 1 and 0 have strengths, measures ability to sink or source current
VDD and GND Rails are the strongest 1 and 0
Under the switch abstraction, G has complete control and S and D have no effect.
In reality, the gate can turn the switch on only if a potential difference of at least Vt
exists between the G and S.
We will look at Vt in detail later on in the course.
Thus signal strengths are related to Vt and therefore p and n transistors produce signals with
different strengths
Strong 1: VDD, Strong 0: GND, Weak 1 :(~VDD -Vt) and Weak 0 :(~GND + Vt).
nMOS
G 1
S
0
*** Strong 0***
1
Weak 1
pMOS
G 0
0
Weak 0
1
*** Strong 1***
6
CMOS Basics
CMPE 640
CMOS Inverter
Vdd
P1
A
Out
N1
CMOS Inverter
THE CONFIGURATION BELOW FOR A BUFFER IS NOT A GOOD IDEA. WHY?
A
P1
Vdd
N1
BAD IDEA
Out
CMOS Basics
CMPE 640
Vdd
A
P1
A
B
P2
Out
N2
N1
Vdd
A
P1
P2
N1
A
B
B
Out
N2
CMOS Basics
CMPE 640
Pass Transistor
The off-state of a transistor creates a high impedance condition Z at the drain.
No current flows from source to drain. So transistors can be used as switches.
g=0
g
s
Input g = 1 Output
0
strong 0
g=1
s
d
g=1
s
1
Input
g=0
g
s
g=1
degraded 1
g=0
Output
degraded 0
g=0
strong 1
However, as we previously discussed this will produce degraded outputs, if only one
transistor is used as a switch.
9
CMOS Basics
CMPE 640
Transmission Gates
A
P1
N1
A
In
Out
Input
g
a
b
gb
b
gb
g = 0, gb = 1
a
b
g = 1, gb = 0
0
strong 0
g = 1, gb = 0
a
b
g = 1, gb = 0
strong 1
1
g
a
g
b
gb
Output
b
gb
10
CMOS Basics
CMPE 640
2-to-1 MUX
Select
A
In
Out
Select
Out
Select
Out
VDD
Select
CMOS Basics
CMPE 640
D Latch
Positive
level-sensitive
latch
CLK
Latch
CLK
Q
Q
CLK
D
CLK
Q
Q
0
CLK
If CLK is unavailable one extra inverter
needed to generate it using CLK
CLK
CLK
12
CMOS Basics
CMPE 640
D Flip-Flop
Positive
edge-triggered
flip-flop
a.k.a
master-slave
flip-flop
CLK
CLK
D
Flop
Q
Q
CLK
CLK
CLK
QM
D
CLK CLK Master
QM
Master
Latch
Latch
CLK
Slave
Q
CLK CLK Slave
Q
CLK
CLK
CMOS Basics
CMPE 640
D Flip-Flop Operation
D
QM
QM follows D, Q is latched
CLK = 0
QM
QM transferred to Q, QM latched
CLK = 1
CLK
Positive
edge-triggered
flip-flop
D
Q
14
CMOS Basics
CMPE 640
Vdd
B
P1
Vdd
A
P2
Out
N2
N1
15
CMOS Basics
CMPE 640
A
B
Out
16
CMOS Basics
CMPE 640
Vdd
P2
P1
P3
P4
OAI
N1
B
C
N2
N3 N4
17