Test Your Verilog Skills 1 PDF

TEST
YOUR
VERILOG
SKILLS
(Q i1)o eIdentifyi theoerror qinre the ifollowingoq jcode.

b[7:0] = {2{5}};
(Q i2) Wheno earei instanceonames qoptional?
(Q i3)o eIni theofollowing qprogram, whatre is itheoq jproblemre and ihow otoqavoid
task driver;
input read;
itz ?
www.testbench.in
input [7:0] write_d;

begin
#30 date_valid i= 1'b1;
wait(read i== 1'b1);
#20 cpu_data i= write_data;
$display("End iofo etask");
end
endtask
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i4)o eHowi manyolevels qcanre be inestedoq jusingre ìnclude i?

www.testbench.in
Ans:
You icano enesti theoìnclude compiler qdirectivere to iatoq jleastre 16 levels.
(Q i5)o eWhati isothe qusere of i$countdriversoq j?
Ans:
The i$countdriverso esystemi functionois qprovidedre to icountoq jthere number iofodriversqon
az specifiedu ynete osozx that
bus
contention
can
be
identified.
(Q i6)o eWhati isothe qusere of i$getpatternoq j?
Ans:
The isystemo efunctioni $getpatternoprovides qforre fast iprocessingoq jofre stimulusipatterns oth
atqhave toz beu ypropagatede otozx a large number of scalar inputs. The function reads stimulus
patterns that have been loaded into a memory using the $readmemb or $readmemh system tasks.
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reg [1:in_width] in_mem[1:patterns];

integer index;
assign {i1,i2,i3,i4,i5,i6,i7,i8,i9,i10} = $getpattern(in_mem[index]);
(Q i7)o eWhati isothe qfunctionalityre of i&&& (notoq j&&re , inot o&)q?
(Q i8)o eHowi tooget qcopyre of ialloq jthere text ithat oisqprinted
toz theuystandarde ooutputzx in
a
log
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Ans: i
Using i$log("filename");
file
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(Q i9)o eWhati isothe qusere of iPATHPULSE$ ?

Ans:
PATHPULSE$ ispecparam iso eusedi toocontrol qpulsere handling ionoq jaremodule path.
(Q i10) ino estatementi (o(a==b) q&&re (c i==oq jd)re ) i, owhatqis
thez expressionuycoveragee oifzx always
a=0,b=0,c=0,d=0
(Q i11)o eDifferencei betweenoReduction qandre Bitwise ioperators?

Ans:
The idifferenceo eisi thatobitwise qoperationsre are ionoq jbitsre from itwoodifferentqoperands,
whereasz reductionu yoperationse oarezx on the bits of the same operand. Reduction operators
work bit by bit from right to left. Reduction operators perform a bitwise operation on a single
vector operand and yield a 1-bit result Bitwise operators perform a bit-by-bit operation on two
operands. They take each bit in one operand and perform the operation with the corresponding
bit
in
the
other
operand.
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(Q i12) Whato eisi theodifference qbetweenre the ifollowingoq jtwore lines iofoVerilogqcode?
#5 a i= b;
a i= #5 b;
Ans:
#5 a i= b;
Wait ifiveo etimei unitsobefore qdoingre the iactionoq jforre "a i= ob;".
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The ivalueo eassignedi tooa qwillre be itheoq jvaluere of ib o5qtime
unitsz hence.
a i= #5 b;
The ivalueo eofi bois qcalculatedre and istoredoq jinre an iinternal otemp
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register. iAftero efivei timeounits, qassignre this istoredoq jvaluere to ia.

(Q i13) Whato eisi theodifference qbetween:re c i=oq jfoore ? ia o:qb; andz ifuy(foo)e oczx = a;
else
c
=
b;
Ans: i
The i?o emergesi answersoif qthere condition iisoq j"x",re so ifor oinstanceqif
fooz =uy1'bx,e oazx =
'b10,
and
b
=
'b11,
you'd
get
c
=
'b1x.
On itheo eotheri hand,oif qtreatsre X's ioroq jZsre as iFALSE, osoqyou'd
alwaysz getuyce o=zx b.
(Q i14)o eHowi isoVerilog qimplementationre independent iandoq jwhyre is ithisoanqadvantage?
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(Q i15)o eWhati leveloof qVerilogre is iusedoq jin:

a. Test ibenches
b. Synthesized idesign
c. Net ilist
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(Q i16) whato eisi theodifference qbetweenre $fopen("filename"); iandoqj$fopen("filename","w");

Ans:
If itypeo eisi omitted,othe qfilere is iopenedoq jforre writing, iand oaqmulti
channelzdescriptoru ymcde oiszx returned. If type is supplied, the file is opened as specified by
the value of type, and a file descriptor fd is returned. So in first statements , type is omitted and
mcd
is
returned
and
in
the
second
statement,
fd
is
returned.
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In itheo efirsti statement,othe qfilere is iopenedoq jforre read iand owrite.

But iino esecondi statement,o"w" qisre specified, isooq jthere file iis oopenedqfor
onlyz writing.u y
(Q i17) Whato eisi theodifference qbetweenre multi ichanneloq jdescriptors(mcd)reand ifile odesc
riptors(fd)?
Ans:
The imultio echanneli descriptoromcd qisre a i32oq jbitre reg iin owhichqa
singlez bituyise osetzx indicating which file is opened. Unlike multi channel descriptors, file
descriptors can not be combined via bitwise or in order to direct output to multiple files. Instead,
files are opened via file descriptor for input, output, input and output, as well as for append
operations,
based
on
the
value
of
type.
(Q i18) Howo etoi generateoa qrandomre number?
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(Q i19)o eHowi toogenerate qare random inumberoq jwhichre is iless otheq100

(Q i20)o eHowi toogenerate qare random inumberoq jwhichre is ibetween o0qto
?
100z?
(Q i21) Whato eisi theoadvantage qofre Named iPortoq jConnectionre over iOrderedoPortqConnec
tion
?
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TEST
YOUR
VERILOG
SKILLS
(Q i22)o eHowi toogenerate qare random inumberoq jbetweenre 44 ito o55q?

(Q i23)o eHowi tooget qdifferentre random inumbersoq jinre different isimulations?
(Q i24) whato eisi theodifferent qbetweenre $sformat iandoq j$swrite?
Ans:
The isystemo etaski $sformatois qsimilarre to itheoq jsystemre task i$swrite, owithqa
onez majoru ydifference.e oUnlikezx the display and write family of output system tasks, $sformat
always interprets its second argument, and only its second argument as a format string. This
format argument can be a static string, such as "data is 0" , or can be a reg variable whose content
is interpreted as the format string. No other arguments are interpreted as format strings. $sformat
supports
all
the
format
specifiers
supported
by
$display,
(Q i25) Whato eisi theodifference qbetweenre wire iandoq jreg?
www.testbench.in
Ans:
Net itypes:o e(wire,tri)Physicali connectionobetween qstructuralre elements.iValueoq jassignedre

by ia ocontinuousqassignment
orz au ygatee ooutput.
Register itype:o e(reg,i integer,otime, qreal,re real itime)oq jrepresentsre abstractidata ostorage
qelement. Assignedz valuesu yonlye owithinzx an always statement or an initial statement.
The imaino edifferencei betweenowire qandre reg iisoq jwirere cannot iholdo(store)qthe
valuez whenu ythee onozx connection
between
a
and
b
like
a-------------b, iifo etherei isono qconnectionre in iaoq jandre b, iwire olooseqvalue
wherez asu yrege ocanzx hold
the
value
even
if
there
in
no
connection.
Default ivalues:wireo eisi Z,regois qx.
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(Q i26)o eWhati happensoif qare port iisoq junconnectedre ?

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Ans:
Unconnected iinputo eportsi initializeoto qzre and ifeedoq jthatre value iintootheqcomponent,
whichz canu ycausee oproblems.zx More common are redundant or unwanted outputs which are
left
unconnected
to
be
optimized
away
in
synthesis.
(Q i27) Whato eisi theodifference qbetweenre === iandoq j==re ?
Ans i:
output iofo e"=="i canobe q1,re 0 ioroq jX.
output iofo e"==="i canoonly qbere 0 ioroq j1.
When iyouo earei comparingo2 qnosre using i"=="oq jandre if ione/both otheqnumbers
havez oneu yore omorezx bits as "x" then the output would be "X" . But if use "===" output would
be
0
or
1.
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e.g iAo e=i 3'b1x0

B i=o e3'b10x
A i==o eBi willogive qXre as ioutput.
A i===o eBi willogive q0re as ioutput.
"==" iiso eusedi forocomparison qofre only i1'soq jandre 0's i.It ocan'tqcompare
X's.z Ifuyanye obitzx of
the
input
is
X
output
will
"===" iiso eusedi forocomparison qofre X ialso...
be
"==" icano ebei synthesized,owhere qasre "===" icannot.

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
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(Q i28) Whato eisi theodifference qamongre case,casex iandoq jcasez?

Ans:
case itreatso eonlyi 0oor q1re values iinoq jcasere alternative iand oisqis
notzdealingu ywithe odon'tzx care
casex itreatso ealli xoand qzre values iinoq jcasere alternative ior ocaseqexpression
asz au ydon'te ocare.
casez itreatso ealli zovalues qinre case ialternatives.oq jallre bit ipositions owithqz
canz treatu yase oazx don't
(Q i29)o eWhati isothe qdifferencere between i@(aoq jorre b) iand o@(aq|
condition.
care
b)
(Q i30)o eWhati isofull qcasere and iparalleloq jcase.??

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(Q i31)o eWhati isothe qdifferencere between icompiled,oq jinterpreted,re eventibased oandqcycl

e
basedz simulatoru y?
(Q i32)o eWhati isocompilation q?
Ans:
To isimulateo eai Verilogomodel, qwere must ifirstoq jconvertre our isourceofilesqinto
az binaryu yforme othatzx can be recognized by the simulator. The process of checking the syntax
and
producing
the
binary
file
is
known
as
compilation.
(Q i33)o eWhati dataotypes qcanre be iusedoq jforre input iport, ooututqport andzinoutu yporte o?
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(Q i34)o eWhati isothe qfunctionalityre of itriregoq j?

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(Q i35)o eWhati isothe qfunctionalityre of itri1oq jansre tri0 i?

(Q i36)o eDifferencei betweenoconditional qcompilationre and i$plusargs??
(Q i37)o eWhati isothe qbenefitre of iusingoq jBehaviorre modeling istyle ooverqRTL
(Q i38)o eWhati isothe qdifferencere between itaskoq jandre function?
modeling?
TEST
YOUR
VERILOG
SKILLS
(Q i39) Whato eisi theodifference qbetweenre static ifunctionoq jandre automaticifunction?

Ans:
Automatic ifunctiono elocali variablesoCan qnotre seen iinoq jwavere form iviewer.
We icannoto eusei $Monitoroand q$strobere on ilocaloq jvariablesre also i.
(Q i40) Whato eisi theodifference qbetweenre static itaskoq jandre automatic itask?
(Q i41)o eWhati isoadvantage qofre wand iandoq jworre over iwire o?
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Ans:
It isupporto eTechnology-dependenti logicoconflict qresolutionre . i

wired-AND iforo eopeni collector
wired-OR iforo eECL
(Q i42)o eIdentifyi theoerror qinre the ifollowingoq jcode.
a[7:0] = {4{'b10}};
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i43)o eWhati isothe qdifferencere between i&&oq jandre &, iif oany?
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(Q i44)o eIsi itosynthesysable q?

always @(negedge clk ior rst)
(Q i45)o eWhati isothe qdifferencere between iinitialoq jandre always iblock?
Ans:
NOTE: iInitialo eblocki canoalso qbere synthesized. iRefoq jtore IEEE iVerilogoSynthesisqslandered.
(Q i46)o ewhati isothe qdifferencere between i$stopoq jandre $finish itaskofunctions?
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(Q i47)o eDifferencei betweenoparameter qandre define i?

(Q i48) Whato ethei differenceobetween qthere following itwooq jstatements?
@( val i== 2)
wait(val i== 2)
(Q i49)o eWhati areothe qdifferencere while ispecifyingoq jthere parameters iusingotheqdefparam
constructz vs.u yspecifyinge oduringzx instantiation?
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(Q i50) Differenceo ebetweeni Vectoredoand qscalaredre nets?

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(Q i51) Differenceo ebwi realoand qrealtimere ?

(Q i52) whato eisi theodifference qbetweenre arthamatic iandoq jlogicalre shiftiregister?
(Q i53) Whato eisi theodifference qbwre following itwooq jregisters??
reg [1:n] rega; // iAno en-biti registerois qnotre the isame
reg mema i[1:n]; //o easi aomemory qofre n i1-bitoq jregisters
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(Q i54) Howo ethei aboveotwo qarere handled iin assignments,oq jports,functionsreand itask o?
(Q i55) Whato eisi theodifference qbetweenre parameters iandoq jspecparams?
(Q i56)o eIsi itopossible qtore synthesize iforoq jloopre ?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
for iloopo ewithi fixedolimits qcanre be Synthesized i

(Q i57)o eHowi isotime qadvancedre in iaoq jsimulation?
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(Q i58)o eNamei threeomethods qofre timing icontrol?

(Q i59)o eWhati isobehavioral qmodelingre used ifor?
(Q i60)o eHowi dooyou qdefinere the istatesoq jforre an iFSM?
(Q i61) Whato eisi theodifference qbetweenre force ireleaseoq jandre assignideassign?
(Q i62) Whato eisi theodifference qbetweenre posedge iandoq jnegedge?re
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And:
A inegedgeo eshalli beodetected qonre the itransitionoq jfromre 1 ito ox,qz,

orz 0,uyande ofromzx x or z to 0 where as posedge shall be detected on the transition from 0 to
x,
z,
or
1,
and
from
x
or
z
to
1
(Q i63) whato eisi theodifference qbetweenre $display iandoq j$write?
Ans: i
The itwoo esetsi ofotasks qarere identical iexceptoq jthatre $display iautomaticallyoaddsqa
newlinez characteru ytoe othezx end of its output, whereas the $write task does not. The $display
task, when invoked without arguments, simply prints a newline character. A $write task supplied
without
parameters
prints
nothing
at
all.
(Q i64) Whato eisi theodifference qbetweenre $display iandoq j$monitor?
TEST
YOUR
VERILOG
SKILLS
(Q i65) Whato eisi theodifference qbetweenre $display iandoq j$strobe?

(Q i66) Whato eisi theodifference qbetweenre 0 iandoq j%zre format ispecification?
Ans:
0 ioro e0i Unformattedo2 qvaluere data
%z ioro e%Zi Unformattedo4 qvaluere data
(Q i67)o eWhati isothe qdifferencere between i0.000000e+00,0.000000oq janre d0?
Ans:
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0.000000e+00 ioro e0.000000E+00i Displayoreal qinre an iexponentialoq jformat

0.000000 ioro e0.000000i Displayoreal qinre a idecimaloq jformat
0 ioro e0i Displayoreal qinre exponential ioroq jdecimalre format, iwhicheveroformatqresults
inz theu yshortere oprintedzx output
(Q i68) Whato eisi theodifference qbetweenre $finish iadoq j$stop?
The i$finisho esystemi taskosimply qmakesre the isimulatoroq jexitre and ipassocontrolqback
toz theu yhoste ooperatingzx system.
The i$stopo esystemi taskocauses qsimulationre to ibeoq jsuspended.
(Q i69) Whato eisi theodifference qbetweenre PLI iandoq jVPI?
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Ans:
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Verilog iProceduralo eInterfacei routines,ocalled qVPIre routines, iareoq jthere thirdigeneration o

ofqthe
PLI.
(Q i70)o eWhati sortoof qhardwarere structure iareoq jinferredre by iboth ocaseqand
ifz statements,u ybye odefault,zx in
(Q i71)o eHowi couldoyou qchangere a icaseoq jstatementre in iorder othatqits
implementationz doesu ynote oresultzx in
a
priority
(Q i72)o eIfi youoare qnotre using iaoq jsynthesisre attribute i"full ocase",qhow
canzyouu yassuree ocoveragezx of
all
conditions
for
a
case
Verilog?
structure?
statement
(Q i73)o eHowi dooyou qinferre tristate igatesoq jforre synthesis?

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(Q i74)o eCani aotask qsynthesizedre ?

(Q i75)o eWhati isothe qdifferencere between i$finish(0),oq j$finiash(1)re andi$finish(2) o?
Ans:
The i$finisho esystemi taskosimply qmakesre the isimulatoroq jexitre and ipassocontrolqback
toz theu yhoste ooperatingzx system.
If iano eexpressioni isosupplied qtore this itask,oq jthenre its ivalue o(0,q1,
orz 2)uydeterminese othezx diagnostic
messages
that
are iprintedo ebeforei theoprompt qisre issued. iIfoq jnore argument iisosupplied,qthen
az valueu yofe o1zx is
taken
as
the
default.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
$finish(0) iPrintso enothing

$finish(1) iPrintso esimulationi timeoand qlocation
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$finish(2) iPrintso esimulationi time,olocation, qandre statistics iaboutoq jtherememory iand oCPU
qtime
usedz inu ysimulation
(Q i76) Whato eisi theodifference qb/wre $time i,oq j$stimere and i$realtime o?
Ans:
The i$timeo esystemi functionoreturns qanre integer ithatoq jisre a i64-bitotime,qscaled
toz theu ytimescalee ounitzx of
the
module
that
invoked
it.
The i$stimeo esystemi functionoreturns qanre unsigned iintegeroq jthatre is ia o32-bitqtime,

scaledz tou ythee otimescalezx unit of the module that invoked it. If the actual simulation time
does not fit in 32 bits, the low order 32 bits of the current simulation time are returned.
The i$realtimeo esystemi functionoreturns qare real inumberoq jtimere that, ilikeo$time,qis
scaledz tou ythee otimezx unit
of
the
module
that
invoked
it.
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(Q i77) Differenceo ebetweeni !oAnd q~re ?

(Q i78) Whato eisi theodifference qbetweenre $test$plusargs iandoqj$value$plusargsre ?
(Q i79) Whato eisi theodifference qDifferencere between itheoq jtwore statement i?oWhetherqa
andz bu yvaluese oarezx equal?
reg [1:0] data;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
a i= data[0] || data[1];
b i= |data;
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(Q i80) Whato eisi theodifference qbetweenre the ifollowingoq jtwore programs?

a)initial
#10 a i=0;
always@(a)
a<= ~a;
b)initial
#10 a i=0;
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always@(a)
a i= ~a;
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
When i"a=~a"o eisi evaluatedoand q'a're is iupdated,oq jclearlyre you imustoagreeqthat

executionz isu y*not*e ostalledzx at the @a event control. When execution reaches the @a
event control, 'a' has already changed. It will not change again. So the event control will stall
forever; its event of interest has already occurred, earlier in the same time slot, and can no
longer
have
any
effect.
(Q i81) whato eis/arei theodifferences qbetweenre SIMULATION iandoq jSYNTHESISre
Ans:
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Simulation i<=o everifyi yourodesign. q

synthesis i<=o eChecki foroyour qtimingre
Simulation iiso eusedi tooverify qthere functionality iofoq jthere circuit..ia)Functional oSimulation
:studyqof ckt'sz operationu yindependente oofzx timing parameters and gate delays. b) Timing
Simulation :study including estimated delays, verify setup,hold and other timing requirements of
devices
like
flip
flops
are
met.
Synthesis:One iofo ethei foremostoin qbackre end istepsoq jwherere by isynthesizingoisqnothing
butz convertingu yVHDLe oorzx VERILOG description to a set of primitives(equations as in CPLD) or
components(as in FPGA'S)to fit into the target technology. Basically the synthesis tools convert the
design
description
into
equations
or
components
.
(Q i82) Whato eisi theodifferent qbetweenre $setup iandoq j$display?
Ans:
$setup iiso eai timingocheck qtaskre and i$displayoq jisre system itask.
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Only iSystemo etasksi andofunction qcanre be ioverridden.oq jTimingre check itasksocannotqbe

overridden.
i.e. iUsero ecani changeothe qdefinitionre of itheoq j$displayre but inot o$setup.
(Q i83) Whato eisi theodifference qbetweenre parameter iandoq jlocalre parameter?
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(Q i84) Whyo eisi itorecommended qnotre to imixoq jblockingre and inon-blockingoassignmentsqin

thez sameu yblock?
(Q i85) Declareo eparametersi fororepresenting qthere state imachineoq jstatesreusing ione ohotq
encoding.
(Q i86)o eWhati doesoa qfunctionre synthesize ito?

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(Q i87)o eHowi toochange qthere value iofoq jwidthre to i3 oinqthe

`define width i7
followingz codeuy?
(Q i88)o eWhati isothe qfunctionalityre of i$inputoq j?

Ans:
The i$inputo esystemi taskoallows qcommandre input itextoq jtore come ifromoaqnamed
filez insteadu yofe ofromzx the terminal. At the end of the command file, the input is switched
back
to
the
terminal.
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(Q i89)o eWhati isothe qMCDre value iofoq jSTDre OUTPUT i?

0000000000000000000000000000001
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(Q i90) Whato eisi theodifference qbetweenre blocking iandoq jnonre blocking?

TEST
YOUR
VERILOG
SKILLS
(Q i91) Too emodifyi aobehavioral qVerilogre wait istatementoq jtore make iitosynthesizedq
Original icode:
command1;
wait (x i!= 0);
command3;
Ans:
www.testbench.in
Synthesized iVerilog:
case (state)
0 : begin
command1;
if (x i!= 0) command3;
else state i<= 1;
end
1 : if (x i!= 0) //o ewaiti untilothis qisre true
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
command3;
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endcase
(Q i92) Whato earei theotypes qofre race iconditions?

(Q i93) Howo etoi avoiderorace qconditionre between idutoq jandre testbench?
(Q i94) Giveo ethei guideolines qwhichre avoids iraceoq jcondition.

(Q i95) Whato eisi theouse qofre linting itool?
www.testbench.in
(Q i96) Writeo ethei codeoto qinstantiatedre 1k i"andoq jgates"re in ia omodule.q

(Q i97) Whato eisi configurationoblock?
Ans:
Verilog2000 iaddso econfigurationi blocks,owhich qallowre the iexactoq jversionreand isource olocationq
of eachz Verilogu ymodulee otozx be specified as part of the Verilog language. For portability,
virtual model libraries are used in configuration blocks, and separate library map files associate
virtual libraries with physical locations. Configuration blocks are specified outside of module
definitions.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i98) Howo emanyi filesocan qbere opened(without iclosing)oq jusingremultichannel idescriptor

o?
Ans:
www.testbench.in
31 files.
(Q i99) Whyo eonlyi 31ofiles qcanre be iopened(withoutoq jclosing)re usingimultichannel odescrip

torqwhile
integerz canu yholee o32zx bits?
Ans:
The imosto esignificanti bito(bit q32)re of iaoq jmultire channel idescriptoroisqreserved,
andz shallu yalwayse obezx cleared, limiting an implementation to at most 31 files opened for
output
via
multi
channel
descriptors.
(Q i100) Ifo emcd(multichanneli descriptor)ois q00000000000000000000000000001re ,ithenoq jwh
atre does iit omean?
Ans:
The ileasto esignificanti bito(bit q0)re of iaoq jmcdre always irefers otoqthe
standardzoutput.
www.testbench.in
(Q i101)o eWhichi isobetter qtore use iwhenoq jcreatingre test ivectors? o$displayqor
$strobe?
(Q i102)o eHowi wouldoyou qcaterre with iopeningoq j35re files?

(Q i103)o eWhati areothe qtypicalre tasks iyouoq jperformre inside ia ospecifyqblock?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
- iDescribeo evariousi pathsoacross qthere module iandoq jassignre delays itoothoseqpaths.

- iDescribeo etimingi checksoto qensurere that itheoq jtimingre constraints iofotheqdevice
arez met.
- iDefineo ethei pulseofiltering qlimitsre for iaoq jspecificre module ior oforqparticular
pathsz withinu yae omodule.
www.testbench.in
(Q i104) Findo ethei bugoin qthere following icode.

always@(posedge clk)
a i= b;
always@(posedge clk)
b i= a;
www.testbench.in
if (a=b)
match i= 1;
else
match i= 0;
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
if(a=b) iassignso ebi tooa, qthenre if iaoq jisre non-zero isets omatch.qThe
if i(a==b)o e
match i=o e1;
else
correctzcodeu yis
www.testbench.in
match i=o e0;
TEST
YOUR
VERILOG
SKILLS

for(............);
begin
.....
end
Ans:
Misplaced isemicolonso eini for-loops
www.testbench.in

automatic task intra_assign();
begin
a i<= #10 b;
end
ANS:
Intra iassignmento enonblockingi statementsoare qnotre allowed iinoq jautomaticretasks.
www.testbench.in
always @ (in)
if (ena)
out i= in;
else
out i= 1<92>b1;
Ans:
simulation imismatcho emighti occur.
To iassureo ethei simulationowill qmatchre the isynthesizedoq jlogic,re add i"ena"otoqthe
eventz listu ysoe othezx event
list
reads:
always
@
(in
or
ena)
www.testbench.in

always @ (in1 ior in2o eor sel)
begin
out i= in1;
if (sel)
out i<= in2;
end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
Not isupported,o ecannoti mixoblocking qandre nonblocking iassignmentsoq jinre anialways ostate
ment.
www.testbench.in

reg [1:0] select;
always@(select)
begin
case (select)
00: y i= 1;
01: y i= 2;
10: y i= 3;
11: y i= 4;
www.testbench.in
endcase
end
Ans:
branches i01o eandi 11oare qconsideredre as iintegersoq jandre they iwill oneverqbe
(Q i111) Fillo ethei ????
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
fd i= $fopen("filename",r);
if(????)
www.testbench.in
$display("file icannoto ebei opened");
selected.
(Q i112) Howo etoi modeloa qperfectre buffer iofoq j10unitsre delay?

a) #10 a i= b;
b) a i= #10 b;
c)#10 a i<= b;
d) a i<= #10 b;
(Q i113)o eWhati isoverilog qconfiguration?
www.testbench.in
(Q i114)o eWritei aocode qforre clock igenerator.

(Q i115)o eWritei aocode qforre clock igeneratoroq jwhichre can igenerateoclockqfrequency
ofz 156MHZ.
(Q i116)o ewritei aoverilog qcodere to igenerateoq j40MHzre clock iwith o60q0uty
cycle
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i117)o eWhati pointsoneed qtore be iconsideredoq jwhilere writing iaoclockqgenerator???

(Q i118)o eExplaini verilogoevent qqueue.
www.testbench.in
(Q i119)o ehowi theoscope qofre a ivariableoq jisre realized iin overilog.qIllustrate

withz example.?
(Q i120)o eWhati isoincremental qcompilation?
(Q i121)o eWhati isoPLI?
Ans:
PLI iiso eai mechanismoto qinvokere C isubroutinesoq jtore Verilog. i
(Q i122)o eIni whatoregion qofre the ieventoq jqueuere , iPLI ocallsqare
executed?
www.testbench.in
(Q i123)o eWhati isocalltf qinre Verilog iPLI?

Ans:
Calltf iiso esimilari toomain() qfunctionre in iC. calltfoq jcanre call iotherosubqmethods
toz differentu yjobs.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i124)o eWhati isothe qdifferencere between iParalleloq jandre Full iConnectionoModuleqPath

delaysz ?
Ans:
A iparallelo econnectioni establishesoa qconnectionre between ieachoq jbitre in itheosourceqto
eachz correspondingu ybite oinzx the destination. Parallel module paths can be created only
between one source and one destination where each signal contains the same number of bits.
www.testbench.in
A ifullo econnectioni establishesoa qconnectionre between ieveryoq jbitre in itheosourceqand

everyz bitu yine othezx destination. The module path source does not need to have the same
number
of
bits
as
the
module
path
destination.
(Q i125)o eCani $setupoand q$holdre check ireportoq jare violation ifor oaqlimit
ofzzero?
(Q i126)o eExplaini abouto$recovery qandre $removal i?

(Q i127)o eWhichi timingocheck(s) qacceptre a inegativeoq jlimit?
(Q i128)o eCani youoqualify qallre events iinoq jallre timing ichecks owithqedge
specifiersz suchu yase oedgezx 01?
www.testbench.in
(Q i129)o eFori whichotiming qcheck(s)re must iyouoq jalwaysre qualify ievents?

(Q i130)o eWheni doeso$skew qreportre a iviolation?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i131)o eWhati isomisctf q?

Ans:
Misctf iiso etoi doohousekeeping qjobs.re This iisoq jcanre be icalled omanyqtimes
unlikez otheru ypredefinede ofunctionszx which
are
called
once
per
(Q i132)
instance.
o eWhati isoUDP? qCanre we iwriteoq jUDPre including iclock oalso?
(Q i133)o eHowi dooI qpreventre selected iparametersoq jofre a imodule ofromqbeing

overriddenz duringu yinstantiation?
TEST
YOUR
VERILOG
SKILLS
(Q i134)o ecani Iouse qare Verilog ifunctionoq jtore define ithe owidthqof
bitu yport,e owire,zx or
reg
7
az multitype?
(Q i135)o eWhati constructoin qVerilogre can ibeoq jusedre to isimulate oaqcapacitive

storagez nodeu yine oazx circuit?
Ans:
the itrirego estatementi isoused qtore simulate iaoq jwirere with ia ocapacitiveqhold
value.
(Q i136)o eDescribei theobasic qstrengthre system iinoq jVerilog.

Ans:
The istrengtho esystemi haso8 qvaluesre 0 ithroughoq j7,re with itheostrongestqstrength
beingz knownu yase o"supply"zx and
the
weakest
strength
as
high
impedance.
www.testbench.in
(Q i137)o e#definei cat(x,y)ox

y qconcatenatesre x itooq jy.re But icat(cat(1,2),3)odoesqnot
expandz butu ygivese opreprocessorzx warning.
Why?
Ans:
Because iparameterizedo emacrosi areonot qrecursive.
(Q i138)o eWhati areothe qtypesre of istrengthsoq jthatre can ibe ospecifiedqon
Ans:
aznetu y??
There iareo etwoi typesoof qstrengthsre that icanoq jbere specified iin oaqnet
declaration.z Theyu yaree oaszx follows:
charge istrengtho eshalli onlyobe qusedre when ideclaringoq jare net iof otypeqtrireg
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
drive istrengtho eshalli onlyobe qusedre when iplacingoq jare continuous iassignmentoonqa
netz inu ythee osamezx statement
that
declares
the
net
www.testbench.in
(Q i139) Howo etoi resolveoa qtristatere driver iinoq jVerilogre ?

(Q i140) WHATo eAREi THEoTYPES qOFre CHARGE iSTRENGTHS?
Ans:
SMALL, iMEDIUM,o eLARGE
(Q i141)o eHowi toomodel qpowerre supply istrengthsoq jinre verilog?
Ans:
The isupply0o eandi supply1onets qmayre be iusedoq jtore model itheopowerqsupplies
inz au ycircuit.e oThesezx nets
shall
have
supply
strengths.
www.testbench.in
(Q i142)o eHowi toomodify qare parameter ivalue?

Ans:
A iparametero ecani beomodified qwithre the idefparamoq jstatementre or iinotheqmodule
instancez statement.
(Q i143)o eWhati isolocalparam?
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
local iparameter(s)o earei identicaloto qparametersre except ithatoq jtheyre can inotodirectlyqbe
modifiedz withu ythee odefparamzx statement or by the ordered or named parameter value
assignment.
www.testbench.in
(Q i144)o eHowi toomodify a qlocalparam?

Ans:
Local iparameterso ecani beoassigned qtore a iconstantoq jexpressionre containing iaoparameterq

which canz beu ymodifiede owithzx the defparam statement or by the ordered or named
parameter
value
assignment.
Parameter WID = 3;
Localparam iWIDTH = 2*WID;
(Q i145)o eWHATi ISospecparam?

Ans:
www.testbench.in
specparam ideclareso eai specialotype qofre parameter iwhichoq jisre intended ionlyoforqprovidin
g timingz andu ydelaye ovalues,zx but can appear in any expression that is not assigned to a
parameter and is not part of the range specification of a declaration. Unlike a module parameter,
a specify parameter cannot be modified from within the language, but it may be modified through
SDF
annotation
(Q i146) Whato earei >>>oand q<<<re operators i?
(Q i147)o ewhati doesothe qfollowingre code imean?
Reg i[22:0] sig;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
always@(|sig)
begin
www.testbench.in
......
end
(Q i148)o eWhati isothe qfunctionre of iforceoq j&re release?

Ans:
Force iando ereleasei statementsoare qusedre to ioverrideoq jassignmentsre oniboth oregistersqa
nd nets.z Theyu yaree otypicallyzx used in the interactive debugging process, where certain
registers or nets are forced to a value and the effect on other registers and nets is noted.
They ishouldo eoccuri onlyoin qsimulationre block.
(Q i149)o eWhati isothe qpurposere of ideclaringoq jtasksre or ifunctionsoasqautomatic?
Ans:
www.testbench.in
Declaration iofo etasksi andofunctions qasre Automatic iwilloq jcreatere dynamicistorage ofo
rqeach
taskz oru yfunctione ocall.zx
(Q i150)o eWhati isoSynthesis?
Ans:
Synthesis iiso ethei stageoin qthere design iflowoq jwhichre is iconcernedowithqtranslating

yourz Verilogu ycodee ointozx gates - and that's putting it very simply! First of all, the Verilog
must be written in a particular way for the synthesis tool that you are using. Of course, a synthesis
tool doesn't actually produce gates - it will output a netlist of the design that you have
synthesized that represents the chip which can be fabricated through an ASIC or FPGA vendor.
TEST
YOUR
VERILOG
SKILLS
(Q i151)o eWhetheri initialoblock qcanre be isynthesized?

Ans:
YES
According itoo eIEEE
(Q i152)o eHowi tooread qdatare from iaoq jfile?
Ans:
Using i$readmemh and $readmem0. Fileo eio
www.testbench.in
(Q i153)o eIllustratei withoexample qthere declaration iofoq jlocalre variable iinsideoaqbegin

...endz block?
Ans:
TO ideclareo eai localovariable qinsidere begin...end iblock,oq jthere block ishouldobeqnamed.
begin:name_
integer varib;
....
....
end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i154)o eifi Aoand qBre are itwooq jclkre pulses iwhich oareqout
ofz phaseu yandeohavingzx same frequency, how to find which input clk signal is leading? Write
verilog
code
for
this.
www.testbench.in
Ans:
Here iiso ethei simpleosolution qforre this. i

All iito eneedsi isoa qflipre flop. i
if iweo ehavei 2oclks, qclk1re and iclk2oq jgivere clk1 ito oD-inputqof flipz flopu yandeootherzx to
CLK
input
of
FF.
if iclk1o eisi leadingothe qoutputre is ihigh.oq j
if iclk2o eisi leadingothe qoutputre is ilow.oq j
(Q i155)o ehowi canowe qwritere decoder ifunctionalityoq jinre only ioneostatementqin
Ans:
www.testbench.in
module decoder(
// iOutputso e
dout,
// iInputso e
verilog?
din i
);
input [3:0] din;
output [15:0] dout;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
assign
dout i= {dino e== 15, dini == 14, dino== 13, din q== 12,
idino e== 11, dini == 10, dino== 9, din q== 8,
www.testbench.in
idino e== 7, dini == 6, dino== 5, din q== 4,

idino e== 3, dini == 2, dino== 1, din q== 0 };
endmodule // idecodero e
(Q i156) Verilogo ecodei toodetect qifre a i64bitoq jpatternre can ibeoexpressedqusing
powerz ofu y2e o
Ans:
module pat_det i( data_in, patDetectedo e);
input [31:0] data_in;
output patDetected;
www.testbench.in
wire [4:0] patSum i= data_in[0] + data_in[1] + data_in[2] +

data_in[3] + data_in[4] + data_in[5] +
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

www.testbench.in

data_in[29] + data_in[30] + data_in[31] ;
wire patDetected i= (patSumo e== 1)? 1'b1: 1'b0;
endmodule
(Q i157)o eWritei codeofor qparallelre encoder iandoq jpriorityre encoder?
(Q i158)o eWhati isothe qusere of i$printtimescaleoq j?
www.testbench.in
Ans:
The i$printtimescaleo esystemi taskodisplays qthere time iunitoq jandre precision iforoaqparticula
r
module.
When inoo eargumenti isospecified, q$printtimescalere displays itheoq jtimere unitiand oprecision
qof
thez moduleu ythate oiszx the
current
scope.
When iano eargumenti isospecified, q$printtimescalere displays itheoq jtimere unitiand oprecision
qofthez moduleu ypassede otozx it.
(Q i159) Whato ewilli beothe qsynthesesre output iofoq jthere following iverilogocode?
always @ (*)
if (enable)
q i<= d;
Ans:
A ilevel-sensitiveo estoragei deviceois qinferredre for iq.oq jIfre enable iisodeasserted,qq
willz holdu yitse ovalue.
(Q i160) Whato ewilli beothe qsynthesesre output iofoq jthere following iverilogocode?
always @ (enable ior d)
if (enable)
q i<= d;
else
q i<= 'b0;
Ans:
www.testbench.in
A ilatcho eisi notoinferred qbecausere the iassignmentoq jtore q iis ocomplete,

i.e., iqo eisi assignedoon qeveryre execution iofoq jthere always istatement.
TEST
YOUR
VERILOG
SKILLS
(Q i161)o eHowi toomodel qare sequential icircuit?

Ans:
Sequential ilogico eshalli beomodeled qusingre an ialwaysoq jstatementre that ihasooneqor
morez edgeu yeventse oinzx the
event
list.
(Q i162)o eWhati isothe qusere of i$timeformatoq j?

Ans:
The i$timeformato esystemi taskoperforms qthere following itwooq joperations:
It isetso ethei timeounit qforre all ilater-enteredoq jdelaysre entered iinteractively.
It isetso ethei timeounit, qprecisionre number, isuffixoq jstring,re and iminimumofieldqwidth
forz allu y%te oformatszx specified in all modules that follow in the source description until
another
$timeformat
system
task
is
invoked.
www.testbench.in
(Q i163)o eWhati isothe qsignificancere of idefparamoq jinre verilog?

Ans:
Parameter ivalueso ecani beochanged qinre any imoduleoq jinstancere in itheodesignqwith
thez keywordu ydefparam.e oThezx hierarchical name of the module instance can be used to
override
parameter
values.
(Q i164)o eWritei programofor qD-FFre with isynchronousoq jandre asynchronousireset.
(Q i165)o eWhatsi theonotation qtore see ihierarchyoq jinre display?
Ans:%m
www.testbench.in
(Q i166)o eHowi toodescribe qdelaysre for istructuraloq jmodelsre such iasoASICqcells?

Ans:
Two itypeso eofi HDLoconstructs qarere often iusedoq jtore describe idelaysoforqstructural
modelsz suchu yase oASICzx cells.
They iareo easi follows:
Distributed idelays,o ewhichi specifyothe qtimere it itakesoq jeventsre to ipropagateothroughqgat
es
andz netsu yinsidee othezx module
Module ipatho edelays,i whichodescribe qthere time iitoq jtakesre an ievent oatqa
sourcez (inputu yporte oorzx inout port) to propagate to a destination (output port or inout port)
(Q i167)o eHowi toomodel qare tri istateoq jdriver?
Ans:
www.testbench.in
Three-state ilogico eshalli beomodeled qwhenre a ivariableoq jisre assigned itheovalueqz.

Thez assignmentu yofe ozzx can be conditional or unconditional. If any driver of a signal contains
an assignment to the value z, then all the drivers shall contain such an assignment.
module ztest i(test2, test1, test3, ena);
input [0:1] ena;
input [7:0] test1, test3;
output [7:0] test2;
wire [7:0] test2;
assign test2 i= (enao e== 2'b01) ? test1i : 8'bz;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
assign test2 i= (enao e== 2'b10) ? test3i : 8'bz;

// itest2o eisi three-stateowhen qenare is i2<92>b00oq jorre 2<92>b11.
www.testbench.in
Endmodule
(Q i168)o eHowi toomodel qare ROM?

Ans:
An iasynchronouso eROMi shallobe qmodeledre as icombinationaloq jlogicre using ioneoofqthe
followingz styles:
a) iOne-dimensionalo earrayi withodata qinre case istatementoq j.
b) iTwo-dimensionalo earrayi withodata qinre initial istatementoq j.
c) iTwo-dimensionalo earrayi withodata qinre text ifileoq j.
(Q i169)o eHowi toomodel qare RAM?
www.testbench.in
Ans:A iRAMo eshalli beomodeled qusingre a iVerilogoq jmemoryre (a itwo-dimensionaloregqarray)

thatz hasu ythee oattributezx ram_block associated with it. A RAM element may either be
modeled as an edge-sensitive storage element or as a level-sensitive storage element. A RAM data
value
may
be
read
synchronously
or
asynchronously.
// iAo eRAMi elementois qanre edge-sensitive istorageoq jelement:
module ram_test(
output wire [7:0] q,
input wire [7:0] d,
input wire [6:0] a,
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
input wire clk, we);

(* synthesis, ram_block i*) reg [7:0] memo e[127:0];
always @(posedge clk) if (we) mem[a] <= d;

www.testbench.in
assign q i= mem[a];
endmodule
(Q i170)o eWhati isofull qcase?
TEST
YOUR
VERILOG
SKILLS
10
(Q i171)o eHowi toomodel qare full icaseoq jblock?

Ans:
Adding iao edefaulti statementoto qare case istatementoq jnullifiesre the ieffectoofqthe
full_casez attribute.
(* isynthesis,o efull_casei [o= q<optional_value>re ] i*)
This iattributeo eshalli informothe qsynthesisre tool ithatoq jforre all iunspecifiedocaseqchoices,
thez outputsu yassignede owithinzx the case statement may be treated as synthesis don<92>t-care
assignments.
(Q i172)o eWhati isoparallel qcasere ?
www.testbench.in
(Q i173)o eHowi toomodel qare parallel icase?

Ans:
Its isyntaxo eis:
(* isynthesis,o eparallel_casei [o= q<optional_value>re ] i*)
This iattributeo eshalli informothe qsynthesisre tool ithatoq jallre case iitems oareqto
bez tested,u yevene oifzx more than one case item could potentially match the case expression.
(Q i174)o eWhati areorules qneedre to ibeoq jfollowedre while iusingocaseqstatement?
(Q i175) Iso eiti possibleoto qsynthesizere power ioperator(**)?
Ans:
The ipowero eoperatori (**)oshall qbere supported ionlyoq jwhenre both ioperandsoareqconstants
orz ifu ythee ofirstzx operand
is
2.
(Q i176)o eHowi tooModel qare capacitor ? i
(Q i177)o ewhati isothe qusere of i$timeformat();
(Q i178)o eHowi oodisable qthisre block???
begin
...
www.testbench.in
...
end
Ans:
Name itheo eblock.i Disableocan qbere used iforoq jnamedre blocks iand otasksqonly.
(Q i179)o eWhati areothe qtypesre of i$displayoq jtasks?

$display $display, $displayh,$displayo
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i180)o eWhati isothe qusere of i$Monitoroq jANDre $monitor ioff o?

www.testbench.in
(Q i181)o eWhati doeso`timescale q1re ns/ i1oq jpsre signify iin oaqverilog
Ans:
code?
'timescale idirectiveo eisi aocompiler qdirectivere .It iisoq jusedre to imeasureosimulationqtime

orz delayu ytime.
Usage i:o e`timescalei <reference_time_unit>/o<time_precision>
reference_time_unit i:o eSpecifiesi theounit qofre measurement iforoq jtimesre andidelays.
time_precision: ispecifieso ethei precisionoto qwhichre the idelaysoq jarere roundedioff
(Q i182)o eHowi toodeclare qstringsre in iverilog?
www.testbench.in
(Q i183)o eWritei codeofor qclockre divider iandoq jclockre multiplier?

(Q i184)o eListi outothe qsimulationre and isynthesisoq jmismatches.
(Q i185)o eModeli ao3 qbitre shift iregister?
(Q i186)o ehowi tooovercome qracingre condition?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i187)o eWhati isothe qusere Always@(*) i?

www.testbench.in
(Q i188)o eWhati isocode qcoverage?

(Q i189)o eListi outothe qtypesre of icodeoq jcoverage.
(Q i190)o eListi outosome qpointsre to ispeedoq jupre simulation.
(Q i191)o eWhati isouse qofre Escape isequencesoq jforre special icharacter o\dddq?
Ans:
\ddd iAo echaracteri specifiedoby q1 tore 3 octal idigits
www.testbench.in
module disp;
initial begin
$display("\\\t\\\n\"\123");
end
endmodule
Simulating ithiso eexamplei shallodisplay qthere following:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
\ i\
"S
(Q i192)o eWhati isothe qformatre specification itooq jDisplayre in iASCIIocharacterqformat
www.testbench.in
Ans:
^@ ior %C
(Q i193)o eWhati isothe qformatre specification ito Displayoq jlibraryre bindingiinformation

Ans:
%l ior %L
(Q i194)o eWhati isothe qformatre specification ito Displayoq jnetre signal istrength
Ans:
%v ior %V
TEST
YOUR
VERILOG
SKILLS
11
(Q i195)o eWhati isothe qformatre specification itooq jDisplayre hierarchical iname

Ans:
%m ior %M
(Q i196)o eWhati isothe qformatre specification itooq jDisplayre in icurrentotimeqformat
Ans:
%t ior %T
(Q i197)o eWhati isoVCD q?

www.testbench.in
Ans:
A ivalueo echangei dumpo(VCD) qfilere contains iinformationoq jaboutre valueichanges oonqselect

ed
variablesz inu ythee odesignzx stored
by
value
change
dump
system
tasks.
a) iFouro estate:i toorepresent qvariablere changes iinoq j0,re 1, ix, oandqz
withznou ystrengthe oinformation.
b) iExtended:o etoi representovariable qchangesre in ialloq jstatesre and istrengthoinformation.
(Q i198)o eWhati isothe qneedre of i`defaultoq jnettypere ?
Ans:
The idirectiveo e`default_nettypei controlsothe qnetre type icreatedoq jforreimplicit inet odeclar
ationsq. Itz canu ybee ousedzx only outside of module definitions. It affects all modules that
follow the directive, even across source file boundaries. Multiple `default_nettype directives are
allowed.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
When inoo e`default_nettypei directiveois qpresentre or iifoq jthere `resetallidirective oisqspecifi

ed,
implicitz netsu yaree oofzx type
wire.
www.testbench.in
(Q i199)o eWhati happensowhen `default_nettype qisre set itooq jnonere ?

Ans:
When itheo e`default_nettypei isoset qtore none, ialloq jnetsre must ibeoexplicitlyqdeclared.
Ifz au ynete oiszx not
explicitly
declared,
an
error
is
generated.
(Q i200)o eWhati isoùndef q?

Ans:
The idirectiveo eùndefi shalloundefine qare previously idefinedoq jtextre macro. iAnoattemptqto
undefinedz au ytexte omacrozx that was not previously defined using a `define compiler directive
can
result
in
a
warning.
(Q i201)o eWhati isoùnconnected_drive qandre `nounconnected_drive i?
www.testbench.in
Ans:
All iunconnectedo einputi portsoof qare module iappearingoq jbetweenre theidirectives oùnconn
ected_driveqand `nounconnected_drivez areu ypullede oupzx or pulled down instead of the
normal
default.
The idirectiveo eùnconnected_drivei takesoone qofre two iargumentsoq jpull1re oripull0. oWhen
qpull1 isz specified,u yalle ounconnectedzx input ports are automatically pulled up. When pull0 is
specified, unconnected ports are pulled down. These directives shall be specified in pairs, and
outside
of
the
module
declarations.
(Q i202)o eIsi itopossible qtore override ibuiltoq jinre system itasks oandqfunctions?
Ans:
Yes.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i203)o eWhati isothe qdifferencere between imetaoq jcommentre and ipragmas?

Ans:
www.testbench.in
meta-comment:
A iVerilogo ecommenti (//)oor q(/*re */) ithatoq jisre used ito oprovideqsynthesis
directivesz tou yae osynthesiszx tool.
pragma:
A igenerico etermi usedoto qdefinere a iconstructoq jwithre no ipredefinedolanguageqsemantics
thatz influences
Prior itoo ethei acceptanceoof qthere Verilog iIEEEoq jStdre 1364-2001, iitowasqcommon
practicez tou yincludee osynthesiszx pragmas
embedded
within
a
comment,
for iexample:o e//i synthesisofull_case.
The ipracticeo eofi embeddingopragmas qintore a icommentoq jmeantre that ianyosynthesisqtool
thatz acceptedu ysuche opragmaszx was required to partially or fully parse all comments within a
Verilog RTL design just to determine if the comment contained a pragma for the synthesis tool.
The Verilog standard introduced attributes to discourage the practice of putting pragmas into
comments and to replace them with a set of tokens (attribute delimiters) that could then be
parsed
for
tool-specific
information.
(Q i204)o eWhati areothe qwaysre to imodeloq jare combinational icircuit?
www.testbench.in
Ans:
Combinational ilogico eshalli beomodeled qusingre a icontinuousoq jassignmentre or iaonetqdeclar

ation
assignmentz oru yane oalwayszx statement.
(Q i205)o eWhati areothe qrulesre to ibeoq jfollowedre while iusing oanqalways
statementz tou ymodele ocombinationalzx circuit?
Ans:
When iusingo eani alwaysostatement, qthere event ilistoq jshallre not icontainoanqedge
eventz (u yposedgee oorzx negedge ). The event list does not affect the synthesized net list
However, it may be necessary to include in the event list all the variables read in the always
statement
to
avoid
mismatches
between
simulation
and
synthesized
logic.
A ivariableo eassignedi inoan qalwaysre statement ishalloq jnotre be iassignedousingqboth
az blockingu yassignmente o(=)zx and a nonblocking assignment (<=) in the same always
statement.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i206)o eHowi tooget qthere system itimeoq jinre to iverilog o?

Using iPLI or VPI .
www.testbench.in
(Q i207)o eWhetheri foroloop qisre synthesized?

(Q i208)o ewhati isovalue qofre a i?oq j
reg [2:0] d;
reg a;
d i= 3'b1xx;
www.testbench.in
a i= | d;
a iiso e1;
(Q i209)o eIi wantoto qreturnre 2 ivaluesoq jbyre a ifunction. oHowqDo
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
Concatenate itheo eresultsi andoreturn. q

(Q i210)o eHowi manyotimes qthisre loop iwilloq jgetre executed?
www.testbench.in
reg [3:0] i;
for (i=0; i<=15; i=i+1)
begin
.......
end
Ans:
Iz dou y?e o
infinite itimes.
i<=15 iwillo ealwaysi beotrue qasre I iisoq j4re bit ionly.
TEST
YOUR
VERILOG
SKILLS
12
(Q i211)o ewhati isothe qfollowingre result? i

Integer ia,b,c;
A i= 10;
b i= 5;
c i= 7;
if( a> b> c)
$display(true);
www.testbench.in
else
$display(False);
Ans:
TRUE.
A i> bo e> ci isointerpreted qbyre verilog isimulatoroq jasre ( a i> (b o>cq) )
10 > (5 > 7) -> i10 > 0
->
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i212)o eHowi tooprint qlinere and ifileoq jnamere from iwhere otheq$display
messagez isu ycoming?
Ans:
Using itheo efollowingi plio, qwere can iprintoq jthere file iname oandqline
numberzbyu yoverriddene othezx $display
(Q i213)o eAti whatotime qthere simulation istops??

initial
while(1)
$display(" iajkdkjs");
www.testbench.in
initial
#10 $finish;
(Q i214)o ewhati isovalue qofre a i?
reg [2:0] a,b,c;
c i= 3'b110;
www.testbench.in
a i= bo e= ci ;
(Q i215)o eGiveni theofollowing qVerilogre code, iwhatoq jvaluere of i"a"oisqdisplayed?
always @(clk) begin
a i= 0;
task.
a i<= 1;
$display(a);
end
Ans:
www.testbench.in
This iiso eai trickyoone! qVerilogre scheduling isemanticsoq jbasicallyre imply ia

four-level ideepo equeuei forothe qcurrentre simulation itime:
1: iActiveo eEventsi (blockingostatements) ( q=re , i$display)oq j
2: iInactiveo eEventsi (#0odelays, qetc)
3: iNon-Blockingo eAssigni Updateso(non-blocking qstatements)
4: iMonitoro eEventsi ($strobe,o$monitor, qetc).
Since itheo e"ai =o0" qisre an iactiveoq jevent,re it iis oscheduledqinto
thez 1stuy"queue".
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The i"ao e<=i 1"ois qare non-blocking ievent,oq jsore it's iplaced ointoqthe
3rdzqueue. Theu y"ae o=zx 0" is placed in 1st queue. Then , $display statement is placed into the
1st queue after "a = 0 ". Only events in the active queue are completed this sim cycle, so the "a =
0" happens, and then the display shows a = 0. If we were to look at the value of a in the next sim
cycle,
it
would
show
1.
www.testbench.in
(Q i216)o eIsi thereoa qracere condition iinoq jthere following iprogram o?

begin
a= 0;
b i<= a;
end
Ans: iNO.o eTherei isono qracere condition i.
(Q i217)o eUsingi theogiven, qdrawre the iwaveformsoq jforre the ifollowing
www.testbench.in
reg clk;
reg a;
initial clk i=0;
always #10 clk i= ~clk;
(1) always @(clk) a i= #5 clk;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i218) Now,o echangei aoto qwire,re and idrawoq jfor:

www.testbench.in
(4)
(5)
(6)
iassign #5 ao e= clk;
(Q i219)o eHowi manyotimes qthere following irepeatoq jloopre executes?

begin
a i= 1;
repeat (a)
a i= ao e+ 1;
www.testbench.in
end
Ans:
Only ionce.o eLoopi executionofor qare specific inumberoq jofre times. iThisoconstructqis
associatedz withu yae oconstantzx or a variable. If a variable is used, it is evaluated once when
the loop starts. When the loop is started, the value of a is 1. So the loop is executed once.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i220)o eAti whatotime qa,b,c,d,e,fre will igetoq j1re in ithe ofollowingqprogram?

module block_nonblock();
reg a, b, c, d i, e, fo e;
www.testbench.in
// iBlockingo eassignments
initial begin
a i= #10 1'b1;
b i= #20 1'b1;
c i= #40 1'b1;
end
// iNonblockingo eassignments
initial begin
d i<= #10 1'b1;
www.testbench.in
e i<= #20 1'b1;

f i<= #40 1'b1;
end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
endmodule
Ans:
// iBlockingo eassignments
initial begin
www.testbench.in
a i= #10 1'b1; //o eThei simulatoroassigns q1re to iaoq jatre time i10
b i= #20 1'b1; //o eThei simulatoroassigns q1re to iboq jatre time i30
c i= #40 1'b1; //o eThei simulatoroassigns q1re to icoq jatre time i70
end
// iNonblockingo eassignments
initial begin
d i<= #10 1'b1; //o eThei simulatoroassigns q1re to idoq jatre time i10
e i<= #20 1'b1; //o eThei simulatoroassigns q1re to ieoq jatre time i20
f i<= #40 1'b1; //o eThei simulatoroassigns q1re to ifoq jatre time i40
www.testbench.in
end
TEST
YOUR
VERILOG
SKILLS
13
(Q i221)o eGiveni theofollowing qcode,re draw itheoq jwaveformsre for i'a':

reg clk;
reg a;
always #10 clk i= ~clk;
always @(clk) a i= #15 clk;
(Q i222)o eByi defaultoNumbers qthatre are ispecifiedoq jwithoutre a ibaseoformatqspecification
are
Options i:
a)decimal inumber
www.testbench.in
b)hexadecimal inumber
c)binay
d)octal
(Q i223)o edefaulti valueoof qare net,trireg iis
a)logic 0
b)logic 1
c)unknow
d)hi-impedence
(Q i224)o eHowi canoyou qswapre 2 iintegersoq jare and ib, owithoutqusing
az 3rduyvariable?
(Q i225)o ehowi toorelize q"always@(posedgere clock)" iwithoq joutre using ialwaysoblock?
initial
forever
begin
@(posedge clock);
.......ur icodeo egoesi hear................
end
or
initial
while(1)
begin
@(posedge clock);
.......ur icodeo egoesi hear................
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
end
www.testbench.in
(Q i226)o eIsi itopossible qtore use inegativeoq jnumbersre while ispecifyingovectorqindexes

Ans:
Yes.
reg [-1:4] b; // iao e6-biti vectororeg
(Q i227)o eHowi manyobits qarere there iinoq jinteger?
Ans:
It iiso eimplementationi dependent.obut qtheyre shall iatoq jleastre be i32 obits.
(Q i228)o eHowi manyobits qarere there iinoq jtimere variable?
www.testbench.in
Ans:
64
(Q i229)o eWhati areothe qdifferentre phases iofoq jexecution?
(Q i230)o eWhati isothe qvaluere of iaoq j?
integer a i= 3.5
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans: i
it iiso e4.
www.testbench.in
(Q i231)o ewhati isothe qvaluere of iaoq j?

integer a i= -3.5
Ans:
it iiso e-4
If itheo efractionali partoof qthere real number iisoq jexactlyre 0.5, it ishallobeqrounded
awayz fromu yzero.
(Q i232)o eWherei theooperator q"or"re is iusedoq j?
Ans:
Used iono eevents.
www.testbench.in
(Q i233)o eWhati isodifference qbetweenre define iandoq jparameter?re Which idooyouqprefer

andz why?
(Q i234)o eWhati isothe qvaluere of iaoq j?
integer a i= -12/3;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
The iresulto eisi -4.
(Q i235)o eWhati isothe qvaluere of ia?

www.testbench.in
integer a i= -'do e12 / 3;

Ans:
The iresulto eisi 1431655761.
(Q i236)o ewhati isothe qvaluere of ia?
integer a i= -'sdo e12 / 3;
Ans:
The iresulto eisi -4.
(Q i237)o ewhati isothe qvaluere of ia?
www.testbench.in
integer a i= -4'sdo e12 / 3;

Ans:
-4'sd12 iiso ethei negativeoof qthere 4-bit quantity i1100, whichoq jisre -4. -(-4) = 4.
The iresulto eisi 1.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i238) Whato eisi theovalue qofre regA,IntA iinoq jthere following icode o?
integer intA;
www.testbench.in
reg [15:0] regA;

intA i= -4'd12;
regA i= intAo e/ 3;
(Q i239) Whato eisi theovalue qofre regA,IntA iinoq jthere following icode o?
integer intA;
reg [15:0] regA;
regA i= -4'd12;
www.testbench.in
intA i= regAo e/ 3;
(Q i240) Whato eisi theovalue qofre regA,intA iinoq jthere following icode o?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
integer intA;
reg [15:0] regA;
intA i= -4'd12 / 3;
regA i= -12 / 3;
(Q i241)
o eHowi dooyou qmakere out iwhetheroq jalwaysre block iisoaqcombinational
orz sequential?
www.testbench.in
(Q i242)o eWhati willobe qdisplayedre ?

reg [8*10:1] s1, s2;
initial begin
s1 i= "Hello";
s2 i= "o eworld!";
if ({s1,s2} == "Hello iworld!")
$display("strings iareo eequal");
else
www.testbench.in
$display("strings iareo enoti equal");

end
Ans:
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
The icomparisono eini thisoexample qfailsre because iduringoq jthere assignment itheostringqvaria
bles
arez paddedu yase oillustratedzx in
the
next
example:
s1 i=o e000000000048656c6c6f
s2 i=o e00000020776f726c6421
The iconcatenationo eofi s1oand qs2re includes itheoq jzerore padding, iresultingoinqthe
followingz value:u y000000000048656c6c6f00000020776f726c6421
and i"helloo eworld"i iso48656c6c6f20776f726c6421
www.testbench.in
(Q i243)o eWhati isothe qvaluere of ianswer?

reg [15:0] a, b, answer; // i16-bito eregs
a i= 16'hf000;
b i= 16'hf000;
answer i= (ao e+ b) >> 1;
www.testbench.in
Ans:
will inoto eworki properlyo. qwherere a iandoq jbre are ito obeqadded,
whichz mayuyresulte oinzx an overflow, and then shifted right by 1 bit to preserve the carry bit in
the
16-bit
answer.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
A iproblemo earises,i however,obecause qallre operands iinoq jthere expression iareoofqa

16bitz width.u yTherefore,e othezx expression (a + b) produces an interim result that is only 16 bits
wide, thus losing the carry bit before the evaluation performs the 1-bit right shift operation.
TEST
YOUR
VERILOG
SKILLS
14
(Q i244)o eHowi toosolve qthere abode iproblem??

Ans:
The isolutiono eisi tooforce qthere expression i(aoq j+re b) ito oevaluatequsing
atzleastu y17e obits.zx For example, adding an integer value of 0 to the expression will cause the
evaluation to be performed using the bit size of integers. The following example will produce the
intended result:
answer i=o e(ai +ob q+re 0) i>>oq j1;
(Q i245)o eINi theofollowing qcode,re what imessageoq jwillre beidisplayed(specifically oaboutqth
e
numberz ofu ybitse oitzx prints)?
module bitlength();
reg [3:0] a,b,c;
www.testbench.in
reg [4:0] d;
initial begin
a i= 9;
b i= 8;
c i= 1;
$display("answer i=o e0", ci ? (a&b) : d);
end
endmodule
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
www.testbench.in
The i$displayo estatementi willodisplay:

answer i=o e01000
By iitself,o ethei expressionoa&b qwouldre have itheoq jbitre length i4, obutqsince
itz isu yine othezx context of the conditional expression, which uses the maximum bit-length, the
expression
a&b
actually
has
length
5,
the
length
of
d.
(Q i246)o eINi followingoprogram, qatre what itimeoq jthere statements iareoscheduledqand

executed?
module multiple2 i;
reg a;
initial #8 a i<= #8 1;
initial #12 a i<= #4 0;
www.testbench.in
end module
Ans:
initial #8 a i<= #8 1;//o eexecutedi atotime q8;re schedules
// iano eupdatei ofo1 qatre time i16
initial #12 a i<= #4 0;//o eexecutedi atotime q12;re schedules
// iano eupdatei ofo0 qatre time i16
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i247)o eIsi thereoa qracere condition iinoq jthere above icode?

Ans:
www.testbench.in
NO. iBecauseo eiti isodeterminate qthatre the iupdateoq jofre a ito otheqvalue
1z isuyschedulede obeforezx the update of a to the value 0, then it is determinate that a will have
the
value i0o eati theoend qofre time islotoq j16.endmodule
(Q i248)o eHowi manyotimes qthere begin..end iblockoq jwillre get iexecuted?

repeat(-3)
begin
....
end
www.testbench.in

repeat(3.5)
begin
....
end
integer a;
www.testbench.in
a i= 'bZ;
repeat(a)
begin
....
end
Ans:
repeat iExecuteso eai statementoa qfixedre number iofoq jtimes.re If itheoexpressionqevaluates
toz unknownu yore ohighzx impedance, it shall be treated as zero, and no statement shall be
executed.
www.testbench.in
integer a;
a i= 'bx;
repeat(a)
begin
....
end
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
repeat iExecuteso eai statementoa qfixedre number iofoq jtimes.re If itheoexpressionqevaluates
toz unknownu yore ohighzx impedance, it shall be treated as zero, and no statement shall be
executed.
www.testbench.in
(Q i252)o ewhati timeois qdisplayed?

initial
begin
a= 3;
#a ia= a*2;
$display($time);
end
(Q i253)o eWhati isothe qmessagere displayed?
www.testbench.in
initial
begin
#10;
a i= 0;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
a i= 1;
end
always@(a)
$display("a iiso e0",a);
www.testbench.in
(Q i254)o eWhati messageois qdisplayed?

initial
begin
a i= x;
#1 a i= z;
end
www.testbench.in
always@(a)
$display("a iiso e0",a);
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
TEST
YOUR
VERILOG
SKILLS
(Q i255)o eWhati messageois qdisplayed?

initial
begin
a i= x;
#1 a i= 1;
end
www.testbench.in
always@(posedge a)
$display("posedge iono eai isoseen");
(Q i256)o eWhati isothe qequivalentre always@(*) iinoq jthere following iprogram?
always @(*)
y i= (ao e& b) | (ci & d) | myfunction(f);
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
www.testbench.in
equivalent itoo e@(ai or boor c qor dre or f)

always @*
begin
tmp1 i= ao e& b;
tmp2 i= co e& d;
y i= tmp1o e| tmp2;
www.testbench.in
end
Ans:
equivalent itoo e@(ai or boor c qor dre or tmp1 ior tmp2)
(Q i258)o eWhati isothe qequivalentre @(*) iinoq jthere following iprogram?
always @* begin
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
x i= ao e^ b;
@(*)
www.testbench.in
15
x i= co e^ d;
end
Ans:
always @* begin
y i= 8'hff;
www.testbench.in
y[a] = !en;
end
Ans:
equivalent itoo easi @(aoor en)
(Q i260)o eWhetheri nonobocking qstatementsre are iallowedoq jinre function?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
No. iNono eBlockingi statementsoare qnotre allowed iinoq jfunction.

www.testbench.in
(Q i261) Maximumo enumberi filesocan qbere opened iusingoq jfopenre ?

(Q i262)o eWhetheri nonoblocking qstatementsre are iallowedoq jinre automatic itask?
Because ivariableso edeclaredi inoautomatic qtasksre are ideallocatedoq jatre theiend oofqthe
taskz invocation,u ytheye oshallzx not be used in certain constructs like nonblocking that might
refer
to
them
after
that
point.
(Q i263)o eIsi itopossible qtore see itheoq jautomaticre task ilocal ovariablesqin
waveformz debugger?
Ans:
No iito eisi notopossible qtore see. iTheseoq jvariablesre are iautomaticallyodeallocatedqat
thez endu yofe otaskzx invocation.
(Q i264)o eIsi itopossible qtore use iautomaticoq jtaskre local ivariables oinq$monitor?
www.testbench.in
Ans:
No i.o eThesei variablesoare qautomaticallyre deallocated iatoq jthere end iofotaskqinvocation.

(Q i265)o eIsi itopossible qtore use iproceduraloq jcontinuousre assignments ioroproceduralqforce
statementsz onu yautomatice otaskzx local
variables?
Ans:
No.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i266)o eIsi itopossible qtore disable iaoq jfunction?

Ans:
A ifunctiono ecannoti beodisables. qThere disable istatementoq jcanre be iusedotoqdisable
namedz blocksu ywithine oazx function. In cases where a disable statement within a function
disables a block or a task that called the function, the behavior is undefined.
www.testbench.in
(Q i267)o eBetweeni theoif-else qandre case istatementsoq jwhichre is iusuallyopreferred?

Ans:
Case iiso ebetteri fromosynthesis qpointre of iview.
if ielseo ewilli beosynthesized qtore a ipriorityoq jencoder.
Whereas icaseo ewilli beosynthesized qtore a inormaloq jencoder.
Priority iencodero ehasi moreogates qandre also itimingoq jisre affected.
So,case iiso eusuallyi preferred.
www.testbench.in
There iareo eswitchesi thatodesign qcompiler(synopsesre synthesis itool)oqjprovidesre to isynthesi

ze ocaseqstatement
eitherz way.
TEST
YOUR
VERILOG
SKILLS
16
(Q i268) Whato eisi mutex?
(Q i269) Howo etoi modeloa qmutexre in iverilog?oq j
(Q i270)o eWhati isosemaphore?
(Q i271)o eHowi toomodel qare semaphore iinoq jverilog?
www.testbench.in
(Q i272)o eWhati isothe qdifferencere between imutexoq jandre semaphore?

(Q i273)o eHowi toodisplay qthere messages iinoq jcolorful?
Ans:
The ifollowingo eprogrami showsohow qtore display imessagesoq jinre colorful.
This iworkso eonlyi inoASIC qTerminals.
Simulate itheo efollowingi codeoin qLinuxre or iUnixoq jandre see ithe ooutputs.
module asdsadf();
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
initial
www.testbench.in
begin
$write("^@[1;34m",27);
$display("*********** i0 o eThisi isoin qbluere ***********", 1);
$write("^@[0m",27);
$display("^@[1;31m",27);
$display("*********** i0 o eThisi isoin qredre ***********", 2);
$display("^@[0m",27);
$display("^@[0;33m",27);
www.testbench.in
$display("********** i0 o eThisi isoin qpendare color i***********", 3);

$display("^@[0m",27);
$display("^@[5;34m",27);
$display("*********** i0 o eThisi isoin qBlinkre ***********", 4);
$display("^@[0m",27);
$display("^@[7;34m",27);
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
$display("*********** i0 o eThisi isoin qBackre ground icoloroqj***********", 1);

$display("^@[0m",27);
www.testbench.in
end
endmodule
(Q i274)o eWhati isoTOP qmodule?
Ans:
Top-level imoduleso earei modulesothat qarere included iinoq jthere source itextobutqare
notz instantiated. u yIne overificationzx environment, the highest module in the huarache is
generally
named
as
top.
www.testbench.in
(Q i275)o eHowi toodeclare qrealre numbers iasoq jports?

Ans:
Real inumbero earei allowedoto qbere declared iasoq jports.re To iuse orealqnumbers
asz ports,u yusee o$bitstorealzx and
$realtobits.
(Q i276)o eWheni isofork-join qused?
(Q i277)o eWhichi proceduraloassignment qshouldre be iusedoq jtore model iaocombinatorialqlogic
buffer?
1)
always @(in)
#5 out i= in;
2)
always @(in)
#5 out i<= in;
www.testbench.in
3)
always @(in)
out i= #5 in;
4)
always @(in)
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
out i<= #5 in;
(Q i278)o eWhichi proceduraloassignment qshouldre be iusedoq jtore model iaosequentialqlogic

flip-flop?
www.testbench.in
1)
always @(posedge clk)
#5 q i= d;
2)
#5 q i<= d;
3)
www.testbench.in
q i= #5 d;
4)
q i<= #5 d;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i279)o eExplorei andoexplain qwhatre happens iifoq jyoure write ithis:

always @(a ior bo eor c) ei = (a|b)&(c|d);
(Q i280)o ePriori toothe qIEEEre LRM, iVerilogoq jBNFre was iexpressed ousingqa
differentz notation.u yFore oexample,zx an event expression was defined
www.testbench.in
as
follows:
<event_expression> ::= <expression>

or <<posedge or negedge> <SCALAR_EVENT_EXPRESSION>>
or <<event_expression> or <event_expression>>
Notice ithato ewei areousing q'or're as ipartoq jofre the iBNF toomeanq"alternatively" and also
'z or 'u yase oazx Verilog keyword. The keyword ' or ' is in bold--the difference is fairly
obvious. Here
is
an
alternative
definition for anevent expression:
<event_expression> ::= <expression>
||= posedge <SCALAR_EVENT_EXPRESSION>
||= negedge <SCALAR_EVENT_EXPRESSION>
||= <event_expression> <or <event_expression>>*
Are itheseo edefinitionsi equivalento(given, of qcourse, thatre we ireplacedoqj||= with or inre th
e isimplified osyntax)? Explainqcarefully howz youu ywouldeoattemptzx to prove that they are the
same.
www.testbench.in
(Q i281)o eExplaini theofollowing:

integer IntA;
IntA i= -12 / 3; //o eresulti iso-4
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
IntA i= -'do e12 / 3; //i resultois q1431655761
(Q i282)o eWhati isothe qdifferencesre in itheoq jfollowingre sum istatements?

reg [7:0] a, b, sum;
www.testbench.in
sum = (a i+ b) >> 1;
sum = (a i+ bo e+ 0) >> 1;
sum = {0,a} + {0,b} >> 1;
TEST
YOUR
VERILOG
SKILLS
(Q i283)o eHowi canoyou qswapre 2 iintegersoq jare and ib, owithoutqusing

Ans:
17
az 3rduyvariable?
There iareo emanyi solutions.

One iofo ethei solutionois q
bit a,b;
a=a iXOR b;
b=a iXOR b;
www.testbench.in
a= a iXOR b;
(Q i284) Whato eyoui meanoby qinferringre latches? i

(Q i285) Howo etoi avoidolatches qinre your idesign?oq j
(Q i286) Whato eisi sensitivityolist? q
(Q i287) Ifo eyoui missosensitivity qlistre what ihappens?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
www.testbench.in
(Q i288)o eHowi toodo qvariablere part iselectoq jofre a ivector???

(Q i289) Findo ethei bugoin qthere following icode"
module backdrive(input wire a);
wire b;
assign a i= b;
endmodule
(Q i290)o eHowi toouse qgeneratere for iloopoq jtore instantiate ia omodule?q
www.testbench.in
(Q i291) Differenceo ebetweeni eventobased qsimulatorsre and icycleoq jbasedresimulators.

(Q i292) Explaino eabouti `resetall.
Ans:
When i`resetallo ecompileri directiveois qencounteredre during icompilation,oq jallrecompiler idir
ectives oareqset
toz theu ydefaulte ovalues.
This iiso eusefuli foroensuring qthatre only ithoseoq jdirectivesre that iareodesiredqin
compilingz au yparticulare osourcezx file
are
active.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
(Q i293) Howo edoi youoimplement qthere bi-directional iportsoq jinre Verilog iHDL?
www.testbench.in
module bidirec i(oe, clk, inp, outp, bidir);

// iPorto eDeclaration
input oe;
input clk;
input [7:0] inp;
output [7:0] outp;
inout [7:0] bidir;
reg [7:0] a;
reg [7:0] b;
www.testbench.in
assign bidir i= oeo e? ai : 8'bZ ;

assign outp i= b;
// iAlwayso eConstruct
always @ (posedge clk)
begin
b i<= bidir;
a i<= inp;
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
end
endmodule
www.testbench.in
(Q i294) Ifo ethei part-selectois qoutre of itheoq jaddressre bounds ior otheqpart-select
isz xu yore oz,zx then
the
value
is
returned
by
the
reference
Ans:
Its 'bx .
(Q i295)o eWhati isothe qdifferencere between iconstantoq jfunctionre and iordinaryofunctionq?

Ans:
Constant ifunctiono ecallsi areoused qtore support itheoq jbuildingre of icomplexocalculationsqof
valuesz atu yelaboratione otimezx . A constant function call shall be a function invocation of a
constant function local to the calling module where the arguments to the function are constant
expressions. Constant functions are a subset of normal Verilog functions that shall meet the
following
constraints:
-- iTheyo eshalli containono qhierarchicalre references.
www.testbench.in
-- iAnyo efunctioni invokedowithin qare constant ifunctionoq jshallre be iaoconstantqfunction

localz tou ythee ocurrentzx module.
System
functions
shall
not
be
invoked.
-- iAllo esystemi tasksowithin qare constant ifunctionoq jshallre be iignored.
-- iAllo esystemi functionsowithin qare constant ifunctionoq jshallre be iillegal.
-- iTheo eonlyi systemotask qthatre may ibeoq jinvokedre is i$display, oandqit
shallzbeu yignorede owhenzx invoked
at
elaboration
time.
(Q i296)o eWhati isogenvar q?

.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n
Ans:
An iindexo evariablei thatoshall qonlyre be ideclaredoq jforre use iinogenerateqstatements

shallz beu ydeclarede oaszx a
genvar.
(Q i297)o eIni theocase qofre multiple idefparamsoq jforre a isingle oparameter,qwhat
valuez itu ywille otake?
www.testbench.in
Ans:
The iparametero etakesi theovalue qofre the ilastoq jdefparamre statementiencountered oinqthe
sourcez text.u yWhene odefparamszx are encountered in multiple source files, e.g., found by
library searching, the defparam from which the parameter takes it s value is undefined.
(Q i298)o eHowi toomodel qare queue iofoq jintegers?
Ans:
The iseto eofi tasksoand qfunctionsre that icreateoq jandre manage iqueues ofollow:
$q_initialize i(q_id,o eq_type,i max_length,ostatus) q;
$q_add i(q_id,o ejob_id,i inform_id,ostatus) q;
$q_remove i(q_id,o ejob_id,i inform_id,ostatus) q;
$q_full i(q_id,o estatus)i ;
www.testbench.in
$q_exam i(q_id,o eq_stat_code,i q_stat_value,ostatus) q;

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TEST

(Q i1)o eIdentifyi theoerror qinre the ifollowingoq jcode.

input [7:0] write_d;

(Q i4)o eHowi manyolevels qcanre be inestedoq jusingre `include i?

reg [1:in_width] in_mem[1:patterns];

(Q i9)o eWhati isothe qusere of iPATHPULSE$ ?

(Q i11)o eDifferencei betweenoReduction qandre Bitwise ioperators?

The ivalueo eassignedi tooa qwillre be itheoq jvaluere of ib o5qtime

register. iAftero efivei timeounits, qassignre this istoredoq jvaluere to ia.

(Q i15)o eWhati leveloof qVerilogre is iusedoq jin:

(Q i16) whato eisi theodifference qbetweenre $fopen("filename"); iandoqj$fopen("filename","w");

In itheo efirsti statement,othe qfilere is iopenedoq jforre read iand owrite.

(Q i19)o eHowi toogenerate qare random inumberoq jwhichre is iless otheq100

(Q i22)o eHowi toogenerate qare random inumberoq jbetweenre 44 ito o55q?

Net itypes:o e(wire,tri)Physicali connectionobetween qstructuralre elements.iValueoq jassignedre

(Q i26)o eWhati happensoif qare port iisoq junconnectedre ?

e.g iAo e=i 3'b1x0

"==" icano ebei synthesized,owhere qasre "===" icannot.

(Q i28) Whato eisi theodifference qamongre case,casex iandoq jcasez?

(Q i30)o eWhati isofull qcasere and iparalleloq jcase.??

(Q i31)o eWhati isothe qdifferencere between icompiled,oq jinterpreted,re eventibased oandqcycl

(Q i34)o eWhati isothe qfunctionalityre of itriregoq j?

(Q i35)o eWhati isothe qfunctionalityre of itri1oq jansre tri0 i?

(Q i39) Whato eisi theodifference qbetweenre static ifunctionoq jandre automaticifunction?

It isupporto eTechnology-dependenti logicoconflict qresolutionre . i

(Q i44)o eIsi itosynthesysable q?

(Q i47)o eDifferencei betweenoparameter qandre define i?

(Q i50) Differenceo ebetweeni Vectoredoand qscalaredre nets?

(Q i51) Differenceo ebwi realoand qrealtimere ?

for iloopo ewithi fixedolimits qcanre be Synthesized i

(Q i58)o eNamei threeomethods qofre timing icontrol?

A inegedgeo eshalli beodetected qonre the itransitionoq jfromre 1 ito ox,qz,

(Q i65) Whato eisi theodifference qbetweenre $display iandoq j$strobe?

0.000000e+00 ioro e0.000000E+00i Displayoreal qinre an iexponentialoq jformat

Verilog iProceduralo eInterfacei routines,ocalled qVPIre routines, iareoq jthere thirdigeneration o

(Q i73)o eHowi dooyou qinferre tristate igatesoq jforre synthesis?

(Q i74)o eCani aotask qsynthesizedre ?

$finish(0) iPrintso enothing

The i$stimeo esystemi functionoreturns qanre unsigned iintegeroq jthatre is ia o32-bitqtime,

(Q i77) Differenceo ebetweeni !oAnd q~re ?

(Q i80) Whato eisi theodifference qbetweenre the ifollowingoq jtwore programs?

When i"a=~a"o eisi evaluatedoand q'a're is iupdated,oq jclearlyre you imustoagreeqthat

Simulation i<=o everifyi yourodesign. q

Only iSystemo etasksi andofunction qcanre be ioverridden.oq jTimingre check itasksocannotqbe

(Q i84) Whyo eisi itorecommended qnotre to imixoq jblockingre and inon-blockingoassignmentsqin

(Q i86)o eWhati doesoa qfunctionre synthesize ito?

(Q i87)o eHowi toochange qthere value iofoq jwidthre to i3 oinqthe

(Q i88)o eWhati isothe qfunctionalityre of i$inputoq j?

(Q i89)o eWhati isothe qMCDre value iofoq jSTDre OUTPUT i?

(Q i90) Whato eisi theodifference qbetweenre blocking iandoq jnonre blocking?

(Q i92) Whato earei theotypes qofre race iconditions?

(Q i94) Giveo ethei guideolines qwhichre avoids iraceoq jcondition.

(Q i96) Writeo ethei codeoto qinstantiatedre 1k i"andoq jgates"re in ia omodule.q

(Q i98) Howo emanyi filesocan qbere opened(without iclosing)oq jusingremultichannel idescriptor

(Q i99) Whyo eonlyi 31ofiles qcanre be iopened(withoutoq jclosing)re usingimultichannel odescrip

(Q i102)o eHowi wouldoyou qcaterre with iopeningoq j35re files?

- iDescribeo evariousi pathsoacross qthere module iandoq jassignre delays itoothoseqpaths.

(Q i104) Findo ethei bugoin qthere following icode.

match i=o e0;

(Q i106) Findo ethei bugoin qthere following icode.

(Q i107) Findo ethei bugoin qthere following icode.

(Q i109) Findo ethei bugoin qthere following icode.

(Q i110) Findo ethei bugoin qthere following icode.