High-Step-Up Dc-Dc Converter Using Voltage

Multiplier Cell with Ripple Free Input Current

Ryuga Hosoki and Hirotaka Koizumi
Department of Electrical Engineering
Tokyo University of Science
6-3-1, Niijuku, Katsushika-ku, Tokyo, Japan
Email: j4313658@ed.tus.ac.jp, littlespring@ieee.org
In this paper, high-step-up dc-dc converter using voltage
multiplier cell with ripple free input current is proposed. The
proposed circuit applied MC to the interleave part of the
interleave boost converter with cascade TL boost converter.
The proposed circuit is assumed to be applied to a fuel cell. To
save the deterioration of a fuel cell, the duty ratio of the
interleave part is fixed at 0.5. The output voltage of the
proposed circuit is controlled by the duty ratio of TL part. To
realize a high voltage transfer function, the proposed circuit
uses the MC technique, which also reduces the switch voltage
stress. In section II, the circuit topologies of two high-step-up
converter are described. In section III, the circuit topology of
the proposed circuit is explained. In section IV, experimental
results are shown. In section V, conclusion is described.

AbstractIn this paper, a voltage multiplier cell applied to

high-step-up dc-dc converter with ripple free input current is
proposed. The voltage multiplier cell is inserted in the
conventional interleave boost converter with cascade
Three-Level (TL) boost converter, which offers high voltage
transfer function. The voltage multiplier cell and TL converter
makes the voltage stress of all the semiconductor devices lower
than the output voltage of each step. Furthermore, the input
current ripple closes to zero when the interleave converters duty
ratio is 0.5. The circuit configuration and operation of the
proposed converter are described. The circuit operation has been
confirmed by circuit experiments.
Keywords high-step-up converter; current ripple; voltage stress;

I.

INTRODUCTION

II.

Recently, environmental problems, such as global warming

by the increased carbon dioxide, are serious. In growing
interest to environmental problems, electrical energy obtained
from the fuel cell is focused on the clean energy, small
environmental impact and low emissions of carbon dioxide
[1]-[3]. In addition, emphasis about the development and
research of environmental technologies such as called
microgrid with the fuel cell [4] and fuel cell vehicle (FCV) [5]
is increasing. However, the unit cells output voltage of a fuel
cell is low. Therefore, the boost dc-dc converter is needed
when the output voltage of application is higher than the
output voltage of a fuel cell. In addition, a fuel cell causes life
span deterioration when a fuel cell is connected to the boost
converter with large input current ripple [6]. To solve these
problems, the interleaved and the three level (TL) converters
[7]-[9] were proposed.
The input current ripples of the interleaved and the TL
converters are reduced by the driving signal which has a
phase difference of for each switch. However, these boost
dc-dc converters must operate under the extremely high duty
ratios when the fuel cell is applied to the microgrid or FCV.
Then, a switched-inductor (SL) [10], a switched-capacitor
(SC) [11] and a multiplier cell (MC) [12] were proposed,
which enable the conventional boost converter to obtain
higher gain at low duty ratio. Moreover, the interleave boost
converter with cascade TL boost converter [13] was proposed.
This converter enables high-step-up and low input current
ripple.

978-1-4799-0224-8/13/$31.00 2013 IEEE

CONVENTIONAL HIGH-STEP-UP BOOST DC-DC

CONVERTERS

A. High Voltage Ratio Non-Isolated Dc-Dc Converter for

Fuel Cell Power Source Applications [13]
Fig. 1 shows the circuit topology of the high voltage ratio
non-isolated dc-dc converter for fuel cell power source
applications [13]. This converter can be divided into two parts.
The interleave part is composed of the input voltage source
Vin, the two inductors L1, L2, the two switches S1, S2, the two
diodes D1, D2 and the dc link capacitor CLK. The TL part is
composed of the dc link capacitor CLK, the inductor L3, the
two switches S3, S4, the two diodes D3, D4, the two output
capacitors C1, C2 and the load resistance R. The interleave part
of this circuit which reduces the input current ripple divides
an input current into two inductors. Moreover, TL part reduces
the voltage stress of all the switches, the diodes, and the
capacitors. The duty ratio DIT is defined as on term of the
switches S1 and S2 in one switching cycle TS. Also, the duty
ratio DTL is defined as on term of the switches S3 and S4. The
voltage transfer function of the high voltage ratio non-isolated
dc-dc converter for fuel cell power source applications is
Vo
1
.

Vin
1 DIT 1 DTL

834

(1)

Interleave Part
L1

Interleave Part
D1

TL Part
L3

L2
D2

D3
S3

C1

S4

C2

S1

Vin

CLK
S2

L1

CM1
iCM1vCM1

iL1

D
DM2 1
DM1 D L3 iL3
2

vL1
L2 iL2
R Vo

iin
Vin

D4

vL2
S1
vgs1

vds1
S2

vgs2

iCM2 vCM2
CM2
MC
vds2

CLK

vL3
S3
vgs3
VLK
S4
vgs4

C1iC1
VC1

C2 iC2 R
vds4 V

Vo

C2

CM1

L1

DM2
DM1

L2

The duty ratio D is defined as on term of the switches S1, S2 in

one switching cycle TS. The voltage transfer function of
voltage multiplier cells applied to non-isolated dc-dc
converter when m = 1 is

D1
D2

CM2

MC

S1
Vin

Co

Vo
2
.

Vin
1 D

R Vo

S2

III.

The input current ripple iin of this circuit is shown in the

following equation.
TS D IT 1 2 D IT
V
L
1 DIT in

TS
2 DIT 1Vin
L
iin 0

(5)

In addition, the input current ripple of this converter is

similar to (2), (3) and (4) under each duty ratio but the
equations of the input current ripple replace DIT with D.

Voltage multiplier cells applied to non-isolated dc-dc converter

iin

vds3

Fig. 3. Voltage multiplier cell applied to high-step-up interleave dc-dc

converter with ripple free input current.

Interleave Converter

iin

D3

D4

Fig. 1. High voltage ratio non-isolated dc-dc converter for fuel cell
power source applications [13].

Fig. 2.
[12].

TL Part

[ D IT 0.5 ]

(2)

[ D IT 0.5 ]

(3)

[ D IT 0.5 ]

(4)

PROPOSED CIRCUIT

In this section, high-step-up dc-dc converter using voltage

multiplier cell with ripple free input current is proposed. Fig.
3 shows the proposed circuit topology. The proposed circuit
combines the interleave part of high voltage ratio non-isolated
dc-dc converter [13] with MC for providing a high voltage
transfer function and to lower the voltage stress of the
switches in the interleave part. The output voltage of the
proposed circuit is controlled by the duty ratio DTL. In
addition, each inductor current ripple cancels each other when
the duty ratio of the switches S1 and S2 are fixed at 0.5 and the
input current ripple closes to zero.

B. Voltage Multiplier Cells Applied to Non-Isolated

Dc-Dc Converter [12].
Fig. 2 shows the circuit topology of voltage multiplier cells
applied to non-isolated dc-dc converter. This converter is
composed of the input voltage source Vin, the two inductors L1,
L2, the two switches S1, S2, MC (capacitors CM1, CM2, diodes
DM1, DM2), the two diodes D1, D2, the output capacitor Co and
the load resistance R. The voltage stress of the switches S1, S2
is reduced by the charged MCs capacitors CM1, CM2. When m
is the number of MC cells, the transfer function of this
converter becomes (m + 1) times.

835

The proposed circuit has the following advantages.

1)

A high voltage transfer gain under the low duty ratio;

2)

Voltage stress of all the switching devices is low;

3)

Input current ripple closes to zero.

DITTS
DTLTS

TS
DITTS

vgs1
vgs2
vgs3
vgs4
iL1

vgs1
vgs2
vgs3
vgs4
iL1

iL2

iL2

iL3

iL3

iCM1

iCM1

iCM2

iCM2

vCM1
vCM2

vCM1
vCM2
iC1

iC1
iC2

iC2

Vo

Vo

TS

L1

DTLTS

CM1
iCM1 vCM1

iL1
vL1

iin

D1
DM2
DM1
D2

iDM1

L2 iL2

iDM2

Vin

vgs1

vds1
S2

iL3

iin

vL2

S4

D1
DM2
DM1
D2

iDM1

Vin

iL3

L3

L1

S2

vds2

Fig. 4. Waveforms of the proposed converter under each state, (a) DTL <
0.5, (b) DTL 0.5.

S4

Vin

vds1

vgs1

iL3

L3

S2

CM1 CM 2 CM ,

(6)

C1 C 2 C .

(7)

iL1

vds2

iCM1

vL1

vL2

vgs1

vds1
S2

i
C1 C1
VC1

vds3

VLK

CLK

S4

i
C2 C2
VC2

vds4

Vo

Io
R

Vo

vgs4
D4

(c)

L3

iCM2 vCM2
CM2

vds2

S3

vgs3

D1
DM2
DM1
D2

iDM2

S1
Vin

CM1
vCM1

iDM1

L2 iL2
iin

D3

vL3

iCM2 vCM2
CM2

A. Circuit Configuration
L1

C2iC2
VC2

Io

D4

vgs2

The proposed circuit can be divided into two parts. The

interleave part which is composed of the input voltage source
Vin, the two inductors L1, L2, the two switches S1, S2, MC
(capacitors CM1, CM2, diodes DM1, DM2), the two diodes D1, D2
and the DC link capacitor CLK. The TL part is composed of the
DC link capacitor CLK, the inductor L3, the two switches S3, S4,
the two diodes D3, D4, the two output capacitors C1, C2 and
the load resistance R. The duty ratio DIT is defined as on term
of the switches S1 and S2 in one switching cycle TS. Also, the
duty ratio DTL is defined as on term of the switches S3 and S4.
The capacitances of CM1, CM2 and C1, C2 satisfy the following
equations,

vds4

(b)
D1
DM2
DM1
D2

iDM1

S1

i
C1 C1
VC1

VLK

CLK

iDM2

vL2

iin

Vo

vgs4

iL1
vL1

vds3

vgs3

CM1
iCM1 vCM1

L2 iL2

D3

vL3 S

vgs2

t [s]
T1 T2 T3 T4 T5 T6 t [s]
T1 T2 T3T4 T5 T6
t0 t1 t2 t3 t4 t5 t6
t2 t3 t4 t5 t6
t0 t1
State 1 2 3 4 5 6
State 1 2 3 4 5 6
(b)
(a)

i
C2 C2
VC2

Io

D4

iCM2 v
CM2
CM2

vds1

vgs1

vds4

(a)

iDM2

S1

iC1
C1
VC1

vgs4

CM1
iCM1 vCM1

vL1

vds3

VLK

CLK

vds2

iL1

L2 iL2

S3

vgs3

vgs2

L1

D3

vL3

iCM2 v
CM2
CM2

vL2
S1

L3

iL3

D3

vL3 S

iC1
C1
VC1

vds3

vgs3
CLK

VLK
S4

C2iC2
VC2

vds4

Io
R

Vo

vgs4

vgs2

(d)

D4

Fig. 5. Current flow of proposed converter under the condition DTL <
0.5, (a) States 1, 3, (b) State 2, (c) States 4, 6 (d) State 5.

1) Analysis of interleave part under the condition DIT =

0.5: The ideal voltage transfer function of the interleave part
is calculated under the condition DIT = 0.5. When on term of
the switches S1 and S2 in one switching cycle is set to DIT TS,
the following equations will be realized during the period t0 t3 and the period t3 - t6, respectively.

B. Circuit Operation

TS
2
TS
t 3 t 6 T4 T5 T6
2

Fig. 4 shows waveforms of the proposed circuit under each

state. The capacitances of the capacitors CLK, C1 and C2 are
sufficiently large. Fig. 4 (a), (b) shows the waveforms under
the condition DTL < 0.5 and DTL > 0.5. The operation of the
proposed circuit in one switching period TS can be divided
into six states as shown in Fig. 4. In each state, the terms T1 (t0
- t1) - T6 (t5 - t6) are defined as shown in Fig. 4. Fig. 5 shows
the current flow of the proposed circuit under the condition
DTL < 0.5. Fig. 6 shows the current flow of the proposed
circuit under the condition DTL > 0.5.

t 0 t 3 T1 T2 T3

(8)
(9)

In states 1, 2 and 3, the switch S1 is on for t0 - t3. As shown in

Figs. 5 and 6, TL part is fed by the inductor current iL2 and the
capacitor current iCM2. In states 1, 2 and 3, the following
equations are satisfied.
(10)
V in v L 2 v CM 1 0

836

L1

CM1
iCM1 vCM1

iL1
vL1

L2 iL2
iin

D1
DM2
DM1
D2

iDM1
iDM2
iCM2

vL2
S1

Vin

vgs1

iL3

L3

CLK

vds2

VLK
S4

vL2

DM2
DM1
D2

iDM2

Vin

vgs1

iL3

L3

vds1
S2

vds2

iCM1

vL1

iin

CLK

CM1
vCM1

vgs1

vds1

S4

vds2

CM1
iCM1 vCM1

vL1

iDM2

vL2

vgs1

vds1

L3

iL3

vds2

iC1

Vo

S3

vds3

C1
VC1

vds4

i
C2 C2
VC2

VLK
S4

Vo

L3

iL3
vL3 S3

vds3

vgs3
VLK
S4

vds4

iC1
C1
VC1
C2iC2
VC2

V in v CM 1 dt

V in dt 0

t6

t3

T1 T3 T4 T6

Vo

v CM 1 dt

2
TS

t6

v
t3

V LK
2

(18)

(19)

(20)
(21)

CM 1 dt

1 2 DTL T
4

(22)

t 2 t1 t5 t 4 T2 T5 DTL TS .

D4

(23)

The averaged voltage of the inductor L3 is zero.

1
TS

t6

t0

v L 3 dt 0

(24)

In states 1 and 3, the inductor L3 is discharged and the output

capacitors C1 and C2 are charged. The following equation is
satisfied.
(25)
V LK v L 3 V o 0
In state 2, the inductor L3 is charged, the output capacitor C1 is
discharged and the output capacitor C2 is charged. The
following equation is satisfied.
(26)
V LK v L 3 V C 2 0
In states 4 and 6, the circuit operation in these states is similar
to states 1 and 3 in TL part. The following equation is
satisfied.
(27)
V LK v L 3 Vo 0
In state 5, the inductor L3 is charged, the output capacitor C1 is
charged and the output capacitor C2 is discharged. The
following equation is satisfied.
(28)
V LK v L 3 Vo VC 2 0

(14)

2 t3
2 t6
(15)
vCM 2 dt
vCM 2 dt
TS t 0
TS t3
The averaged voltages of the inductors L1 and L2 are zero in
steady state.
VCM 2

Vin vCM 1 V LK dt 0

Io

(11)
Vin v L1 0
In states 4, 5 and 6, the switch S1 is on for t3 t6. As shown in
Figs. 5 and 6, TL part is fed by the inductor current iL1 and the
capacitor current iCM1. In states 4, 5 and 6, the following
equations are satisfied.
(12)
V in v L1 v CM 1 V LK 0
(13)
V in v L 2 0
Averaged voltages of the capacitors CM1 and CM2 in half
switching cycle VCM1 and VCM2 are given as follows.

t0

t6

t3

t1 t 0 t 3 t 2 t 4 t 3 t 6 t 5

D3

Fig. 6. Current flow of proposed converter under the condition DTL

0.5, (a) States 1, 3, (b) State 2, (c) States 4, 6 (d) State 5.

t3

t3

t0

2) Analysis of TL part under the condition DTL < 0.5:

The ideal voltage transfer function of the TL part is calculated
under the condition DTL < 0.5. When on term of the switches
S3 and S4 in one switching cycle is set to DTLTS, the following
equations are satisfied,

vgs4

VLK
4
Vin

D4

(c)

CLK

(16)

Also, by substituting (8), (9) and (14) into (18), and (19),
the following equations are obtained.

vgs4

(d)

2
TS

in dt

Io

vgs3
CLK

vgs2

VCM 1

t0

D3

vL3

iCM2 vCM2
CM2

S2

t3

TS

Io
R

v L1 dt 0

VCM 1 VCM 2

D1
DM2
DM1
D2

iDM1

L2 iL2

S1

C2iC2
VC2

t0

D4

iCM2 vCM2
CM2

S2

L1 iL1

Vin

vds4

VLK

vgs2

iin

i
C1 C1
VC1

(b)
D1
DM2
DM1
D2

iDM2

vL2
S1

vds3

vgs3

iDM1

Vin

vgs4

iL1

L2 iL2

TS

D3

vL3 S

iCM2 v
CM2
CM2

vgs2

L1

Vo

D1

iDM1

S1

t6

D4

(a)

CM1
iCM1 vCM1

vL1

iin

C2iC2
VC2

vds4

1 t6
(17)
v L 2 dt 0
TS t0
By substituting (11), (12), and (10), (13), into (16), and (17)
the following equations can be obtained.

Io

vgs4

iL1

L2 iL2

i
C1 C1
VC1

vds3

vgs3

vgs2

L1

D3

vL3 S

vCM2
CM2

vds1
S2

1
TS

837

TABLE I

By substituting (25)-(28) into (24), the following equation

is obtained.

1
2
TS
2

t4

t3

t1

V
t0

VLK

LK

Vo dt

Vo dt

t5

t4

t2

t1

VLK

VLK

THE MEASURED VALUES OF CIRCUIT ELEMENTS IN

CIRCUIT EXPERIMENT

VC 2 dt

Vo VC 2 dt 0

(29)

By substituting (22) and (23) into (29), ideal voltage

transfer function is obtained under the condition DTL < 0.5.
Vo
1

VLK
1 DTL

(30)

3) Analysis of TL part under the condition DTL 0.5:

The ideal voltage transfer function of the proposed circuit is
calculated in TL part under the condition DTL 0.5. When
on term of the switches S3 and S4 in one switching cycle is set
to DTL TS, the following equations are satisfied,
t1 t 0 t 3 t 2 t 4 t 3 t 6 t 5
(31)
2 DTL 1 T ,
T1 T3 T4 T6
S
4
(32)
t 2 t1 t 5 t 4 T 2 T5 1 DTL T S .
In states 1 and 3, the inductor L3 is charged and the output
capacitors C1 and C2 are discharged. The following equation
is satisfied.
(33)
V LK v L 3 0

Value

Inductance [H]
Inductor L1
ESR [m]
Inductance [H]
Inductor L2
ESR [m]
Inductance [H]
Inductor L3
ESR [m]
Capacitance [F]
Capacitor C1
ESR [m]
Capacitance [F]
Capacitor C2
ESR [m]
Capacitance [F]
Capacitor CM1
ESR [m]
Capacitance [F]
Capacitor CM2
ESR [m]
Capacitance [F]
Capacitor CLK
ESR [m]
Output resistance Ro []

331
18.3
328
18.3
842
28
857
20.7
860
20.6
3.25
5.00
3.24
5.04
479
31.6
200

As well as (4), the input current ripple iin of the proposed

circuit is obtained under the condition 0 DTL < 1.
(40)
iin 0
IV.

CIRCUIT EXPERIMENT

A. Experimental Condition
A proposed converter was built and tested. The driving
signal was generated with an FPGA Altera Cyclone
EP1C6T144C8N. The input voltage source Vin = 4.0 [V], the
switching frequency fS = 30 [kHz], and each duty ratio DIT =
0.5, and DTL = 0 to 0.7 were given. Table I shows the
measured values of the circuit elements. In addition,
IPP16CN10L G for the switches S1 and S2, IRF510 for the
switches S3 and S4, STPS3030CT for the diodes DM1 and DM2,
STPS40120CT for D1 - D4 were used.

In state 2, the inductor L3 and the output capacitor C1 are

discharged, and the output capacitor C2 is charged. The
following equation is satisfied.
(34)
V LK v L 3 V C 2 0
In states 4 and 6, the circuit operation is similar to states 1 and
3 in TL part. The following equation is satisfied.
(35)
V LK v L 3 0
In state 5, the inductor L3 is discharged, the output capacitor
C1 is charged and the output capacitor C2 is discharged. The
following equation is satisfied.
(36)
V LK v L 3 Vo VC 2 0
By substituting (33)-(36) into (24), the following equation
is obtained.
t2
1 t1
2 VLK dt VLK VC 2 dt
t1
TS t0
(37)
t4
t5

2 VLK dt VLK Vo VC 2 dt 0
t3
t4

By substituting (31) and (32) into (37), the ideal voltage

transfer function is obtained under the condition DTL > 0.5.
Vo
1
(38)

VLK
1 DTL
Thus, by substituting (21) into (30) and (38), the ideal
voltage transfer function is obtained under the condition 0
DTL < 1.
Vo
4
(39)

Vin
1 DTL

Element

B. Experimental Results
Fig. 7 shows the experimental waveforms of the proposed
converter under the condition DIT = 0.5, DTL = 0.6. Fig. 7(a)
shows the drain-source voltages vds1 and vds2, the input current
ripple iin, and the dc link capacitor voltage VLK. The
maximum voltage stresses of the switches S1 and S2 were
respectively 9.1 and 9.2 [V] except switching surge voltage.
The dc link capacitor voltage was 15.4 [V]. The input current
ripple was 13.6 [mA]. Fig. 7(b) shows the drain-source
voltages vds3 and vds4, the inductor current iL3, and the output
voltage Vo. The voltage stresses of the switches S3 and S4 were
respectively 18.4 and 18.6 [V]. The output voltage was 37.0
[V]. Thus, the proposed circuit made the voltage stress of all
the switching devices lower than the output voltage of each
stage and the input current ripple was close to zero. The
measured power conversion efficiency was = 88.7 [%].
Fig. 8 shows the characteristics of the voltage transfer
functions vs duty ratio DTL. The voltage transfer function of

838

the proposed circuit in the circuit experiment was close to the

theoretical value, and the proposed circuit had higher voltage
transfer function than a boost type TL converter under low
duty ratio. The experimental value is lower than the
theoretical value because of the effects of the equivalent series
resisters and the forward voltage drop of each diode.
V.

CONCLUSION

In this paper, high-step-up dc-dc converter using voltage

multiplier cell with ripple free input current has been
proposed. The proposed circuit has advantages of the
interleave converter and the TL converter. The input ripple is
close to zero by fixing the duty ratio DIT at 0.5. In addition,
the voltage stress of the switches in the interleave part is
reduced by combining high voltage ratio non-isolated dc-dc
converter [13] and the MC. As a result, high boost gain
becomes available without increasing DTL. The operation
principles and analysis in steady-state have been confirmed by
circuit experiments.

(a)

839

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(b)
Fig. 7. The experimental waveforms of the proposed converter under the
condition DIT = 0.5, DTL = 0.6 (a) Interleave part; vertical: (vds1, vds2 : 10
[V/div], VLK : 10 [V/div], iin : 0.050 [A/div](AC coupling)); horizontal: 5.0
[s/div] (b) TL part; vertical: (vds3, vds4 : 20 [V/div] , iL3 : 0.050 [A/div] (AC
coupling), Vo : 20 [V/div]) ; horizontal: 5.0 [s/div]

Theoretical value
Experimental value
Theoretical value of boost type TL converter [8]

Voltage Transfer Function Vo / Vin

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applications,IEEE Ind. Electron. Mag., vol. 3, pp. 3246, Mar. 2009.
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Duty Ratio DTL

Fig. 8.

Characteristics of the voltage transfer functions vs duty ratio DTL.