IPJ- W1700

Monza R6 Tag Chip Datasheet

Rev 3.0
th

December 9 , 2014

Overview
The Monza R6 UHF RFID tag chip is optimized for serializing items such as apparel,
electronics, cosmetics, documents and jewelry. It delivers unmatched read performance and data
integrity for effective RFID business systems and record-breaking encoding performance to
enable the lowest applied tag cost. The Monza R6 tag chip includes revolutionary technologies
such as automatic performance adjustments and encoding diagnostics that reinforce the position
of the Monza tag chip family as the RFID industry leader.

Features
Industry leading read sensitivity of up to
-22.1 dBm with a dipole antenna,
combined with excellent interference
rejection, delivers exceptional read
reliability
Superior write sensitivity of up to 18.8
dBm with a dipole antenna for
unparalleled encoding reliability
Fast memory write speed of 1.6 ms for
32 bits
Encoding throughput up to 9,500
tags/minute using the Impinj STP
source tagging platform
Up to 96-bits of EPC memory
48-bits of Serialized TID
EPCglobal and ISO 18000-63 compliant,
Gen2v2 compliant

Unmatched data integrity with Integra

Technology for encoding diagnostics
Maintains performance across different
dielectrics with AutoTune Technology
Reduced tag manufacturing variability
via patent-pending Enduro Technology
FastID mode enables 2x to 3x faster
EPC+TID inventory for authentication
and other TID-based applications
TagFocus mode suppresses previously
read tags to enable capture of more tags
Scalable serialization built-in with
Monza Self-Serialization
Impinjs field-rewritable NVM,
optimized for RFID, provides
100,000-cycle or 50-year retention
reliability

www.impinj.com
Copyright 2014, Impinj, Inc.
Impinj, Powered by Impinj, Monza,
FastID, and TagFocus are either
registered trademarks or trademarks of Impinj, Inc.
For more information, contact rfid_info@impinj.com

Monza R6 Tag Chip Datasheet

Table of Contents
1

Introduction ........................................................................................................................1
Scope ..................................................................................................................................1
Reference Documents .........................................................................................................1
Functional Description .......................................................................................................2
2.1 Memory ..............................................................................................................................2
2.2 Advanced Monza Features Support More Effective Inventory ..........................................3
2.3 Support for Optional Gen 2 Commands .............................................................................3
2.4 Data Integrity Features (Integra technology) ..................................................................3
2.4.1 Memory Self-Check .....................................................................................................3
2.4.2 TID Parity ....................................................................................................................3
2.4.3 MarginRead Command ................................................................................................4
2.4.4 Recommended MarginRead Usage Guidelines ...........................................................5
2.5 Monza R6 Tag Chip Block Diagram ..................................................................................6
2.6 Pad Descriptions .................................................................................................................6
2.7 Differential Antenna Input..................................................................................................6
2.8 Monza R6 Tag Chip Dimensions .......................................................................................7
2.9 Power Management ............................................................................................................7
2.10 AutoTune ............................................................................................................................8
2.11 Modulator/Demodulator .....................................................................................................8
2.12 Tag Controller.....................................................................................................................8
2.13 Nonvolatile Memory...........................................................................................................8
Interface Characteristics .....................................................................................................9
3.1 Making Connections ...........................................................................................................9
3.2 Impedance Parameters ......................................................................................................10
3.3 Reader-to-Tag (Forward Link) Signal Characteristics .....................................................11
3.4 Tag-to-Reader (Reverse Link) Signal Characteristics ......................................................12
Tag Memory .....................................................................................................................13
4.1 Monza R6 Tag Chip Memory Map ..................................................................................13
4.2 Memory Banks .................................................................................................................14
4.2.1 Reserved Memory ......................................................................................................14
4.2.1.1 Access Password .................................................................................................14
4.2.1.2 Kill Password ......................................................................................................14
4.2.1.3 PermaLock ..........................................................................................................14
4.2.1.4 AutoTune Disable and AutoTune Value .............................................................14
4.3 Logical vs. Physical Bit Identification .............................................................................15
4.3.1 EPC Memory (EPC data, Protocol Control Bits, and CRC16) ..................................15
4.3.2 Tag Identification (TID) Memory..............................................................................16
4.3.3 User Memory .............................................................................................................16
Absolute Maximum Ratings .............................................................................................17
5.1 Temperature ......................................................................................................................17
5.2 Electrostatic Discharge (ESD) Tolerance .........................................................................17
5.3 NVM Use Model ..............................................................................................................17
Ordering Information ........................................................................................................18
Notices ........................................................................................................................................19
1.1
1.2

ii

Copyright 2014, Impinj, Inc.

Monza R6 Tag Chip Datasheet

1 Introduction
1.1 Scope
This datasheet defines the physical and logical specifications for Gen 2-compliant Monza R6 tag silicon, a readertalks-first, radio frequency identification (RFID) component operating in the UHF frequency range.

1.2 Reference Documents

EPCTM Radio Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860
MHz 960 MHz, Version 2.0 (Gen 2 Specification). The conventions used in the Gen 2 Specification (normative
references, terms and definitions, symbols, abbreviated terms, and notation) were adopted in the drafting of this
Monza R6 Tag Chip Datasheet. Users of this datasheet should familiarize themselves with the Gen 2 Specification.
Impinj Monza R6 Wafer Specification
Impinj Monza Wafer Map Orientation
EPC Tag Data Standards Specification 1.7
EPCglobal Interoperability Test System for EPC Compliant Class-1 Generation-2 UHF RFID Devices v.1.2.4,
August 4, 2006. (Monza R6 tag chips are compliant with this Gen 2 interoperability standard.)

Copyright 2014, Impinj, Inc.

Monza R6 Tag Chip Datasheet

2 Functional Description
The Monza R6 tag chip fully supports all requirements of the Gen 2 specification as well as many optional
commands and features (see Section 2.3 below). In addition, the Monza tag chip family provides a number of
enhancements:

Superior sensitivity for high read and write reliability

Industry-leading memory write speed, delivering the highest encoding rates

TagFocus inventory mode, a Gen 2 compliant method for capturing more hard-to-read tags by
suppressing those that have already been read, by extending their S1 flag B-state

FastID inventory mode, a Gen 2 compliant, patent-pending method for EPC+TID based inventory that is
2-3 times faster than previous methods

A patent-pending Enduro technology makes inlay manufacture less sensitive to die-attach pressure,
resulting in less variance and more predictable performance in final inlay product

AutoTune technology allows Monza R6 inlays to maintain high performance independent of the tagged
items dielectric. In addition smaller form factor designs can meet bandwidth requirements with AutoTune.
Smaller antennas reduce manufacturing cost and increase the number of applications.

Integra technology, a suite of diagnostics which ensures consistently accurate data delivery that business
can depend on

2.1

Memory

Optimized for item-level tagging, Monza R6 tag chips offer EPC memory of up to 96 bits, serialized TID. Monza
R6 does not have any user programmable passwords. As per the Gen 2 specifications the passwords are
PermaReadLocked and set to zero. It follows that Monza R6 is not killable and does not utilize the Access
command. See Table 2-1 for the memory organization.
Table 2-1 Monza R6 Memory Organization
Memory Section

Description

User

None
Serial Number48 bits

TID
(not changeable)

Extended TID Header16 bits

Company/Model Number32 bits

EPC

Up to 96 bits

AutoTune Disable and Readout

Reserved

Kill Password - None

Access Password - None

Copyright 2014, Impinj, Inc.

Monza R6 Tag Chip Datasheet

2.2 Advanced Monza Features Support More Effective

Inventory
Monza tag chips support two unique, patent-pending features designed to boost inventory performance for
traditional EPC and TID-based applications:

TagFocus mode minimizes redundant reads of strong tags, allowing the reader to focus on weak tags that
are typically the last to be found. Using TagFocus, readers can suppress previously read tags by indefinitely
refreshing their S1 B state.

FastID mode makes TID-based applications such as authentication practical by boosting TID-based
inventory speeds by 2 to 3 times. Readers can inventory both the EPC and the TID without having to
perform an access command. Setting the EPC word length to zero enables TID-only serialization.

2.3

Support for Optional Gen 2 Commands

Monza R6 tag chips support the optional commands listed in Table 2-2.
Table 2-2 Supported Optional Gen 2 Specification Commands
Command

BlockWrite

Lock

Code

11000111

11000101

Length
(bits)

>57

60

Details

Accepts valid one-word commands

Accepts valid two-word commands if pointer is an even

value

Returns error code (000000002) if it receives a valid twoword command with an odd value pointer

Returns error code (000000002) if it receives a command

for more than two words

Does not respond to block write commands of zero words

Monza R6 uses an alternative version of the lock

command

There is only a single lock bit which is described in the

Gen2 specification

To permalock all of the memory a lock command must be

sent with a payload of all ones FFFFFh.

2.4 Data Integrity Features (Integra technology)

Monza R6 has several data integrity features that enhance encoding and data reliability. These features include
memory self-check, TID parity, and the MarginRead command.

2.4.1

Memory Self-Check

Monza R6 performs a memory check on its NVM at every power-up. If a bit is weakly encoded an internal flag is
set. When the tag is singulated it will respond back with a zero length EPC. A reader could then consider this tag for
exception handling.

2.4.2

TID Parity

Monza R6 is encoded with even parity over the 48 bit serial number portion of the TID. A reader should calculate
even parity with bitwise exclusive-OR as follows.
Copyright 2014, Impinj, Inc.

Monza R6 Tag Chip Datasheet

X = TID bit(30h) TID bit(31h) TID bit(5Eh) TID bit(5Fh)

If X = 0 the TID data is good

If X = 1 the TID data has an error in it

2.4.3

MarginRead Command

Table 2-3, Table 2-4, and Table 2-5 provide details about the custom Impinj MarginRead command.
Table 2-3 MarginRead Command Code
Command

MarginRead

Length

Code

Details

(bits)

67

1110000000000001

The MarginRead command allows checking for

sufficient write margin of known data

The tag must be in the OPEN/SECURED state to

respond to the command

If a tag receives a MarginRead command with an

invalid handle, it ignores that command

The tag responds with the Insufficient Power error

code if the power is too low to execute a
MarginRead

The tag responds with the Other error code if the

margin is bad for a bit in the mask or if a nonmatching bit is sent by the reader

The MarginRead command is only applicable for

programmable sections of the memory

Table 2-4 MarginRead Command Details

MarginRead
Command
#bits

Details

Mem

Bit

Bank

Pointer

EBV

00: Reserved

Starting

11100000

01: EPC

Bit

00000001

10: TID

Address

11: User

Pointer

Code
16

Length

Mask

RN

CRC-16

Variable

16

16

Length in Bits

Copyright 2014, Impinj, Inc.

Mask
Value

handle

Monza R6 Tag Chip Datasheet

Table 2-5 MarginRead Command Field Descriptions
Field

Description

Mem Bank

The memory bank to access.

Bit Pointer

An EBV that indicates the starting bit address of the mask

Length of the mask field from 1-255.

A value of zero shall result in the command being ignored

This field must match the expected values of the bits

The chip checks that each bit matches what is in the mask field with margin

The tag will ignore any MarginRead command received with an invalid handle

Length

Mask
RN

The tag response to the MarginRead Command uses the preamble specified by the TRext value in the Query
command that initiated the round. See Table 2-6 for tag response details.
Table 2-6 Tag Response to a passing MarginRead Command

2.4.4

Header

RN

CRC-16

#bits

16

16

Description

handle

Recommended MarginRead Usage Guidelines

There are several ways that the MarginRead command could be used with Monza R6. Monza R6 comes preserialized and the MarginRead command allows a programming reader to check that the pre-serialized data is well
written and does not need to be re-encoded. Another recommended use of MarginRead is secondary and
independent verification of the encoding quality. MarginRead can also be used for diagnosis when doing failure
analysis on tags.

Copyright 2014, Impinj, Inc.

Monza R6 Tag Chip Datasheet

2.5 Monza R6 Tag Chip Block Diagram

AutoTune

RF+
POWER
MANAGEMENT
MODULATOR/
DEMODULATOR

TAG
CONTROLLER

NONVOLATILE
MEMORY
(NVM)

RF-

OSCILLATOR

ANALOG FRONT END

DIGITAL CONTROL

Figure 2-1 Block Diagram

2.6 Pad Descriptions

Monza R6 tag chips have two external pads available to the user: one RF+ pad, and one RF- pads. RF+ and RFform a single differential antenna port. Table 2-7 (see also
Figure 2-1, and Figure 2-2). Note that none of these pads connects to the chip substrate.
Table 2-7 Pad Descriptions
External Signals

External
Pad

RF+

RF-

Description

Differential RF Input Pads for Antenna.

2.7 Differential Antenna Input

All interaction with the Monza R6 tag chip, including generation of its internal power, air interface, negotiation
sequences, and command execution, occurs via its differential antenna port. The differential antenna port is
connected with the RF+ pad connected to one terminal and the RF- pad connected to the other terminal.

Copyright 2014, Impinj, Inc.

Monza R6 Tag Chip Datasheet

RF+

RF-

Figure 2-2 Monza R6 tag chip die orientation

2.8 Monza R6 Tag Chip Dimensions

Chip dimensions

464.1 m x 400 m rectangular die size

166 m x 380 m pad size

112 m pad spacing at center of die

154 m pad spacing at edge of die

2.9 Power Management

The tag is activated by proximity to an active reader. When the tag enters a readers RF field, the Power
Management block converts the induced electromagnetic field to the DC voltage that powers the chip.

Copyright 2014, Impinj, Inc.

Monza R6 Tag Chip Datasheet

2.10 AutoTune
The AutoTune block adjusts Monza R6 power harvesting from the inlay antenna by adjusting the chips input
capacitance. This adjustment occurs at power up and is held for the remainder of the time that Monza R6 is
powered.

2.11 Modulator/Demodulator
The Monza R6 tag chip demodulates any of a reader's three possible modulation formats, DSB-ASK, SSB-ASK, or
PR-ASK with PIE encoding. The tag communicates to a reader via backscatter of the incident RF waveform by
switching the reflection coefficient of its antenna pair between reflective and absorptive states. Backscattered data is
encoded as either FM0 or Miller subcarrier modulation (with the reader commanding both the encoding choice and
the data rate).

2.12 Tag Controller

The Tag Controller block is a finite state machine (digital logic) that carries out command sequences and also
performs a number of overhead duties.

2.13 Nonvolatile Memory

The Monza R6 tag chip embedded memory is nonvolatile memory (NVM) cell technology, specifically optimized
for exceptionally high performance in RFID applications. All programming overhead circuitry is integrated on chip.
Monza R6 tag chip NVM provides 100,000 cycle endurance or 50-year data retention.
The NVM block is organized into two segments:

EPC Memory with up to 96 bits

Reserved Memory (which contains the AutoTune Disable bit).

The ROM-based Tag Identification (TID) memory contains the EPCglobal class ID, the manufacturer identification,
and the model number. It also contains an extended TID consisting of a 16-bit header and 48-bit serialization.

Copyright 2014, Impinj, Inc.

Monza R6 Tag Chip Datasheet

3 Interface Characteristics
This section describes the RF interface of the tag chip and the modulation characteristics of both communication
links: reader-to-tag (Forward Link) and tag-to-reader (Reverse Link).

3.1

Making Connections

Figure 3-1 shows antenna connection for Monza R6 tag chips.

Figure 3-1: Antenna Connection for Inlay Production

This connection configuration for inlay production contacts the Monza R6 tag chip RF+ pad to one antenna terminal
and the RF- pad to the opposite polarity terminal. Enduro pads allow relatively coarse antenna geometry, and thus
enable relaxed resolution requirements for antenna patterning compared to bumped products. The diagram in Figure
3-1 shows the recommended antenna trace arrangement and chip placement having antenna traces partially
overlapping the Enduro pads but not extending into the clear space between Enduro pads.

Copyright 2014, Impinj, Inc.

Monza R6 Tag Chip Datasheet

3.2

Impedance Parameters

In order to realize the full performance potential of the Monza R6 tag chip, it is imperative that the antenna present
the appropriate impedance at its terminals. A simplified lumped element tag chip model, shown in Figure 3-2, is the
conjugate of the optimum source impedance, which is not equal to the chip input impedance. This indirect, sourcepull method of deriving the port model is necessary due to the non-linear, time-varying nature of the tag RF circuits.
The model is a good mathematical fit for the chip over a broad frequency range. The lumped element values are
listed in Table 3-1, where Cmount is the parasitic capacitance due to the antenna trace overlap with the chip surface,
Cp appears at the chip terminals and is intrinsic to the chip, and Rp represents the energy conversion and energy
absorption of the RF circuits.

Figure 3-2: Tag Chip Linearized RF Model

Table 3-1 shows the values for the chip port model for the Monza R6 tag chip, which apply to all frequencies of the
primary regions of operation (North America, Europe, and Japan).
Table 3-1 Chip Port Parameters
Parameter

Typical Value

Comments

Cp

1.23 pF

Intrinsic chip capacitance when AutoTune is

mid-range, including Enduro pads.

Rp

1.2 kOhm

Calculated for linearized RF model shown in

Figure 3-2. Measured Rp = 1.56 kOhm using
network analyzer.

Cmount

0.21 pF

Typical capacitance due to adhesive and

antenna mount parasitics. Total load
capacitance presented to antenna model of
Figure 3-2 is:
Cp + Cmount

10

Chip Read Sensitivity

- 20 dBm

Chip Write Sensitivity

- 16.7 dBm

Measured at 25 C; R=>T link using DSBASK modulation with 90% modulation depth,
Tari=25 s, and a T=>R link operating at
170 kbps with Miller M=8 encoding.

Copyright 2014, Impinj, Inc.

Monza R6 Tag Chip Datasheet

3.3 Reader-to-Tag (Forward Link) Signal Characteristics

Table 3-2 Forward Link Signal Parameters
Parameter

Minimum

Typical

Maximum

Units

960

MHz

+20

dBm

Comments

RF Characteristics
Carrier Frequency

860

Maximum RF Field
Strength

Data Encoding
Modulation Depth
Ripple, Peak-to-Peak

Received by a tag with dipole antenna while

sitting on a maximum power reader antenna

phase-reversal amplitude shift keying

PIE
80

Europe: 865868 MHz

Double and single sideband amplitude shift

keying;

DSB-ASK,
SSB-ASK,
or PR-ASK

Modulation

North America: 902928 MHz

Pulse-interval encoding
100

(A-B)/A, A=envelope max., B=envelope min.

Portion of A-B

Rise Time (tr,10-90%)

0.33Tari

sec

Fall Time (tf,10-90%)

0.33Tari

sec

6.25

25

PIE Symbol Ratio

1.5:1

2:1

Duty Cycle

48

82.3

Ratio of data symbol high time to total symbol

time

Pulse Width

MAX(0.26
5Tari,2)

0.525Tari

Pulse width defined as the low modulation time

(50% amplitude)

Tari

Data 0 symbol period

Data 1 symbol duration relative to Data 0

Copyright 2014, Impinj, Inc.

11

Monza R6 Tag Chip Datasheet

3.4 Tag-to-Reader (Reverse Link) Signal Characteristics

Table 3-3 Reverse Link Signal Parameters
Parameter

Minimum

Typical

Maximum

Units

Comments

Modulation Characteristics

Modulation

ASK

Data Encoding

Baseband
FM0 or
Miller
Subcarrier

Change in Modulator
Reflection Coefficient
|| due to Modula tion

0.8

Duty Cycle

Symbol Period

45

50

FET Modulator

|| = |reflect - absorb| (per read/write

sensitivity, Table 3-21)
55

1.5625

25

Baseband FM0

3.125

200

Miller-modulated subcarrier

40

640

kHz

Miller Subcarrier
1
Frequency

Note 1: Values are nominal minimum and nominal maximum, and do not include frequency tolerance. Apply
appropriate frequency tolerance to derive absolute periods and frequencies.

12

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Monza R6 Tag Chip Datasheet

4 Tag Memory
4.1

Monza R6 Tag Chip Memory Map

Table 4-1 Physical/Logical Memory Map

Memory
Bank
Number

102

Memory
Bank Name

TID
(ROM)

Memory
Bank Bit
Address

15

13

12

11

10

TID_Serial[15:0]

40h-4Fh

TID_Serial[31:16]

30h-3Fh

TID_Serial[47:32]

20h-2Fh

Extended TID Header

00h-0Fh

Manufacturer ID
1

60h-6Fh

EPC[31:16]

50h-5Fh

EPC[47:32]

EPC

40h-4Fh

EPC[63:48]

(NVM)

30h-3Fh

EPC[79:64]

20h-2Fh

EPC[95:80]

10h-1Fh

Protocol-Control Bits (PC)

00h-0Fh

CRC-16

RESERVED
(NVM)

RFU[12:0]=000h
A

Manufacturer ID
EPC[15:0]

50h-5Fh

Model Number

70h-7Fh

E0h-EFh

002

14

50h-5Fh

10h-1Fh

012

Bit Number

ATV[2:0]

Factory Calibration B [14:0]

40h-4Fh

Factory Calibration A [15:0]

30h-3Fh

Access Password[15:0]=0000h

20h-2Fh

Access Password[31:16]=0000h

10h-1Fh

Kill Password[15:0]=0000h

00h-0Fh

Kill Password[31:16]=0000h

Copyright 2014, Impinj, Inc.

13

Monza R6 Tag Chip Datasheet

4.2 Memory Banks

Described in the following sections are the contents of the NVM and ROM memory, and the parameters for their
associated bit settings.

4.2.1

Reserved Memory

Reserved Memory contains the Access and Kill passwords which are programmed to zero. It also contains the
AutoTune disable bit, marked A in the memory map, and the AutoTune value, marked ATV[2:0] in word 0xE. The
AutoTune value represents the tuning capacitance scale, from zero to four. When the AutoTune disable bit is zero
AutoTune works as normal. When the bit is one, AutoTune is disabled and the capacitance on the front end assumes
the mid-range value.

4.2.1.1 Access Password

The Access Password is a 32-bit value stored in Reserved Memory 20h to 3F h MSB first. Monza R6 does not
implement an Access Password and acts as though it has a zero-valued Access Password that is permanently
read/write locked.

4.2.1.2 Kill Password

The Kill Password is a 32-bit value stored in Reserve Memory 00 h to 1F h, MSB first. Monza R6 does not
implement a Kill Password and acts as though it has a zero-valued Kill Password that is permanently read/write
locked.

4.2.1.3 PermaLock
To permalock all of the memory a lock command must be sent with a payload of all ones, FFFFFh.

4.2.1.4 AutoTune Disable and AutoTune Value

The AutoTune disable bit is the first bit in word 05h, marked A in the memory map, and the AutoTune value,
marked ATV[2:0] in word 0Eh. The factory programmed value of the AutoTune disable bit is zero. The AutoTune
value represents the tuning capacitance scale, from zero to four. A value of zero removes 100 fF of capacitance
across the RF input of the tag and a value of four adds 100 fF across the RF input of the chip. See Table 4-2 for the
mapping between AutoTune value and the change in input capacitance. A reader acquires the AutoTune value by
issuing a single word Read command to word 0Eh in the reserved memory bank. The AutoTune value is not
writable.
To disable AutoTune a reader issues a Write command or a single word BlockWrite command to word 05h. Only the
AutoTune disable bit will change and the rest of bits in the payload will be ignored. If the tags memory is locked
then the AutoTune disable bit will also be locked.
When the AutoTune disable bit is zero AutoTune works as normal and when the bit is one AutoTune is overridden
and the capacitance across the RF input is set to 0 fF. When AutoTune is disabled, the readout of AutoTune value
does not represent the value of capacitance across the RF input to the tag.
Table 4-2 AutoTune Value
Autotune Value

14

Change in Input Capacitance (fF)

0h

-100

1h

-40

2h

3h

+40

4h

+100
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Monza R6 Tag Chip Datasheet

4.3 Logical vs. Physical Bit Identification

For the purposes of distinguishing most significant from least significant bits, a logical representation is used in this
datasheet where MSBs correspond to large bit numbers and LSBs to small bit numbers. For example, Bit 15 is the
logical MSB of a memory row in the memory map. Bit 0 is the LSB. A multi-bit word represented by WORD[N:0]
is interpreted as MSB first when read from left to right. This convention should not be confused with the physical bit
address indicated by the rows and column addresses in the memory map; the physical bit address describes the
addressing used to access the memory.

4.3.1

EPC Memory (EPC data, Protocol Control Bits, and CRC16)

As per the Gen 2 specification, EPC memory contains a 16-bit cyclic-redundancy check word (CRC16) at memory
addresses 00h to 0Fh, the 16 protocol-control bits (PC) at memory addresses 10h to 1Fh, and an EPC value beginning
at address 20h.
The protocol control fields include a five-bit EPC length, a one-bit user-memory indicator (UMI = 0), a one-bit
extended protocol control indicator, and a nine-bit numbering system identifier (NSI). The factory-programmed
value is 3000h. In Monza R6 the EPC length may only be set to zero, two, four, or six which corresponds with the
values of 0000h , 1000h , 2000h , or 3000h . All other bits are non-programmable and set to zero. Any attempt to write
an unsupported length results in an unsupported EPC length field error code being backscattered.
The tag calculates the CRC16 upon power-up over the stored PC bits and the EPC specified by the EPC length field
in the stored PC. For more details about the PC field or the CRC16, see the Gen 2 specification.
A reader accesses EPC memory by setting MemBank = 012 in the appropriate command, and providing a memory
address using the extensible-bit-vector (EBV) format. The CRC-16, PC, and EPC are stored MSB first (i.e., the
EPCs MSB is stored in location 20h).
The EPC memory bank of Monza R6 supports a maximum EPC size of 96 bits, which is the factory-programed EPC
length. It is possible to adjust the EPC size down from 96 bits, according to the parameters laid out in the Gen 2
standard. For Monza R6 chips (IPJ -W1700), the EPC value written into the chip during factory test is listed below
in Table 4-2. The X nibbles in the pre-programmed EPC are pre-serialized values that follow the Impinj Monza
Self-Serialization formula for Monza R6.
Table 4-3 EPC at Factory-Program
Impinj Part Number
IPJ-W1700

EPC Value Pre-programmed at the Factory (hex)

E280 1160 XXXX XXXX XXXX XXXX

Copyright 2014, Impinj, Inc.

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Monza R6 Tag Chip Datasheet

4.3.2

Tag Identification (TID) Memory

The ROM-based Tag Identification memory contains Impinj-specific data. The Impinj MDID (Manufacturer
Identifier) for Monza R6 is 100000000001 (the location of the manufacturer ID is shown in the memory map tables
above, and the bit details are given in Table ). Note that a logic 1 in the most significant bit of the manufacturer ID
(as in the example bordered in solid black in the table) indicates the presence of an extended TID consisting of a 16bit header and a 48-bit serialization. The 48-bit serialization has even parity as discussed in section 2.4.2. The
Monza R6 tag chip model number is located in the area bordered by the dashed line in TID memory row 10h-1Fh as
shown in Table 3. The non-shaded bit locations in TID row 00h-0Fh store the EPCglobal Class ID (0xE2).
Table 4-4 TID Memory Details
Memory
Bank

Memory Bank
Bit Address

Bit Number

50h-5Fh

TID_SERIAL[15:0]

40h-4Fh

TID_SERIAL[31:16]

30h-3Fh

TID_SERIAL[47:32]

Description

102
TID

20h-2Fh

10h-1Fh

(ROM)

00h-0Fh

4.3.3

Monza R6 Model Number

0

User Memory

Monza R6 contains no user memory bank.

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Copyright 2014, Impinj, Inc.

Monza R6 Tag Chip Datasheet

5 Absolute Maximum Ratings

Stresses beyond those listed in this section may cause permanent damage to the tag. These are stress ratings only.
Functional operation of the device at these or any other conditions beyond those indicated in the operational sections
of this datasheet is not guaranteed or implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

5.1 Temperature
Several different temperature ranges will apply over unique operating and survival conditions. Table 5-1 lists the
ranges that will be referred to in this specification. Tag functional and performance requirements are met over the
operating range, unless otherwise specified.
Table 5-1 Temperature parameters
Parameter

Minimu
m

Extended Operating
Temperature
Storage
Temperature

Typical

Maximum

Units

Comments

40

+85

Default range for all

functional and performance
requirements

40

+85/125

At 125C data retention is 1

year.

Assembly Survival
Temperature

+150

Applied for one minute

Temperature Rate of
Change

C /
sec

During operation

5.2 Electrostatic Discharge (ESD) Tolerance

The tag is guaranteed to survive ESD as specified in Table 5-2.
Table 5-2 ESD Limits
Parameter

Minimu
m

ESD

Typica
l

Maximum

Units

Comments

2,000

HBM (Human Body Model)

5.3 NVM Use Model

Tag memory is designed to endure 100,000 write cycles or retain data for 50 years.

Copyright 2014, Impinj, Inc.

17

Monza R6 Tag Chip Datasheet

6 Ordering Information
Contact RFID_sales@impinj.com for ordering support.

Part Number

Form

Product

Processing Flow

IPJ-W1700-K00

Wafer

Monza R6 tag chip

Padded, thinned (to ~109 m), and diced

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Copyright 2014, Impinj, Inc.

Monza R6 Tag Chip Datasheet

Notices
Copyright 2014, Impinj, Inc. All rights reserved.

Impinj gives no representation or warranty, express or implied, for accuracy or reliability of

information in this document. Impinj reserves the right to change its products and services and
this information at any time without notice.
EXCEPT AS PROVIDED IN IMPINJS TERMS AND CONDITIONS OF SALE (OR AS OTHERWISE AGREED
IN A VALID WRITTEN INDIVIDUAL AGREEMENT WITH IMPINJ), IMPINJ ASSUMES NO LIABILITY
WHATSOEVER AND IMPINJ DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATED TO SALE
AND/OR USE OF IMPINJ PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO
FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT.
NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY PATENT, COPYRIGHT,
MASK WORK RIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT IS GRANTED BY THIS
DOCUMENT.
Impinj assumes no liability for applications assistance or customer product design. Customers should provide
adequate design and operating safeguards to minimize risks.
Impinj products are not designed, warranted or authorized for use in any product or application where a malfunction
may reasonably be expected to cause personal injury or death or property or environmental damage (hazardous
uses) or for use in automotive environments. Customers must indemnify Impinj against any damages arising out of
the use of Impinj products in any hazardous or automotive uses.
Impinj, Monza, AutoTune, TagFocus, FastID, Enduro and Monza Self-Serialization are trademarks of Impinj, Inc.
All other product or service names are trademarks of their respective companies.
These products may be covered by one or more U.S. patents. See www.impinj.com/patents for details.

Copyright 2014, Impinj, Inc.

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