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Lecture 16
D/A Converters
D/A examples
Serial charge redistribution DAC
Practical aspects of current-switch DACs
Segmented current-switch DACs
ADC Converters
Sampling
Sampling switch induced distortion
Sampling switch charge injection
Nominally C1=C2
Operation sequence:
Discharge C1 & C2, S3& S4
closed
For each bit in succession
beginning with LSB, b0:
S1 open- if bi=1 C1
precharge to VREF if bi=0 to
GND
S1 closed-S2 & S3 & S4
open- Charge sharing C1 &
C2
of precharge on C1
+ of charge previously
stored on C2 C2
EECS 247 Lecture 16: Data Converters
b2
Example: 12bit
DAC
6-bit MSB
DAC R string
6-bit LSB DAC
binary
weighted
charge
redistribution
Complexity lower
reset
...
...
...
.
Vout
32 C
16C
8C
4C
2C
b5
b4
b3
b2
b1
b0
6bit
resistor
ladder
6-bit
binary weighted
charge redistribution DAC
Switch
Network
2004 H.K. Page 4
Homework 6:
Compare sensitivity
of these two
segmented DACs
to component
mismatches
Vout
32 C
16C
8C
4C
2C
b5
b4
b3
b2
b1
b0
...
...
...
.
VREF
Switch
Network
EECS 247 Lecture 16: Data Converters
6bit
resistor
ladder
Practical Aspects
Current-Switched DACs
Segmented
Current-Switched DAC
4-bit MSB
Unit element
DAC + 4-bit
binary
weighted
DAC
Note: 4-bit
MSB DAC
requires extra
4-to-16 bit
decoder
Digital code
for both
DACs stored
in a register
EECS 247 Lecture 16: Data Converters
4-bit MSB
Unit element
DAC + 4-bit
binary
weighted
DAC
Note: 4-bit
MSB DAC
requires extra
4-to-16 bit
decoder
Digital code
for both
DACs stored
in a register
EECS 247 Lecture 16: Data Converters
MSB Decoder
Domino Logic
Domino logic
Example: D4,5,6,7=1
Out=1
Register
Latched NAND gate:
CTRL=1 OUT=INB
IN
Register
EECS 247 Lecture 16: Data Converters
I/2
Current
Divider
I/2
Current Divider
Id =
d Id
Id
d Id
Id
I d1 + I d 2
2
I d1 I d 2
I/2
I/2
M1
M2
I/2+dId /2
M1
I/2-dId /2
M2
Id
d W L
+ d Vth
W
VG S Vt h L
Ideal Current
Divider
Real Current
Divider
M1& M2 mismatched
During 1
I1(1) = 12 I o (1 + 1 )
I
(1)
2
I1( 2 ) = 12 I o (1 1 )
= I o (1 1 )
1
2
( 2)
2
Io/2
= I o (1 + 1 )
1
2
Io/2
I1
I2
fclk
I 2(1) + I 2( 2 )
2
I o (1 1 ) + (1 + 1 )
=
2
2
I
= o
2
I2 =
/ 2 error 1
Io
During 1
I1(1) = 12 I o (1 + 1 )
I
(1)
2
I1( 2 ) = 12 I o (1 1 )
= I o (1 1 )
1
2
I 3(1) = 12 I1(1) (1 + 2 )
( 2)
2
= I o (1 + 1 )
1
2
Io/4
I3
= I o (1 + 1 )(1 + 2 )
I4
I2
fclk
I 3( 2 ) = 12 I1( 2 ) (1 2 )
= 14 I o (1 1 )(1 2 )
1
4
Io/2
Io/4
I (1) + I 3( 2 )
I3 = 3
2
I o (1 + 1 )(1 + 2 ) + (1 1 )(1 2 )
=
2
4
I
= o (1 + 1 2 )
4
/ 2 error 2
I1
fclk
/ 2 error 1
Io
Summary
D/A Converter
D/A architecture
Unit element complexity proportional to 2B- excellent DNL
Binary weighted- complexity proportional to B- poor DNL
Segmented- unit element MSB + binary weighted LSB complexity
proportional (2B1-1) + B2 DNL compromise between the two
Static performance
Dynamic performance
Component matching
Glitches
Symmetrical switching rather than sequential switching
Current source self calibration
Dynamic element matching
Re-Cap
Analog Input
Analog
Preprocessing
How can we
build circuits
that "sample"
A/D
Conversion
DSP
Anti-Aliasing
Filter
Sampling
+Quantization
000
...001...
110
D/A
Conversion
"Bits to
Staircase"
Analog
Post processing
Reconstruction
Filter
Analog Output
Ideal Sampling
1
In an ideal world,
zero resistance
sampling switches
would close for the
briefest instant to
sample a continuous
voltage vIN onto the
capacitor C
Not realizable!
vIN
vOUT
S1
1
T=1/fS
vIN
vOUT
S1
1
T=1/fS
Continuous
Time
T/H signal
(SD Signal)
Clock
DT Signal
Practical Sampling
1
vIN
vOUT
M1
kT/C noise
Finite Rsw limited bandwidth
Rsw = f(Vin) distortion
Switch charge injection
Clock jitter
kT/C Noise
k BT 2
C
12
2B 1
C 12k BT
VFS
8
12
14
16
20
0.003 pF
0.8 pF
13 pF
206 pF
52,800 pF
Acquisition Bandwidth
The resistance R of
switch S1 turns the
sampling network into a
lowpass filter with
risetime = RC =
Assuming Vin is
constant during the
sampling period and C
is initially discharged
vIN
vOUT
R S1
C
vout (t ) = vin (1 e t / )
Switch On-Resistance
1
Vin Vout t =
<<
2 fs
1
Vin e
2 f s
<<
Vin = VFS
Worst Case:
<<
R <<
vIN
vOUT
R S1
C
1
T
2 ln 2 B 1
1
1
2 f sC ln 2 B 1
Example:
B = 14,
1
T=1/fS
C = 13pF, fs = 100MHz
Switch On-Resistance
I D ( triode ) = Cox
gON = Cox
gON
dI D ( triode )
dVDS
VDS 0
W
W
(VGS Vth ) = Cox (VDD Vth Vin )
L
L
W
(VDD Vth )
L
Vin
= go 1
VDD Vth
for
gON
W
VDS
VGS VTH
VDS ,
L
2
go = Cox
Sampling Distortion
vout =
T
Vin
2 VDD Vt h
vi n 1 e
Sampling Distortion
Sampling Distortion
SFDR is very sensitive to
sampling distortion
Decreasing by a factor
of 2 improves HD3 by
25dB!
Solutions:
Overdesign Larger
switches
increased switch
charge injection
Complementary switch
Maximize VDD/VFS
decreased dynamic
range
Constant VGS ? f(Vin)
10bit ADC T/ = 20
VDD Vth = 2V
VFS = 1V
Complementary Switch
1
go
1B
gon
gop
1
1B
Complementary Switch
Issues
Complementary Switch
Effect of Supply Voltage Scaling
go
gon
gop
1B
1
1B
As supply voltage scales down input voltage range for constant go shrinks
Complementary switch not effective when VDD becomes comparable to Vth
EECS 247 Lecture 16: Data Converters
Transient Analysis
to 1.5us
VDD
M1
10 / 0.35
M2
M3
10 / 0.35
10 / 0.35
10 / 0.35
M8
M6
10 / 0.35
M4
10 / 0.35
C1
Supply
1pF
VDD = 3V
VSS = 0V
C2
C3
M5
1pF
1pF
10 / 0.35
M12
P
M11
M9
M11
10 / 0.35
VP1
10 / 0.35
10 / 0.35
VS1
1.5V
1MHz
Chold
1pF
100ns
Supply
VDD = 3V
VSS = 0V
VDD
M1
M2
10 / 0.35
10 / 0.35
C1
C2
1pF
1pF
P_Boost
P_N
VP1
100ns
P is LOW
VDD
M3
~ 2 VDD
(boosted clock)
10 / 0.35
OFF
VDD
VDD
M4
C3
1pF
Sampling switch
M11 is OFF
10 / 0.35
Device
OFF
VDD
M12
M11
OFF
10 / 0.35
OFF
VS1
1.5V
1MHz
Chold
C3 charged to VDD
1pF
Input voltage
source
P is HIGH
10 / 0.35
M8
C3 previously
charged to VDD
VDD
C3
1pF
M11
M9
10 / 0.35
10 / 0.35
VS1
1.5V
1MHz
Chold
1pF
Complete Circuit
Clock Multiplier
for M3
Practical Sampling
1
vIN
vOUT
M1
VH
VIN -Vth
VIN
VIN
VL
Cs
VO
VO
M1
VIN
toff
Sampling
Switch Charge Injection
Cross section view
LD
Cov
Cov
VH
VIN -Vth
VIN
VL
VO
VIN
t
V
t- toff
t
Since clock fall time >> device speed
During the period (t- to toff) current in channel discharges channel charge
into source
Only source of error Charge transfer from Cov into Cs
EECS 247 Lecture 16: Data Converters
VG
VH
Cov
VIN -Vth
VIN
D
Cs
VL
VO
V =
Cov
Co v + Cs
(Vi +Vt h VL )
Co v
(Vi + Vth VL )
Cs
Vo = Vi (1 + ) + Vos
where =
VIN
Co v
Cs
; Vo s =
Co v
Cs
t- toff
(Vth VL )
12/0.35
VIN
M1
VG
VO
VH
Cs=1pF
VIN
VIN +Vth
VL
VO
Co v = 0.3 fF / Cox = 5 f F / 2 Vth = 0.5V
=
Co v
Vos =
Co v
Cs
Cs
1 2 x0.3 fF /
1pF
VIN
= .36% 7 bit
(Vth VL ) = 1.8mV
t- toff
VG
M1
VIN
VH
VIN +Vth
VO
VIN
Cs=1pF
VL
VO
VIN
toff
Co v
Co v + Cs
Cov
Cov + Cs
(VH VL )
1
2
Qc h
(VH VL )
2
Cs
Cs
VIN
VL
VO
1 WCox L
where =
2
Cs
Co v
VIN -Vth
Cs
Vo = Vi (1 + ) + Vos
Vos =
VH
VIN
1 W Cox L (VH Vt h )
(VH VL )
2
Cs
toff
Assumption channel charge divided between S & D 50% & 50%
Source of error channel charge transfer + charge transfer from Cov into Cs
VG
12/0.35
VH
VIN
VIN -Vth
VO
M1
VIN
Cs=1pF
VL
VO
VIN
Cov = 0.3 f F / Cox = 5 f F / 2 Vth = 0 . 5V VD D = 3V
= 1/ 2
WLCox
Cs
12 x0.35x5 f F /
1pF
toff
1 WC L (V V )
Vos =
(VH VL ) ox H th = 9mV 26.3mV = 45.3mV
Cs
2
Cs
Co v
VOS
45mV
2.1%
1.8mV
.36%
Clock fall time
Both errors are a function of clock fall time, input voltage level, source impedance
& sampling capacitance
Cs
Cox
1 Qc h
(VG S Vth )
2 Cs
FOM = Vo
FOM
Cs
Co x
W
L
1 WCox L ( (VH Vi Vt h ) )
(VGS Vt h ) 2
Cs
L2
Issues:
DC offset
Input dependant error voltage distortion
Solutions:
Complementary switch?
Addition of dummy switches?
Bottom-plate sampling?