###UVM##

Top----------------------------------------|
|
|
Test--------------------------------|
|Env------------------------------ |
|
| |
Scoreboard
| |
|
| |
||
|
|
| |Agent--------------------| |
|
| |
|
||
sequencer |
|
| |
| Mon
||
|
|
|
| |
|
||
||
|DUT<================> Driver
|
| |
|
| |
|
|
| |
|
| |
---------------------| |
|
| -------------------------------|
|
|
|
|
----------------------------------------------------------------------------------

|
|
|
|

|
| | |
|
|
|
| |

|
|
|
|

UVM class hierarchy

uvm_void
|
uvm_object
|
------------------------------------------------|
|
|
|
uvm_transaction
uvm_phase uvm_config uvm_report_object
|
|
uvm_sequence_item
uvm_component
|
|
uvm_sequence
|
--------------------------------------------------------------------------------------|
|
|
|
|
|
|
uvm_driver
uvm_monitor
uvm_sequenc
er uvm_agent uvm_scoreboard
uvm_env
uvm_test
Phases :
build - > connect -> run
-> report
`uvm_macros:
generic class:
class generic extends uvm_component;
`uvm_component_utils(generic)

function new(string name, uvm_component parent)

super.new(name,parent);
endfunction:new
//Build
function void build_phase(uvm_phase phase)
super.build_phase(phase);
endfunction: build_phase
//Identical for connect and report
task void run_phase(uvm_phase phase)
super.run_phase(phase);
endtask: run_phase
endclass: generic
//////////////
Interface :
//////////////
holds signals of DUT
sample_interface.sv:
interface sample_interface;
logic inputs;
bit output;
endinterface: sample_interface

//////////////
Top :
//////////////
creates instances of DUT , testbench , interfaces.
connects them
registers interfaces
provides signals to DUT

top.sv :
`include "DUT.v"
`include "sample_interface.sv"
module top;
import uvm_pkg::*;
sample_interface vif(); //create instance
DUT dut(vif.inputs,vif.output); // Connect
initial begin
`uvm_resource_db#(virtual sample_interface)::set(.scope(ifs),.name(sample_in
terface)) //Register
run_test();

end
initial begin
//clk = 1;
end
endmodule:top
////////////////////////////////
Transactions:
///////////////////////////////
specifies inputs to DUT
multiple transactions } sequence -> sequencer -> driver
transaction class:
class sample_transaction extends uvm_sequence_item;
rand inputs;
bit output;
function new(string name, uvm_component parent)
super.new(name,parent);
endfunction:new
`uvm_object_utils_begin(sample_transaction)
`uvm_field_int(inputs,UVM_ALL_ON)
`uvm_field_int(output,UVM_ALL_ON)
`uvm_object_utils_end(sample_transaction)
endclass: sample_transaction
/////////////////////////////////////////////
Sequence:
////////////////////////////////////////////
class sample_sequence extends uvm_sequence#(sample_transaction);
`uvm_object_utils(sample_sequence);
function new(string name, uvm_component parent)
super.new(name,parent);
endfunction:new
task body()
repeat ( 10 ) begin
sample_transaction s_trans;
s_trans = sample_transaction::type_id::create(..);
start_item(s_trans);
// blocking function .. waits till
s_trans is created
assert(s_trans.randomize())
finish_item(s_trans);
// blocking function .. waits till
s_trans is finished
end

endtask: body
endclass: sample_sequence

///////////////////////////////////////////////////////
Sequencer
///////////////////////////////////////////////////////
sends sequ to driver
sequencer:
typedef uvm_sequencer#(sample_transaction) sample_sequencer;
////////////////////////////////////////////////////////
Driver:
///////////////////////////////////////////////////////
gets sequence from sequencer ; drives inputs to DUT .
sequencer| export

->

driver| port

port -> 1:1 with export

*analysis_port -> 1:many exports
//TLM - Transaction Level Modelling
top class--------------------------------------------|
Producer ( calls fn ) -> Consumer ( implements fn) |
-----------------------------------------------------class topclass extends ..
function connect_phase( uvm_phase)
producer.port.connect(consumer.export);
endfunction
endclass : topclass
class consumer
uvm_blocking_put_imp #( sample_transaction, consumer) imp1;
task test( sample_transaction t)
//
endtask: test
endclass : consumer
class producer
uvm_blocking_put_port #( sample_transaction) imp1;
task run_phase()
sample_transaction t;

imp1.test(t);
endtask: run_phase
endclass : producer

driver :
class sample_driver extends uvm_driver
`uvm_component_utils(sample_driver)
sample_interface vif;
sample_transaction s_trans;
function new(string name, uvm_component parent)
super.new(name,parent);
endfunction:new
//Build
function void build_phase(uvm_phase phase)
super.build_phase(phase);
`uvm_resource_db#(virtual sample_interface)::read_by_name(.scop
e(ifs),.name(sample_interface)) //Register
endfunction: build_phase

task void run_phase(uvm_phase phase)

seq_item_port.get_next_item(s_trans);
vif.inputs = s_trans.inputs;
seq_item_port.item_done(s_trans);
endtask: run_phase
endclass : sample_driver
/////////////////////////////////////////////////
Monitor :
/////////////////////////////////////////////////
class sample_monitor extends uvm_monitor
`uvm_component_utils(sample_monitor)
`uvm_analysis_port #(sample_transaction) an_port;
sample_interface vif;

function new(string name, uvm_component parent)

super.new(name,parent);
endfunction:new
//Build
function void build_phase(uvm_phase phase)
super.build_phase(phase);
`uvm_resource_db#(virtual sample_interface)::read_by_name(.scop

e(ifs),.name(sample_interface)) //Register
an_port = new(.name("an_port"),.parent(this))
endfunction: build_phase

endclass : sample_monitor
/////////////////////////////////////////////////
Agent :
/////////////////////////////////////////////////
class sample_agent extends uvm_agent
`uvm_component_utils(sample_agent)
`uvm_analysis_port #(sample_transaction) an_port1;
sample_driver sa_drv;
sample_monitor sa_mon;
sample_sequencer sa_seqr;
function new(string name, uvm_component parent)
super.new(name,parent);
endfunction:new
//Build
function void build_phase(uvm_phase phase)
super.build_phase(phase);
sa_drv = sample_driver::type_id::create(..)
sa_mon = sample_monitor::type_id::create(..)
sa_seqr = sample_sequencer::type_id::create(..)
an_port = new(.name("an_port"),.parent(this))
endfunction: build_phase

function connect_phase(uvm_phase phase)

super.connect_phase(phase);
sa_drv.seq_item_port.connect(sa_seqr.seq_item_export)
sa_mon.an_port.connect(an_port1)
endfunction : connect_phase
endclass : sample_agent
///////////////////////////////////////////////////////
Scoreboard
///////////////////////////////////////////////////////

use FIFO

class sample_scoreboard extends uvm_scoreboard

`uvm_component_utils(sample_scoreboard)
`uvm_analysis_port #(sample_transaction) sb_port;
`uvm_tlm_fifo#(sample_transaction) fifo_port;
sample_transaction sa_tx;
function new(string name, uvm_component parent)
super.new(name,parent);
endfunction:new
//Build
function void build_phase(uvm_phase phase)
super.build_phase(phase);
sb_port = new(.name("an_port"),.parent(this));
fifo_port = new(.name("fifo_port",.parent(this)));
endfunction: build_phase

function connect_phase(uvm_phase phase)

super.connect_phase(phase);
sb_port.connect(fifo_port)
endfunction : connect_phase
task run_phase ()
fifo_port.get(sa_tx);
compare();
endtask: run_phase
endclass : sample_scoreboard
///////////////////////////////
ENV
//////////////////////////////
class sample_env extends uvm_env
`uvm_component_utils(sample_env)
sample_agent sa_ag;
sample_scoreboard sa_sb;
function new(string name, uvm_component parent)
super.new(name,parent);
endfunction:new
//Build
function void build_phase(uvm_phase phase)

super.build_phase(phase);
sa_ag = sample_agent::type_id::create(..)
sa_sb = sample_scoreboard::type_id::create(..)
endfunction: build_phase

function connect_phase(uvm_phase phase)

super.connect_phase(phase);
sa_ag.an_port.connect(sa_sb.sb_port);
endfunction : connect_phase

endclass : sample_env

///////////////////////////////////////////////
TEST
//////////////////////////////////////////////
class sample_test extends uvm_test
`uvm_component_utils(sample_test)
sample_env sa_env;
function new(string name, uvm_component parent)
super.new(name,parent);
endfunction:new
//Build
function void build_phase(uvm_phase phase)
super.build_phase(phase);
sa_env = sample_env::type_id::create(..)
endfunction: build_phase
task run_phase()
sample_sequence seq;
phase.raise_objection(.obj(this))
seq = sample_sequence::type_id::create(..)
assert(seq.randomize())
seq.start(sa_env.sa_ag.sa_seqr);
phase.drop_objection(.obj(this))
endtask: run_phase

endclass : sample_test