INVERTERS AND LOGIC

GATES

NMOS Inverter
5V
R
ID = 5/R

VIN
5V

+
VDS
_

5V

When VIN is logic 1,

VOUT is logic 0.

Constant nonzero
VOUT current flows through
transistor.
0V

ID = 0

VIN

Power is used even

though no new
0V
computation is being
performed.

VOUT
5V

+
VDS
_

When VIN changes to logic 0, transistor gets cutoff. ID goes to 0.

Resistor voltage goes to zero. VOUT pulled up to 5 V.

PMOS Inverter
5V

Constant nonzero

VIN

current flows through

VDS
VOUT transistor.
+

0V
ID = -5/R

5V

5V

When VIN is logic 0,

VOUT is logic 1.

Power is used even

though no new
computation is being
performed.

VIN

VDS
VOUT
+

5V
ID = 0

0V

When VIN changes to logic 1, transistor gets cutoff. ID goes to 0.

Resistor voltage goes to zero. VOUT pulled down to 0 V.

Analysis of CMOS
Inverter
We can follow the same
VDD (Logic 1)

VIN

VOUT

NMOS is pull-down device

PMOS is pull-up device
Each shuts off when not pulling

procedure to solve for currents

and voltages in the CMOS
inverter as we did for the single
NMOS and PMOS circuits.
Remember, now we have two

transistors so we write two I-V

relationships and have twice
the number of variables.
We can roughly analyze the

CMOS inverter graphically.

4

NMOS Inverter

ID

VGS = 3 V

X
Linear ID vs VDS given
by surrounding circuit
X

VGS = 1 V
VDS5

Linear KVL and KCL Equations

+

(p)
S
VG

VDD (Logic 1)
S

VGS(p) = VIN VDD

VOUT

D
D

VIN
+V

GS(n
)

VGS(n) = VIN

+
VDS(n)
_

Use these equations

to write both I-V equations in
terms of VDS(n) and ID(n)

VGS(p) = VDS(n) - VDD

ID(p) = -ID(n)
VDS(n) = VOUT
VDS(p) = VOUT VDD
VDS(p) = VDS(n) - VDD
6

ID(n)

CMOS Analysis
As VIN goes up, VGS(n) gets bigger
and VGS(p) gets less negative.

NMOS I-V curve

PMOS I-V curve
(written in terms of
NMOS variables)

VIN = VGS(n)
= 0.9 V

VDS(n)
VDD

ID(n)

CMOS Analysis

As VIN goes up, VGS(n) gets bigger

and VGS(p) gets less negative.

NMOS I-V curve

PMOS I-V curve
(written in terms of
NMOS variables)

VIN = VGS(n)
= 1.5 V

VDS(n)
VDD

ID(n)

CMOS Analysis
As VIN goes up, VGS(n) gets bigger
and VGS(p) gets less negative.

NMOS I-V curve

PMOS I-V curve
(written in terms of
NMOS variables)

VIN = VGS(n)
= 2.0 V

VDS(n)
VDD

ID(n)

CMOS Analysis

As VIN goes up, VGS(n) gets bigger

and VGS(p) gets less negative.

NMOS I-V curve

PMOS I-V curve
(written in terms of
NMOS variables)

VIN = VGS(n)
= 2.5 V

VDS(n)
VDD

10

ID(n)

CMOS Analysis
As VIN goes up, VGS(n) gets bigger
and VGS(p) gets less negative.

NMOS I-V curve

PMOS I-V curve
(written in terms of
NMOS variables)

VIN = VGS(n)
= 3.0 V

VDS(n)
VDD

11

ID(n)

CMOS Analysis
As VIN goes up, VGS(n) gets bigger
and VGS(p) gets less negative.

NMOS I-V curve

PMOS I-V curve
(written in terms of
NMOS variables)

VIN = VGS(n)
= 3.5 V

VDS(n)
VDD

12

ID(n)

CMOS Analysis
NMOS I-V curve
PMOS I-V curve
(written in terms of
NMOS variables)

As VIN goes up, VGS(n) gets

bigger
and VGS(p) gets less negative.

VIN = VGS(n)
= 4.1 V

VDS(n)
VDD

13

CMOS Inverter VOUT vs. VIN

VOUT

both
sat.

VDD

curve very
steep here;
only in C for
small interval
of VIN

NMOS:
cutoff
PMOS:
triode
NMOS:
saturation

NMOS:
triode

NMOS:
triode

PMOS:
saturation

PMOS:
cutoff

PMOS:
triode

VDD

14

VIN

CMOS Inverter ID

ID

VIN
VDD

15

Important Points
No ID current flow in Regions A and E if nothing attached to

output; current flows only during logic transition

If another inverter (or other CMOS logic) attached to output,
transistor gate terminals of attached stage do not permit
current: current still flows only during logic transition
VDD

VDD

S
D
VIN

S
VOUT1

VOUT2

16

CMOS Inverter Transfer characteristics

Drain current of NMOS

In

n
2

V in

V tn

Drain current of PMOS

Ip

Vin VDD Vtp

2

2
17

CMOS Inverter Transfer characteristics

At logic threshold, In = Ip
p
n
2
V in V tn
V in V DD V tp 2
2
2
p
n
V in V tn
V in V DD V tp
2
2
n
V in V tn V in V DD V tp
p

V in 1

n
V tn V DD V tp
p
18

CMOS Inverter Transfer characteristics

V DD
V in

V tp V tn
1

n
p

n
p

If n = p and Vtp = Vtn

V DD
Vin
2

19

CMOS Inverter
pW p
L p

nW n

Ln

Mobilities are unequal : n = 2.5 p

Z = L/W

Zpu/Zpd = 2.5:1 for a symmetrical CMOS

inverter
20

Pseudo NMOS Inverter

21

Pseudo NMOS Inverter

22

Enhanced load NMOS Inverter

23

Enhanced load NMOS Inverter

Dissipation is high since current flows when Vin = 1
Vout can never reach Vdd (effect of channel)
Vgg can be derived from a switching source (i.e. one
phase of a clock, so that dissipation can be
significantly reduced
If Vgg is higher than Vdd, and extra supply rail is
required
24

Depletion loadNMOS Inverter

25

Depletion loadNMOS Inverter

Pull-Up is always on Vgs = 0; depletion
Pull-Down turns on when Vin > Vt
With no current drawn from outputs, Ids
for both transistors is equal

26

Transfer Characteristics
Vin

Decreasing
Zpu/Zpd

Increasing
Zpu/Zpd

VDD

Vinv
VDD

Vo

Point where Vo = Vin is called Vinv

Transfer Characteristics and Vinv can be shifted by altering ratio
of pull-up to Pull down impedances
27

NMOS Depletion Mode Inverter

Dissipation is high since rail to rail current flows when
Vin = Logical 1
Switching of Output from 1 to 0 begins when Vin
exceeds Vt of pull down device
When switching the output from 1 to 0, the pull up
device is non-saturated initially and this presents a
lower resistance through which to charge capacitors
(Vds < Vgs Vt)

28

Summary of NMOS Inverter

Resistive load inverter takes up too much area for and IC
design.
The saturated load configuration is the simplest design,
but VH never reaches VDD, and it has a slow switching
speed.
The linear load inverter fixes the speed and logic level
issues, but it requires an additional power supply for the
load gate.
.
29

Summary of NMOS Inverter

The depletion-mode NMOS load requires the most processing
steps, but needs small area to achieve the high speed,
VH = VDD, and best combination of noise margins.
The Pseudo NMOS inverter offers the best speed with the
lowest area

30

Cascading NMOS Inverters

Dissipation is high since current flows when Vin = 1
Vout can never reach Vdd (effect of channel)
Vgg can be derived from a switching source (i.e. one

phase
of a clock, so that dissipation can be significantly
reduced
If Vgg is higher than Vdd, and extra supply rail is

required

31

Cascading NMOS Inverters

Determine pull up to pull-down ratio for
driven inverter

Assume equal margins around inverter; Vinv =

0.5 Vdd
Depletion mode transistor has gate connected
to source, i.e. Vgs = 0
Ids = K (Wpu/Lpu) (-Vtd)2/2
32

Cascading NMOS Inverters

Assume both transistors in saturation, therefore :Ids = K
(W/L) (Vgs Vt)2/2

Enhancement mode device Vgs = Vinv, therefore

Ids = K (Wpd/Lpd) (Vinv Vt)2/2

33

Cascading NMOS Inverters

Assume currents are equal through both
channels (no current drawn by load)
(Wpd/Lpd) (Vinv Vt)2 = (Wpu/Lpu) (-Vtd)2
Convention Z = L/W
Vinv = Vt Vtd / (Zpu/Zpd)1/2

34

Cascading NMOS Inverters

Substitute in typical values Vt = 0.2 Vdd ; Vtd = -0.6 Vdd ;
Vinv = 0.5 Vdd
This gives Zpu / Zpd = 4:1 for an nmos inverter directly
driven by another inverter

35

Pull-Up to Pull-Down Ratio for an nMOS inverter

driven
through 1 or more pass transistors
Inverter 1
A
Vin1

Vdd
B

Inverter 2

Vdd
C

Vout2

It is often the case that two inverters are connected

via a series of switches (Pass Transistors)

36

Super Buffer
off-chip capacitances are typically an order of magnitude larger
than on-chip capacitances.

- VLSI gates that are used in logic circuitry are sized to

drive other gates of comparable size.
- if these smaller gates are connected to a much larger
load capacitance, they are not sized
optimally.
- a gate can typically not drive a capacitance that has a much
larger capacitance than its own junction capacitance.
37

- a super buffer is a circuit that consists of a series of gates,

- we define the relative size of each subsequence

gate using the optimal sizing factor ()
- we start with a typical logic gate and then design
a subsequent stage that is larger by a factor of
- we continue to add stages until the final
capacitance that is to be driven (Cload) is a factor
of larger than the last state of the super buffer.
- we define the number of stages in the super
buffer as N
38

Super Buffer

- we

define Cg as the gate capacitance of the next state.

- we define Cd as the output drain capacitance of current stage.

- we can derive an expression to find the total delay as a function of (N, ).
- this expression gives us a relationship between N and .
- we can differentiate this expression to find the optimal scaling factor:

Cd
ln1
Cg
39

Super Buffer
-

we first find.

- this defines how much larger each subsequent stage is

relative to its driving stage
- we continue to add stages until the final Cg that can be
driven is Cload

40

Inverting Super Buffer

41

Inverting Super Buffer

1. Positive logic transition (0 to 1) on input Vin, allows

inverter formed by Tr t1 and T2 to turn ON.

2. Due to this gate T3 is pulled down towards 0Volt with
a small delay
3. Hence, T3 is cut-off while T4 is turned ON and the
output is pulled down quickly
4. Negative logic transition (1 to 0) on input Vin, allows
gate T3 to rise quickly to VDD
5. T4 is also turned off by Vin
42

Inverting Super Buffer

T3 is made to conduct with VDD on its gate with
twice the average voltage that would apply if the
gate
was tied as in the conventional nMOS inverter
Since Id proportional to Vgs, doubling effective Vgs
will increase Id thus reducing delay in charging Cl
on
the output transition symmetry achieved

43

Non Inverting Super Buffer

44

Non Inverting Super Buffer

Negative logic transition (1 to 0) on input Vin, allows
inverter formed by Tr T1 to turn ON and T2 to turn
OFF
Input Vin on gate T3 turns it OFF
Hence, T3 is cut-off while T4 is turned ON and the
output is pulled down quickly since T1 is turned on.
Positive logic transition (0 to 1) on input Vin, allows
gate T3 to rise quickly to VDD

45

Non Inverting Super Buffer

T4 is also turned off by T1 as it is cut-off
T3 is made to conduct with Vin on its gate as in
the conventional nMOS inverter.
Since Id proportional to Vgs, doubling effective
Vgs will increase Id thus reducing delay in
discharging

46

Static Complementary CMOS

Pull-up network (PUN) and pull-down network (PDN)

VDD

PMOS transistors only

In1
In2

PUN

InN

F(In1,In2,InN)

In1
In2
InN

pull-up: make a connection from VDD to F

when F(In1,In2,InN) = 1

PDN

pull-down: make a connection from F to

GND when F(In1,In2,InN) = 0
NMOS transistors only

PUN and PDN are dual logic networks

47

NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A

Y = X if A a n d B

Y = X if A O R B

N M O S T r a n si sto r s p a s s a str o n g 0 b u t a w e a k 1
48

PMOS Transistors in Series/Parallel Connection

PMOS switch closes when switch control input is low
A

Y = X if A AND B = A + B

Y = X if A OR B = AB

PMOS Transistors pass a strong 1 but a weak 0

49

49

Threshold Drops
VDD

PUN

VDD

VDD
0 VDD

VGS

CL
PDN
VDD

VDD 0
D

CL

0 VDD - VTn
CL

VGS

VDD |VTp|
S

CL

D
50

50

Complementary CMOS Logic Style

51

51

Example Gate: NAND

52

52

Example Gate: NOR

53

53

CMOS Logic Structures

1. CMOS Complementary Logic
VDD

E
C

Z = A*B + C(D+E)

B
Z

D
E

GND

54

54

CMOS Complementary Logic

VDD

VDD

C
D

Vgs [p]
P device

Vout

Vin

D
E

N device
Vss

GND

55

Complex CMOS Gate

B
A
C
D

OUT = D + A (B + C)
A

D
B

56

CMOS Logic Structures

57

57

CMOS Logic Structures

Static logic circuits hold their output values
indefinitely
Dynamic logic circuits store the output in a
capacitor, so it decays with time unless it is
refreshed.

58

Pass Transistors
Transistors can be used as switches
g=0

g
s

d
g=1

d
g=0

g
s

Input g = 1 Output
0
strong 0

Input
d

g=1
s

g=1

g=0
g=0

degraded 1
Output
degraded 0
strong 1

59

Pass Transistor
Pass-transistor circuits are formed by dropping the

PMOS transistors and using only NMOS pass transistors

In this case, CMOS inverters (or other means) must be
used periodically to recover the full VDD level since the
NMOS pass transistors will provide a VOH of VDD VTn in
some cases
The pass transistor circuit requires complementary
inputs and generates complementary outputs to pass on
to the next stage

60

Pass Transistor
This figure shows a simple

XNOR implementation
using pass transistors:
If A is high, B is passed
through the gate to the
output
If A is low, -B is passed
through the gate to the
output

61

Pass Transistor
At right,
(a) is a 2-input NAND pass

transistor circuit
(b) is a 2-input NOR pass
transistor circuit

Each circuit requires 8

transistors, double that

required using
conventional CMOS
realizations

62

Pass Transistor
Pass-transistor logic gate can implement Boolean

functions NOR, XOR, NAND, AND, and OR depending

upon the P1-P4 inputs, as shown below.

63

P1,P2,P3,P4 = 0,0,0,1 gives F(A,B) = NOR

P1,P2,P3,P4 = 0,1,1,0 gives F(A,B) = XOR
P1,P2,P3,P4 = 0,1,1,1 gives F(A,B) = NAND
P1,P2,P3,P4 = 1,0,0,0 gives F(A,B) = AND
P1,P2,P3,P4 = 1,1,1,0 gives F(A,B) = OR

Circuit can be
operated with
clocked P pull-up
device or inverterbased latch

Transmission Gates

N-Channel MOS Transistors pass a 0 better than a 1

P-Channel MOS Transistors pass a 1 better than a 0

This is the reason that N-Channel transistors are used in the pulldown network and P-Channel in the pull-up network of a CMOS
gate. Otherwise the noise margin would be significantly reduced.

64

Transmission Gates

A transmission gate is a essentially a switch that connects

two points. In order to pass 0s and 1s equally well, a pair
of transistors (one N-Channel and one P-Channel) are
used as shown below:

When s = 1 the two transistors conduct and connect x and

y
The top transistor passes x when it is 1 and the bottom transistor

passes x when it is 0

65

When s = 0 the two transistor are cut off disconnecting x

and y

Transmission Gates
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
Input

g
a

b
gb

b
gb

g = 0, gb = 1
a
b

g = 1, gb = 0
0
strong 0

g = 1, gb = 0
a
b

g = 1, gb = 0
strong 1
1

g
a

g
b

gb

Output

symbols

gb

66

Transmission Gates

Implementing XOR gates

With NAND gates and inverters:

With transmission gates:

67

Why would one of these circuits be preferable to the

other?

Transmission Gates

Implementing a multiplexer with transmission gates:

When S = 0, input X1 is connected to the output Y

When S = 1, input X2 is connected to the output Y

68

Static
NMOS
Totem-Pole Output

Vdd

as we have seen previously

Does not need to be

refreshed
Which is why it is called static

PMOS Acts as Constant

Current Source for Active

Pull-Up
Faster rise-times as compared

to non-CMOS
implementations

output
input

ground
69

Static CMOS

Complementary MOS
Example of a 2-input

VDD

NAND gate
output
Input 1
Input 2

ground
70

Dynamic NMOS
Output is 1 unless

Vdd

discharged
f1 Charges Output
f2 Conditionally Discharges
Output

f1
output
input

f2
ground
71

NOR2 Using pseudo nmos

72

Gates Using pseudo nmos

73

DCSVL
VDD

M1

VDD

M2

Out
A
A
B
B

Out

PDN1

PDN2

VSS

VSS

Differential Cascode Voltage Switch Logic (DCVSL)

74

DCVSL Example
Out
Out

XOR-NXOR gate

75

75

Complementary Pass Transistor Logic

A
A
B
B

Pass-Transistor
Network

A
A
B
B

Inverse
Pass-Transistor
Network

(a)

F=AB

F=A+B

F=AB
AND/NAND

F=A

(b)

F=A+B

B
OR/NOR

F=A

EXOR/NEXOR

76

76

Transmission Gate
C
A

C
A

B
C

C
C = 2.5 V
A = 2.5 V

B
CL

C=0V

77

77

Resistance of Transmission Gate

30
2.5 V

Rn
s 20
m
h
o
,
e
c
n
a
t
s
is
e 10
R

0
0.0

Rp

2.5 V

Rn
Vou t
Rp

0V
Rn || Rp

1.0

Vou t , V

2.0

78

78

Pass-Transistor Based Multiplexer

S

VDD
S

VDD

M2
F

S
M1
B

GND
In1

In2

79

79

Transmission Gate XOR

B

M2

F
M1
B

M3/M4

80

80

Dynamic CMOS
In static circuits at every point in time (except

when switching) the output is connected to either

GND or VDD via a low resistance path.
fan-in of n requires 2n (n N-type + n P-type) devices

Dynamic circuits rely on the temporary storage of

signal values on the capacitance of high

impedance nodes.
requires on n + 2 (n+1 N-type + 1 P-type) transistors

81

81

Dynamic logic

82

82

Dynamic Gate
Clk

Clk

Mp

Mp

Out
In1
In2
In3
Clk

CL
PDN

Out
A
C
B

Me

Clk

Me

Two phase operation

Precharge (CLK = 0)
Evaluate (CLK = 1)

83

Dynamic Gate
Clk

Clk

Mp

off
Mp on

Out
In1
In2
In3
Clk

CL
PDN

1
Out
((AB)+C)

A
C
B

Me

Clk

off
Me on

Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)

84

84

Footed and unfooted logic

85

85

Footed and unfooted logic

86

Footed and unfooted logic

87

Conditions on Output
Once the output of a dynamic gate is discharged,

it cannot be charged again until the next

precharge operation.
Inputs to the gate can make at most one
transition during evaluation.
Output can be in the high impedance state during

and after evaluation (PDN off), state is stored on

CL
88

Properties of Dynamic Gates

Logic function is implemented by the PDN only

number of transistors is N + 2 (versus 2N for static complementary

CMOS)

Full swing outputs (VOL = GND and VOH = VDD)

Non-ratioed - sizing of the devices does not affect

the logic levels

Faster switching speeds
reduced load capacitance due to lower input capacitance (Cin)
reduced load capacitance due to smaller output loading (Cout)
no Isc, so all the current provided by PDN goes into discharging CL

89

89

Properties of Dynamic Gates

Overall power dissipation usually higher than static

CMOS
no static current path ever exists between VDD and GND

(including Psc)
no glitching
higher transition probabilities
extra load on Clk

PDN starts to work as soon as the input signals

exceed VTn, so VLT, VIH and VIL equal to VTn

low noise margin (NML)

Needs a precharge/evaluate clock

90

90

Issues in Dynamic Design 1:

Charge Leakage
CLK
Clk

Mp

Out
CL

A
Clk

Me

Evaluate

VOut
Precharge

Leakage sources
Dominant component is subthreshold current
91

91

Solution to Charge Leakage

Keeper

Clk

Mp

Mkp

CL

Out

B
Clk

Me

Same approach as level restorer for pass-transistor logic

92

92

Issues in Dynamic Design 2:

Charge Sharing
Clk

Mp

Out

CL

B=0
Clk

Charge stored originally on CL is

redistributed (shared) over CL and CA
leading to reduced robustness

CA
Me

CB

93

93

Charge Sharing
VDD

case 1) if Vout < VTn

VDD

Clk

Mp

Mp

Out

Out

CL

=
BB
00

Clk

CL

Ma

Ma

M
Mb

Mee
M

XX
a
CC
a

CC
bb

C L VDD = C L Vout t + Ca VDD V Tn V X

or
Ca
V out = Vout t V DD = -------- V DD V Tn V X
CL

case 2) if Vout > VTn

Ca
---------------------
Vout = V DD
C
+
C
a
L

94

94

Solution to Charge Redistribution

Clk

Mp

Mkp

Clk
Out

A
B
Clk

Me

Precharge internal nodes using a clock-driven transistor (at the cost of

increased area and power)

95

95

Cascading Dynamic Gates

V
Clk

Mp

Clk

Mp

Out1

Me

Clk

Out2
In

In
Clk

Clk

Me

Out1

VTn
V

Out2
t
Only 0 1 transitions allowed at inputs!

96

96

Cascading Dynamic Gates

97

97

Cascading Dynamic Gates

98

Domino Logic
Clk
In1
In2
In3
Clk

Mp

11
10

PDN

Me

Out1

Clk

Mp Mkp

Out2

00
01

In4
In5
Clk

PDN

Me

99

Domino Logic
Clk

Ini
Inj
Clk

PDN

Ini
Inj

PDN

Ini
Inj

PDN

Ini
Inj

PDN

100

100

Properties of Domino Logic

Only non-inverting logic can be implemented
Very high speed
static inverter can be skewed, only L-H transition
Input capacitance reduced smaller logical effort

101

101

Designing with Domino Logic

VDD

VDD
VDD

Clk

Mp

Clk
Out1

Mp

Mr
Out2

In1
In2

PDN

PDN

In4

In3

Can be eliminated!
Clk

Me

Clk

Me

Inputs = 0
during precharge
102

102

Footless Domino
VD
C

VD

Mpk

C
O

Mpk

0
I

VD

I
1

O
1

I
0

Mpk

I
1

n
0

The first gate in the chain needs a foot switch Precharge is

rippling short-circuit current A solution is to delay the clock for
each stage
103

103

Differential (Dual Rail) Domino

off
Clk
Out = AB

on

Mp Mkp

Mkp

Clk

Mp

!A

Out = AB

!B

B
Clk

Me

Solves the problem of non-inverting logic

104

104

np-CMOS
Clk
In1
In2
In3
Clk

Mp

PDN

Me

11
10

Out1

Clk

Me

In4
In5

PUN
00
01

Clk

Mp

Out2
(to PDN)

Only 0 1 transitions allowed at inputs of PDN Only 1 0

transitions allowed at inputs of PUN
105

105

NORA Logic
Clk
In1
In2
In3
Clk

Mp

11
10

Out1

PDN

Clk

Me

In4
In5

PUN
00
01

Clk

Me

to other
PDNs

Mp

Out2
(to PDN)

to other
PUNs

106

106