Professional Documents
Culture Documents
(a)
I.
I NTRODUCTION
(b)
Fig. 1. (a) International Technology Roadmap for Semiconductors (ITRS)
based technology trends for scaling of MOSFETs for higher performances.
(b) Conventional scaling of MOSFETs till 2011 without use of exotic FET
structures and using standard CMOS processes.
Gate-Metal
(a)
(b)
(c)
Channel-Silicon
(d)
(e)
(f)
Fig. 2. (a) Early Intel FINFEts (b) Trigate (c) Omega-Gate (d) Pi- Gate (e)
Gate All Around (GAA) (d) Crosssection of Nanowire FET (SNWTs)
Fig. 3.
Fig. 4.
II.
Fig.1 shows the the advancements in conventional MOSFET designs till 2001-2012. Fig.1 (a) shows the International
Technology Roadmap for Semiconductors (ITRS) based technology trends for scaling of MOSFETs for higher performances. ITRS predicts the future of industries technology for
commercial purposes. From this we can see that the industry
is expected to use MOSFETs of channel lengths of 14nm by
the end of this year (2016). Also it predicts that by year 2020
commercial requirements will be of sub-10nm MOSFETs. So
the research in the field these exotic sub 10nm devices are
very much needed. Fig 1(b) shows some the latest technology
advancements to the present day from Intel using almost
standard CMOS processes and convectional FET geometries.
We will begin by reviewing the present and popular candidates for sub-10 nm transistors. We will explore the pros and
cons of each of them. After the literature survey we will move
towards the structural details of the GAA based nano-wire
SNWTs in section III. We will see the latest research work in
the field of GAA fabrication, transport mechanism, parasitics,
noise and variability. Then we will move the abstraction of
the equations developed in earlier sections in terms of verilogA modelling. We simulated the SNWTs in both analog and
digital sub-blocks. Using the simulations I tried to predict the
circuit performance of the conventional blocks in future (when
SNWTs will be used commercially).
A. Transport Mechanism
The basic carrier transport mechanism of the nano-wire
SNWTs is fundamentally different than FINFETs. According
to [7] we see the mechanism for the channel formed under the
GAA (Gate All Around) is ballistic transport behaviour. Fig 4
shows the illustration.
As devices are scaled to the nano-scale dimension, ballistic
transport of carriers becomes increasingly important. It is
possible that the channel length is shorter than the mean
free path such that the channel carriers will not suffer from
any scattering events. However, in the quasi-ballistic regime
Vout
Ft is freq at which
(Iout/Iin)VD=0 =1
Iout Ft=Gm/(2*pi*CG)
Vin
RDS =
dIDS
dt
-1
Gm:Transconductance
M3
M4
Iin
Intrinsic drain
capacitor, CD
Intrinsic Gate
capacitor, CG
M1
Fig. 5.
M2
M5
INPUT Differential Stage
Fig. 6.
(1)
Vin
Vin
where Vinj and Bsat are the injection velocity and ballistic
efficiency. Eq.(1) describes how fast carriers are injected from
the source-Vinj, and how efficiently carriers will be transported
through the channel-Bsat. The more the carriers are reflected,
e.g., rc, the lower the Bsat is, as shown in Fig. 1, where rc
is the reflection coefficient, and the correlation between Bsat
and rc can be given by:
Bsat =
(1 rc )
(1 + rc )
1 VD,sat
(VGS VT H )
(3)
C IRCUIT S IMULATIONS
CG
CD
CD
CD
Inverter
Fan-Out of 4
IV.
(2)
CD
CD
CG
Fig. 7.
CD
Vout
Vout
C ONCLUSION
[2]
[3]
[4]
[5]
[6]
[7]