Fall 2016 / EE5/7321

Homework #2
Assigned on: September 12, 2016
Due by: September 27, 2016
General instructions

Review materials (concepts and derivations) introduced in lectures 1-5

Start each problem on a fresh page (not the sub-parts)
While submitting, submit answers to the problems in order
State your assumptions very clearly in case of ambiguities
If you find more than one approach to solve problems, present all of your ideas
Write your name and student ID only on either the first or last page using a separate cover sheet
Number all pages serially using numerals or alphanumeric characters

Problem #1

10X5 = 50points

This question would help revise concepts related to MOS device and basic circuit design. Please mark all
correct answers to the following multiple choice questions.
1.1. Which of the following are true about MOSFET devices?
(a)
(b)
(c)
(d)

MOS stands for Metallurgy Of Semiconductors

MOSFET current conduction is due to drift phenomenon
An externally induced voltage at the gate is fundamental to inversion layer
Naming of Source and Drain regions are only dependent on aspect ratio

1.2. Which of the following are true about NMOS transistors

(a) The threshold voltage can be positive or negative depending on geometry
(b) Channel length modulation parameter () is always positive
(c) Current flows from drain to source
(d) Threshold voltage is a fixed value based on process, it cannot be changed by external voltages
1.3. In a MOS device
(a)
(b)
(c)
(d)

CGS and CGD both have both geometry and voltage dependencies
CGS is takes minimum value at saturation while CGD goes to maximum value
CDB and CSB are contributed from reverse bias p-n diode formation
High frequency gain of an amplifier is independent of intrinsic capacitors

1.4. For an NMOS device

(a) The DC component of input current has almost zero value
(b) The AC component of input current has a finite value
(c) Small signal parameters are derived first independent of large signal parameters and are tweaked for
best performance
(d) DC operating points are first fixed and small signal values are uniquely computed

1.5. In a MOS device

(a)
(b)
(c)
(d)

Drawn channel length may sometimes be smaller than effective electrical length
There are trapped charges in the gate oxide due to processing that affects VT
A metal connection is used on highly doped regions to make external contacts
Current conduction is by majority carriers

1.6. In a MOS device

(a) Output impedance is largest when the device is in saturation region
(b) Output impedance is smallest when the device is in saturated region

(c) In the linear region of operation, output impedance is a function of aspect ratio
(d) Early voltage cannot be interpreted from channel length modulation parameter

1.7. In a single transistor based amplifier

(a)
(b)
(c)
(d)

Source in a common source w/o degeneration is at DC ground but not AC ground

Source in a common source with degeneration is at AC ground but not DC ground
Input voltage is commonly connected to the gate
Drain in a common source w/o degeneration is at AC ground but not at DC ground

1.8. In a positive voltage system (all DC voltages in circuit >0V)

(a) For a common gate amplifier, maximum small signal current occurs in saturation
(b) Gate terminal is both DC ground and AC ground
(c) Current gain of the common gate stage is approximately unity
(d) Drain of a common drain NMOS based amplifier is connected to max voltage

1.9. In a single transistor based amplifier

(a) Common source with degeneration is used to increase output impedance
(b) Common source amplifier with degeneration does not provide phase inversion
(c) The maximum intrinsic gain of basic CS amplifier w/o degeneration is independent of biasing
condition
(d) CG stage and CS stages (w/o degeneration) provide same voltage gain but opposite phase shift when
driven with a very low output impedance driving source
1.10. For single transistor amplifiers
(a) CG stage has low input impedance and CD stage has low output impedance
(b) CD stage provides close to unity voltage gain and CG stage provides close to unity current gain
(c) CG and CD stages are non-inverting in nature
(d) Voltage gain of CS stage with large transconductance and degeneration product is a ratio of load and
degeneration impedances

Problem #2

50points

Consider an NMOS structure that is made with the following characteristics

tOX = 100 A, N a = 8 1014 cm 3 , VT 0 = 0.7V , n = 580cm 2 / V sec

(a) Calculate the process transconductance
(b) Calculate the body-bias coefficient
(c) An NMOS is made with W=10m and L=1m. Calculate the drain current if VGS=2V, VDS=1V,VSB=1V
(d) Repeat the calculation for current when VGS=2V, VDS=3V,VSB=0V

Problem #3

50points

Use the following process parameters

NMOS: TOX = 9.10 9 m, n = 350.10 4 [ m 2 / V S ],VT 0 = 0.7V , = 0.1V 1 , = 0.45
PMOS: TOX = 9.109 m, n = 100.104 [m 2 / V S ],VT 0 = 0.8V , = 0.2V 1 , = 0.4
2.1. For W/L=50/0.5 and ID=500uA, compute the transconductance and output impedance of both
NMOS and PMOS; Also find the intrinsic voltage gain
10 points
2.2. Derive expression for intrinsic transistor gain in terms of bias current ID and aspect ratio (W/L). If the
1
channel length modulation is given by , plot intrinsic gain vs drain current with channel length
L
as parameter
10 points
2.3. Derive the drain current ID for the PMOS structure shown below, and obtain the effective aspect
ratio of the two series connected transistors (i.e. obtain the (W/L)eff of a single transistor that will
replace these two in terms of individual (W/L). Extend this analysis for N Series connected PMOS
transistors [ignore channel length modulation]
20 points

G
W

L

W

L

VSG

S +

VSD

2.4. To be used as a current mirror, transistors should be in saturation; however being in saturation may
not necessarily mean that they can be used as a current mirror; Explain this phenomenon conceptually
for the PMOS and NMOS gate-drain connected transistors shown below
10 points
VDD

G
S

B
D

(a) PMOS

(b) NMOS

Problem #4

50points

Assume these device parameters k ' = 250A / V 2 , VT 0 = 0.5V , = 0.25V 1 , | F |= 0.3, = 0.5
3.1 For the following circuits, determine the input voltage VIN for VOUT =1.5V (all voltages between 0-3V)
25 points
3.2 Compute small signal parameters g m , rofor all three circuits

25 points

3V

3V

3V
1k

1k

10k

(4/0.25)

VOUT

VOUT

VOUT
VIN

(4/0.25)

VIN

(4/0.25)

200
VIN

1.2V

300
(a)

(b)

(c)

Problem #5

50points

Use the following process parameters

TOX = 9.109 m, n = 350.104 [m 2 / V S ],VT 0 = 0.7V , = 0.45

For the amplifier shown below, assume =0
(a) What is the small-signal gain if M1 is in saturation with ID=1mA?
15 points
(b) Compute the value of input voltage and the small signal gain when M1 is at the edge of triode region
20 points
(c) Compute the value of input voltage and small signal gain when M1 is pushed further into triode
region by 50mV
20 points

3V
2k
VOUT

VIN

M1(50/0.5)

Problem #6

50points

Analyze the following NMOS based circuits

(a) Write the large signal equations of voltage and currents and identify circuit functionalities
15 points
(b) Derive small signal parameters, Av,Ai,Rin,Rout for both cases (list clearly the assumptions and
approximations that you make for simplification with detailed justifications). Obtain these expressions
under the condition RF>>RD
35 points

VDD

VDD

RD

M1

VIN

RF
VOUT

VOUT
VIN

M1

RF
RD