SpyGlass Lint/CDC Analysis for XILINX

FPGA
Satrajit Pal

WHITE PAPER

Atrenta, Inc.
2077 Gateway Place
Suite 300
San Jose, CA 95110
Atrenta Inc, 2014 | All rights reserved

Contents
1.

Introduction ................................................................................................................ 3

2.

SpyGlass-FPGA-Kit: The SpyGlass XILINX FPGA Solution ....................................... 4

3.

SpyGlass-FPGA-Kit: Using the Kit .............................................................................. 6

4.

Conclusion ................................................................................................................. 6

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1. INTRODUCTION
As the cost of doing ASIC design skyrockets, FPGAs are becoming an attractive
alternative for system-on-chip (SoC) types of design. Large numbers of
increasingly complex designs are now done with FPGAs, making verification a
major task. Besides the usual issues of width mismatch, connectivity or
synthesis-simulation mismatch, there are also problems related to multiple
asynchronous clock domain crossings (CDC) like meta-stability, data
re-convergence, FIFO integrity, and more.
Given that a verification flow using SpyGlass for ASICs already exists for the
problems highlighted above, this document describes the steps required to take
an RTL design for XILINX FPGAs through SpyGlass to make it Lint and CDC clean.
A typical SpyGlass flow for an RTL design is as shown in Figure 1:

Figure 1: SpyGlass flow for RTL design analysis

CDC analysis for an FPGA is very similar to an ASIC design. So why it is that FPGA
based design doesnt work if taken through SpyGlass as is?
For complete CDC analysis, RTL models have to be synthesizable. There should be
no black-boxes, and that is where the problem begins. FPGA libraries for hard
macros are optimized for simulation and thus contain many behavioral constructs
which are non-synthesizable. Besides, design constraints do not always confirm to
Synopsys Design Constraints (SDC) standards.
Black-boxes are generated due to the un-synthesizable library models (library files
are simulation centric with large number of un-synthesizable constructs),
encrypted vendor-IPs or missing RTL descriptions for IPs.

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Figure 1 also highlights the various types of problems faced with the different
design components when the design is taken through SpyGlass.
As a solution, SpyGlass provides a kit, SpyGlass-FPGA-Kit that addresses these
problem areas, thereby minimizing user intervention.
This kit requires SpyGlass 5.2 release or higher.
The subsequent sections will describe the problems and their solutions in the
context of the SpyGlass-FPGA-Kit.
2. SPYGLASS-FPGA-KIT FOR XILINX FPGA SOLUTION
Figure 2 below illustrates the flow to take a Xilinx FPGA-based design through
SpyGlass.

Figure 2: SpyGlass Xilinx FPGA Kit Flow

The Design Read step requires handling of Xilinx library. The Verilog descriptions of
the cells are simulation centric, and hence not synthesis friendly. The .lib models
do not cover all the cells, and in some cases only have the interface information.
When these models are taken through SpyGlass, they generate black-boxes.
CDC analysis requires a fully synthesized design. Presence of the black-boxes will
result in incomplete analysis.
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SpyGlass has a mechanism, in the form of SpyGlass Design Constraint (SGDC)

models, to provide design clock information, such that CDC analysis can be
completely performed even in the presence of black-boxes.
As part of the kit, SpyGlass provides pre-created models for most of the Xilinx
Library cells whose descriptions cannot be directly used from the Xilinx libraries.
These models are integrated into the Kit. Mostly, these are SGDC models, but
incase the clock domains of cell outputs vary depending on configurations, then
HDL models are required.
Design Constraints, if present, can be read into SpyGlass. If constraints are in the
form of Xilinx design constraints (XDC), SpyGlass will be able to use it as is. But if it is
in the form of user constraint file (UCF) compatible with Xilinx ISE/ PlanAhead tools,
then it has to be converted to XDC using the ISE tcl command - write_xdc.
The Audit Run of SpyGlass gives the black-box information.
If there are Black-Boxes that have no SGDC models, then user has to provide the
clock information through SGDC models for CDC analysis.
To simplify things, the kit generates a template file with the SGDC models for all
the unconstrained black-boxes in the design. The user has to just provide the
clock names of the black-boxes.

Figure 3: SpyGlass design constraints for back-box handling

The advantage that SpyGlass provides, is with these SGDC models for the
black-boxes, CDC issues at the interface of the black-boxes will be detected.
Once all the setup files (design + constraint files) are created and added to the
flow, the design can be taken through SpyGlass Lint and CDC analysis.
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3. SPYGLASS-FPGA-KIT: USING THE KIT

The README that comes with the kit guides the user to:
Setup the environment
Setup the design
Handle the black-boxes
Perform Lint/CDC analysis
Interested users can access the SpyGlass-FPGA-Kit from the Atrenta website.
There is a complete tutorial on taking a sample FPGA design through the
SpyGlass-FPGA-Kit. Please contact Atrenta Support for access to
SpyGlass-FPGA-Kit.
4. CONCLUSION
SpyGlass Lint and CDC are critical analysis tools for RTL designs that identify chip
killer problems and shorten design cycle time.
This document highlights the issues that come up when taking a XILINX
FPGA-based design through the default SpyGlass flow.
With SpyGlass-FPGA-Kit, a step-by-step guide is provided to the user to take the
FPGA based RTL through SpyGlass for Lint/ CDC analysis with minimum effort. The
approach takes care of handling Xilinx library files, design files and design
constraints.

End of Document

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