TEXAS A&M UNIVERSITY

Department of Electrical and Computer Engineering

College Station, Texas 77843

ELEN-665 Final Project

Design of CMOS Ring VCO and Quadrature LC VCO
for 8 phases Generation

Qiyuan Liu and Xiangyong Zhou

ABSTRACT
In this project, both a 4-stage differential multipath ring VCO and a series quadrature LC VCO with
polyphase filter are designed to generate 8-phase output. The design is implanted using TSMC 0.35um
technology and Spectre simulation shows that -120dBc/Hz phase noise at 1MHz offset is achieved for
both topologies. The tuning range is from 1.2GHz to 1.5GHz and the phase error is controlled below 2
degree.

I. INTRODUCTION
Multiphase generation is widely used in high speed wireless and wire-line communication systems. In
wireless application, one example is phase-array receiver which is based on multiple-antenna phased
arrays. In wire-line application, one popular example is the phase detector in the clock and data recovery
(CDR) system. The availability of accurate multiphase signals is a prerequisite for the implementation of
high performance and that is probably why the study of multiphase generation has attracted the interest of
many researchers.
In design of multiphase VCOs, one of the most critical issues is the tradeoff of phase noise and phase
error. The phase noise in wireless communication emits interference energy at adjacent bands which is
critical to minimize for proper operation of the entire system. The phase noise in SerDes simply integrates
to form the rms random jitter which subtracts from the jitter margin. The phase noise requirement for this
project is -120dBc which is a pretty common value seen on papers and can satisfy the requirement of a lot
of applications. The phase error between different phases is important for image rejection in wireless
communication system and for minimizing jitter for inter-chip communication systems. Less than 1 deg
of phase error is required for wireless communication while for SerDes a less stringent requirement is set
for jitter performance.

II. BACKGROUND
One of the good properties of the topology of ring oscillator is that it can generate multi-phase output
directly. That is why multiphase ring oscillators are kind of dominant in research and industry. In this
project, a 4 stage multipath ring oscillator is designed for 8 phase output generation.
LC oscillator is also very attractive since it can provide better phase noise performance. Efforts have been
made to generate multiphase output using LC oscillator. Generally there are three methods for the aim of
multiphase generation [1]. At present the most popular method is to let the LC VCO oscillate at a higher
frequency, and then use the frequency divider to obtain multiple phases at lower frequency. This
frequency division approach has the additional benefit of avoiding any pushing /pulling effect on the
VCO due to the strong signal from the power amplifier. As a drawback, however, a higher oscillation
frequency and higher power consumption due to the high speed divider circuit are usually demanded.
Multiphase output can also be obtained by using a polyphase filter, usually realized as an RC polyphase
filter. Also this approach introduces substantial power consumption and the buffers are needed for the
preceding VCO in order not to decrease the Q of the LC tank. A third method of generating multiphase
output is by cross-coupling LC-tank VCOs. The combination of a direct connection and a cross
connection forces two VCOs to oscillate in quadrature. Buy cross coupling more number of VCOs, more
output phases can be achieved. In this project, 8 phases output is implemented by combing the second and

third approach. A quadrature VCO is first used to generate 4 phases output and then a polyphase filter is
adopted to do the 4 to 8 phase conversion.

III. PROPOSED DESIGN

III.1 Design of Ring VCO for 8-Phase Output Generation
For good phase noise, power and frequency trade-off, the ring oscillator design used a multipath 4 stage
differential topology (shown in Fig 1). The last stage of the four inverters is cross-coupled to get a net 180
phase shift over the loop. The single-ended schematic of each inverting cell is shown in Fig 2 [2].

Fig 1 Multipath 4 stage differential ring VCO topology

Fig 2 Single-ended schematic of each inverting cell

The oscillating frequency of the proposed ring oscillator can be estimated by the following equation,
where and are the phase difference between primary and secondary input to the output phases, R,C
are the output resistance and capacitance of each stage and gms is the secondary input transconductance.

Transistor P1 is fixed, however, the gate voltage of P0 and P2 can be adjusted to change the oscillating
frequency, in which P2 is for course tuning. To get larger tuning range, the size of P0 and P2 should be
increased. To get higher center frequency, P1 and N0 can made larger to increase the biasing current.
The phase noise performance of the ring oscillator can be analyzed based on the following equations:

In which,

The phase noise can be expressed as:

The phase noise due to flicker noise can be expressed as:

In this topology, N0 has an optimal value around half size of N0 in terms of phase noise. A width sweep
can be done to find it.
Generally considering the design issues above the dimensions of the transistors are listed in Table 1.
Table 1 Dimension of transistors in each inverting cell
Transistor
P0
P1
P2
N0

W
12u
13u
20u
30u

L
600n
600n
600n
600n

8 Phase Ring VCO simulation Result

The required running range of the ring oscillator is 1.2GHz to 1.5GHz. Fig 3 shows that the tuning range
is satisfied over the control voltage from 0V to 1.65V with an average slope of 188MHz/V. The curve
above 1.65V then flattens out and cannot be used to provide relatively constant VCO gain anymore.

Fig 3 Frequency tuning of ring VCO

Fig 4 shows the change of Kvco with the control voltage which is the derivative of the tuning range curve.
It can be seen that the VCO gain is within 157MHz/V to 200MHz/V while the control voltage is within
0V to 1.65V with a percentage range of 25% variation. This variation must be accounted for when
designing the loop dynamics of the PLL response so as to make the loop stable and fast enough under all
VCO gains.

Fig 4 KVCO changing with control voltage

The phase noise at 1MHz offset over the entire tuning range is shown in Fig 5. The achieved phase noise
is pretty good (around -120dBc/Hz). However, flicker noise is not considered in this simulation since the
flicker noise model is not provided in the tsmc35 model of the Cadence. One general way to deal with
flicker noise is to increase the size of transistors. However, this may lead to the frequency drop since the
parasitic capacitors are also increased which may lead to a serious problem in designing high frequency
ring oscillators. However, in this design, the multipath topology has a boost effect which can compensate
for the frequency drop which gives more freedom for the designer to optimize the flicker noise
performance.

Fig 5 Phase noise changing with control voltage

The amplitude of the output signal of the ring oscillator within the tuning range is shown in Fig 6. Using
swept PSS simulation, the amplitude is shown to vary between 1.26V to 1.43V, which is sufficient to
drive a following VCO buffer and the variation in amplitude is also satisfactory over the entire frequency
range. The output power is over 12dBm when referred to a 50Ohm load.

Fig 6 Amplitude changing with oscillating frequency

The current consumed by the VCO is shown below. The overall current is around 28mA with a supply
voltage of 3V. This amount of power is comparable with the reference paper we used while even getting a
better phase noise performance.
The performance of the designed ring VCO is compared with the other ring VCOs found in literature
(shown in Table 2). The comparison is based on a figure of merit (FOM) defined as:

Design
[3]
[4]
[5]
This Work

Table 2 Dimension of transistors in each inverting cell

Pdiss
Tuning Range
Phase Noise
Technology
(mW)
(GHz)
(1MHz)
0.12um CMOS
15
3.2-10
-90
0.6um CMOS
30
0.75-1.2
-117
0.18um CMOS
80
4.3-6.1
-85
0.35um CMOS
84
1.15-1.51
-120

FOM
-154
-165.8
-140
-164

III.2 Design of Quadrature LC VCO for 8-Phase Output Generation

P-QVCO and S-QVCO
The first and best known implementation of this principle is the parallel quadrature VCO (P-QVCO)
proposed by Rofougaran et al as shown in Fig 7 [6]. In this topology, the coupling between the two VCOs
is enforced by transistors Mcpl placed in parallel with the switch transistors Msw. However, the recent
paper introduce an alternative way of cross coupling two differential VCOs to series quadrature VCO (SQVCO), in which the coupling transistor Mcpl is placed in series with Msw (shown in Fig 8), rather than
in parallel. The idea is motivated by the fact that in P-QVCO, Mcpl can contribute a lot to phase noise.
By connecting Mcpl in series with Msw in S-QVCO, a cascode structure is formed and the contribution
of the noise from cascode transistor Mcpl can be reduced. Besides, the cross-coupled switches in SQVCO operate in the triode region for most of the oscillation period, and their flicker noise is lower than
the one for the coupling pair. Considering the better noise performance, S-QVCO topology is adopted in
this design.

Fig 7 Parallel quadrature VCO (P-QVCO)

Fig 8 Series quadrature VCO (S-QVCO)

A linear model for the QVCO is shown in Fig 9, in which Gm represents the transconductance of the
negative-resistance pair (Msw) and Gmc represents the transconductance of the coupling pair. The
oscillation frequency will be slightly displaced from the tank resonance frequency. Fig 10 shows the
phasors of the voltage across the tank and the currents entering the tank. The linear model can also be
used to analyze the performance of the nonlinear oscillator by redefining Gm and Gmc as the effective
transconductance and the effective coupling transconductance respectively [1,7,8]:

GM

I I ,1
A0

, GMc

I Q ,1
A0

where I I ,1 is the component of the first current harmonic in-phase with Vx and I Q ,1 is the quadrature
component of the first current harmonic.

Fig 9 Linear model for QVCO

Fig 10 Voltage and current for tank X

In P-QVCO, both phase noise and phase error are strongly dependant on the coupling factor, which is
defined as the ratio:

Wcpl
Wsw

The smaller the coupling factor is, the better phase noise will be achieved. However, a small coupling
factor will lead to a big phase error. So there is obviously a trade-off of phase noise and phase error in PQVCO design.
In S-QVCO, on the contrary, the phase error is almost independent of the coupling factor for all
reasonable values. In this case, the phase error depends only on the actual amount of mismatch between
ideally identical components, once the QVCO architecture has been selected. Thus, you have much more
flexibility to optimize the phase noise of S-QVCO. That is another good advantage of S-QVCO compared
with P-QVCO.
To estimate Gm and Gmc in the S-QVCO, a highly simplified picture for the differential current
waveforms in 4 different phase cases are shown in Fig 11. During phase 2 and 4, the cross-coupled
switches operate in the triode region and never switch off completely. The bias current is therefore shared
between both branches. While, in phase 1 and 3, the bias current is injected into only one branch.

Fig 11 A highly simplified picture for the differential current waveforms

The current levels indicated with I1 and I2 in Fig 5 also depend on :

I1 I 2 (1 2 ) Itail
Thus, we can estimate I I ,1 and I Q ,1

I I ,1

I Q,1

(2 I tail I 2 I1 )
1

(2 I tail I1 I 2 )

Thus, the coupling factor can be estimated as:

(1 ) I tail
4

I tail

In this design, the tail current is 12mA and the measure average current during phase 2 corresponding to
I1 is around 4mA. Thus the coupling factor is calculated to be around 0.5.
S-QVCO Design
Considering the advantage of S-QVCO over P-QVCO described above, the S-QVCO topology is adopted
in this design. The schematic is shown in Fig 12 and the main device dimensions are listed in Table 3.
The inductor model used in this design is shown in Fig 13 and the parasitic values are listed in Table 4.
The Q of the inductor is around 8 (It is very difficult to get a Q larger than 5, so this model is taken from a
published paper on VCO). The tail current is chosen to be 12mA (power consumption of 72mW), so that
a good gm can which will ensure the oscillation under various control condition. Since there is no
Accumulation-Mode Varactor offered in the library, we connect Bulk, Source and Drain of a PMOS
transistor together to form one terminal of the varactor, and use the gate as the other terminal. In this way,
we can get a relatively large cap tuning from 2.8pF to 1.2pF. However, the range is not enough for the
requirement, so a cap bank is needed to enhance the tuning range.

Fig 12 S-QVCO schematic

Table 3 S-QVCO device dimensions
Transistor
W
L
Mvaractor 30x10um
2um
Mcpl
115x10um
400nm
Msw
40x10um
400nm
Mtail
100x10um
1um

Fig 13 Inductor model

Table 4 Inductor parasitics
Parasitics
Value
Lind
1.5nH
Rind
1.6Ohm
Cside
49fF
Rside
3.13Ohm
Cmid
129fF
Rmid
13.1Ohm
Ccp
40fF
The cap bank is controlled by 4 bit thermometer code and the value of each cap cell is 1pF. The detailed
schematic is shown in Fig 14.

Fig 14 Capacitor bank for S-QVCO

By adjusting the control voltage from 2V to 2.8V and adjusting the cap from the cap bank from 0p to 3pF
a frequency tuning range from 1.19GHz to 1.52GHz can be achieved (shown in Fig 15). Certain overlap
is kept to ensure that there is no blind zone.

Fig 15 Frequency tuning of QVCO

A phase noise of -130dBc/Hz at 1MHz offset is achieved and enough margin since the noise performance
will definitely get worse when the QVCO is connected to the polyphase filter to generate the eight phases.
Polyphase Design
The rest work now is to convert the 4 phase signal from QVCO to 8 phases using polyphase filter.
Polyphase filter is widely used for 4-phase I/Q generation because of its good image rejection property.
Fig 16 shows how differential quadrature phases are generated from a differential input [9]. The
differential signal may be decomposed into two equal amplitude quadrature sequences, on clockwise and
the other counterclockwise. When the input signal frequency is at the RC pole, the polyphase rejects the
clockwise sequence and only the counter clockwise sequence comprising perfect balanced quadrature
survives at the output. Using this property, the concept can be used to convert quadrature phases into 8
phases. The 3rd order 4 to 8 phases converting polyphase filter topology is shown in Fig 17.

Fig 16 Image rejection property of polyphase filter

Fig 17 4 to 8 polyphase filter topology

Kaukovuori et.al gave a detailed analysis for poly phase filters and gave a lot of inset on the design of this
kind of filter [10]. The image rejection ratio is a figure-of-merit (FOM) for a PPF used for I/Q generation
and
to get a good image filtering performance, third order poly phase filter is adopted in this design. The IRR
as a function of frequency is

The pole splitting factors are defined as:

k2

, k3 1
2
3

To achieve equivalent minimum IRR of every two notches, the following condition must be satisfied:

k3 k2 2
Which means middle frequency should be the geometry average of the low and high frequency.
The relative bandwidth is defined as:

BWrel

max
2k2 2 1.9k2 0.9
min

In this design we want a relative bandwidth of 1.25.The loss of the filter is another issue to consider. As a
rule of thumb, the signal losses 3dB per stage, so generally 9dB loss is expected in a 3 stage poly phase
filter.

In this design, the low frequency pole is located at 1.2GHz and the high frequency pole is located at
1.5GHz. The optimized middles frequency should be 1.34GHz which is the geometry average of low and
high frequency. The capacitors are of equal value of 1pF, and thus the resistances are calculated to be
106.1, 118.6 and 132 respectively.
The Matlab code used to optimize the poly filter is listed as below:
R1=106.1;
R2=118.6;
R3=132;
C3=1e-12;
C2=1e-12;
C1=1e-12;
w1=1/(R1*C1);
w2=1/(R2*C2);
w3=1/(R3*C3);
s=tf('s');
s1=j*w1;
s2=j*w2;
s3=j*w3;
IIR=((s+s1)*(s+s2)*(s+s3))^2/((s-s1)*(s-s2)*(s-s3))^2;
bode(IIR,{2*pi*1e9,2*pi*2e9})
k2=w1/w2;
k3=w1/w3;
BW=2*k2^2-1.9*k2+0.9

8 Phase Quadrature VCO simulation Result

In order to simulate the designed QVCO and Polyphase Filter above, a buffer stage between them is
needed. A simple differential pair with AC-coupled input is adopted in this design. The output resistance
of the buffer is carefully optimized. The transient simulation of the 8 phase output signal is shown in Fig
18. From the output waveform, a 1V peak amplitude is achieved which means 10dBm output power when
referred to a 50Ohm load resistance. The phase error is roughly measured using the phase function in
Cadence calculator and we can see that the phase error is smaller than 2 deg which meets the design
requirement (shown in Fig 19). PSS and Pnoise simulation is run for the system (QVCO, buffer and PPF)
and the phase noise performance at 1MHz offset is -126.6dBc/Hz which is shown in Fig 20. The general
performance of the QVCO for 8 phase output generation using polyphase filter is summarized in Table 3.
Comparison is made with other 8 phase generator found in literature. Most of the design parameters are
competitive to other design in literature, though the power consumption still needs to be optimized.

Fig 18 8 phase transient output signal

Fig 19 Phase of 8 transient output signal

Fig 20 Phase noise performance of the LC phase noise generator

Table 3 8 Phase QVCO with polyphase filter performance summary and comparison
Vdd
Pdiss
Tunning
Phase Noise
Design
Technology
fo(GHz)
(V)
(mW)
Range(%)
(1MHz)
[11]
0.13um CMOS
37
1.2
16.4
8.3
-94.3
[12]
SiGe: C BiCMOS
2.5
2
32
20
-104.9
1.5
3
72
22.2
-126.6
This Work
0.35um CMOS

DISCUSSION
In this project, two different topologies are used to generate 8-phase output. Both of the ring VCO and the
LC VCO with polyphase filter can handle the tuning range from 1.2GHz and 1.5GHz. The ring oscillator
is optimized to have a good phase noise performance of -120dBc/Hz at 1MHz offset and the LC oscillator
has even better phase noise performance. The total power consumption of the ring oscillator is 84mW,
while the power consumption of the QVCO stage alone is 72mW. The buffer to drive the polyphase filter
also consumes a lot of power to get good oscillating performance. Generally, the design meets all the
specifications of this project. However, further power consumption optimization still needs to be done in
the future.

REFERENCE
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[9] Farbod Behbahani, Yoji Kishigami, John Leete, and Asad A. Abidi, CMOS Mixer and Polyphase
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