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Sum out S0 and carry out Cout of the Full Adder 1 is valid only
after the propagation delay of Full Adder 1. In the same way, Sum
out S3 of the Full Adder 4 is valid only after the joint propagation
delays of Full Adder 1 to Full Adder 4. In simple words, the final
result of the ripple carry adder is valid only after the joint
propogation delays of all full adder circuits inside it.
Full adder.
To understand the working of a ripple carry adder completely, you
need to have a look at the full adder too. Full adder is a logic
circuit that adds two input operand bits plus a Carry in bit and
outputs a Carry out bit and a sum bit.. The Sum out (Sout) of a
full adder is the XOR of input operand bits A, B and the Carry in
(Cin) bit. Truth table and schematic of a 1 bit Full adder is shown
below
There is a simple trick to find results of a full adder. Consider the
second last row of the truth table, here the operands are 1, 1, 0 ie
(A, B, Cin). Add them together ie 1+1+0 = 10 . In binary system,
the number order is 0, 1, 10, 11. and so the result of 1+1+0
is 10 just like we get 1+1+0 =2 in decimal system. 2 in the
decimal system corresponds to 10 in the binary
system. Swapping the result 10 will give S=0 and Cout = 1 and
the second last row is justified. This can be applied to any row in
the table.
The number of gate levels for the carry propagation can be found
from the circuit of full adder. The signal from input carry C in to
output carry Cout requires an AND gate and an OR gate, which
constitutes two gate levels. So if there are four full adders in the
parallel adder, the output carry C5 would have 2 X 4 = 8 gate
levels from C1 to C5. For an n-bit parallel adder, there are 2n gate
levels to propagate through.
7 References
Theory of operation[edit]
A ripple-carry adder works in the same way as pencil-and-paper
methods of addition. Starting at the rightmost (least significant)
digit position, the two corresponding digits are added and a result
obtained. It is also possible that there may be a carry out of this
digit position (for example, in pencil-and-paper methods, "9+5=4,
carry 1"). Accordingly, all digit positions other than the rightmost
need to take into account the possibility of having to add an extra
1, from a carry that has come in from the next position to the
right.
This means that no digit position can have an absolutely final
value until it has been established whether or not a carry is
coming in from the right. Moreover, if the sum without a carry is 9
(in pencil-and-paper methods) or 1 (in binary arithmetic), it is not
even possible to tell whether or not a given digit position is going
to pass on a carry to the position on its left. At worst, when a
whole sequence of sums comes to ...99999999... (in decimal)
or ...11111111... (in binary), nothing can be deduced at all until
the value of the carry coming in from the right is known, and that
carry is then propagated to the left, one step at a time, as each
digit position evaluated "9+1=0, carry 1" or "1+1=0, carry 1". It
is the "rippling" of the carry from right to left that gives a ripplecarry adder its name, and its slowness. When adding 32-bit
integers, for instance, allowance has to be made for the
possibility that a carry could have to ripple through every one of
the 32 one-bit adders.
Carry lookahead depends on two things:
1. Calculating, for each digit position, whether that position is
going to propagate a carry if one comes in from the right.