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One of the important subjects of GATE Electronics and Communication Engineering Examis Digital
Circuits. The notes provided here would help you to gain an in-depth insight on Digital Circuits. All
important information is covered for each and every topic which is completely relevant for cracking GATE
Examination. So all-in-all what we have here is a set comprehensive study notes covering complete syllabus
on Digital Circuits for GATE Electronics and Communication Engineering Exam.
Here are a list of topics that will help you to kick-start with your preparation ofGATE Digital Circuits
subject:
Number Systems: A number is a collection of symbols. In a number system, there is an ordered set of
symbols known as digits. There are two types of number systems Positional number system and Nonpositional number system.
Combinatorial Circuits: A combinational logic circuit consists of logic gates whose output at any time
determined from only the present combination of inputs. It consists of input variables, logic gate and output
variables.
Sequential Circuits: In sequential logic circuit, the output is dependent upon the present inputs as well as the
past inputs and outputs. Sequential circuit is of two types namely Synchronous Sequential Circuit and
Asynchronous Sequential Circuit.
Data Converters: There are two types of data converters namely Digital to Analog Converter (DAC) and
Analog to Digital Converter (ADC). It is possible to convert the analog signal into digital and vice-versa. We
can get analog from digital through ADC and can get digital from analog through DAC.
Semiconductor Memories: Memories are used in the computer to store the data. Memories are broadly
classified as registers, primary memory and secondary memory.
8085 microprocessor: This microprocessor is an 8-bit microprocessor. It has 8 bit data bus and 16 bit address
bus and is capable of addressing 64Kb of memory. It also has 8 bit ALU 8 bit ALU that can perform 8 bit
operations.
Number Systems
Arithmetic operations using decimal numbers are quite common. However, in logical design it is necessary to
perform manipulations in the so-called binary system of numbers because of the on-off nature of the physical
devices used.
A number is a collection of symbols. In a number system, there is an ordered set of symbols known as digits.
Binary Codes: Binary codes are codes which are represented in binary system with modification from original
ones.
In general, N bits can represent up to 2N distinct values.
Conversely, to represent a range of M values, the number of bits required is
The base or radix of a number system is the number of digits present. The decimal numeral system
has a base or radix of 10, where the set of 10 symbols (digits) is {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}. The
weights are in powers of ten.
(an bn) + (an-1 bn-1) ++ (a0 b0) + (f1 b-1) + (f2 b-2) ++ (fm b-m)
where,
A base of a number system or radix defines the range of values that a digit may have.
In the binary system or base 2, there can be only two values for each digit of a number, either a 0 or
a 1.
In the octal system or base 8, there can be eight choices for each digit of a number: 0, 1, 2, 3,
4, 5, 6, 7.
In the decimal system or base 10, there are ten different values for each digit of a number: 0, 1,
2, 3, 4, 5, 6, 7, 8, 9.
Weighted Binary System: Weighted binary codes are those which obey the positional weighting
principles, each position of a number represents a specific weight. Example: Decimal, BCD, 8421,
2421, 5211, etc.
Non-weighted Codes: Non-weighted codes are codes that are not positionally weighted. That is each
position within the binary number is not assigned a fixed value. Example: Gray code, Excess 3 code,
etc.
BCD Code: In computing and electronic systems, binary-coded decimal (BCD) is an encoding for decimal
numbers in which each digit is represented by its own binary sequence.
Its main virtue is that it allows easy conversion to decimal digits for printing or display and faster
decimal calculations.
In BCD, a digit is usually represented by four bits which, in general, represent the values / digits /
characters 0-9.
To BCD-encode a decimal number using the common encoding, each decimal digit is stored in a four-bit
nibble. The position weights of the BCD code are 8, 4, 2, 1.
Thus, the BCD encoding for the number 127 would be: 0001 0010 0111
Its drawbacks are the increased complexity of circuits needed to implement mathematical operations and a
relatively inefficient encoding. It occupies more space than a pure binary representation.
Example: BCD addition for (148 + 157) = ?
When sum of 2 digits is greater than or equal to 9, then we need to add 6 i.e., 0110.
Weighted Code Number Systems:
Gray Code: This code is unweighted code. The gray code exhibits only a single bit change from one code
number to the next. This is a variable weighted code and is cyclic.
Binary to Gray Code Conversion:
1. Write down the number in binary codes.
2. The Most Significant Bit (MSB) of the gray code will be same as the MSB of binary code.
3. Perform XOR operation on MSB and next bit to the MSB in binary number.
4. Repeat step 3 till all bits of binary number have been XO Red, the resultant code is the gray code equivalent to
binary code.
Starting from left to right, add each adjacent pair of binary digits to get next andgray code digit
(discard the carry if generated).
Add each binary digit to the generated gray digit in the next adjacent position (discard the carry if
generated).
Excess-3 Code: The excess-3 is a non weighted code used to represent decimal numbers. It can be derived by
adding 3 to each decimal digit and then converting the result to four bits binary.
The code derives its name from the fact that each binary code is the corresponding 8421 code plus 0011 (3).
Example:
2421 Code
This is a weighted code, its weights are 2, 4, 2 and 1. A decimal number is represented in 4 bit form and the
total 4 bits weight is
2 + 4 + 2 + 1 = 9.
Hence, 2421 code represents the decimal numbers from 0 to 9.
Complements
Complements are used in digital computer system for simplifying the subtraction operation and for logical
manipulation.
There are two types of complements for each base r system,
1. The r s complement
2. The (r 1)s complement
The rs Complement
Given a positive number N with base r with an integer part of n digits. The rs complement of N is defined as
rn N for N 0 and 0 for N = 0.
e.g., 10s complement of (25.639)10 is (102 25.639)
100 25.639 = 74 361, here the number of digits in integer part is 2
means n = 2
The (r 1)s Complement
Given, a positive number N in base r with an integer part of n digits and a fraction part of m digits, the (r 1)s
complement of N is defined as rn rm N.
Key Points
Representation of Integers
The are three possible ways to represent a number
1. Signed magnitude method
2. Ones complement method
3. Twos complement method
Signed Magnitude Method
Number is divided into two parts, one is sign bit and other part for magnitude, In example we are using 5 bit
register to represent 6 and +6.
Range of Number For n bit register, MSB will be a sign bit and (n 1) bits will be magnitude.
Drawback of signed magnitude method is that 0 will be having 2 different representation one will be
10000 i.e., 0 and the other one will be 00000 + 0.
1s Complement Method
Positive numbers are represented in same way as in sign magnitude method. If number is negative, then it is
represented using 1s complement method. For this, we first need to represent the number with positive sign
and then take 1s complement of this number.
Example: Suppose we are using 5 bit register. The representation of 6 will be represented as below.
Drawback of 1s complement method is that there are two different representation for zero, one is 0
and other is +0.
2s Complement Method
Positive numbers are represented in same way as in sign magnitude. For representing negative number, we
take 2s complement of the corresponding positive number.
2s complement representation allows the use of binary arithmetic operations on signed integers,
yielding the current 2s complement result.
Positive Numbers: Positive 2s complement numbers are represented as the simple binary.
Negative Numbers: Negative 2s complement numbers are represented as the binary number that
when added to a positive number of the same magnitude equals zero.
Combinational Logic Circuit: A combinational logic circuit consists of logic gates whose output
is determined by the combination of current inputs.
No feedback is required.
No memory is required.
Sequential Logic Circuit: This Circuit consists of logic gates arranged in parallel and its output is determined
by the combination of the current input and the prior output. Sequential circuit also contains memory elements
that are capable to store the information of the prior output.
Logic Gates
A logic gate is an idealised or physical device implementing a Boolean function, that is, it performs a logical
operation in one or more logical inputs and produces a single logical output.
AND Gate
Properties of OR logic:
1. Commutative Law: A + B = B + A
2. Associative Law: (A + B + C) = (A + B) + C = A + (B+ C)
NAND Gate
NOR gate follows commutative law but not follow associative law
EXOR Gate
Enable input = 0
Disable input = 1
When both the inputs are different, then output becomes high or logic 1.
When both the inputs are same, then output becomes low or logic 0.
Note:
EXNOR Gate
Enable input = 1
Disable input = 0
When both the inputs are same, then output .becomes high or logic 1.
When both the inputs are different, then output becomes low or logic 0.
Boolean Algebra
1. NOT-Operation theorem:
2. AND-Operation theorem:
3. OR-Operation theorem:
4. Distribution theorem: A + BC = A (A + B)(A + C)
Note:
5. Demorgans Theorem:
6. Transposition Theorem: (A + B) (A + C) = A + BC
7. Consensus Theorem: This theorem is used to eliminate redundant term. It is applicable only when if a boolean
function contains three variables. Each variable used two times. Only one variable is complemented or
uncomplemented. Then the related terms so that complemented or uncomplemented variable is the
answer.
SOP (Sum of Product): (Minimum Term)
A sum of product expression is two or more AND functions or functions together. Each product term is known
as minimum term.
Example:
o
Example:
o
Note:
With n variables maximum possible minimum and maximum terms = 2n
With n variables maximum possible logic expression =
Duality Theorem: To convert positive logic into negative logic and vice-versa, dual function are used.
Example:
2 variable K Map:
3 variable K Map:
4 variable K Map:
Designing Combinational Circuits: The steps to design combinational circuits are as the following:
1. Understand the problem
2. Find the required number of input and output variables
3. Construct a truth table using the relationship between the input and output
4. Obtain the Boolean function or the logical expression from the truth table using Karnaugh Map.
5. Draw a logic circuit based on the obtained logical expression.
Arithmetic Circuits
Arithmetic circuits are used to perform addition and subtraction. Binary adder performs binary addition and
binary subtractor performs binary subtraction.
Classification of Adder: (i) Half Adder and (ii) Full Adder
Classification of Subtractor: (i) Half Subtractor and (ii) Full Subtractor
Half Adder: This circuit is used for addition of two one bit numbers.
Sum (S) =
Carry (C) = AB
Full Adder
A full adder is a combinational logic circuit that performs the arithmetic sum of three input bits. It consists of
three inputs and two outputs.
Sum (S) =
Carry (C0) = AB + BC + AC
Half Subtractor
It is a combinational logic circuit that subtracts two bit and produces their difference and borrow.
Difference (D)
Borrow (B0) =
Full Subtractor
It is a combinational logic circuit that performs subtraction involving three bit namely minued bit, subtrahend
bit and borrow from the previous stage
Difference (D)
Multiplexer (MUX)
It is a combinational circuit that selects binary information from one of the many input lines and
directs it to a single output line.
MUX is also called: Many to one, Data selector, Universal circuit, or Parallel data serial.
Multiplexing means transmitting a large number of information units over a smaller number of
channels or lines. It is abbreviated as MUX.
There are 2n input lines and n selection lines whose bit combinations determine which input is
selected.
m = 2n implies n = log m where m = Number of data inputs, and n = Number of select lines.
2 1 MUX :
Universal equation
Implementation of one MUX using another MUX:
Demultiplexer (DEMUX)
It is a circuit that receives information on a single line and transmits this information on one of
2n possible output lines.
The selection of a specific output line is controlled by the bit values of n selected lines.
1 2 Demux:
D0 = SI
D1 = SI
1 4 Demux:
o
o
o
o
Decoders
A decoder is a combinational circuit that converts binary information from n input lines to a
maximum 2n unique output lines.
If the n-bit decoded information has unused or dont-care combinations, the decoder output will have
fewer than 2n outputs.
The decoders presented here are n-to-m-line decoders, where m 2n. Their purpose is to generate the
2n (or fewer) minterms of n input variables.
2 4 Decoder:
Encoders
The output lines generate the binary code corresponding to the input value.
Sequential Circuits
In sequential logic circuit, the output is dependent upon the present inputs as well as the past inputs and
outputs.
Synchronous Sequential Circuit: Change in input signals can affect memory elements only upon
activation of clock signals.
Asynchronous Sequential Circuit: Change in input signals can affect memory elements at any
instant of time. These are faster than synchronous circuit.
Flip Flops:
It is a one-bit memory cell which stores the 1-bit logical data (logic 0 or logic 1).
The most commonly used application of flip flops is in the implementation of a feedback circuit.
As a memory relies on the feedback concept, flip flops can be used to design it.
In synchronous sequential circuit, Memory elements are clocked flip flops and generally edge
triggered.
In asynchronous sequential circuit, Memory elements are unclocked flip flops / time delay elements
which are generally level triggered.
Flip flop circuit is also known as bistable multivibrator or latch because it has two stable states (1
state, 0 state).
There are mainly four types of flip flops that are used in electronic circuits.
T Flip Flop
The Set-Reset (SR) flip flop is designed with the help of two NOR gates or two NAND gates.
With both S=1 and R=1, the occurrence of a clock pulse causes both outputs to momentarily go to 0. When the
pulse is removed, the state of the flip-flop is indeterminate, depending on whether the set or reset input of the
flip-flop remains a 1 longer than the transition to 0 at the end of the pulse.
Characteristic Table
Excitation Table:
JK Flip Flop
A JK flip-flop eliminates indeterminate state of the SR type. Inputs J and K behave like inputs S and R to set
and clear the flip-flop (In JK flip-flop, the letter J is for set and the letter K is for clear).
When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its complement
state. If Q=1, it switches to Q=0 and vice versa.
Characteristic Table
Excitation Table
D-Flip Flop: D flip flop is also known as Transparent latch, Delay flip flop or data flip flop. The D input goes
directly into the S (J) input and the complement of the D input goes to the R (K) input.
If D = 1, the flip-flop is switched to the set state (unless it was already set).
Truth Table
Characteristic Table
Excitation Table
T Flip Flop: The T flip-flop is a single input version of the JK flip-flop where T is connected to both J and
K inputs directly.
When T = 0, the flip flop enters into Hold mode, which means that the output, Q is kept the same as it
was before the clock edge.
When T = 1, the flip flop enters into Toggle mode, which means the output Q is negated after the
clock edge, compared to the value before the clock edge.
Truth Table
Characteristic Table
Excitation Table
The race around condition will occur in JK flip flop when J = K = 1 and tpd (FF) < tpw.
Master Slave (MS) Flip Flop: A master-slave flip-flop is constructed from two seperate flip-flops. One circuit
serves as a master and the other as a slave. Input clock is applied to master and Inverted clock applied to
slave.
In Master Slave flip flop output is changes only when slave output is changing.
The master flip-flop is enabled on the positive edge of the clock pulse and the slave flip-flop is
disabled by the inverter.
The information at the external J and K inputs is transmitted to the master flip-flop.
When the pulse returns to 0, the master flip-flop is disabled and the slave flip-flop is enabled. The
slave flip-flop then goes to the same state as the master flip-flop.
Flip Flop Conversions: The flip flop conversions are classified into different types which are:
Characteristic Table
Registers: When a group of flip flop is used to store a word (group of bits) then it is called register. To
store n bits, n flip flops are cascaded in register. If in a register, the binary information can be moved from
stage to stage, this type of registers are called shift registers. According to data movement in a register, shift
registers can be classified as
1. Serial Input Serial Output (SISO)
2. Serial Input Parallel Output (SIPO)
3. Parallel Input Serial Output (PISO)
4. Parallel Input Parallel Output (PIPO)
Serial Input Serial Output (SISIO)
In N bits SISO registers to provide N bits data, Serially in require N clock pulse, and Serially
out require (N-1) clock pulse.
To provide N-bit data: Serial in require N clock pulse, and Serial outno clock pulse require
SISO can convert serial data or temporal code to parallel or serial code.
In PIPO register for parallel input number of pulse required is 1 clock pulse.
In PIPO register for parallel output number of pulse required is 0 clock pulse.
Summary of Registers
Counter
A counter is a sequential logic circuit capable of counting the number of clock pulses arriving at its
clock input.
For a counter circuit having n flip flops, Maximum possible states (N) = 2n
MOD number is the Number of states present in a counter is known as modulus count or MOD
number.
For n-flip flops counter will have 2n different states then this counter is said MOD- 2n counter.
MOD-M Counter
MOD number indicates frequency division obtained from the last flip flops.
MOD-MN counter:
o
Input frequency = f
Classification of Counters: Based upon the applying clock pulse, counters are classified in two categories.
1. Synchronous counter
2. Asynchronous counter (ripple counter)
In asynchronous counter flip flop applied with external clock acts as LSB bit.
If all states are used then with input frequency f, then output frequency will be f/2n
Calculation of Time Period of Flip Flop: In n-bit ripple counter if propagation delay of each flip flop is
tpd(FF), then the time period of clock is given by
TCLK ntpd(FF)
Non-binary Ripple Counter: Decode counter or BCD counter is example of non-binary counter. It requires 4
flip flops.
Synchronous Counters
In this type of counter, there are no connections of first flip flop output to clock input of the next flip flop.
Ring Counter: It is a circular shift register with only flip flop being set at any particular time, all others are
cleared. It is a shift register with feedback.
Maximum Clock Frequency: If input frequency is f, then at the output of every flip flop we get
f/N frequency. In ring counter, if propagation delay of each flip flop is tpd(FF) then
TCLK tpd(FF);
Jhonson Ring Counter: Jhonson ring counter is also called as Twisted ring counter, Switch tail counter,
Creeping counter, or Mobies counter.
In n bit Jhonson counter maximum used states = 2n, unused states = 2n 2n.
If input clock frequency is f, then output frequency of each flip flop is f /2n and duty cycle is 50%.
Disadvantage of Jhonson Ring Counter: Lockout may occur. To decode each state one, two input
AND or NOR gate is used.
Data Converters
DAC and ADCs: It is possible to convert the analog signal into digital and vice-versa. We can get analog
from digital through DAC and can get digital from analog through ADC.
Digital to Analog Converter (DAC): D/A converter (also called a DAC) accepts an n-bit digital word and
produces an analog sample.
where, k = Proportionality factor, bn = 1;if nth bit of digital input is 1, bn = 0; if nth bit of digital input is 0.
Classification of DAC:
A DAC can be constructed by using a Summing Amplifier and a set of resistors R, 2R, 4R, 8R, etc as
its inputs.
The circuit consists of a reference voltage Vf , N binary-weighted resistors R, 2R, 4R, 8R, . . . , 2(N1)
R, N single-pole double-throw switches, and an op amp together with its feedback resistance Rf =
R/2.
V0 = -Rf If = -Vf D
Accuracy of the DAC depends critically on the accuracy of Reference voltage, the precision of the
binary-weighted resistors, and the perfection of the switches.
A disadvantage of the binary-weighted resistor network is that for a large number of bits (N > 4) the
spread between the smallest and largest resistances becomes quite large. This implies difficulties in
maintaining accuracy in resistor values.
Inverting Amplifier
= weight of LSB
VFS = Vr
4. Percentage Resolution
5. Maximum Error Maximum error acceptable in ADC and DAC equals to resolution.
Note: Resolution (R-2R ladder type) =
A/D converter (also called an ADC) accepts an analog sample VA and produces an N-bit digital word.
Examples of ADC usage are digital volt meters, cell phone, thermocouples, and digital oscilloscope.
Types of A/D Converters: Dual Slope A/D Converter, Successive Approximation A/D Converter,
Flash A/D Converter, Delta-Sigma A/D Converter, etc.
Conversion time (tc) is independent of the value of the analog input voltage (Va).
Functional component
It utilizes 2N -1 comparators to compare the input signal level with each of the 2N -1 possible
quantization levels.
The outputs of the comparators are processed by an encoding-logic block to provide the N bits of the
output digital word.
The following components are present in the Dual slope A/D converter:
o
Integrator
Counter
Clock
Control Logic
Comparator
Semiconductor Memories
Memory
Registers: Registers are memories located within the Central Processing Unit (CPU). Various
types of registers are available within CPU. Registers are small but CPU can access it
quickly. Some of the registers available in the system are given below.
o Instruction Register, ALU I/O registers, Status Register, Stack pointer register, Program
counter, etc.
Primary Memory: It is classified into two types, namely RAM and ROM.
Secondary Memory: Disk memory is used to hold programs and data over the longer term. The
contents of a disk are NOT lost if the power is turned off. Disks are much slower than Register.
RAM can be classified into two types, namely Static RAM and Dynamic RAM.
Access time of SRAM is less and thus these memories are faster memories.
As SRAM is consists of flip-flops thus, refreshing is not required.
Less number of memory cells are required in SRAM for unit area.
Classification of ROMs:
1. Mask programmed ROM: The required contents of the memory is programmed during fabrication. Data
stored this way can never be altered. It can be implemented using Fixed AND Fixed OR Circuit.
2. PROM (Programmable ROM): Required content is written in a permanent way by burning out internal
interconnections (fuses). It is a one-off procedure. It can be implemented using Fixed AND
Programmable OR Circuit.
3. EPROM (Erasable PROM): Data is stored as a charge on an isolated gate capacitor (floating gate).
Data is removed by exposing the PROM to the ultraviolet light.
4. EEPROM (Electrically Erasable PROM): It is also called as Flash Memory. The content can be reprogrammed by applying a suitable voltages to the EEPROM pins. The Flash Memories are very
important data storage devices for mobile applications.
PLA is implemented using AND-OR gate arrays and programmed for specific logic functions.
It is used where the number of dont care conditions are excessive.
In PLAs both AND and OR arrays are programmable.
The AND and OR gates are fixed for any PLA chip.
It depends on the number of inputs and outputs of PLA.
Combinational circuits, Sequential Circuits, Compact circuits can be implemented using PLAs.
PAL is implemented using AND gate arrays are programmable and OR gate arrays are fixed.
Because only AND gates are programmable, the PAL is easier to program, but it is not as flexible
as the PLA (programmable logic array).
8085 Microprocessor
Bit: A bit is a single binary digit.
Word: A word refers to the basic data size or bit size that can be processed by the arithmetic and logic unit of
the processor. A 16-bit binary number is called a word in a 16-bit processor.
Memory Word: The number of bits that can be stored in a register or memory element is called a memory
word.
Bus: A bus is a group of wires (lines) that carry similar information.
System Bus: The system bus is a group of wires used for communication between the microprocessor and
peripherals.
Address Bus: It carries the address, which is a unique binary pattern used to identify a memory
location or an I/O port.
Data Bus: The data bus is used to transfer data between memory and processor or between I/O device
and processor.
Control Bus: The control bus carry control signals, which consists of signals for selection of memory
or I/O device from the given address, direction of data transfer and synchronization of data transfer in
case of slow devices.
8085 Microprocessor:
It is a programmable electronics chip (Integrated Circuit (IC)). A single IC has computing and decision making
capabilities similar to central processing unit of a computer.
It is used in almost all types of electronics devices like mobile phones, printers, washing machines, etc. and
also used in advanced applications like radars, satellites and flights.
It has 8 bit data bus and 16 bit address bus, thus it is capable of addressing 64 KB of memory.
It has 8 bit ALU 8 bit ALU that can perform 8 bit operations.
Lower order address bus is multiplexed with data bus to minimize the chip size.
The 8085 microprocessor is an 8-bit processor available as a 40-pin IC package (shown the figure
below) and uses +5 V for power. It can run at a maximum frequency of 3 MHz.
The 8085 has extensions to support new interrupts, with three maskable interrupts (RST 7.5, RST 6.5
and RST 5.5), one non-maskable interrupt (TRAP) and one externally serviced interrupt (INTR).
Three control signals are available on chip: (i) RD: it is a active low signal. Which indicate that the
selected IO or Memory device is to be read and data is available on the data bus. (ii) WR: it is a active
low signal which indicate that the data on the data bus are to be written into a selected memory or IO
location. (iii) ALE: it is a +ve going pulse generated every time the 8085 begins an operation
(machine cycle), which indicate that the bits on AD7-AD0 are address bits.
Three status signals are available on chip: (i) IO/M: this is a status signal used to differentiate
between IO and Memory operations. If it is high then IO operation and If it is low then Memory
operation. (ii) S1 and S0: status signals similar to IO/M, can identify various operations that are rarely
used in the systems.
Addition, Subtraction
Increment, Decrement
Clear, etc.
ALU includes the accumulator, the temporary register, the arithmetic and logic circuits and flags. It
always stores result of operations in Accumulator.
It provides status, control and timing signals, which are required for the operation of memory and I/O
devices.
8085 System Bus: Microprocessor communicates with memory and other devices (input and output)
using three buses: Address Bus, Data Bus and Control Bus.
Address Bus: The Address bus consists of 16 wires. The size of the address bus determines the size of
memory, which can be used. To communicate with memory the microprocessor sends an address on
the address bus to the memory. Address bus is unidirectional, i.e., numbers only sent from
microprocessor to memory.
Data Bus: Bus is bidirectional. Size of the data bus determines what arithmetic can be done. Data bus
also carries instructions from memory to the microprocessor.
Memory size = 2A x D where, A denotes the address lines, and D denotes the data lines.
Control Bus: Control bus are various lines which have specific functions for coordinating and
controlling P operations. The control bus carries control signals partly unidirectional, partly
bidirectional. Control signals are things like read or write.
Registers:
8085 has six general purpose registers to store 8 bit data, these are identified as B, C, D, E, H and L. They can
be combined as register pairs BC, DE and HL to perform some 16 bit operations.
Accumulator: The accumulator is an 8 bit register included as a part of Arithmetic Logic Unit (ALU).
This register is used to store 8 bit data and to perform arithmetic and logical operations. The result of
an operation is stored in the accumulator.
Flag Register: The ALU includes five flip-flops. They are called Zero (Z), Carry (CY), Sign (S),
Parity (P) and Auxiliary Carry (AC) flags. The microprocessor uses these flags to test data
conditions. The conditions (set or reset) of the flags are tested through the software instructions. The
combination of the flag register and the accumulator is called Program Status Word (PSW) and PSW
is the 16-bit unit for stack operation.
Program Counter (PC): This 16 bit register deals with sequencing the execution of instruction. The
microprocessor uses this register to sequence the execution of the instructions. The function of the
program counter is to point to the memory address from which the next byte is to be fetched.
Stack Pointer (SP): The stack pointer is also a 16 bit register used as a memory pointer. It points to a
memory location in read-write memory, called the stack.
Instruction Register/Decoder: Temporary store for the current instructions of a program. Latest
instruction sent here from memory prior to execution. Decoder then takes instruction and decodes or
interprets the instruction. Decoded instruction then passed to next stage.
Memory Address Register: Holds address, received from PC of next program instruction.
Control Generator: It generates signal within P to carry out the instructions which have been
decoded.
Register Selector: This block controls the use of the register stack.
General Purpose Registers: P requires extra registers for versatility. It can be used to store
additional data during a program.
Operations of Microprocessor:
The microprocessor performs the following four operations using address bus, data bus and control bus:
One-Byte Instructions: A 1-byte instruction includes the opcode and operand in the same byte.
Operands are internal registers and are coded into the instruction.
Two-Byte Instructions: In a two-byte instruction, the first byte specifies the operation code and the
second byte specifies the operand. Source operand is a data byte immediately following the opcode.
Three-Byte Instructions: In a three byte instruction, the first byte specifies the opcode and the
following two bytes specify the 16-bit address. Note that, the second byte is the low-order address and
the third byte is the high-order address.
Immediate Addressing:
Example: MVI A, 12 H
Register Addressing:
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Example: MOV B, C
Direct Addressing:
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Used to accept data from outside devices to store in the accumulator or send the data stored in
the accumulator to the outside device.
Indirect Addressing:
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Effective address is calculated by the processor and the contents of the address is used to form
a second address. The second address is where the data is stored.
Implicit addressing:
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In this addressing mode the data itself specifies the data to be operated upon.
These instructions are used to transfer data from one register to another register, from memory to
register or register to memory.
When an instruction of data transfer group is executed, data is transferred from the source to the
destination without altering the contents of the source.
2. Arithmetic instructions:
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These instructions are used to perform arithmetic operations such as addition, subtraction, increment
or decrement of the content of a register or memory.
Examples: ADD, ADC, ADI, DAD, SUB, INR and DCR etc.
3. Logical instructions:
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These instructions are used to perform logical operations such as AND, OR, compare, rotate etc.
Examples: ANA, ANI, ORA, ORI, XRA, CMA, CMC, STC, CMP, RLC, RAL and RAR etc.
4. Branching Instructions:
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These instructions are used to perform conditional and unconditional jump, subroutine call and return,
and restart.
Examples: JZ, JNZ, JC, JNC, JP, JM, JPE, JPO, CALL, RET and RST etc.
The microprocessor operations related to data manipulation can be summarized in four functions:
copying data, performing arithmetic operations, performing logical operations, testing for a given
condition and alerting the program sequence.
Example-1: Write 8085 assembly program for multiplying two 8 bit numbers.
JNZ LOOP
HLT; Halt
Example-2: Writh 8085 assembly program to find the largest number in an array of data.
LXI H, 1000; Load the address of the first element of the array in HL pair
LOOP: INX H
AHEAD: DCR B
HLT
Programmed I/O (PIO): It is fairly easy to implement, but requires the processor to constantly read
or write a single memory word (8-bits, 16-bits or 32-bits, depending on the device interface) until the
data transfer is complete. Although PIO is not necessarily slower than DMA, it does consume more
processor cycles and can be detrimental in a multi-processing environment.
DMA: It allows a system to issue an I/O command to a device, initiate a DMA transaction and then
place the process in a waiting queue. The system can now continue by selecting another process for
execution, thereby utilizing the CPU cycles typically lost when using PIO. The DMA controller will
inform the system when its current operation has been completed by issuing an interrupt signal.
Although the data is still transferred 1 memory unit at a time from the device, the transfer to main
memory now circumvents the CPU because the DMA controller can directly access the memory unit.
Device wishing to perform DMA asserts the processors bus request signal.
Processor completes the current bus cycle and then asserts the bus grant signal to the device.
The processor senses in the change in the state of bus grant ack signal and starts listening to the data
and address bus for DMA activity.
The DMA device performs the transfer from the source to destination address.
During these transfers, the processor monitors the addresses on the bus and checks if any location
modified during DMA operations is cached in the processor. If the processor detects a cached address
on the bus, it can take one of the two actions:
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Processor invalidates the internal cache entry for the address involved in DMA write
operation
Once the DMA operations have been completed, the device releases the bus by asserting the bus
release signal.
Processor acknowledges the bus release and resumes its bus cycles from the point it left off.
The 8085 microprocessor has two pins available for DMA mode of I/O communication:HOLD (Hold) and
HLDA (Hold Acknowledge).
HOLD: This is an active high input signal to the 8085 from another master requesting the use of the
address and data buses. After receiving the HOLD request, the Microprocessor relinquishes the buses
in the following machine cycle. All buses are tri-stated and a Hold Acknowledge signal is sent out.
The Microprocessor regains the control of buses after HOLD goes low.
HLDA: This is an active high output signal indicating that the MPU is relinquishing the control of the
buses. Typically, an external peripheral such as DMA controller sends a request a high signal to the
HOLD pin. The processor completes the execution of the current machine cycle; floats (high
impedance state) the address, the data, and the control lines; and sends the Hold Acknowledge
(HLDA) signal. The DMA controller takes control of the buses and transfers data directly between
source and destination, thus bypassing the microprocessor. At the end of data transfer, the controller
terminates the request by sending a low signal to the HOLD pin, and the microprocessor regains
control of the buses.