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CONTENTS
+ 0 ) 2 6 - 4
Learning Objectives
DC Load Line
Q-Point and Maximum
Undistorted Output
Need for Biasing a Transistor
Factor Affecting Bias
Variations
Stability Factor
#&
LOAD LINES
AND DC BIAS
CIRCUITS
Beta Sensitivity
Stability Factor for CB and
CE Circuits
Different Methods for Transistor Biasing
Base Bias
Base Bias with Emitter
Feedback
Base Bias with Collector
Feedback
Base Bias with Collector
and Emitter Feedbacks
Emitter Bias with two Supplies
Voltage Divider Bias
Load Line and Output
Characteristics
AC Load Line
CONTENTS
CONTENTS
2220
Electrical Technology
VCC = I C RL +VCE
IC =
VCC VCE
RL RL
VCC B
RL
IC
Active
Region
D
Cut-off
C
A
VCE
VCC
Fig. 58.1
VCE VCC
+
RL RL
Active Region
All operating points (like C, D, E etc. in Fig. 58.1) lying between cut-off and saturation points
form the active region of the transistor. In this region, E/B junction is forward-biased and C/B
junction is reverse-biasedconditions necessary for the proper operation of a transistor.
Quiescent Point
It is a point on the dc load line, which represents the values of IC and V CE that exist in a transistor
circuit when no input signal is applied.
It is also known as the dc operating point or working point. The best position for this point is
midway between cut-off and saturation points where V CE = 12 V CC (like
VCC = 20 V
VEE = 30
point D in Fig. 58.1).
mA
IC
IE
RE = 15 K
4B
RL 5 K
IC 3
Q-POINT
2
1
IB
VCB
0
0
(a)
10
(b)
Fig. 58.2
A
15 20
VCB
2221
The line A B represents the load line for the given circuit. We will now find the actual operating
point.
IE = V EE /R E= 30 V/15 K = 2 mA
neglecting V BE
IC = IE IE = 2 mA;
V CB = V CC IC R L = 20 2 5 = 10 V
Hence, Q-point is located at (10 V ; 2 mA) as shown in Fig. 58.2 (b)
Example 58.2. In the CB circuit of Fig. 8.3 (a), find
(a) dc operating point and dc load line
(b) maximum peak-to-peak unclipped signal
(c) the approximate value of ac source voltage that will cause clipping.
(Electronics and Telecom Engg. Jadavpur Univ.)
Solution.
20 V
10 V
VCC
(a) IC(sat) = R
= 2 mA
IC
IC
IE
L
mA
point B
RE 20 K
10 K RL 2.0 B
V CB at cut-off
=V CC = 20 V
1.5
point A
Hence,
AB
is
the
dc
load line
1.0
RS 1K
and
is
shown
in
Fig.
58.3
(b).
Q
0.5
VCB
Now, IE =10/20 = 0.5 mA
VS
A
IC IE = 0.5 mA
0
5 10 15 20 V
CB
VCB
= V CC IC R L
= 20 0.5 10
(b)
(a)
=15
V
Fig. 58.3
The Q-point is located at (15 V, 0.5 mA)
(b) It is obvious from Fig. 58.3 (b) that maximum positive swing can be from 15 V to 20 V i.e.
5 V only. Of course, on the negative swing, the output swing can go from 15 V down to zero volt.
The limiting factor being cut-off on positive half-cycle, hence maximum unclipped peak-to-peak
voltage that we can get from this circuit is 2 5 = 10 V.
(c) The approximate voltage gain of the above circuit is
V R 10 K
= 10
Av = 0 = L =
VS RS 1K
It means that signal voltage will be amplified 10 times. Hence, maximum value of source
voltage for obtaining unclipped or undistorted output is
V 10 V p p
_
= 1Vp p
Vs = 0 =
VCC 30 V
10
10
mA B
IC
6
Example 58.3. For the CE circuit IB
K
5
R
L
shown in Fig. 58.4 (a), draw the dc load R
B 1.5 M
IC 4
line and mark the dc working point on it.
Assume b=100 and neglect V.
Q
2
(Applied Electronics, Punjab Univ.)
VCE
Solution. Cut-off point A is located
A
IE
where, IC = 0 and V CE = V CC = 30 V. Satura0
V
30
25
20
15
10
5
tion point B is given where V CE = 0 and
VCE
IC(sat) = 30 V/5 K = 6 mA.
(b)
(a)
Line AB represents the load line in Fig. 58.4
Fig. 58.4
(b).
2222
Electrical Technology
Let us find the dc working point from the given values of resistances and supply voltage.
IB = 30 V/1.5 M = 20 A;
IC = IB =100 20 = 2000 A = 2 mA ;
VC = V CC IC R L = 30 2 5 = 20 V
Hence, Qpoint is (20 V ; 2 mA) as shown in Fig. 58.4.
IC
IC
Saturation
I C(sat)
Q2
Cut-Off
Q1
0
0 VCE
A
B
(a)
VCE
I CQ
Q3
VCEQ
VCE
A
B
B
(b)
(c)
Fig. 58.5
If the Q-point Q2 is located near saturation point, then clipping first starts at point B as shown
in Fig. 58.5 (b). It is caused by saturation. The maximum negative swing = V CEQ.
In Fig. 58.5 (c), the Q-point Q3 is located at the centre of the load line. In this condition, we get
the maximum possible output signal. The point Q3 gives the optimum Q-point. The maximum
undistorted signal = 2VCEQ.
In general, consider the case shown in Fig. 58.6. Since I C
A < B, maximum possible peak-to-peak output signal = 2 A.
If the operating point were so located that A > B, then maxiQ
mum possible peak-to-peak output signal = 2B.
When operating point is located at the centre of the load
line, then maximum undistorted peak-to-peak signal is = 2 A
= 2 B = V CC = 2 V CEQ.
Under optimum working conditions corresponding to Fig.
0
58.5 (c), ICQ is half the saturation value given by V CC/R L (Art. 8.1).
VCE
B
A
1 VCC VCC
=
I CQ = .
Fig. 58.6
2 RL 2 R
Example 58.4. Determine the value of RB required to adjust the circuit of Fig. 58.7 to optimum operating point. Take = 50 and VBE = 0.7 V.
Solution. As seen from above
V
20
=1mA
ICQ = CC =
2 RL 2 10
The corresponding base current is
ICQ 1
= = 2 A
I BQ =
50
2223
RB =
VCC
RB
20V
RL 10K
C
Vout
2
For normal operation of a transistor amplifier
circuit, it is essential that there should be a
C1
RS
(a) forward bias on the emitter-base junction and
(b) reverse bias on the collector-base junction.
VS
In addition, amount of bias required is important for establishing the Q-point which is dictated by the mode of operation desired.
Fig. 58.7
If the transistor is not biased correctly, it would
1. work inefficiently and
2. produce distortion in the output signal.
It is desirable that once selected, the Q-point should remain stable i.e. should not shift its
position due to temperature rise etc. Unfortunately, this does not happen in practice unless special
efforts are made for the purpose.
and IB constant
dICO
Larger the value of S, greater the thermal instability and vice versa (in view of the above, this
factor should, more appropriately, be called instability factor !).
The stability factor may be alternatively expressed by using the well-known equation IC = I +
(I + ) ICO which, on differentiation with respect to IC, yields.
dI
1
(1 +)
dI
dI
I = B + (1 + ) CO = B + (1 +)
S=
1(dI B / dIC )
dIC
dIC
dI C
S
The stability factor of any circuit can be found by using the general formula
1+ RB / RE
S=
1+ (1 ) ( RB / RE )
2224
where
Electrical Technology
R B = total series parallel resistance in the base
R E = total series dc resistance in the emitter
= dc alpha of the transistor
IC
IC dI B
Obviously, K is dimensionless ratio and can have values ranging from zero to unity.
I C = I E + I CO
dIC
=0 + 1
dI CO
or
S =1
(ii) CE Circuit
IC = IB + (1 + ) ICO
dIC
= (1 + )
dICO
treating IB as a constant
S = (1 + ).
If = 100, then S = 101 which means that IC changes 101 times as much as ICO.
2225
+VCC
IC ( sat ) = CC
RE + RL
2. IC can be found as follows :
Consider the supply, base, emitter and ground route. Applying Kirchhoff
s Voltage Law, we have
I B RB VBE I E RE + VCC = 0
or
V CC = IB R B + V BE + IER E
IE IC
Now
IB = IC/ and
Substituting these values in the above equation, we have
I R
VCC C B + VBE + I C RE
S=
VCE
IE
RE
VE
VC
...(i)
IC
5.
RL
Fig. 58.8
VCC VBE
VCC
RE + RB /
RE + RB /
(we could have applied the -rule given in Art. 57.24)
3. collector-to-ground voltage
V C = VCC ICR L
4. emitter-to-ground voltage
V E = IER E ICR E
IC
neglecting VBE
1 + RB / RE
1 + RB / RE
=
1+ RB /(1+) RE 1+ RB / R
1
1 + RE / RB
Example 58.5. For the circuit shown in Fig. 58.9, find
(i) IC(sat) , (ii) IC , (iii) VC , (iv) V E, (v) V CE and (vi) K .
6. The -sensitivity of this circuit is K =
VCC =30V
IC
R
RL 2K
B 300K
V
30
= 10 mA
IC ( sat ) = CC =
Solution. (i)
RE + RL 1+ 2
VCE
=100
VCC
30
=
= 7.5 mA
(ii)
actual IC
VC
IE
RE + RB / 1+ 300 /100
V
(iii)
V C = V CC IC R L = 30 2 7.5 = 15 V
1K RE E
(iv)
V E IE R E IC R E = 7.5 1 = 7.5 V
(v)
V CE = V C V E = 15 7.5 = 7.5 V
Fig. 58.9
1
=
K =
(vi)
1 + 100 1/ 300 0.75
Example 58.6. The base-biased transistor circuit of Fig. 58.10 is subjected to increase in
junction temperature from 25C to 75C. If increases from 100 to 150 with rising temperature,
calculate the percentage change in Q-point values (IC, VCE ) over the temperature range. Assume
that VBE remains constant at 0.7 V.
Solution. At 25C
IB =
2226
Electrical Technology
IC = IB = 100 0.113 = 11.3 mA
+12V
VCC
IC
RC 500
RB
At 25
IB = 0.113 mA
=100-150
100K
Fig. 58.10
16.95 11.3
100 = 50 (increase)
11.3
3.52 6.35
100 = 44.57 (decrease)
6.35
It is seen that Q-point is very much dependent on temperature and makes the base-bias
arrangement very unstable.
% VCE =
VCC
(I C+ I B)
RB
IB
RL
IC
VCE
+
VBE
_
Fig. 58.11
IC
. RB + VBE VCC I C RL
IC =
VCC VBE
VCC
RL + RB / RL + RB /
This is also the approximate value of IE (again, we could take the help of -rule). The sensitivity factor is given by
I
1
K =
= 1 C
I C ( sat )
RL / RB
S=
VCC
1 + RB / RL
1+ RB /(1+) RL RL + RB /
Example 58.7. In Fig. 58.11, VCC =12 V, VBE = 0.7 V, RL = 1K, RB = 100K, = 100.
Find (i) IC , (ii) VCE , (iii) IB ,(iv) K and (v) S.
2227
(i)
IC I E =
12 0.7
= 5.6 mA
1 + 100 /100
(ii)
V CE 12 (5.65 1) = 6.35 V
(iv)
KB =
1
= 0.5
1 + 100 1/100
+VCC
(I C+ IB)
RL
RB
VCE
VC
VCC VBE
RE + RL + RB /
RE
RL VCC I C RL
VE
IE
IC
IB
Fig. 58.12
VE = I E RE IC RE ; V CE = VC VE
VCE VCC I C ( RL + RE )
S=
1 + RB /( RE + RL )
1 + RB / ( RE + RL )
1
IC
It can be proved that K = 1 +( R + R ) / R =1 I
E
L
B
C ( sat )
Obviously, K will be degraded with increase in R B.
15V
K =
1
= 0.2
1 +100(10 +10) / 50
or
K = 1 IC /IC(sat) = 1 0.6/0.75=0.2
Obviously, K will be degraded with increase in R B .
IC
RL
RB
10 K
500 K
VCE
=100
10 K
RE
Fig. 58.13
2228
Electrical Technology
+
V
If
V
V
and
R
R
/,
I
=
V
/R
.
EE
BE
E
B
E
EE
B
R B _ BE
RE
If V E is the emitter to ground voltage, then
IE
IB R B V BE V E = 0
VEE
or V E = (IBR B + V BE) = (V BE + IC R B /) V BE
Fig. 58.14
1 + RB / RE
1
KB =
For this circuit, S =
and
1+ RB / RE
1 +RE / RB
Example 58.9. For the circuit of Fig. 58.15, find (i) IE , (ii) IC , (iii) VC , (iv) V E , (v) VCE ,
(vi) stability factor and (vii) K for a of 50. Take VBE = 0.7 V.
(Electronics-II, Bangalore Univ. 1995)
Solution. (i) I E =
10 0.7
VEE VBE
=
= 0.46 mA
RE + RB / 20 +10 / 50
(ii) IC IE = 0.46 mA
(iii) VC = V CC IC R L = 20 0.46 10 = 15.4 V
(iv) V E = (V BE + IC R B /)
= (0.7 + 0.46 10/50) = 0.8 V
(v) VCE= V C V E= 15.4 ( 0.8) = 16.2 V
(vi)
S=
(vii) K =
1 + RB / RE
1 + 10 / 20
= 1.485
=
1 + RB / RB 1 + 10 / 50 20
Fig. 58.15
1
1
=
00.01
1 + R E / R 1 + 50 20 /10
RE
RE
RE
Also, V C = V CC ICR L
* It is also known as Universal Bias Stabilization Circuit.
+VCC
RL
R1
VCE
+ V
R2 V2 BE
_
RE
IE
Fig. 58.16
VC
VE
2229
V CE = V C V E = V CC ICR L IER E
V CC IC (R L + R E) IC IE
VCC
As before,
IC(sat)
RL + RE
It is seen from above calculations that value of was never used anywhere. The base voltage
is set by V CC and R 1 and R 2. The dc bias circuit is independent of transistor . That is why it is such a
very popular bias circuit.
1
K =
1 +RE /( R1 || R2 )
S=
1 + ( R1 || R2 ) / Re
1 + ( R1 || R2 ) /(1 + ) RE
1 + ( R1 || R2 ) / RE
1 + ( R1 || R2 ) / RE
+VCC
+VCC
IC
B
R2
RL
R1
R1
V2 =Vth
A
R th
R2
I B R B
Rth
VBB
Vth
(a)
(b)
+
VBE _ I E
RE
(c)
Fig. 58.17
Vth = V2 = VCC .
R2
R1 + R2
and
Rth = R1 || R2 =
R1 R2
( R1 + R2 )
The original circuit is reduced to that shown in Fig. 58.17 (c) where V th = V BB ;. R th = R B.
Now, applying K V L to the base-emitter loop, we get
V B B IB R B V BE IER E = 0
Substituting the value of IE = (1 + ) IB in (i) above, we get
VBB VBE
IB =
RB + (1+) RE
However, if we substitute the value of IB = IE /(1 + ), we
get
VBB VBE
IE =
RE + RB /(1+)
V CE = V CC ICR L IER E V CC IC(R L + R E)
Fig. 58.18
The above results could also be obtained directly by applying -rule (Art. 58.12)
Using -rule
As per -rule (Art. 58.12) when R E is transferred to the base circuit, it becomes (1 + ) R E and
is in parallel with R 2 as shown in Fig. 8.18. Now, V CC drops over R 1 and R 2 || (1 + ) R E
2230
Electrical Technology
R2 || (1+) RE
R1 + R2 ||(1+) RE
V E = V B V BE ; IE = V E/R E
VB =VCC
and so on.
20 V
IC
2K
14 K
Solution.
VCE
VCC
20
(a) IC ( sat ) = R + R = 2 + 6 = 2.5 mA
L
E
(b) IC IE V 2 /R E = 6/6 = 1 mA
(c) V CE = V CC IC (R L + R E) = 20 1 (2 + 6) = 12 V
V2
6K
6K
Fig. 58.19
1
K =
= 0.0138
1 + 50 6 / 4.2
20 V
20 V
IC
4K
4K
100 K
R B=20 K
25 K
V BB=4 V
6K
IC ( sat ) =
6K
IE
(b)
(a)
VCC
20
=
= 2 mA
RL + RE 4 + 6
R2
25
= 20
=4 V
R1 + R2
125
4 0.3
V V
= 0.62mA
I E = 2 BE =
6
RE
Fig. 58.20
I C = I B = 50 11.3
= 0.565 mA
IE = (1 + IB
= 576 A
= 0.576 mA
10
13.8
15
VCE
20V
14.3
15
10
VCE
(b)
(a)
Fig. 58.21
2231
Fig. 58.22
Fig. 58.23
10 0.7
V V
= 20A
I B = CC BE =
Actual
470
RB
IC = IB =100 20 = 2000 A = 2 mA
VCE= V CC IC R L = 10 2 2 = 6 V
This locates the Q-point in Fig. 58.23.
Suposse an ac input signal voltage injects a sinusoidal base current of peak value 10 A into
the circuit of Fig. 58.22. Obviously, it will swing the operating or Q-point up and down along the
load line.
When positive half-cycle of IB is applied, the Q-point shifts to point C which lies on the
(20 + 10) = 30 mA line.
Similarly, during negative half-cycle of input base current, Q-point shifts to point D which lies
on the (20 10) = 10 A line.
By measurement, at point C, IC = 2.9 mA. Hence, V CE = 10 2 2.9 = 4.2 V
Similarly, at point D, IC measures 1.1 A.Hence, V CE = 10 2 1.1 = 7.8 V
It is seen that V CE decreases from 6 V to 4.2 V i.e. by a peak value of (6-4.2) = 1.8 V when base
current goes positive. On the other hand, V CE increases from 6 V to 7.8 V i.e. by a peak value of
(7.8 6) = 1.8 V when input base current signal goes negative. Since changes in V CE represent
changes in output voltage, it means that when input signal is applied, IB varies according to the signal
2232
Electrical Technology
2233
V2 = 20 4/(4 + 16) = 4 V
VCC= 20 V mA
If we neglect V BE , V2= V E ; IE ,
ac Load Line
3 K RL
5.13
R1 16 K
VE V2 4
C2
dc Load Line
=
=
IE =
4B
RE RE 2
C1
IC
= 2 mA
I CQ
Q
2
Also, IC IE = 2 mA.
Hence, ICQ = 2 mA
VCEG
R2 4 K V2 R 2 K V
v
16 A
E
E
The corresponding value S
0
20 V
15
10
5
of V CEQ can be found by drawVCE
ing dotted line in Fig. 58.25 (b)
(b)
(a)
or may be calculated as
Fig.
58.25
under :
AC Load Line
Cut-off pont,
V CE(cut-off) = V CEQ + ICQ R ac
Now, for the given circuit, ac load resistance is R ac = R C = 3K
Cut-off point = 10 + 2 3 = 16 V [Fig. 58.25 (b)].
VCEQ
10
Saturation point, I c( sat ) = I CQ + R = 2 + 3 = 5.13mA
ac
Hence, line joining 16-V point and 5.13 mA point gives ac load line as shown in Fig. 58.25 (b).
As expected, this line passes through the Q-point.
Now, ICQ. R ac = 2 3 = 6 V and V CEQ = 10 V. Taking the smaller quantity, maximum peak output
signal = 6 V. Hence, peak-to-peak value = 2 6 = 12 V.
Example 58.13. Find the
mA
dc and ac load lines for CE cir7
cuit shown in Fig. 58.26 (a).
6
Solution. The given circuit
5
VCC= 20V
is identical to that shown in Fig.
IC
4
58.25 (a) except for the addition R1 16 K 3 K RL C
of 6-K resistor. This makes R A C
3
vout
= 3 K || 6 K = 2 K because col6K
2
lector feeds these two resistors
R2
1
in parallel. The dc loadline
V2 RE
VE
would remain unaffected. 4 K
2K
0
Change would occur only in the
ac load line.
(a)
AC Load Line
V CE(cut-off) = V CEO + ICQR ac =
Fig. 58.26
10 + 2 2 = 14 V
IC(sat) = ICO + V CEO/R ac = 2 + 10/2 = 7 mA
Q
14
5
10
15
VCE
20 V
(b)
Example 58.14. Draw the dc and ac load lines for the CB circuit shown in Fig. 58.27 (a).
Which swing starts clipping first ?
Solution. The dc load line passes through cut-off point of 30 V and saturation point of V CC/R L
= 1 mA.
Now, IE 20/40 = 0.5 mA ; IC IE = 0.5 mA; ICQ = 0.5 mA
V CB = V CC ICR C = 30 0.5 30 = 15 V ; V CBQ = 15 V
2234
Electrical Technology
VEE -20V 30V VCC
RE
mA
1.5
40K 30K RC
IC
1.0
C2
vS
0.5
30K
5 10
15
20
VCB
(a)
22.5
C1
25 30V
(b)
Fig. 58.27
Hence, dc operating point or Q-point is (15 V, 0.5 mA) as shown in Fig. 58.27 (b).
The cut-off point for ac load line is = V CBQ + ICQ R A C
Since collector sees an ac load of two 30 K resistors in parallel, hence R ac = 30 K || 30 K
=15 K.
VCBQ + ICQ R ac=15 + 0.5 15 = 22.5 V
Saturation current for ac line is = ICQ + V CBQ/R ac = 0.5 + 15/15 = 1.5 mA
The line joining these two points (and also passing through Q) gives the ac load line as shown
in Fig. 58.27 (b).
Note. Knowing ac cut-off point and Q-point, we can draw the ac load line. Hence, we need not find the
value of saturation current for this purpose.
As seen, positive swing starts clipping first because ICQ R ac is less than V CBQ. Obviously, maximum peak-to-peak signal that can be obtained from this circuit = 2 7.5 = 15 V.
Example. 58.15. For the circuit shown in Fig. 58.27 (a), find the approximate value of source
voltage us that will cause clipping. The voltage source has an internal resistance of 1 K.
Solution. As found out in Ex. 58.14, the maximum swing of the unclipped output = 2 7.5 =
15 V.
Now,
Vout Rac 15
=
= = 15
Vs
RS 1
15V p p
V
= 1Vp-p
VS = out =
15
A
A =
[10 V, 2 mA]
3. What is the maximum peak-to-peak signal that can be obtained from the circuit of Fig. 58.30 ?
[20 Vpp]
4. Find the value of maximum peak-to-peak output of signal that can be obtained from the circuit of Fig.
58.31.
[10 Vpp]
20V
5K
20V
-25V
50K
30V
-10V
10K
30V
20K RC
10K
5K
RL
VCB
2235
50K
RE
20K
30K
-15V
Fig. 58.28
Fig. 58.29
Fig. 58.30
Fig. 58.31
OBJECTIVE TESTS 58
1. The dc load line of a transistor circuit
(a) has a negative slope
(b) is a curved line
(c) gives graphic relation between IC and
IB
(d) does not contain the Q-point.
2. The positive swing of the output signal in a
transistor circuit starts clipping first when Qpoint of the circuit moves
(a) to the centre of the load line
(b) two-third way up the load line
(c) towards the saturation point
(d) towards the cut-off point.
3. To avoid thermal run away in the design of
analog circuit, the operating point of the BJT
should be such that it satisfies the condition
(a) V CE = 1/2 V CC
(b) V CE < 1/2 V CC
(c) V CE > 1/2 V CC
(d) V CE < 0.78 V CC
4. In the case of a BJT amplifier, bias stability is
achieved by
(a) keeping the base current constant
(b) changing the base current in order to
keep the IC and V CB constant
(c) keeping the temperature constant
(d) keeping the temperature and the base
current constant
5. For a transistor amplifier with self-biasing
network, the following components are
used :
R 1 = 4 k , R 2 = 4 k and R E = 1 k
the approximate value of the stability
factor S will be
6.
7.
8.
9.
10.
(a) 4
(b) 3
(c) 2
(d) 1.5
A transistor circuit employing base bias with
collector feedback has greater stability than
the one without feedback because
(a) IC decrease in magnitude
(b) V BE is decreased
(c) of negative feedback effect
(d) IC becomes independent of .
The universal bias stabilization circuit is most
popular because
(a) I C does not depend on transistor
characteristics
(b) its -sensitivity is high
(c) voltage divider is heavily loaded by
transistor base
(d) IC equals IE.
Improper biasing of a transistor circuit leads
to
(a) excessive heat production at collector
terminal
(b) distortion in output signal
(c) faulty location of load line
(d) heavy loading of emitter terminal.
The negative output swing in a transistor circuit starts clipping first when Q-point
(a) has optimum value
(b) is near saturation point
(c) is near cut-off point
(d) is in the active region of the load line.
When a BJT is employed as an amplifier, it
operates
2236
Electrical Technology
(a) in cut-off
(b) in saturation
(c) well into saturation
(d) over the active region.
11. Which of the following method used for biasing a BJT in integrated circuits is considered
independent of transistor beta?
(a) fixed biasing
(b) voltage divider bias
(c) collector feedback bias
(d) base bias with collector feedback.
12. The voltage V 0 of the circuit shown in Fig.
58.32 is,
(a) 5.1 V
(b) 3.1 V
(c) 2.5 V
(d) zero
13. The collector voltage V C of the circuit shown
in Fig. 58.33, is approximately
(a) 2 V
(b) 4.6 V
(c) 9.6
(d) 8.6 V
+ 10 V
2k
+5 V
20 k
VC
2W
Vo
C
20 k
5W
4.3 k
B
E
Fig. 58.33
Fig. 58.32
ANSWERS
1.
7.
13.
(a)
(a)
(a)
2.
8.
(d)
(b)
3.
9.
(c)
(b)
4. (a)
10. (d)
5.
11.
(b)
(b)
6.
12.
(b)
(d)
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