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Volume 1: Design and Synthesis
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
ISO
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and 9001:2008
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service Registered
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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Chapter 2.
Chapter 3.
Chapter 4.
Chapter 5.
Chapter 6.
Chapter 7.
Chapter 8.
Chapter 9.
Qsys Interconnect
Revised:
May 2013
Part Number: QII51021-13.0.0
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iv
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
The Quartus II software organizes and manages the elements of your design within a
project. The project encapsulates information about your design hierarchy, libraries,
constraints, and project settings. Click File > New Project Wizard to quickly create a
new project and specify basic project settings.
When you open a project, a unified GUI displays integrated project information. The
Project Navigator allows you to view and edit the elements of your project. The
Messages window lists important information about project processing.
You can save multiple revisions of your project to experiment with settings that
achieve your design goals. Quartus II projects support team-based, distributed work
flows and a scripting interface.
Quick Start
To quickly create a project and specify basic settings, click File > New Project Wizard.
Figure 11. Quick Project Setup with New Project Wizard
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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12
Stores
Click to Access
File Format(s)
Project file
Project settings
Assignments>Settings
Assignments>Device
Assignments>Assignment Editor
Project database
Compilation results
Project>Export Database
Project>Export Design Partition
Project > Clean Project
Timing constraints
Clock properties,
exceptions, setup/hold time
Tools>TimeQuest Timing
Analyzer
View>Project Navigator
File>New
Programming files
Device programming
options and information
Assignments>Settings
Tools>Programmer
Project libraries
Assignments>Settings
View>Project Navigator
Tools>Qsys
Project>Upgrade IP Components
Tools>MegaWizard Plug-In
Manager
Archive files
Project>Archive Project
IP files
13
Figure 12. Basic Project Directory (Gray Files and Directories Optional)
<Quartus II Project Directory>
<project_name>. qpf - Quartus II Project file
<revision_name>.bsf - represents design in schematics
<revision_name>.qsf - stores revisions project settings and constraints
<revision_name>_assignments_default.qdf- stores default project settings and constraints
<revision_name>.sdc - stores timing constraints in Synopsys Design Constraints format
<logic_design_file>. v or .vhd - RTL source code
<Qsys_system_name>.qsys - Qsys system file
<logic_design_file>.vqm - logic from EDA synthesis tool
<instance name> - QII IP synthesis files
<instance name>_sim - QII IP simulation files
<Qsys_system_name> - Qsys system and IP files
simulation - EDA simulation files
symbols - EDA board-level symbol tool files
board - EDA board-level signal integrity tool files
timing - EDA board-level timing analysis tool files
View and modify the design hierarchy (right-click > Set as Top-Level Entity)
View and update logic design files and constraint files (right-click > Open)
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Fitter reports
h Refer to the List of Compilation Reports in Quartus II Help for a complete list.
Analyze the detailed project information in these reports to determine correct
implementation. Right-click report data to locate and edit the source in project files.
Figure 14. Report Panel
15
Suppressing Messages
Suppress display of unimportant messages so they do not obscure valid messages.
Right-click messages and choose any of the following:
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Create a Symbol File for Current File for display in schematic editors
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Placement constraints
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Create a unique revision to optimize a design for different criteria, such as by area
in one revision and by fMAX in another revision. When you create a new revision
the default Quartus II settings initially apply.
You create, delete, specify current, and compare revisions in the Revisions dialog box.
Each time you create a new project revision, the Quartus II software creates a new .qsf
using the revision name.
To compare each revisions synthesis, fitting, and timing analysis results side-by-side,
click Project > Revisions and then click Compare.
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In addition to viewing the compilation results of each revision, you can also compare
the assignments for each revision. This comparison reveals how different
optimization options affect your design.
Figure 111. Comparing Project Revisions
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Description
Qsys
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Figure 113. Qsys System Integration Tool and MegaWizard IP Core Editor
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Use the SEARCH_PATH assignment to define the project libraries. The Quartus II
software supports multiple SEARCH_PATH assignments. Specify only one source
directory for each SEARCH_PATH assignment.
f For more information, refer to IP core user guides on the IP and Megafunctions
Documentation section of the Altera website, and to Creating a System with Qsys in the
Quartus II Handbook.
Compile all RTL and gate-level simulation model libraries for your device,
simulator, and design language automatically
(Tools > Launch Simulation Library Compiler).
Include files (.edf, .vqm) generated by other EDA design entry or synthesis tools
in your project as synthesized design files
(Project > Add/Remove File from Project)
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The Quartus II software optionally generates the following files for other EDA tools:
Figure 117. Quartus II Generated Files for Other EDA Tools
<Quartus II Project Directory>
simulation - EDA simulation files
<EDA_simulator>
<.vo, .vho, .sv for simulation>
symbols - EDA board-level symbol tool files
<EDA_board_symbol_tool_name>
<.fx or .xml for symbol generation and board-level verification>
board - EDA board-level signal integrity tool files
hspice or ibis
<.sp or .ibs for signal integrity analysis>
timing - EDA board-level timing analysis tool files
<EDA_board_timing_tool_name>
<STAMP model files, .data, .mod, and .lib>
board - EDA board-level boundary scan tool files
bsdl
< Boundary Scan Description Language File (.bsd)>
Refer to Synopsys Synplify Support, Mentor Graphics Precision Synthesis Support, Mentor
Graphics LeonardoSpectrum Support, and Simulating Altera Designs in the Quartus II
Handbook for more information about using other EDA tools.
Archiving Projects
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Optimize and lock down the compilation results for individual blocks. Export the
post-synthesis or post-fit netlist as a Quartus II Exported Partition File (.qxp)
(Project > Export Design Partition). You can then import the partition as a new
project design file.
Purge the content of the project database (Project > Clean Project) to remove
unwanted previous compilation results at any time.
Project Filesproject settings (.qsf), design files, and timing constraints (.sdc)
f Refer to Quartus II Incremental Compilation for Hierarchical and Team-Based Design and
Design Planning for Partial Reconfiguration in the Quartus II Handbook for more
information about partitions, incremental compilation, and device reconfiguration.
Click Processing > Start > Start Analysis & Synthesis to generate a postsynthesis netlist.
3. Click Project > Export Database and specify the Export directory.
4. In a later version of the Quartus II software, click New Project Wizard and create a
new project with the same top-level design entity name as the migrated project.
117
5. Click Project > Import Database and select the <project directory>/export_db/
exported database directory. The Quartus II software opens the compiled project
and displays compilation results.
1
You can turn on Assignments > Settings > Compilation Process Settings > Export
version-compatible database if you want to always export the database following
compilation.
Figure 118. Quartus II Version-Compatible Database Structure
Quartus II Project
Settings A
Settings B
Settings C
Settings D
Archiving Projects
You can save the elements of a project in a single, compressed Quartus II Archive File
(.qar) by clicking Project > Archive Project. The .qar captures logic design, project,
and settings files required to restore the project. Use this technique to share projects
between designers, or to transfer your project to a new version of the Quartus II
software, or to Altera support.
You can optionally add compilation results, Qsys system files, and third-party EDA
tool files to the archive. If you restore the archive in a different version of the
Quartus II software, you must include the original .qdf in the archive to preserve
original compilation results.
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2. Click Advanced.
3. Select the File set for archive or select Custom. Turn on File subsets for archive.
4. Click Add and select Qsys system or EDA tool files, as detailed in Figure 115 and
Figure 117. Click OK.
5. Click Archive.
Project source and setting files (.v, .vhd, .vqm, .qsf, .sdc, .qip, .qpf, .cmp, .sip)
119
You can generate or modify these files manually if you use a scripted design flow. If
you use an external source code control system, you can check-in project files anytime
you modify assignments and settings in the Quartus II software. Refer to Figure 115
for a list of IP and Qsys generated files.
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Do not change the forward-slash (/) and back-slash (\) path separators in the .qsf.
The Quartus II software automatically changes all back-slash (\) path separators
to forward-slashes (/)in the .qsf.
Ensure that any external project library exists in the new platforms file system.
Specify file and directory paths as relative to the project directory. For example, for
a project titled foo_design , specify the source files as: top.v, foo_folder/foo1.v,
foo_folder/foo2.v, and foo_folder/bar_folder/bar1.vhdl.
Ensure that all the subdirectories are in the same hierarchical structure and relative
path as in the original platform.
foo_design
foo_design.qsf
top.v
foo_folder
foo1.v
foo2.v
bar_folder
bar1.vhdl
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Relative Paths
Express file paths using relative path notation (../). For example, in the directory
structure shown in Figure 121, you can specify top.v as ../source/top.v and foo1.v as
../source/foo_folder/foo1.v.
Figure 121. Quartus II Project Directory Separate from Design Files
foo_design
quartus
foo_design.qsf
source
top.v
foo_folder
foo1.v
foo2.v
bar_folder
bar1.vhdl
For Linux, the Quartus II software creates the file in the altera.quartus directory
under the <home> directory.
All library files are relative to the libraries. For example, if you specify the
user_lib1 directory as a project library and you want to add the /user_lib1/foo1.v
file to the library, you can specify the foo1.v file in the .qsf as foo1.v. The
Quartus II software includes files in specified libraries.
When copying projects that include libraries, you must either copy your project
library files along with the project directory or ensure that your project library files
exist in the target platform.
On Windows, the Quartus II software searches for the quartus2.ini file in the
following directories and order:
a. USERPROFILE, for example, C:\Documents and Settings\<user name>
b. Directory specified by the TMP environmental variable
c. Directory specified by the TEMP environmental variable
d. Root directory, for example, C:\
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Scripting API
You can use command-line executables or scripts to execute project commands, rather
than using the GUI. The following commands are available for scripting project
management.
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-all_revisions
-include_libraries
-include_outputs
-use_file_set <file_set>
-version_compatible_database
Version-compatible databases are not be available for some device families. If you
require the database files to reproduce the compilation results in the same Quartus II
software version, use the -use_file_set full_db option to archive the complete
database.
Example 16. Create a Project Archive
quartus_sh --archive <name>r
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Example 110 shows the Tcl commands from the flow package to import or export
version-compatible databases. If you use the flow package, you must specify the
database directory variable name. flow and database_manager packages contain
commands to manage version-compatible databases.
Example 110. Import and Export Version-Compatible Databases from flow Package
set_global_assignment -name VER_COMPATIBLE_DB_DIR <directory>
execute_flow flow export_database
execute_flow flow import_database
Example 112 shows the quartus_cdb and the quartus_sh executables to manage
version-compatible databases:
Example 112. quartus_cdb and quartus_sh Executable
quartus_cdb <project> -c <revision>--export_database=<directory>r
quartus_cdb <project> -c <revision> --import_database=<directory>r
quartus_sh flow export_database <project> -c \ <revision>r
quartus_sh flow import_database <project> -c \ <revision>r
Example 113 archives the version-compatible database with the project for
restoration in the same version of the Quartus II software:
Example 113. Archive Compilation Database with Project
quartus_sh --archive -use_file_set full_db [-revision <revisionname>] <project_name>
To report any project libraries specified for a project and any global libraries specified
for the current installation of the Quartus II software, use the get_global_assignment
and get_user_option Tcl commands.
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Example 115 shows that the Tcl script outputs the user paths and global libraries for
an open Quartus II project:
Example 115. Commands to Report Specified Project Libraries
get_global_assignment -name SEARCH_PATHr
get_user_option -name SEARCH_PATHr
f For more information about scripting, refer to Tcl Scripting or Command-Line Scripting
in the Quartus II Handbook. For comprehensive scripting reference, refer to the
Quartus II Settings File Manual.
Version
May 2013
13.0.0
June 2012
12.0.0
November 2011
10.1.1
December 2010
July 2010
November 2009
May 2013
10.1.0
Changes
Template update.
Updated Working with Messages on page 417. Added a link to Help. Removed
Figure 42 on page 47, Figure 411 on page 23, and Figure 412 on page.
Added Managing Projects in a Team-Based Design Environment on page 422 and File
Association on page 42.
Updated Figure 41 on page 46, Figure 42 on page 48, Figure 46 on page 418,
Figure 46 on page 419, and Figure 47 on page 421.
Updated Creating a New Project on page 44, Archiving a Project on page 49,
Restoring an Archived Project on page 411.
Added Quartus II Text Editor on page 42, Reducing Compilation Time on page 432.
10.0.0
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March 2009
Version
9.0.0
Changes
Updated to fix Document Revision History for version 9.0.0.
Updated Figure 41, Figure 47, Figure 48, and Figure 411.
Updated Example 43, Example 44, Example 45, and Example 46.
9.0.0
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
f This chapter provides only an introduction to various design planning features in the
Quartus II software. For more information about Quartus II features and
methodologies, this chapter provides references to other appropriate chapters in the
Quartus II Handbook.
Before reading the design planning guidelines discussed in this chapter, consider your
design priorities. More device features, density, or performance requirements can
increase system cost. Signal integrity and board issues can impact I/O pin locations.
Power, timing performance, and area utilization all affect each other, and compilation
time is affected when optimizing these priorities.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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The Quartus II software optimizes designs for the best overall results; however, you
can change the settings to better optimize one aspect of your design, such as power
utilization. Certain tools or debugging options can lead to restrictions in your design
flow. Your design priorities help you choose the tools, features, and methodologies to
use for your design.
f After you select a device family, to check if additional guidelines are available, refer to
the design guidelines section of the appropriate device handbook.
Tetheredthe design requires an Altera serial JTAG cable connected between the
JTAG port on your board and a host computer running the Quartus II Programmer
for the duration of the hardware evaluation period.
f For descriptions of available IP cores, refer to the Intellectual Property page of the
Altera website.
23
Selecting a Device
The device you choose affects board specification and layout. This section provides
guidelines in the device selection process.
Choose the device family that best suits your design requirements. Families differ in
cost, performance, logic and memory density, I/O density, power utilization, and
packaging. You must also consider feature requirements, such as I/O standards
support, high-speed transceivers, global or regional clock networks, and the number
of phase-locked loops (PLLs) available in the device.
f You can use the Altera Product Selector available on the Altera website to help you
choose your device. You can also review important features of each device family in
the Selector Guides page of the Altera website. Each device family also has a device
handbook, including a data sheet, which documents device features in detail. You can
also see a summary of the resources for each device in the Device dialog box in the
Quartus II software.
h For a list of device selection guides, refer to Devices and Adapters in Quartus II Help.
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Carefully study the device density requirements for your design. Devices with more
logic resources and higher I/O counts can implement larger and more complex
designs, but at a higher cost. Smaller devices use lower static power. Select a device
larger than what your design requires if you want to add more logic later in the
design cycle to upgrade or expand your design, and reserve logic and memory for
on-chip debugging (refer to Planning for On-Chip Debugging Tools on page 210).
Consider requirements for types of dedicated logic blocks, such as memory blocks of
different sizes, or digital signal processing (DSP) blocks to implement certain
arithmetic functions.
If you have older designs that target an Altera device, you can use their resources as
an estimate for your design. Compile existing designs in the Quartus II software with
the Auto device selected by the Fitter option in the Settings dialog box. Review the
resource utilization to learn which device density fits your design. Consider coding
style, device architecture, and the optimization options used in the Quartus II
software, which can significantly affect the resource utilization and timing
performance of your design.
f To obtain resource utilization estimates for certain configurations of Alteras IP, refer
to the user guides for Altera megafunctions and IP MegaCores on the IP and
Megafunctions literature page of the Altera website.
25
Estimating Power
You can use the Quartus II power estimation and analysis tools to provide
information to PCB board and system designers. Power consumption in FPGA
devices depends on the design logic, which can make planning difficult. You can
estimate power before you create any source code, or when you have a preliminary
version of the design source code, and then perform the most accurate analysis with
the PowerPlay Power Analyzer when you complete your design.
You must accurately estimate device power consumption to develop an appropriate
power budget and to design the power supplies, voltage regulators, heat sink, and
cooling system. Power estimation and analysis helps you satisfy two important
planning requirements:
The PowerPlay Early Power Estimator (EPE) spreadsheet allows you to estimate
power utilization for your design.
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You can manually enter data into the EPE spreadsheet, or use the Quartus II software
to generate device resource information for your design.
To manually enter data into the EPE spreadsheet, enter the device resources,
operating frequency, toggle rates, and other parameters for your design. If you do not
have an existing design, estimate the number of device resources used in your design,
and then enter the data into the EPE spreadsheet manually.
If you have an existing design or a partially completed design, you can use the
Quartus II software to generate the PowerPlay Early Power Estimator File (.txt, .csv)
to assist you in completing the PowerPlay EPE spreadsheet.
h For more information about generating the PowerPlay EPE File, refer to Performing an
Early Power Estimate Using the PowerPlay Early Power Estimator in Quartus II Help.
The PowerPlay EPE spreadsheet includes the Import Data macro that parses the
information in the PowerPlay EPE File and transfers the information into the
spreadsheet. If you do not want to use the macro, you can manually transfer the data
into the EPE spreadsheet. For example, after importing the PowerPlay EPE File
information into the PowerPlay EPE spreadsheet, you can add device resource
information. If the existing Quartus II project represents only a portion of your full
design, manually enter the additional device resources you use in the final design.
Estimating power consumption early in the design cycle allows planning of power
budgets and avoids unexpected results when designing the PCB.
f The PowerPlay EPE spreadsheets for each supported device family are available on
the PowerPlay Early Power Estimator and Power Analyzer page of the Altera
website.
When you complete your design, perform a complete power analysis to check the
power consumption more accurately. The PowerPlay Power Analyzer tool in the
Quartus II software provides an accurate estimation of power, ensuring that thermal
and supply limitations are met.
f For more information about power estimation and analysis, refer to the PowerPlay
Power Analysis chapter in volume 3 of the Quartus II Handbook.
27
You can create a preliminary pin-out for an Altera FPGA with the Quartus II Pin
Planner before you develop the source code, based on standard I/O interfaces (such
as memory and bus interfaces) and any other I/O requirements for your system. The
Quartus II I/O Assignment Analysis checks that the pin locations and assignments
are supported in the target FPGA architecture. You can then use I/O Assignment
Analysis to validate I/O-related assignments that you create or modify throughout
the design process. When you compile your design in the Quartus II software, I/O
Assignment Analysis runs automatically in the Fitter to validate that the assignments
meet all the device requirements and generates error messages.
Early in the design process, before creating the source code, the system architect has
information about the standard I/O interfaces (such as memory and bus interfaces),
the IP cores in your design, and any other I/O-related assignments defined by system
requirements. You can use this information with the Early Pin Planning feature in the
Pin Planner to specify details about the design I/O interfaces. You can then create a
top-level design file that includes all I/O information.
The Pin Planner interfaces with the IP core parameter editor, which allows you to
create or import custom megafunctions and IP cores that use I/O interfaces. You can
configure how to connect the functions and cores to each other by specifying
matching node names for selected ports. You can create other I/O-related
assignments for these interfaces or other design I/O pins in the Pin Planner, as
described in this section. The Pin Planner creates virtual pin assignments for internal
nodes, so internal nodes are not assigned to device pins during compilation. After
analysis and synthesis of the newly generated top-level wrapper file, use the
generated netlist to perform I/O Analysis with the Start I/O Assignment Analysis
command.
h For more information about setting up the nodes in your design, refer to Set Up
Top-Level Design File Window (Edit Menu) in Quartus II Help.
You can use the I/O analysis results to change pin assignments or IP parameters even
before you create your design, and repeat the checking process until the I/O interface
meets your design requirements and passes the pin checks in the Quartus II software.
When you complete initial pin planning, you can create a revision based on the
Quartus II-generated netlist. You can then use the generated netlist to develop the toplevel design file for your design, or disregard the generated netlist and use the
generated Quartus II Settings File (.qsf) with your design.
During this early pin planning, after you have generated a top-level design file, or
when you have developed your design source code, you can assign pin locations and
assignments with the Pin Planner.
With the Pin Planner, you can identify I/O banks, voltage reference (VREF) groups,
and differential pin pairings to help you through the I/O planning process. If
migration devices are selected (including HardCopy devices) as described in Device
Migration Planning on page 24, the Pin Migration View highlights the pins that
have changed functions in the migration device when compared to the currently
selected device. Selecting the pins in the Device Migration view cross-probes to the
rest of the Pin Planner, so that you can use device migration information when
planning your pin assignments. You can also configure board trace models of selected
pins for use in board-aware signal integrity reports generated with the Enable
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Advanced I/O Timing option. This option ensures that you get accurate I/O timing
analysis. You can use a Microsoft Excel spreadsheet to start the I/O planning process
if you normally use a spreadsheet in your design flow, and you can export a
Comma-Separated Value File (.csv) containing your I/O assignments for spreadsheet
use when you assign all pins.
When you complete your pin planning, you can pass pin location information to PCB
designers. The Pin Planner is tightly integrated with certain PCB design EDA tools,
and can read pin location changes from these tools to check suggested changes. Your
pin assignments must match between the Quartus II software and your schematic and
board layout tools to ensure the FPGA works correctly on the board, especially if you
must make changes to the pin-out. The system architect uses the Quartus II software
to pass pin information to team members designing individual logic blocks, allowing
them to achieve better timing closure when they compile their design.
Start FPGA planning before you complete the HDL for your design to improve the
confidence in early board layouts, reduce the chance of error, and improve the overall
time to market of the design. When you complete your design, use the Fitter reports
for the final sign-off of pin assignments. After compilation, the Quartus II software
generates the Pin-Out File (.pin), and you can use this file to verify that each pin is
correctly connected in board schematics.
f For more information about I/O assignment and analysis, refer to the I/O Management
chapter in volume 2 of the Quartus II Handbook. For more information about passing
I/O information between the Quartus II software and third-party EDA tools, refer to
the Mentor Graphics PCB Design Tools Support and Cadence PCB Design Tools Support
chapters in the I/O and PCB Tools section in volume 2 of the Quartus II Handbook.
29
Synthesis Tool
The Quartus II software includes integrated synthesis that supports Verilog HDL,
VHDL, Altera Hardware Description Language (AHDL), and schematic design entry.
You can also use supported standard third-party EDA synthesis tools to synthesize
your Verilog HDL or VHDL design, and then compile the resulting output netlist file
in the Quartus II software. Different synthesis tools may give different results for each
design. To determine the best tool for your application, you can experiment by
synthesizing typical designs for your application and coding style. Perform
placement and routing in the Quartus II software to get accurate timing analysis and
logic utilization results.
f Because tool vendors frequently add new features, fix tool issues, and enhance
performance for Altera devices, you must use the most recent version of third-party
synthesis tools. The Quartus II Software Release Notes lists the version of each synthesis
tool that is supported by a given version of the Quartus II software.
The synthesis tool you choose may allow you to create a Quartus II project and pass
constraints, such as the EDA tool setting, device selection, and timing requirements
that you specified in your synthesis project. You can save time when setting up your
Quartus II project for placement and routing.
To use incremental compilation, you must partition your design for synthesis and
generate multiple output netlist files. For more information, refer to Incremental
Compilation with Design Partitions on page 214.
f For more information about synthesis tool flows, refer to Volume 1: Design and
Synthesis of the Quartus II Handbook.
Simulation Tool
Altera provides the Mentor Graphics ModelSim-Altera Starter Edition with the
Quartus II software. You can also purchase the ModelSim-Altera Edition or a full
license of the ModelSim software to support large designs and achieve faster
simulation performance. The Quartus II software can generate both functional and
timing netlist files for ModelSim and other third-party simulators.
Use the simulator version that your Quartus II software version supports for best
results. You must also use the model libraries provided with your Quartus II software
version. Libraries can change between versions, which might cause a mismatch with
your simulation netlist.
For a list of the version of each simulation tool that is supported with a given version
of the Quartus II software, refer to the Quartus II Software Release Notes.
f For more information about simulation tool flows, refer to the appropriate chapter in
the Simulation section in volume 3 of the Quartus II Handbook.
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f For more information about formal verification flows and the supported tools, refer to
Volume 3: Verification of the Quartus II Handbook.
Using a formal verification tool can impact performance results because performing
formal verification requires turning off certain logic optimizations, such as register
retiming, and forces you to preserve hierarchy blocks, which can restrict optimization.
Formal verification treats memory blocks as black boxes. Therefore, you must keep
memory in a separate hierarchy block so other logic does not get incorporated into the
black box for verification. Other restrictions may limit your design, and you must
consult Volume 3: Verification of the Quartus II Handbook for details. If formal
verification is important to your design, plan for limitations and restrictions at the
beginning of the design cycle rather than make changes later.
Reserve I/O pinsrequired if you use the Logic Analyzer Interface (LAI) or
SignalProbe tools, which require I/O pins for debugging. If you reserve I/O pins
for debugging, you do not have to later change your design or board. The LAI can
multiplex signals with design I/O pins if required. Ensure that your board
supports a debugging mode, in which debugging signals do not affect system
operation.
211
Table 21 lists which factors are important for each debugging tool.
In-System Memory
Content Editor
SignalProbe
In-System Sources
and Probes
JTAG connections
System Console
SignapTap II
Logic Analyzer
Table 21. Factors to Consider When Using Debugging Tools During Design Planning Stages
Design Recommendations
Use synchronous design practices to consistently meet your design goals. Problems
with asynchronous design techniques include reliance on propagation delays in a
device, incomplete timing analysis, and possible glitches. In a synchronous design, a
clock signal triggers all events. When you meet all register timing requirements, a
synchronous design behaves in a predictable and reliable manner for all process,
voltage, and temperature (PVT) conditions. You can easily target synchronous designs
to different device families or speed grades.
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Clock signals have a large effect on the timing accuracy, performance, and reliability
of your design. Problems with clock signals can cause functional and timing problems
in your design. Use dedicated clock pins and clock routing for best results, and if you
have PLLs in your target device, use the PLLs for clock inversion, multiplication, and
division. For clock multiplexing and gating, use the dedicated clock control block or
PLL clock switchover feature instead of combinational logic, if these features are
available in your device. If you must use internally-generated clock signals, register
the output of any combinational logic used as a clock signal to reduce glitches.
The Design Assistant in the Quartus II software is a design-rule checking tool that
enables you to verify design issues. The Design Assistant checks your design for
adherence to Altera-recommended design guidelines. You can also use third-party
lint tools to check your coding style.
h For more information about running the Design Assistant, refer to About the Design
Assistant in Quartus II Help.
Consider the architecture of the device you choose so that you can use specific
features in your design. For example, the control signals should use the dedicated
control signals in the device architecture. Sometimes, you might need to limit the
number of different control signals used in your design to achieve the best results.
f For more information about design recommendations and using the Design Assistant,
refer to the Recommended Design Practices chapter in volume 1 of the Quartus II
Handbook. You can also refer to industry papers for more information about multiple
clock design. For a good analysis, refer to Synthesis and Scripting Techniques for
Designing Multi-Asynchronous Clock Designs under Papers (www.sunburstdesign.com).
Managing Metastability
Metastability problems can occur in digital design when a signal is transferred
between circuitry in unrelated or asynchronous clock domains, because the designer
cannot guarantee that the signal meets the setup and hold time requirements during
the signal transfer. Designers commonly use a synchronization chain to minimize the
occurrence of metastable events. Ensure that your design accounts for
synchronization between any asynchronous clock domains. Consider using a
synchronizer chain of more than two registers for high-frequency clocks and
frequently-toggling data signals to reduce the chance of a metastability failure.
213
You can use the Quartus II software to analyze the average mean time between
failures (MTBF) due to metastability when a design synchronizes asynchronous
signals, and optimize your design to improve the metastability MTBF. The MTBF due
to metastability is an estimate of the average time between instances when
metastability could cause a design failure. A high MTBF (such as hundreds or
thousands of years between metastability failures) indicates a more robust design.
Determine an acceptable target MTBF given the context of your entire system and the
fact that MTBF calculations are statistical estimates.
The Quartus II software can help you determine whether you have enough
synchronization registers in your design to produce a high enough MTBF at your
clock and data frequencies.
f For information about metastability analysis, reporting, and optimization features in
the Quartus II software, refer to the Managing Metastability with the Quartus II Software
chapter in volume 1 of the Quartus II Handbook.
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The flat compilation flow is easy to use; you do not have to plan any design partitions.
However, because the Quartus II software recompiles the entire design whenever you
change your design, compilation times can be slow for large devices. Additionally,
you may find that the results for one part of the design change when you change a
different part of your design. You can turn on the Rapid Recompile option to instruct
the software to preserve compatible placement and routing results when the design
changes in subsequent compilations. This option can reduce your compilation time in
a flat or partitioned design when you make small changes to your design.
215
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If you design individual design blocks or partitions separately, you can use the Fast
synthesis and early timing estimate features as you develop your design. Any issues
highlighted in the lower-level design blocks are communicated to the system
architect. Resolving these issues might require allocating additional device resources
to the individual partition, or changing the timing budget of the partition.
Expert designers can also use fast synthesis and early timing estimation to prototype
the entire design. Incomplete partitions are marked as empty in an incremental
compilation flow, while the rest of the design is compiled to get an early timing
estimate and detect any problems with design integration.
Conclusion
Modern FPGAs support large, complex designs with fast timing performance. By
planning several aspects of your design early, you can reduce time in later stages of
the development cycle. Use features of the Quartus II software to quickly plan your
design and achieve the best possible results. Following the guidelines presented in
this chapter can improve productivity, which can reduce cost and development time.
Version
November, 2012
12.1.0
June 2012
12.0.0
Editorial update.
November 2011
11.0.1
Template update.
May 2011
December 2010
11.0.0
Changes
Added link to System Design with Qsys in Creating Design Specifications on page 12
Converted information into new table (Table 11) in Planning for On-Chip Debugging
Options on page 110
Added information about the Rapid Recompile option in Flat Compilation Flow with No
Design Partitions on page 114
Removed details and linked to Quartus II Help in Fast Synthesis and Early Timing
Estimation on page 116
10.1.0
217
Version
July 2010
10.0.0
November 2009
9.1.0
Changes
Removed details about debugging tools from Planning for On-Chip Debugging Options
on page 110 and referred to other handbook chapters for more information
Merged the Planning Design Partitions section with the Creating a Design Floorplan
section. Changed heading title to Planning Design Partitions and Floorplan Location
Assignments on page 115
Updated information on Creating a Top-Level Design File for I/O Analysis on page 18
Changed heading title Top-Down Versus Bottom-Up Incremental Flows to SingleProject Versus Multiple-Project Incremental Flows
Removed information from Fast Synthesis and Early Timing Estimation on page 118
March 2009
9.0.0
No change to content
November 2008
8.1.0
Organization changes
Added reference to new details in the In-System Design Debugging section of volume 3
Added more details to the Design Practices and HDL Coding Styles section
Added references to the new Best Practices for Incremental Compilation and Floorplan
Assignments chapter
May 2008
8.0.0
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
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This chapter provides information and design scenarios to help you partition your
design to take advantage of the Quartus II incremental compilation feature.
The ability to iterate rapidly through FPGA design and debugging stages is critical.
The Quartus II software introduced the FPGA industrys first true incremental design
and compilation flow, with the following benefits:
Preserves the results and performance for unchanged logic in your design as you
make changes elsewhere.
Reduces design iteration time by an average of 75% for small changes in large
designs, so that you can perform more design iterations per day and achieve
timing closure efficiently.
Quartus II incremental compilation supports the Arria, Stratix, and Cyclone series
of devices, with limited support for HardCopy ASICs (for details, refer to
Limitations for HardCopy Compilation and Migration Flows on page 348).
This document contains the following sections:
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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32
33
The Quartus II software also includes a Rapid Recompile feature that instructs the
Compiler to reuse the compatible compilation results if most of the design has not
changed since the last compilation. This feature reduces compilation times for small
and isolated design changes. You do not have control over which parts of the design
are recompiled using this option; the Compiler determines which parts of the design
must be recompiled. The Rapid Recompile feature preserves performance and can
save compilation time by reducing the amount of changed logic that must be
recompiled. You can turn on the Rapid Recompile option in the Quartus II software
on the Incremental Compilation page in the Settings dialog box.
During the debugging stage of the design cycle, you can use incremental compilation
to add the SignalTap II Logic Analyzer incrementally to your design, even if the
design does not have partitions. To preserve the compilation netlist for the entire
design, instruct the software to reuse the compilation results for the
automatically-created "Top" partition that contains the entire design. For more
information, refer to Debugging Incrementally With the SignalTap II Logic
Analyzer on page 313.
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Compilation
Time Savings
Typically saves an average of 75% of compilation time for small design changes in large designs when
post-fit netlists are preserved; there are savings in both Quartus II Integrated Synthesis and the Fitter.
(1)
Performance
Preservation
Excellent performance preservation when timing critical paths are contained within a partition,
because you can preserve post-fitting information for unchanged partitions.
Node Name
Preservation
Area Changes
The area (logic resource utilization) might increase because cross-boundary optimizations are limited,
and placement and register packing are restricted.
fMAX Changes
The designs maximum frequency might be reduced because cross-boundary optimizations are
limited. If the design is partitioned and the floorplan location assignments are created appropriately,
there might be no negative impact on fMAX.
If you use the incremental compilation feature at any point in your design flow, it is
easier to accommodate the guidelines for partitioning a design and creating a
floorplan if you start planning for incremental compilation at the beginning of your
design cycle.
f For more information and recommendations on how to prepare your design to use the
Quartus II incremental compilation feature, and how to avoid negative impact on
your design results, refer to the Best Practices for Incremental Compilation Partitions and
Floorplan Assignments chapter in volume 1 of the Quartus II Handbook.
35
VHDL
(.vhd)
AHDL
(.tdf)
Block
Design File
(.bdf)
EDIF
Netlist
(.edf)
VQM
Netlist
(.vqm)
Partition Top
Design Partition
Assignments
Partition 1
Partition 2
Settings &
Assignments
One Post-Synthesis
Netlist per Partition
Partition Merge
Create Complete Netlist Using Appropriate Source Netlists for Each
Partition (Post-Fit, Post-Synthesis, or Imported Netlist)
One Post-Fit
Netlist per
Partition
Floorplan
Location
Assignments
Settings &
Assignments
Single Post-Fit
Netlist for
Complete Design
Assembler
in parellel
Requirements
Satisfied?
Timing
Analyzer
No
Yes
Program/Configure Device
The diagram in Figure 31 shows a top-level partition and two lower-level partitions.
If any part of the design changes, Analysis and Synthesis processes the changed
partitions and keeps the existing netlists for the unchanged partitions. After
completion of Analysis and Synthesis, there is one post-synthesis netlist for each
partition.
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The Partition Merge step creates a single, complete netlist that consists of
post-synthesis netlists, post-fit netlists, and netlists exported from other Quartus II
projects, depending on the netlist type that you specify for each partition.
The Fitter then processes the merged netlist, preserves the placement and routing of
unchanged partitions, and refits only those partitions that have changed. The Fitter
generates the complete netlist for use in future stages of the compilation flow,
including timing analysis and programming file generation, which can take place in
parallel if more than one processor is enabled for use in the Quartus II software. The
Fitter also generates individual netlists for each partition so that the Partition Merge
stage can use the post-fit netlist to preserve the placement and routing of a partition, if
specified, for future compilations.
If you define partitions, but want to check your compilation results without partitions
in a what if scenario, you can direct the Compiler to ignore all partitions
assignments in your project and compile the design as a "flat" netlist. When you turn
on the Ignore partitions assignments during compilation option on the Incremental
Compilation page, the Quartus II software disables all design partition assignments
in your project and runs a full compilation ignoring all partition boundaries and
netlists. Turning off the Ignore partitions assignments during compilation option
restores all partition assignments and netlists for subsequent compilations.
h For more information on incremental compilation settings, refer to Incremental
Compilation Page and Design Partition Properties Dialog Box in Quartus II Help.
37
Teams with a bottom-up design approach often want to optimize placement and
routing of design partitions independently and may want to create separate
Quartus II projects for each partition. However, optimizing design partitions in
separate Quartus II projects, and then later integrating the results into a top-level
design, can have the following potential drawbacks that require careful planning:
Achieving timing closure for the full design may be more difficult if you compile
partitions independently without information about other partitions in the design.
This problem may be avoided by careful timing budgeting and special design
rules, such as always registering the ports at the module boundaries.
Resource budgeting and allocation may be required to avoid resource conflicts and
overuse. Creating a floorplan with LogicLock regions is recommended when
design partitions are developed independently in separate Quartus II projects.
A unique challenge of team-based design and IP delivery for FPGAs is the fact that
the partitions being developed independently must share a common set of resources.
To minimize issues that might arise from sharing a common set of resources, you can
design partitions within a single Quartus II project or a copy of the top-level design. A
common project ensures that designers have a consistent view of the top-level project
framework.
For timing-critical partitions being developed and optimized by another designer, it is
important that each designer has complete information about the top-level design in
order to maintain timing closure during integration, and to obtain the best results.
When you want to integrate partitions from separate Quartus II projects, the project
lead can perform most of the design planning, and then pass the top-level design
constraints to the partition designers. Preferably, partition designers can obtain a copy
of the top-level design by checking out the required files from a source control system.
Alternatively, the project lead can provide a copy of the top-level project framework,
or pass design information using Quartus II-generated design partition scripts. In the
case that a third-party designer has no information about the top-level design,
developers can export their partition from an independent project if required.
For more information about managing team-based design flows, refer to Exporting
Design Partitions from Separate Quartus II Projects on page 326 and Project
ManagementMaking the Top-Level Design Available to Other Designers on
page 328.
1
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Figure 32 illustrates the incremental compilation design flow when all partitions are
contained in one top-level design.
Figure 32. Summary of Standard Incremental Compilation Design Flow
Perform Analysis & Elaboration
Repeat as Needed
During Design, Verification
& Debugging Stages
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h For more information about how to create and manage design partitions in the Design
Partitions window, refer to Creating Design Partitions in Quartus II Help.
Automatically-Generated Partitions
The Compiler creates some partitions automatically as part of the compilation
process, which appear in some post-compilation reports. For example, the sld_hub
partition is created for tools that use JTAG hub connections, such as the SignalTap II
Logic Analyzer. The hard_block partition is created to contain certain "hard" or
dedicated logic blocks in the device that are implemented in a separate partition so
that they can be shared throughout the design.
Reducing Compilation Time When Changing Source Files for One Partition on
page 311
311
Reducing Compilation Time When Changing Source Files for One Partition
Scenario background: You set up your design to include partitions for several of the
major design blocks, and now you have just performed a lengthy compilation of the
entire design. An error is found in the HDL source file for one partition and it is being
fixed. Because the design is currently meeting timing requirements, and the fix is not
expected to affect timing performance, it makes sense to compile only the affected
partition and preserve the rest of the design.
Use the flow in this example to update the source file in one partition without having
to recompile the other parts of the design. To reduce the compilation time, instruct the
software to reuse the post-fit netlists for the unchanged partitions. This flow also
preserves the performance of these blocks, which reduces additional timing closure
efforts.
Perform the following steps to update a single source file:
1. Apply and save the fix to the HDL source file.
2. On the Assignments menu, open the Design Partitions window.
3. Change the netlist type of each partition, including the top-level entity, to Post-Fit
to preserve as much as possible for the next compilation.
1
For more information about the Analysis and Synthesis report, refer to List
of Compilation and Simulation Reports in Quartus II Help.
4. Click Start Compilation to incrementally compile the fixed HDL code. This
compilation should take much less time than the initial full compilation.
5. Simulate the design to ensure that the error is fixed, and use the TimeQuest Timing
Analyzer report to ensure that timing results have not degraded.
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Use the flow in this example to optimize the results of one partition when the other
partitions in the design have already met their requirements. You can use this flow
iteratively to lock down the performance of one partition, and then move on to
optimization of another partition.
Perform the following steps to preserve the results for partitions that meet their
timing requirements, and to recompile a timing-critical partition with new
optimization settings:
1. Open the Design Partitions window.
2. For the partition in question, set the netlist type to Source File.
1
If you change a setting that affects only the Fitter, you can save additional
compilation time by setting the netlist type to Post-Synthesis to reuse the
synthesis results and refit the partition.
3. For the remaining partitions (including the top-level entity), set the netlist type to
Post-Fit.
1
You can optionally set the Fitter Preservation Level on the Advanced tab in
the Design Partitions Properties dialog box to Placement to allow for the
most flexibility during routing.
313
The flow in this example is similar to design flows in which a module is implemented
separately and is later merged into the top-level, such as in the team-based design
flow described in Designing in a Team-Based Environment on page 338. Generally,
optimization in this flow works only if each critical path is contained within a single
partition due to the effects described in Deciding Which Design Blocks Should Be
Design Partitions on page 314. Ensure that if there are any partitions representing a
design file that is missing from the project, you create a placeholder wrapper file to
define the port interface. For more information, refer to Empty Partitions on
page 328.
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The netlist type for the top-level partition defaults to Source File, so be sure
to change this Top partition in addition to any design partitions that you
have created.
3. If you have not already compiled the design with the current set of partitions,
perform a full compilation. If the design has already been compiled with the
current set of partitions, the design is ready to add the SignalTap II Logic Analyzer.
4. Set up your SignalTap II File using the post-fitting filter in the Node Finder to add
signals for logic analysis. This allows the Fitter to add the SignalTap II logic to the
post-fit netlist without modifying the design results.
To add signals from the pre-synthesis netlist, set the partitions netlist type to
Source File and use the pre-synthesis filter in the Node Finder. This allows the
software to resynthesize the partition and to tap directly to the pre-synthesis node
names that you choose. In this case, the partition is resynthesized and refit, so the
placement is typically different from previous fitting results.
f For more information about setting up the SignalTap II Logic Analyzer, refer to the
Design Debugging Using the SignalTap II Embedded Logic Analyzer chapter in volume 3 of
the Quartus II Handbook.
315
Partitions must have the same boundaries as hierarchical blocks in the design because
a partition cannot be a portion of the logic within a hierarchical entity. You can merge
partitions that have the same immediate parent partition to create a single partition
that includes more than one hierarchical entity in the design. When you declare a
partition, every hierarchical instance within that partition becomes part of the same
partition. You can create new partitions for hierarchical instances within an existing
partition, in which case the instances within the new partition are no longer included
in the higher-level partition, as described in the following example.
In Figure 33, a complete design is made up of instances A, B, C, D, E, F, and G. The
shaded boxes in Representation i indicate design partitions in a tree representation
of the hierarchy. In Representation ii, the lower-level instances are represented inside
the higher-level instances, and the partitions are illustrated with different colored
shading. The top-level partition, called Top, automatically contains the top-level
entity in the design, and contains any logic not defined as part of another partition.
The design file for the top level may be just a wrapper for the hierarchical instances
below it, or it may contain its own logic. In this example, partition B contains the logic
in instances B, D, and E. Entities F and G were first identified as separate partitions,
and then merged together to create a partition F-G. The partition for the top-level
entity A, called Top, includes the logic in one of its lower-level instances, C, because
C was not defined as part of any other partition.
Figure 33. Partitions in a Hierarchical Design
Representation i
Partition Top
A
Partition B
Representation ii
A
C
You can create partition assignments to any design instance. The instance can be
defined in HDL or schematic design, or come from a third-party synthesis tool as a
VQM or EDIF netlist instance.
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317
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You can assign design partitions to physical regions in the device floorplan using
LogicLock region assignments. In the Quartus II software, LogicLock regions are used
to constrain blocks of a design to a particular region of the device. Altera recommends
using LogicLock regions for timing-critical design blocks that will change in
subsequent compilations, or to improve the quality of results and avoid placement
conflicts in some cases. Creating floorplan location assignments for design partitions
using LogicLock regions is discussed in Creating a Design Floorplan With LogicLock
Regions on page 344.
f For more information about when and why to create a design floorplan, refer to the
Best Practices for Incremental Compilation Partitions and Floorplan Assignments chapter in
volume 1 of the Quartus II Handbook.
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settings. For some items, if your design does not follow the recommendation, the
Check Recommendations operation creates a table that lists any nodes or paths in
your design that could be improved. The relevant timing-independent
recommendations for the design are also listed in the Design Partitions window and
the LogicLock Regions window.
To verify that your design follows the recommendations, go to the Timing
Independent Recommendations page or the Timing Dependent Recommendations
page, and then click Check Recommendations. For large designs, these operations
can take a few minutes.
After you perform a check operation, symbols appear next to each recommendation to
indicate whether the design or project setting follows the recommendations, or if
some or all of the design or project settings do not follow the recommendations.
Following these recommendations is not mandatory to use the incremental
compilation feature. The recommendations are most important to ensure good results
for timing-critical partitions.
For some items in the Advisor, if your design does not follow the recommendation,
the Check Recommendations operation lists any parts of the design that could be
improved. For example, if not all of the partition I/O ports follow the Register All
Non-Global Ports recommendation, the advisor displays a list of unregistered ports
with the partition name and the node name associated with the port.
When the advisor provides a list of nodes, you can right-click a node, and then click
Locate to cross-probe to other Quartus II features, such as the RTL Viewer, Chip
Planner, or the design source code in the text editor.
1
Opening a new TimeQuest report resets the Incremental Compilation Advisor results,
so you must rerun the Check Recommendations process.
321
PostSynthesis
Preserves post-synthesis results for the partition and reuses the post-synthesis netlist when the
following conditions are true:
No change that initiates an automatic resynthesis has been made to the partition since the previous
synthesis. (2) For details, refer to What Changes Initiate the Automatic Resynthesis of a Partition? on
page 324.
Compiles the partition from the source files if resynthesis is initiated or if a post-synthesis netlist is not
available. (1)
Use this netlist type to preserve the synthesis results unless you make design changes, but allow the
Fitter to refit the partition using any new Fitter settings.
Post-Fit
Preserves post-fit results for the partition and reuses the post-fit netlist when the following conditions
are true:
No change that initiates an automatic resynthesis has been made to the partition since the previous
fitting. (2) For details, refer to What Changes Initiate the Automatic Resynthesis of a Partition? on
page 324.
When a post-fit netlist is not available, the software reuses the post-synthesis netlist if it is available, or
otherwise compiles from the source files. Compiles the partition from the source files if resynthesis is
initiated. (1)
The Fitter Preservation Level specifies what level of information is preserved from the post-fit netlist. For
details, refer to Fitter Preservation Level for Design Partitions on page 322.
Assignment changes, such as Fitter optimization settings, do not cause a partition set to Post-Fit to
recompile.
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323
Placement
Preserves the netlist atoms and their placement in the design partition. Reroutes the design
partition and does not preserve high-speed power tile usage.
Netlist Only
Preserves the netlist atoms of the design partition, but replaces and reroutes the design partition.
A post-fit netlist with the atoms preserved can be different than the Post-Synthesis netlist because
it contains Fitter optimizations; for example, Physical Synthesis changes made during a previous
Fitting.
You can use this setting to:
Preserve Fitter optimizations but allow the software to perform placement and routing again.
Reapply certain Fitter optimizations that would otherwise be impossible when the placement is
locked down.
h For more information about how to set the Netlist Type and Fitter Preservation Level
settings in the Quartus II software, refer to Setting the Netlist Type and Fitter
Preservation Level for Design Partitions in Quartus II Help.
Deleting Netlists
You can choose to abandon all levels of results preservation and remove all netlists
that exist for a particular partition with the Delete Netlists command in the Design
Partitions window. When you delete netlists for a partition, the partition is compiled
using the associated design source file(s) in the next compilation. Resetting the netlist
type for a partition to Source would have the same effect, though the netlists would
not be permanently deleted and would be available for use in subsequent
compilations. For an imported partition, the Delete Netlists command also optionally
allows you to remove the imported .qxp.
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Any dependent source design file has changed. For more information, refer to
Resynthesis Due to Source Code Changes on page 325.
A dependent source file was compiled into a different library (so it has a different
-library argument).
A dependent source file was added or removed; that is, the partition depends on a
different set of source files.
The partitions root instance has a different entity binding. In VHDL, an instance
may be bound to a specific entity and architecture. If the target entity or
architecture changes, it triggers resynthesis.
You have moved the project and compiled database between a Windows and
Linux system. Due to the differences in the way new line feeds are handled
between the operating systems, the internal checksum algorithm may detect a
design file change in this case.
The software reuses the post-synthesis results but re-fits the design if you change the
device setting within the same device family. The software reuses the post-fitting
netlist if you change only the device speed grade.
Synthesis and Fitter assignments, such as optimization settings, timing assignments,
or Fitter location assignments including pin assignments, do not trigger automatic
recompilation in the incremental compilation flow. To recompile a partition with new
assignments, change the netlist type for that partition to one of the following:
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Post-Fit with the Fitter Preservation Level set to Placement to rerun routing using
existing placement results, but new routing settings (such as delay chain settings)
You can use the LogicLock Origin location assignment to change or fine-tune the
previous Fitter results from a Post-Fit netlist. For details about how you can affect
placement with LogicLock regions, refer to Changing Partition Placement with
LogicLock Changes on page 346.
If you turn on the Rapid Recompile option, the Quartus II software may not
recompile the entire partition from the source code as described in this section; it will
reuse compatible results if there have been only small changes to the logic in the
partition. Refer to Incremental Capabilities Available When A Design Has No
Partitions on page 32 for more information.
If you define module parameters in a higher-level module, the Quartus II software
checks the parameter values when determining which partitions require resynthesis.
If you change a parameter in a higher-level module that affects a lower-level module,
the lower-level module is resynthesized. Parameter dependencies are tracked
separately from source file dependencies; therefore, parameter definitions are not
listed in the Partition Dependent Files list.
If a design contains common files, such as an includes.v file that is referenced in each
entity by the command include includes.v, all partitions are dependent on this file.
A change to includes.v causes the entire design to be recompiled. The VHDL
statement use work.all also typically results in unnecessary recompilations, because
it makes all entities in the work library visible in the current entity, which results in
the current entity being dependent on all other entities in the design.
To avoid this type of problem, ensure that files common to all entities, such as a
common include file, contain only the set of information that is truly common to all
entities. Remove use work.all statements in your VHDL file or replace them by
including only the specific design units needed for each entity.
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Integrate Partition(s)
into Top-Level Design
Repeat as Needed
During Design, Verif
& Debugging Stages
You cannot export or import partitions that have been merged. For more information
about merged partitions, refer to Deciding Which Design Blocks Should Be Design
Partitions on page 314.
The topics in this section provide a description of the team-based design flow using
exported partitions, describe how to generate a .qxp for a design partition, and
explain how to integrate the .qxp into the top-level design:
There are some additional restrictions related to design flows using exported
partitions, described in Incremental Compilation Restrictions on page 347.
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Next, create the appropriate design partition assignments and set the netlist type for
each design partition that will be developed in a separate Quartus II project to Empty.
Refer to Empty Partitions below for details. It may be necessary to constrain the
location of partitions with LogicLock region assignments if they are timing-critical
and are expected to change in future compilations, or if the designer or IP provider
wants to place and route their design partition independently, to avoid location
conflicts. For details, refer to Creating a Design Floorplan With LogicLock Regions
on page 344.
Finally, provide the top-level project framework to the partition designers, preferably
through a source control system. Refer to Project ManagementMaking the TopLevel Design Available to Other Designers on page 328 for more information.
Empty Partitions
You can use a design flow in which some partitions are set to an Empty netlist type to
develop pieces of the design separately, and then integrate them into the top-level
design at a later time. In a team-based design environment, you can set the netlist type
to Empty for partitions in your design that will be developed by other designers or IP
providers. The Empty setting directs the Compiler to skip the compilation of a
partition and use an empty placeholder netlist for the partition.
When a netlist type is set to Empty, peripheral nodes including pins and PLLs are
preserved and all other logic is removed. The peripheral nodes including pins help
connect the empty partition to the design, and the PLLs help preserve timing of
non-empty partitions within empty partitions.
When you set a design partition to Empty, a design file is required during Analysis
and Synthesis to specify the port interface information so that it can connect the
partition correctly to other logic and partitions in the design. If a partition is exported
from another project, the .qxp contains this information. If there is no .qxp or design
file to represent the design entity, you must create a wrapper file that defines the
design block and specifies the input, output, and bidirectional ports. For example, in
Verilog HDL, you should include a module declaration, and in VHDL, you should
include an entity and architecture declaration.
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If partition designers have access to the top-level project framework, the project
will already include all the settings and constraints needed for the design. This
framework should include PLLs and other interface logic if this information is
important to optimize partitions.
If designers are part of the same design environment, they can check out the
required project files from the same source control system. This is the
recommended way to share a set of project files.
Otherwise, the project lead can provide a copy of the top-level project
framework so that each design develops their partition within the same project
framework.
If a partition designer does not have access to the top-level project framework, the
project lead can give the partition designer a Tcl script or other documentation to
create the separate Quartus II project and all the assignments from the top-level
design.
For details about project management scripts you can create with the Quartus II
software, refer toOptimizing the Placement for a Timing-Critical Partition on
page 357.
If the partition designers provide the project lead with a post-synthesis .qxp and
fitting is performed in the top-level design, integrating the design partitions should be
quite easy. If you plan to develop a partition in a separate Quartus II project and
integrate the optimized post-fitting results into the top-level design, use the following
guidelines to improve the integration process:
Ensure that a LogicLock region constrains the partition placement and uses only
the resources allocated by the project lead.
Ensure that you know which clocks should be allocated to global routing resources
so that there are no resource conflicts in the top-level design.
Set the Global Signal assignment to On for the high fan-out signals that should
be routed on global routing lines.
To avoid other signals being placed on global routing lines, turn off Auto
Global Clock and Auto Global Register Controls under More Settings on the
Fitter page in the Settings dialog box. Alternatively, you can set the Global
Signal assignment to Off for signals that should not be placed on global
routing lines.
Placement for LABs depends on whether the inputs to the logic cells within the
LAB use a global clock. You may encounter problems if signals do not use
global lines in the partition, but use global routing in the top-level design.
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Use the Virtual Pin assignment to indicate pins of a partition that do not drive pins
in the top-level design. This is critical when a partition has more output ports than
the number of pins available in the target device. Using virtual pins also helps
optimize cross-partition paths for a complete design by enabling you to provide
more information about the partition ports, such as location and timing
assignments.
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When partitions are compiled independently without any information about each
other, you might need to provide more information about the timing paths that
may be affected by other partitions in the top-level design. You can apply location
assignments for each pin to indicate the port location after incorporation in the
top-level design. You can also apply timing assignments to the I/O ports of the
partition to perform timing budgeting.
f For more information about resource balancing and timing allocation between
partitions, refer to the Best Practices for Incremental Compilation Partitions and Floorplan
Assignments chapter in volume 1 of the Quartus II Handbook.
Determine appropriate timing and location assignments that help overcome the
limitations of team-based design. This requires examination of the logic in the
partitions to determine appropriate timing constraints.
Perform final timing closure and resource conflict avoidance in the top-level
design. Because the partitions have no information about each other, meeting
constraints at the lower levels does not guarantee they are met when integrated at
the top-level. It then becomes the project leads responsibility to resolve the issues,
even though information about the partition implementation may not be available.
Design partition scripts automate the process of transferring the top-level project
framework to partition designers in a flow where each design block is developed in
separate Quartus II projects before being integrated into the top-level design. If the
project lead cannot provide each designer with a copy of the top-level project
framework, the Quartus II software provides an interface for managing resources and
timing budgets in the top-level design. Design partition scripts make it easier for
partition designers to implement the instructions from the project lead, and avoid
conflicts between projects when integrating the partitions into the top-level design.
This flow also helps to reduce the need to further optimize the designs after
integration.
You can use options in the Generate Design Partition Scripts dialog box to choose
which types of assignments you want to pass down and create in the partitions being
developed in separate Quartus II projects.
For an example design scenario using design partition scripts, refer to Enabling
Designers on a Team to Optimize Independently on page 339.
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Exporting Partitions
When partition designers achieve the design requirements in their separate Quartus II
projects, each designer can export their design as a partition so it can be integrated
into the top-level design by the project lead. The Export Design Partition dialog box,
available from the Project menu, allows designers to export a design partition to a
Quartus II Exported Partition File (.qxp) with a post-synthesis netlist, a post-fit netlist,
or both. The project lead then adds the .qxp to the top-level design to integrate the
partition.
A designer developing a timing-critical partition or who wants to optimize their
partition on their own would opt to export their completed partition with a post-fit
netlist, allowing for the partition to more reliably meet timing requirements after
integration. In this case, you must ensure that resources are allocated appropriately to
avoid conflicts. If the placement and routing optimization can be performed in the
top-level design, exporting a post-synthesis netlist allows the most flexibility in the
top-level design and avoids potential placement or routing conflicts with other
partitions.
When designing the partition logic to be exported into another project, you can add
logic around the design block to be exported as a design partition. You can instantiate
additional design components for the Quartus II project so that it matches the
top-level design environment, especially in cases where you do not have access to the
full top-level design project. For example, you can include a top-level PLL in the
project, outside of the partition to be exported, so that you can optimize the design
with information about the frequency multipliers, phase shifts, compensation delays,
and any other PLL parameters. The software then captures timing and resource
requirements more accurately while ensuring that the timing analysis in the partition
is complete and accurate. You can export the partition for the top-level design without
any auxiliary components that are instantiated outside the partition being exported.
If your design team uses makefiles and design partition scripts, the project lead can
use the make command with the master_makefile command created by the scripts to
export the partitions and create .qxp files. When a partition has been compiled and is
ready to be integrated into the top-level design, you can export the partition with
option on the Export Design Partition dialog box, available from the Project menu.
h For more information about how to export a design partition, refer to Using a TeamBased Incremental Compilation Design Flow in the Quartus II Help.
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Global Assignments
The project lead should make all global project-wide assignments in the top-level
design. Global assignments from the exported partition's project are not added to the
top-level design. When it is possible for a particular constraint, the global assignment
is converted to an instance-specific assignment for the exported design partition.
LogicLock Region Assignments
The project lead typically creates LogicLock region assignments in the top-level
design for any lower-level partition designs where designer or IP providers plan to
export post-fit information to be used in the top-level design, to help avoid placement
conflicts between partitions. When you use the .qxp as a source file, LogicLock
constraints from the exported partition are applied in the top-level design, but will
not appear in your .qsf file or LogicLock Regions window for you to view or edit. The
LogicLock region itself is not required to constrain the partition placement in the
top-level design if the netlist type is set to Post-Fit, because the netlist contains all the
placement information. For information on how to control LogicLock region
assignments for exported partitions, refer to the Advanced Importing Options on
page 333.
If you want LogicLock regions in your top-level design (.qsf)If you have
regions in your partitions that are not also in the top-level design, the regions will
be added to your .qsf during the import process.
When you use the Import Design Partition dialog box to integrate a partition into the
top-level design, the import process sets the partitions netlist type to Imported in the
Design Partitions window.
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After you compile the entire design, if you make changes to the place-and-route
results (such as movement of an imported LogicLock region), use the Post-Fit netlist
type on subsequent compilations. To discard an imported netlist and recompile from
source code, you can compile the partition with the netlist type set to Source File and
be sure to include the relevant source code in the top-level design. Refer to Netlist
Type for Design Partitions on page 321 for details. The import process sets the
partitions Fitter Preservation Level to the setting with the highest degree of
preservation supported by the imported netlist. For example, if a post-fit netlist is
imported with placement information, the Fitter Preservation Level is set to
Placement, but you can change it to the Netlist Only value. For more information
about preserving previous compilation results, refer to Netlist Type for Design
Partitions on page 321 and Fitter Preservation Level for Design Partitions on
page 322.
When you import a partition from a .qxp, the .qxp itself is not part of the top-level
design because the netlists from the file have been imported into the project database.
Therefore if a new version of a .qxp is exported, the top-level designer must perform
another import of the .qxp.
When you import a partition into a top-level design with the Import Design Partition
dialog box, the software imports relevant assignments from the partition into the
top-level design, as described for the source file integration flow in Integrating
Assignments from the .qxp on page 332. If required, you can change the way some
assignments are imported, as described in the following subsections.
Importing LogicLock Assignments
LogicLock regions are set to a fixed size when imported. If you instantiate multiple
instances of a subdesign in the top-level design, the imported LogicLock regions are
set to a Floating location. Otherwise, they are set to a Fixed location. You can change
the location of LogicLock regions after they are imported, or change them to a
Floating location to allow the software to place each region but keep the relative
locations of nodes within the region wherever possible. For details, refer to Changing
Partition Placement with LogicLock Changes on page 346. To preserve changes
made to a partition after compilation, use the Post-Fit netlist type.
The LogicLock Member State assignment is set to Locked to signify that it is a
preserved region.
LogicLock back-annotation and node location data is not imported because the .qxp
contains all of the relevant placement information. Altera strongly recommends that
you do not add to or delete members from an imported LogicLock region.
Advanced Import Settings
The Advanced Import Settings dialog box allows you to disable assignment import
and specify additional options that control how assignments and regions are
integrated when importing a partition into a top-level design, including how to
resolve assignment conflicts.
h For descriptions of the advanced import options available, refer to Advanced Import
Settings Dialog Box in Quartus II Help.
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If you are using the Quartus II GUI, use the Export Design Partition
command.
5. Select the option to include just the Post-synthesis netlist if you do not have to
send placement information. If the recipient wants to reproduce your exact Fitter
results, you can select the Post-fitting netlist option, and optionally enable Export
routing.
6. Provide the .qxp to the recipient. Note that you do not have to send any of your
design source code.
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As the recipient in this example, first create a Quartus II project for your top-level
design and ensure that your project targets the same device (or at least the same
device family if the .qxp does not include placement information), as specified by the
IP designer sending the design block. Instantiate the design block using the port
information provided, and then incorporate the design block into a top-level design.
Add the .qxp from the IP designer as a source file in your Quartus II project to replace
any empty wrapper file. If you want to use just the post-synthesis information, you
can choose whether you want the file to be a partition in the top-level design. To use
the post-fit information from the .qxp, assign the instance as a design partition and set
the netlist type to Post-Fit. Refer to Creating Design Partitions on page 39 and
Netlist Type for Design Partitions on page 321.
Using a LogicLock region for the IP core allows the customer to create an
empty placeholder region to reserve space for the IP in the design floorplan
and ensures that there are no conflicts with the top-level design logic.
Reserved space also helps ensure the IP core does not affect the timing
performance of other logic in the top-level design. Additionally, with a
LogicLock region, you can preserve placement either absolutely or relative
to the origin of the associated region. This is important when a .qxp is
imported for multiple partition hierarchies in the same project, because in
this case, the location of at least one instance in the top-level design does
not match the location used by the IP provider.
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4. If required, add any logic (such as PLLs or other logic defined in the customers
top-level design) around the design hierarchy to be exported. If you do so, create a
design partition for the design hierarchy that will exported as an IP core.
5. Optimize the design and close timing to meet the design specifications.
6. Export the level of hierarchy for the IP core into a single .qxp.
7. Provide the .qxp to the customer. Note that you do not have to send any of your
design source code to the customer; the design netlist and placement and routing
information is contained within the .qxp.
As the customer in this example, incorporate the IP core in your design by performing
the following steps:
1. Create a Quartus II project for the top-level design that targets the same device
and instantiate a copy or multiple copies of the IP core. Use a black box wrapper
file to define the port interface of the IP core.
2. Perform Analysis and Elaboration to identify the design hierarchy.
3. Create a design partition for each instance of the IP core (refer to Creating Design
Partitions on page 354) with the netlist type set to Empty (refer to Netlist Type
for Design Partitions on page 321).
4. You can now continue work on your part of the design and accept the IP core from
the IP provider when it is ready.
5. Include the .qxp from the IP provider in your project to replace the empty
wrapper-file for the IP instance. Or, if you are importing multiple copies of the
design block and want to import relative placement, follow these additional steps:
a. Use the Import command to select each appropriate partition hierarchy. You
can import a .qxp from the GUI, the command-line, or with Tcl commands:
If you are using the Quartus II GUI, use the Import Design Partition
command.
b. When you have multiple instances of the IP block, you can set the imported
LogicLock regions to floating, or move them to a new location, and the
software preserves the relative placement for each of the imported modules
(relative to the origin of the LogicLock region). Routing information is
preserved whenever possible. Refer to Changing Partition Placement with
LogicLock Changes on page 346
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6. You can control the level of results preservation with the Netlist Type setting.
Refer to Netlist Type for Design Partitions on page 321.
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If the IP provider did not define a LogicLock region in the exported partition, the
software preserves absolute placement locations and this leads to placement conflicts
if the partition is imported for more than one instance.
Allow access to the full project for all designers through a source control
system. Each designer can check out the projects files as read-only and work on
their blocks independently. This design flow provides each designer with the
most information about the full design, which helps avoid resource conflicts
and makes design integration easy.
Provide a copy of the top-level Quartus II project framework for each designer.
You can use the Copy Project command on the Project menu or create a project
archive.
As the designer of a lower-level design block in this scenario, design and optimize
your partition in your copy of the top-level design, and then follow these steps when
you have achieved the desired compilation results:
1. On the Project menu, click Export Design Partition.
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2. In the Export Design Partition dialog box, choose the netlist(s) to export. You can
export a Post-synthesis netlist if placement or performance preservation is not
required, to provide the most flexibility for the Fitter in the top-level design. Select
Post-fit netlist to preserve the placement and performance of the lower-level
design block, and turn on Export routing to include the routing information, if
required. One .qxp can include both post-synthesis and post-fitting netlists.
3. Provide the .qxp to the project lead.
Finally, as the project lead in this scenario, perform these steps to integrate the .qxp
files received from designers of each partition:
1. Add the .qxp as a source file in the Quartus II project, to replace any empty
wrapper file for the previously Empty partition.
2. Change the netlist type for the partition from Empty to the required level of results
preservation.
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5. Provide the constraints from the top-level design to partition designers using one
of the following procedures:.
As the designer of a lower-level design block in this scenario, perform the appropriate
set of steps to successfully export your design, whether the design team is using
makefiles or exporting and importing the design manually.
If you are using makefiles with the design partition scripts, perform the following
steps:
1. Use the make command and the makefile provided by the project lead to create a
Quartus II project with all design constraints, and compile the project.
2. The information about which source file should be associated with which partition
is not available to the software automatically, so you must specify this information
in the makefile. You must specify the dependencies before the software rebuilds
the project after the initial call to the makefile.
3. When you have achieved the desired compilation results and the design is ready
to be imported into the top-level design, the project lead can use the
master_makefile command to export this partition and create a .qxp, and then
import it into the top-level design.
If you are not using makefiles, perform the following steps:
1. If you are using design partition scripts, source the Tcl script provided by the
Project Lead to create a project with the required settings:
To source the Tcl script in the Quartus II software, on the Tools menu, click
Utility Windows to open the Tcl console. Navigate to the scripts directory, and
type the following command: source <filename> r
To source the Tcl script at the system command prompt, type the following
command: quartus_cdb -t <filename>.tcl r
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2. If you are not using design partition scripts, create a new Quartus II project for the
subdesign, and then apply the following settings and constraints to ensure
successful integration:
Make Virtual Pin assignments for ports which represent connections to core
logic instead of external device pins in the top-level design.
Make floorplan location assignments to the Virtual Pins so they are placed in
their corresponding regions as determined by the top-level design. This
provides the Fitter with more information about the timing constraints
between modules. Alternatively, you can apply timing I/O constraints to the
paths that connect to virtual pins.
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lead can address these conflicts by explicitly importing the partitions into the
top-level design, and using options in the Advanced Import Settings dialog box, as
described in Advanced Importing Options on page 333. After the project lead
obtains the .qxp for each lower-level design block from the other designers, use the
Import Design Partition command on the Project menu and specify the partition in
the top-level design that is represented by the lower-level design block .qxp. Repeat
this import process for each partition in the design. After you have imported each
partition once, you can select all the design partitions and use the Reimport using
latest import files at previous locations option to import all the files from their
previous locations at one time. To address assignment conflicts, the project lead can
take one or both of the following actions:
When LogicLock region assignment conflicts occur, the project lead may take one of
the following actions:
If the placement of different lower-level design blocks conflict, the project lead can
also set the set the partitions Fitter Preservation Level to Netlist Only, which allows
the software to re-perform placement and routing with the imported netlist.
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Use this flow if you re-optimize partitions exported from separate Quartus II projects
by incorporating additional constraints from the integrated top-level design.
The best way to provide top-level design information to designers of lower-level
partitions is to provide the complete top-level project framework using the following
steps:
1. For all partitions other than the one(s) being optimized by a designer(s) in a
separate Quartus II project(s), set the netlist type to Post-Fit.
2. Make the top-level design directory available in a shared source control system, if
possible. Otherwise, copy the entire top-level design project directory (including
database files), or create a project archive including the post-compilation database.
3. Provide each partition designer with a checked-out version or copy of the
top-level design.
4. The partition designers recompile their designs within the new project framework
that includes the rest of the design's placement and routing information as well
top-level resource allocations and assignments, and optimize as needed.
5. When the results are satisfactory and the timing requirements are met, export the
updated partition as a .qxp.
If this design flow is not possible, you can generate partition-specific scripts for
individual designs to provide information about the top-level project framework with
these steps:
1. In the top-level design, on the Project menu, click Generate Design Partition
Scripts, or launch the script generator from Tcl or the command line.
2. If lower-level projects have already been created for each partition, you can turn
off the Create lower-level project if one does not exist option.
3. Make additional changes to the default script options, as necessary. Altera
recommends that you pass all the default constraints, including LogicLock
regions, for all partitions and virtual pin location assignments. Altera also
recommends that you add a maximum delay timing constraint for the virtual I/O
connections in each partition.
4. The Quartus II software generates Tcl scripts for all partitions, but in this scenario,
you would focus on the partitions that make up the cross-partition critical paths.
The following assignments are important in the script:
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Virtual pin assignments for module pins not connected to device I/O ports in
the top-level design.
Location constraints for the virtual pins that reflect the initial top-level
placement of the pins source or destination. These help make the lower-level
placement aware of its surroundings in the top-level design, leading to a
greater chance of timing closure during integration at the top level.
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5. The partition designers source the file provided by the project lead.
To source the Tcl script from the Quartus II GUI, on the Tools menu, click
Utility Windows and open the Tcl console. Navigate to the scripts directory,
and type the following command: source <filename> r
To source the Tcl script at the system command prompt, type the following
command: quartus_cdb -t <filename>.tcl r
6. The partition designers recompile their designs with the new project information
or assignments and optimize as needed. When the results are satisfactory and the
timing requirements are met, export the updated partition as a .qxp.
The project lead obtains the updated .qxp files from the partition designers and adds
them to the top-level design. When a new .qxp is added to the files list, the software
will detect the change in the source file and use the new .qxp results during the next
compilation. If the project uses the advanced import flow, the project lead must
perform another import of the new .qxp.
You can now analyze the design to determine whether the timing requirements have
been achieved. Because the partitions were compiled with more information about
connectivity at the top level, it is more likely that the inter-partition paths have
improved placement which helps to meet the timing requirements.
Design floorplan assignments prevent the situation in which the Fitter must place a
partition in an area of the device where most resources are already used by other
partitions. A physical region assignment provides a reasonable region to re-place logic
after a change, so the Fitter does not have to scatter logic throughout the available
space in the device.
Floorplan assignments are not required for non-critical partitions compiled as part of
the top-level design. The logic for partitions that are not timing-critical (such as
simple top-level glue logic) can be placed anywhere in the device on each
recompilation, if that is best for your design.
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The simplest way to create a floorplan for a partitioned design is to create one
LogicLock region per partition (including the top-level partition). If you have a
compilation result for a partitioned design with no LogicLock regions, you can use the
Chip Planner with the Design Partition Planner to view the partition placement in the
device floorplan. You can draw regions in the floorplan that match the general
location and size of the logic in each partition. Or, initially, you can set each region
with the default settings of Auto size and Floating location to allow the Quartus II
software to determine the preliminary size and location for the regions. Then, after
compilation, use the Fitter-determined size and origin location as a starting point for
your design floorplan. Check the quality of results obtained for your floorplan
location assignments and make changes to the regions as needed. Alternatively, you
can perform synthesis, and then set the regions to the required size based on resource
estimates. In this case, use your knowledge of the connections between partitions to
place the regions in the floorplan.
Once you have created an initial floorplan, you can refine the region using tools in the
Quartus II software. You can also use advanced techniques such as creating
non-rectangular regions by merging LogicLock regions.
f For more information about when creating a design floorplan can be important, as
well as guidelines for creating the floorplan, refer to the Best Practices for Incremental
Compilation Partitions and Floorplan Assignments chapter in volume 1 of the Quartus II
Handbook.
You can use the Incremental Compilation Advisor to check that your LogicLock
regions meet Alteras guidelines, as described in Incremental Compilation Advisor
on page 319.
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When you set a new region Origin, the Fitter uses the new origin and replaces the
logic, preserving the relative placement of the member logic.
When you set the region Origin to Floating, the following conditions apply:
If the regions member placement is preserved with a Post-Fit netlist type, the
Fitter does not change the Origin location, and reuses the previous placement
results.
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When Placement and Routing May Not Be Preserved Exactly on page 347
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For design partitions that are being developed independently in separate Quartus II
projects and contain the logic analyzer, when you export the partition, the Quartus II
software automatically removes the SignalTap II logic analyzer and related SLD_HUB
logic. You can tap any nodes in a Quartus II project, including nodes within .qxp
partitions. Therefore, you can use the logic analyzer within the full top-level design to
tap signals from the .qxp partition.
You can also instantiate the SignalTap II megafunction directly in your lower-level
design (instead of using an .stp file) and export the entire design to the top level to
include the logic analyzer in the top-level design.
f For details about using the SignalTap II logic analyzer in an incremental design flow,
refer to the Design Debugging Using the SignalTap II Embedded Logic Analyzer chapter in
volume 3 of the Quartus II Handbook.
351
PLL settings and timing exceptions are not passed to lower-level designs in the
scripts. For suggestions on managing SDC constraints between top-level and
lower-level projects, refer to the Best Practices for Incremental Compilation Partitions and
Floorplan Assignments chapter in volume 1 of the Quartus II Handbook.
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Pin Assignments for GXB and LVDS Blocks in Design Partition Scripts
Pin assignments for high-speed GXB transceivers and hard LVDS blocks are not
written in the scripts. You must add the pin assignments for these hard IP blocks in
the lower-level projects manually.
353
The Quartus II software does not support creating a partition for any Quartus II
internal hierarchy that is dynamically generated during compilation to implement the
contents of a megafunction.
The path between the input pin and register includes only input ports of partitions
that have one fan-out each.
The following specific circumstances are required for output register cross-partition
register packing:
The path between the register and output pin includes only output ports of
partitions that have one fan-out each.
Output pins with an output enable signal cannot be packed into the device I/O cell if
the output enable logic is part of a different partition from the output register. To
allow register packing for output pins with an output enable signal, structure your
HDL code or design partition assignments so that the register and tri-state logic are
defined in the same partition.
Bidirectional pins are handled in the same way as output pins with an output enable
signal. If the registers that need to be packed are in the same partition as the tri-state
logic, you can perform register packing.
The restrictions on tri-state logic exist because the I/O atom (device primitive) is
created as part of the partition that contains tri-state logic. If an I/O register and its
tri-state logic are contained in the same partition, the register can always be packed
with tri-state logic into the I/O atom. The same cross-partition register packing
restrictions also apply to I/O atoms for input and output pins. The I/O atom must
feed the I/O pin directly with exactly one signal. The path between the I/O atom and
the I/O pin must include only ports of partitions that have one fan-out each.
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f For more information and examples of cross-partition boundary I/O packing, refer to
the Best Practices for Incremental Compilation Partitions and Floorplan Assignments
chapter in volume 1 of the Quartus II Handbook.
Scripting Support
You can run procedures and make settings described in this chapter in a Tcl script or
at a command-line prompt. This section provides scripting examples that cover some
of the topics discussed in this chapter.
Description
-h | -help
Short help
-long_help
Partition name
355
Description
OFF
ON
Specifying the Software Should Use the Specified Netlist and Ignore Source
File Changes
To specify that the software should use the specified netlist and ignore source file
changes, even if the source file has changed since the netlist was created, use the
following command:
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES ON
-section_id "<partition name>".
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357
flow
incremental_compilation
project
$project
#close project
project_close
h The options map to the same as those in the Quartus II software in the Generate
Design Partition Scripts dialog box. For detailed information about each option, refer
to Generate Design Partition Scripts Dialog Box in Quartus II Help.
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Exporting a Partition
To open a project and load the::quartus::incremental_compilation package before
you use the Tcl commands to export a partition to a .qxp that contains both a postsynthesis and post-fit netlist, with routing, use the following script:
# load required package
load_package incremental_compilation
# open project
project_open <project name>
# export partition to the .qxp and set preservation level
export_partition -partition <partition name>
-qxp <.qxp file name> -<options>
#close project
project_close
Makefiles
For an example of how to use incremental compilation with a makefile as part of the
team-based incremental compilation design flow, refer to the read_me.txt file
that accompanies the incr_comp example located in the
/qdesigns/incr_comp_makefile subdirectory.
h When using a team-based incremental compilation design flow, the Generate Design
Partition Scripts dialog box can write makefiles that automatically export lower-level
design partitions and import them into the top-level design whenever design files
change. For more information about the Generate Design Partition Scripts dialog
box, refer to Generate Design Partition Scripts Dialog Box in Quartus II Help.
Conclusion
With the Quartus II incremental compilation feature described in this chapter, you can
preserve the results and performance of unchanged logic in your design as you make
changes elsewhere. The various applications of incremental compilation enable you to
improve your productivity while designing for high-density FPGAs.
359
Version
November 2012
12.1.0
Changes
Added Turning On Supported Cross-boundary Optimizations on page 317.
June 2012
12.0.0
November 2011
11.0.1
Template update.
May 2011
11.0.0
Reorganized Tcl scripting section. Added description for new feature: Ignore partitions
assignments during compilation option.
Removed the explanation of the bottom-up design flow where designers work
completely independently, and replaced with Alteras recommendations for team-based
environments where partitions are developed in the same top-level project framework,
plus an explanation of the bottom-up process for including independent partitions from
third-party IP designers.
Expanded the Merge command explanation to explain how it now accommodates crosspartition boundary optimizations.
Added Viewing the Contents of a Quartus II Exported Partition File (.qxp) section.
Reorganized chapter to make design flow scenarios more visible; integrated into various
sections rather than at the end of the chapter.
Redefined the bottom-up design flow as team-based and reorganized previous design
flow examples to include steps on how to pass top-level design information to lower-level
designers.
Moved SDC Constraints from Lower-Level Partitions section to the Best Practices for
Incremental Compilation Partitions and Floorplan Assignments chapter in volume 1 of the
December 2010
July 2010
October 2009
10.1.0
10.0.0
9.1.0
Quartus II Handbook.
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360
Version
March 2009
9.0.0
November 2008
8.1.0
Changes
Added new section Including or Integrating Partitions into the Top-Level Design.
Removed section OpenCore Plus Feature for MegaCore Functions in Bottom-Up Flows
Added information about using a .qxp as a source design file without importing
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive
The Partial Reconfiguration (PR) feature in the Quartus II software allows you to
reconfigure a portion of the FPGA dynamically, while the remainder of the device
continues to operate. The Quartus II software supports the PR feature for the Altera
Stratix V device family. This chapter provides an overview of partial reconfiguration
and provides design guidelines for using this feature with supported FPGA devices.
1
For assistance with support for partial reconfiguration with the Arria V or
Cyclone V device families, file a service request at mySupport.
This chapter assumes a basic knowledge of Alteras FPGA design flow, incremental
compilation and LogicLock region features available in the Quartus II software. It
also assumes knowledge of the internal FPGA resources such as logic array blocks
(LABs), memory logic array blocks (MLABs), memory types (RAM and ROM), DSP
blocks, clock networks.
This chapter discusses the following topics:
Terminology on page 41
Terminology
This section describes commonly used terminology in this chapter.
project: A Quartus II project contains the design files, settings, and constraints files
required for the compilation of your design.
revision: In the Quartus II software, a revision is a set of assignments and settings for
one version of your design. A Quartus II project can have several revisions, and each
revision has its own set of assignments and settings. A revision helps you to organize
several versions of your design into a single project.
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its ISO
9001:2008
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
Registered
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
Feedback Subscribe
42
incremental compilation: This is a feature of the Quartus II software that allows you
to preserve results of previous compilations of unchanged parts of the design, while
changing the implementation of the parts of your design that you have modified since
your previous compilation of the project. The key benefits include timing preservation
and compile time reduction by only compiling the logic that has changed.
partition: You can partition your design along logical hierarchical boundaries. Each
design partition is independently synthesized and then merged into a complete netlist
for further stages of compilation. With the Quartus II incremental compilation flow,
you can preserve results of unchanged partitions at specific preservation levels. For
example, you can set the preservation levels at post-synthesis or post-fit, for iterative
compilations in which some part of the design is changed. A partition is only a logical
partition of the design, and does not necessarily refer to a physical location on the
device. However, you may associate a partition with a specific area of the FPGA by
using a floorplan assignment.
f For more information on design partitions, refer to the Best Practices for Incremental
Compilation Partitions and Floorplan Assignments chapter in the Quartus II Handbook.
LogicLock region: A LogicLock region constrains the placement of logic in your
design. You can associate a design partition with a LogicLock region to constrain the
placement of the logic in the partition to a specific physical area of the FPGA.
f For more information about LogicLock regions, refer to the Analyzing and Optimizing
the Design Floorplan with the Chip Planner chapter in the Quartus II Handbook.
PR project: Any Quartus II design project that uses the PR feature.
PR region: A design partition with an associated contiguous LogicLock region in a PR
project. A PR project can have one or more PR regions that can be partially
reconfigured independently. A PR region may also be referred to as a PR partition.
static region: The region outside of all the PR regions in a PR project that cannot be
reprogrammed with partial reconfiguration (unless you reprogram the entire FPGA).
This region is called the static region, or fixed region.
persona: A PR region has multiple implementations. Each implementation is called a
persona. PR regions can have multiple personas. In contrast, static regions have a
single implementation or persona.
PR control block: Dedicated block in the FPGA that processes the PR requests,
handshake protocols, and verifies the CRC.
43
Core
Fabric
Transceivers,
PCIe HIP
Transceivers,
PCIe HIP
PLL
CLK
I/O, I/O Registers & Part-Hard Memory PHY
Periphery
Core Fabric
Table 41 describes the reconfiguration type supported by each FPGA resource block,
which are shown in Figure 41.
Table 41. Reconfiguration Modes of the FPGA Resource Block
Hardware Resource Block
Reconfiguration Mode
Logic Block
Partial Reconfiguration
Partial Reconfiguration
Memory Block
Partial Reconfiguration
Transceivers
PLL
Core Routing
Partial Reconfiguration
Clock Networks
Not supported
f The transceivers and PLLs in Altera FPGAs can be reconfigured using dynamic
reconfiguration. For more information on dynamic reconfiguration, refer to the
Dynamic Reconfiguration in Stratix V Devices chapter in the Stratix V Handbook.
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44
Chip_top
PR Region A
PR Module A2
PR Module A3
Static
Region
PR Region B
PR Module B1
PR Module B2
45
SCRUB Mode
In the SCRUB mode, the unchanging CRAM bits from the static region are "scrubbed"
back to their original values. They are neither erased nor reset. The static regions
controlled by the CRAM bits from the same programming frame as the PR region
continue to operate. All the CRAM bits corresponding to a PR region are overwritten
with new data, regardless of what was previously contained in the region.
The SCRUB mode of partial reconfiguration involves re-writing all the bits in an entire
LAB column of the CRAM, including bits controlling any PR regions above or below
the region being reconfigured. As a result, it is not currently possible to correctly
determine the bits associated with a PR region above or below the region being
reconfigured, because those bits could have already been reconfigured and changed
to an unknown value. This restriction does not apply to static bits above or below the
PR region, since those bits never change and you can rewrite them with the same
value as the current state of the configuration bit. You cannot use the SCRUB mode
when two PR regions have a vertically overlapping column in the device.
The advantage of using the SCRUB mode is that the programming file size is much
smaller than the AND/OR mode.
Figure 43 shows the floorplan of a FPGA using SCRUB mode, with two PR regions,
whose columns do not overlap.
Figure 43. Partial Reconfiguration SCRUB Mode
Programming Frame(s)
(No Vertical Overlap)
PR1
Region
PR2
Region
AND/OR Mode
The AND/OR mode refers to how the bits are rewritten. Partial reconfiguration with
AND/OR uses a two-pass method. Simplistically, this can be compared to bits being
ANDed with a MASK, and ORed with new values, allowing multiple PR regions to
vertically overlap a single column. In the first pass, all the bits in the CRAM frame for
a column passing through a PR region are ANDed with 0's while those outside the PR
region are ANDed with 1's. After the first pass, all the CRAM bits corresponding to
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46
the PR region are reset without modifying the static region. In the second pass for
each CRAM frame, new data is ORed with the current value of 0 inside the PR region,
and in the static region, the bits are ORed with 0's so they remain unchanged. The
programming file size of a PR region using the AND/OR mode could be twice the
programming file size of the same PR region using SCRUB mode.
Figure 44 shows two PR regions that overlap the same device columns using the
AND/OR mode.
Figure 44. Partial Reconfiguration AND/OR Mode
Programming Frame(s)
(Vertical Overlap)
PR1
Region
PR2
Region
If you have overlapping PR regions in your design, you must use AND/OR mode to
program all PR regions, including PR regions with no overlap. The Quartus II
software will not permit the use of SCRUB mode when there are overlapping regions.
If none of your regions overlap, you can use AND/OR, SCRUB, or a mixture of both.
The PR bitstream size is approximately half of the size computed above when using
SCRUB mode.
47
no
Is Timing Met
for Each Revision?
yes
no
May 2013
Functionality is
Verified?
Altera Corporation
yes
48
The PR design flow requires more initial planning than a standard design flow.
Planning requires setting up the design logic for partitioning, and determining
placement assignments to create a floorplan. Well-planned partitions can help
improve design area utilization and performance, and make timing closure easier. You
should also decide whether your system requires partial reconfiguration to originate
from the FPGA pins or internally, and which mode you are using; the AND/OR mode
or the SCRUB mode, because this influences some of the planning steps described in
this section.
You must structure your source code or design hierarchy to ensure that logic is
grouped correctly for optimization. Implementing the correct logic grouping early in
the design cycle is more efficient than restructuring the code later. The PR flow
requires you to be more rigorous about following good design practices. The
guidelines for creating partitions for incremental compilation also include creating
partitions for partial reconfiguration.
Use the following best practice guidelines for designing in the PR flow, which are
described in detail in this section:
Register all partition boundaries; register all inputs and outputs of each partition
when possible. This practice prevents any delay penalties on signals that cross
partition boundaries and keeps each register-to-register timing path within one
partition for optimization.
49
The Quartus II software can optimize some types of paths between design
partitions for non-PR designs. However, for PR designs, such inter-partition paths
are strictly not optimized.
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The following code sample has the component declaration in VHDL, showing the
ports of the Stratix V PR control block and the Stratix V CRC block. In Example 41,
the PR function is performed from within the core (code located in Core_Top) and you
must add additional ports to Core_Top to connect to both components.
Example 41. Component Declaration of the PR Control Block and CRC Block in VHDL
-- The Stratix V control block interface
component stratixv_prblock is
port(
corectl: in
STD_LOGIC ;
prrequest: in STD_LOGIC ;
data
: in STD_LOGIC_VECTOR(15 downto 0);
error : out STD_LOGIC ;
ready : out STD_LOGIC ;
done
: out STD_LOGIC
) ;
end component ;
-- The Stratix V CRC block for diagnosing CRC errors
component stratixv_crcblock is
port(
shiftnld: in STD_LOGIC ;
clk
: in STD_LOGIC ;
crcerror: out STD_LOGIC
) ;
end component ;
The following rules apply when connecting the PR control block to the rest of your
design:
The corectl signal must be set to 1 (when using partial reconfiguration from
core) or to 0 (when using partial reconfiguration from pins).
The corectl signal has to match the Enable PR pins option setting in the Device
and Pin Options dialog box on the Setting page; if you have turned on Enable PR
pins, then the corectl signal on the PR control block instantiation must be toggled
to 0.
When performing partial reconfiguration from core, you can connect the prblock
signals to either core logic or I/O pins, excluding the dedicated programming pin
such as DCLK.
Verilog HDL does not require a component declaration. You can instantiate the PR
control block as shown in Example 42 on page 411.
411
Example 42 shows how to instantiate PR control blocks inside your top-level project,
Chip_Top, in Verilog HDL:
Example 42. Instantiating the PR Control Block and CRC Block in Verilog HDL
module Chip_Top (
//User I/O signals (excluding PR related signals)
..
..
//PR interface & configuration signals
pr_request,
pr_ready,
pr_done,
crc_error,
dclk,
pr_data,
init_done
);
//user I/O signal declaration
..
..
//PR interface and configuration signals declaration
input pr_request;
output pr_ready;
output pr_done;
output crc_error;
input dclk;
input [15:0] pr_data;
output init_done
// Following shows the connectivity within the Chip_Top module
Core_Top : Core_Top
port_map (
..
..
);
m_pr : stratixv_prblock
port map(
clk => dclk,
corectl=> '0', //1 - when using PR from inside
//0 - for PR from pins; You must also enable
// the appropriate option in Quartus II settings
prrequest=> pr_request,
data
=> pr_data,
error => pr_error,
ready => pr_ready,
done
=> pr_done
);
m_crc : stratixv_crcblock
port map(
shiftnld=> '1', //If you want to read the EMR register when
clk=> dummy_clk,
//error occurrs, refer to AN539 for the
//connectivity forthis signal. If you only want
//to detect CRC errors, but plan to take no
//further action, you can tie the shiftnld
//signal to logical high.
crcerror=> crc_error
);
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Example 43 shows how to instantiate PR control blocks inside your top-level project,
Chip_Top, in VHDL.
Example 43. Instantiating the PR Control Block in VHDL (Part 1 of 2)
entity Chip_Top is
--PR INTERFACE & CONFIGURATION SIGNALS
port(
(pr_request:in STD_LOGIC;
dclk
:in STD_LOGIC;
pr_data
:in STD_LOGIC_VECTOR (15 downto 0);
pr_ready:out STD_LOGIC;
pr_done
:out STD_LOGIC;
crc_error:out STD_LOGIC;
init_done:out STD_LOGIC;
..
..
)
end Chip_top;
--declare all components to be instantiated
component Core_Top is
port( ..
..
);
end component ;
component stratixv_prblock is
port( corectl:in STD_LOGIC; --1 - when using PR from inside
--0 for PR from pins; You must also enable
--the appropriate option in Quartus II settings
clk:
in STD_LOGIC;
prrequest:in STD_LOGIC;
data: in STD_LOGIC_VECTOR (15 downto 0);
error: out STD_LOGIC;
ready: out STD_LOGIC;
done: out STD_LOGIC);
end component;
component stratixv_crcblock is
port(shiftnld:in STD_LOGIC;
clk:
in STD_LOGIC;
crcerror:out STD_LOGIC);
end component;
architecture struct of Chip_Top is
-- signal declaration
..
..
signal pr_error: STD_LOGIC;
signal crcblkclk: STD_LOGIC; -- this can be a dummy clock, but
-- if you want to read out EMR it
-- should be a real clock signal;
-- don't connect to dclk.
413
f For more information on port connectivity for reading the Error Message Register
(EMR), refer to AN539: Test Methodology of Error Detection and Recovery using CRC in
Altera FPGA Devices.
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414
The Quartus II software automatically instantiates a wire-LUT for each port of the PR
region to lock down the same location for all instances of the PR persona, as shown in
Figure 46.
Figure 46. Wire-LUTs at PR Region Boundary
Partial 1
Static Region
If one persona of your PR region has a different number of ports than others, then you
must create a wrapper so that the static region always communicates with this
wrapper. In this wrapper, you can create dummy ports to ensure that all of the PR
personas of a PR region have the same connection to the static region.
The sample code in Example 44 on page 415 and Example 45 on page 416 each
create two personas; persona_1 and persona_2 are different functions of one PR
region. Note that one persona has a few dummy ports.
415
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416
process (a, b, c, p)
begin
q <= (p*a - b*c);
end process;
end synth;
entity persona_2 is
port( a:in STD_LOGIC_VECTOR (2 downto 0);
b:in STD_LOGIC_VECTOR (2 downto 0);
c:in STD_LOGIC_VECTOR (2 downto 0); --never used in this persona
p:out STD_LOGIC_VECTOR (3 downto 0);
q:out STD_LOGIC_VECTOR (7 downto 0)); --never used in this
persona
end persona_2;
architecture synth of persona_2 is
begin
process(a, b)
begin
p <= a *b;
--note q is not assigned a value in this persona
end process;
end synth;
417
Freezing all non-global inputs for the PR region ensures there is no contention
between current values that may result in unexpected behavior of the design after
partial reconfiguration is complete. Global signals going into the PR region should not
be frozen to high.The Quartus II software freezes the outputs from the PR region;
therefore the logic outside of the PR region is not affected. Figure 47 shows how to
freeze the inputs.
Figure 47. Freezing at PR Region Boundary
Hardware-Generated
Freeze
Data1
1
PR Region
Data2
User PR_in_freeze
Global
Clocks
During partial reconfiguration, the static region logic should not depend on the
outputs from PR regions to be at a specific logic level for the continued operation of
the static region.
The easiest way to control the inputs to PR regions is by creating a wrapper around
the PR region in RTL. In addition to freezing all inputs high, you can also drive the
outputs from the PR block to a specific value, if required by your design. For example,
if the output drives a signal that is active high, then your wrapper could freeze the
output to GND.
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419
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PR regions are allowed to contain output ports that are used outside of the PR region
as global signals.
Global signals can only be used to route certain secondary signals into a PR region.
Table 42 shows the restrictions for each block. Data signals and other secondary
signals not listed in the table, such as synchronous clears and clock enables are not
supported
Table 42. Supported Signal Types for Driving Clock Networks in a PR Region
Block Types
LAB
Clock, ACLR
RAM
DSP
Clock, ACLR
If a global signal feeds both static and reconfigurable logic, the restrictions in
Table 42 also apply to destinations in the static region. For example, the same global
signal cannot be used as an SCLR in the static region and an ACLR in the PR region.
421
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422
1. From the Assignments menu, click Device, then click Device and Pin Options.
2. In the Device and Pin Options dialog box, select General in the Category list and
turn on Enable PR pins from the Options list.
3. Click Configuration in the Category list and select Passive Parallel x16 from the
Configuration scheme list.
4. Click OK, or continue to modify other settings in the Device and Pin Options
dialog box.
5. Click OK.
Table 43 lists the dedicated pins available for use with partial reconfiguration:
Table 43. Partial Reconfiguration Dedicated Pins Description
Pin Name
PR_REQUEST
PR_READY
PR_DONE
PR_ERROR
DATA[15:0]
DCLK
Pin Type
Input
Output
Output
Output
Input
Bidirectional
Pin Description
Dedicated input when Enable PR pins is turned on;
otherwise, available as user I/O.
Logic high on pin indicates the PR host is requesting
partial reconfiguration.
Dedicated output when Enable PR pins is turned on;
otherwise, available as user I/O.
Logic high on this pin indicates the Stratix V control block
is ready to begin partial reconfiguration.
Dedicated output when Enable PR pins is turned on;
otherwise, available as user I/O.
Logic high on this pin indicates that partial reconfiguration
is complete.
Dedicated output when Enable PR pins is turned on;
otherwise, available as user I/O.
Logic high on this pin indicates the device has
encountered an error during partial reconfiguration.
Dedicated input when Enable PR pins is turned on;
otherwise available as user I/O.
These pins provide connectivity for PR_DATA when Enable
PR pins is turned on.
Dedicated input when Enable PR pins is turned on;
PR_DATA is sent synchronous to this clock.
This is a dedicated programming pin, and is not available
as user I/O even if Enable PR pins is turned off.
f For a more detailed description of different configuration modes for Stratix V devices,
and specifically about FPPx16 mode, refer to the Configuration, Design Security, and
Remote System Upgrades in Stratix V Devices chapter of the Stratix V Handbook.
1
You can enable open drain on PR pins from the Device and Pins Options dialog box
in the Settings page of the Quartus II software.
423
PR Program
file (.rbf) in
external memory
PR Control
Block (CB)
Internal
Host
PR
Region
PR Control
Block (CB)
External
Host
PR
Region
The PR mode is independent of the full chip programming mode. For example, you
can configure the full chip using a JTAG download cable, or other supported
configuration modes. When configuring PR regions, you must use the FPPx16
interface to the PR control block whether you choose to partially reconfigure the chip
from an external or internal host.
When using an external host, you must implement the control logic for managing
system aspects of partial reconfiguration on an external device. By using an internal
host, you can implement all of your logic necessary for partial reconfiguration in the
FPGA, therefore external devices are not required to support partial reconfiguration.
When using an internal host, you can use any interface to load the PR bitstream data
to the FPGA, for example, from a serial or a parallel flash device, and then format the
PR bitstream data to fit the FPPx16 interface on the PR Control Block.
To use the external host for your design, turn on the Enable PR Pins option in the
Device and Pin Options dialog box in the Quartus II software when you compile
your design. If this setting is turned off, then you must use an internal host. Also, you
must tie the corectl port on the PR control block instance in the top-level of the
design to the appropriate level for the selected mode.
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Figure 49 shows the handshaking control signals used for partial reconfiguration.
When using an external host, the interface ports on the control block are mapped to
FPGA pins. When using an internal host, these signals are within the core of the
FPGA.
Figure 49. Partial Reconfiguration Interface Signals
From Pins or
FPGA Core
PR_Data[15:0]
PR_done
PR_ready
CRC_error
PR_error
PR_request
Clk
corectl
CRC_Error: The CRC_Error generated from the devices CRC block, is used to
determine whether to partially reconfigure a region again, when encountering a
CRC_Error.
PR_REQUEST: Sent from your control logic to CB indicating readiness to begin the
PR process.
425
Reconfiguring a PR Region
Figure 410 shows a system in which your PR Control logic is implemented inside the
FPGA. However, this section is also applicable for partial reconfiguration with an
external host. The PR control block (CB) represents the Stratix V PR controller inside
the FPGA. PR1 and PR2 are two PR regions in a user design. In addition to the four
control signals (PR_REQUEST, PR_READY, PR_DONE, PR_ERROR) and the data/clock signals
interfacing with the PR control block, your PR Control IP should also send a control
signal (PR_CONTROL) to each PR region. This signal implements the freezing and
unfreezing of the PR Interface signals. This is necessary to avoid contention on the
FPGA routing fabric.
Figure 410. Example of a PR System with Two PR Regions
Static Region
PR1
Region
PR2
Region
PR1_Control
PR2_Control
PR_Request
PR Control
Block (CB)
PR Control Logic
PR_Ready, PR_Error,
PR_Done, CRC_Error
Partial Reconfiguration
Data/Clock via FPPx16
After the FPGA device has been configured with a full chip configuration at least
once, the INIT_DONE signal is released, and the signal is asserted high due to the
external resistor on this pin. The INIT_DONE signal must be assigned to a pin to
monitor it externally. When a full chip configuration is complete, and the device is in
user mode, the following steps describe the PR sequence:
1. Begin a partial reconfiguration process from your PR Control logic, which initiates
the PR process for one or more of the PR regions (asserting PR1_Control or
PR2_Control in Figure 410). The wrapper HDL described earlier freezes (pulls
high) all non-global inputs of the PR region before the PR process.
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2. Send PR_REQUEST signal from your control logic to the PR Control Block (CB). If
your design uses an external controller, monitor INIT_DONE to verify that the chip
is in user mode before asserting the PR_REQUEST signal. The CB initializes itself to
accept the PR data and clock stream. After that, the CB asserts a PR_READY signal to
indicate it can accept PR data. Exactly four clock cycles must occur before sending
the PR data to make sure the PR process progresses correctly. Data and clock
signals are sent to the PR control block to partially reconfigure the PR region
interface.
If there are multiple PR personas for the PR region, your PR Control IP must
determine the programming file data for partial reconfiguration.
When there are multiple PR regions in the design, then the same PR control IP
determines which regions require reconfiguration based on system
requirements.
At the end of the PR process, the PR control block asserts a PR_DONE signal and
de-asserts the PR_READY signal.
If you want to suspend sending data, you can implement logic to pause the
clock at any point.
3. Your PR control logic must de-assert the PR_REQUEST signal within eight clock
cycles after the PR_DONE signal goes high. If your logic does not de-assert the
PR_REQUEST signal within eight clock cycles, a new PR cycle starts.
4. If your design includes additional PR regions, repeat steps 2 3 for each region.
Otherwise, proceed to step 5.
5. Your PR Control logic de-asserts the PR_CONTROL signal(s) to the PR region. The
freeze wrapper releases all input signals of the PR region, thus the PR region is
ready for normal user operation.
6. You must perform a reset cycle to the PR region to bring all logic in the region to a
known state. After partial reconfiguration is complete for a PR region, the states in
which the logic in the region come up is unknown.
The PR event is now complete, and you can resume operation of the FPGA with the
newly configured PR region.
At any time after the start of a partial reconfiguration cycle, the PR host can suspend
sending the PR_DATA, but the host must suspend sending the PR_CLK at the same time.
If the PR_CLK is suspended after a PR process, there must be at least 20 clock cycles
after the PR_DONE or PR_ERROR signal is asserted to prevent incorrect behavior.
Table 44 on page 427 contains other clock requirements for partial reconfiguration.
f For an overview of different reset schemes in Altera devices, please refer to the
Recommended Design Practices chapter in the Quartus II Handbook.
427
4 (exact)
20 (minimum)
20 (minimum)
DONE_to_REQ_low
8 (maximum)
At any time during partial reconfiguration, to pause sending PR_DATA, the PR host can
stop toggling PR_CLK. The clock can be stopped either high or low.
At any time during partial reconfiguration, the PR host can terminate the process by
de-asserting the PR request. A partially completed PR process results in a PR error.
You can have the PR host restart the PR process after a failed process by sending out a
new PR request 20 cycles later.
In case you terminate a PR process before completion, and follow it up with a FPGA
reset using the nConfig signal, you must keep the PR_CLK signal running through the
FPGA reset cycle to avoid causing the partial reconfiguration to lock up.
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Figure 411 shows the partial reconfiguration cycle waveform for the hand-shaking
protocol.
Figure 411. Partial Reconfiguration Timing Diagram
DONE_to_REQ_low
PR_REQUEST
PR_CLK
READY_to_FIRST_DATA
PR_DATA[15:0]
Dn-1MSW DnLSW
DnLSW
DONE_to_LAST_CLK
PR_READY
PR_DONE
PR_ERROR
CRC_ERROR
During these steps, the PR control block might assert a PR_ERROR or a CRC_ERROR
signal to indicate that there was an error during the partial reconfiguration process.
Assertion of PR_ERROR indicates that the PR bitstream data was corrupt, and the
assertion of CRC error indicates a CRAM CRC error either during or after completion
of PR process. If the PR_ERROR or CRC_ERROR signals are asserted, you must plan
whether to reconfigure the PR region or reconfigure the whole FPGA, or leave it
unconfigured.
429
Figure 412 shows the connection setup for partial reconfiguration with an external
host in the FPPx16 configuration scheme.
Figure 412. Connecting to an External Host
Memory
VCCPGM
VCCPGM
VCCPGM
ADDR DATA[15:0]
10 KW
10 KW
10 KW
Stratix V Device
External Host
(MAX V Device or
Microprocessor)
CONF_DONE
nSTATUS
nCONFIG
nCE
MSEL[4:0]
DATA[15:0}
DCLK
PR_REQUEST
PR_DONE
PR_READY
PR_ERROR
PR_CONTROL
PR_RESET
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Memory
Address
External
Host
DATA[7:0]
DATA[15:0]
PR_REQUEST1
PR_DONE1
PR_READY1
PR_ERROR1
PR_REQUEST
PR_DONE
PR_READY
PR_ERROR
FPGA1
DATA[15:0]
nCE
PR_REQUEST
PR_DONE
PR_READY
PR_ERROR
FPGA2
PR_REQUEST2
PR_DONE2
PR_READY2
PR_ERROR2
DATA[15:0]
nCE
PR_REQUEST5
PR_DONE5
PR_READY5
PR_ERROR5
PR_REQUEST
PR_DONE
PR_READY
PR_ERROR
FPGA5
431
The PR dedicated pins (PR_REQUEST, PR_READY, PR_DONE, and PR_ERROR) can be used as
regular I/Os when performing partial reconfiguration with an internal host. For the
full FPGA configuration upon power-up, you can set the MSEL[4:0] pins to match the
configuration scheme, for example, AS, PS, FPPx8, FPPx16, or FPPx32. Alternatively,
you can use the JTAG interface to configure the FPGA device. At any time during
user-mode, you can initiate partial reconfiguration through the FPGA core fabric
using the PR internal host.
Figure 414 shows an example of the configuration setup when performing partial
reconfiguration using the internal host. In this example, the programming bitstream
for partial reconfiguration is received through the PCI Express link, and your logic
converts the data to the FPPx16 mode.
Figure 414. Connecting to an Internal Host
VCCPGM
10 KW
VCCPGM
10 KW
VCCPGM
10 KW
Stratix V Device
nSTATUS
CONF_DONE
nCONFIG
nCE
MSEL[4:0]
PR
Controller
EPCS
DATA
DCLK
nCS
ASDI
AS_DATA1
DCLK
nCSO
ASDO
User Logic
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433
When you want to encrypt the bitstreams, you can encrypt the PR images only
when the base image is encrypted.
The Encryption Key Programming (.ekp) file generated when encrypting the base
image must be used for encrypting PR bitstream.
Base
Revision with
Persona a
Partial
Reconfiguration
Design
pr_region.msf
static.msf
base.sof
Revision b
Revision c
b.sof
b.msf
c.sof
c.msf
When these individual revisions are compiled in the Quartus II software, the
assembler produces Masked SRAM Object Files (.msf) and the SRAM Object Files
(.sof) for each revision, as shown in Figure 415. The .sof files are created as before
(for non-PR designs). Additionally, .msf files are created specifically for partial
reconfiguration, one for each revision. The pr_region.msf file is the one of interest for
generating the PR bitstream. It contains the mask bits for the PR region. Similarly, the
static.msf file has the mask bits for the static region. The .sof files have the
information on how to configure the static region as well as the corresponding PR
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region. The pr_region.msf file is used to mask out the static region so that the
bitstream can be computed for the PR region. The default file name of the
pr_region.msf corresponds to the location of the PR region unless the associated
LogicLock region has a non-default name. In that case, the .msf file is named after the
region.
1
c_pr_region
.msf
pr_region.msf
a.pmsf
b_pr_region
.msf
b.pmsf
b.sof
base.sof
c.pmsf
c.sof
Once all the .pmsf files are created, process the PR bitstreams by running the
quartus_cpf -o command to produce the raw binary .rbf files for reconfiguration.
Figure 417 shows how three bitstreams can be created to partially reconfigure the
region with persona a, persona b, or persona c as desired.
If one wishes to partially reconfigure the PR region with persona a, use the a.rbf
bitstream file, and so on for the other personas.
Figure 417. Generating PR Bitstreams
a.rbf
a.pmsf
b.pmsf
b.rbf
c.pmsf
c.rbf
In the Quartus II software, the Convert Programming Files window supports the
generation of the required programming bitstreams. This is described Generating PR
Programming Files Using the CPF GUI on page 435. When using the quartus_cpf
from the command line, the following options for generating the programming files
are read from an option text file, for example, option.txt.
If you want to use SCRUB mode, before generating the bitstreams create an option
text file, with the following line:
use_scrub=on
435
If you have initialized M20K blocks in the PR region (ROM/Initialized RAM), then
add the following line in the option text file, before generating the bitstreams:
write_block_memory_contents=on
If you want to compress the programming bitstream files, add the following line in
the option text file. This option is available when converting base .sof to any
supported programming file types, such as .rbf, .pof and JTAG Indirect
Configuration File (.jic).
bitstream_compression=on
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4. Select input files to convert (only a single .msf and .sof file are allowed). Click
Add.
5. Click Generate to generate the .pmsf file.
Write memory contents: Turn this on when you have a .mif file that was used
during compilation. Otherwise, turning this option on forces you to use double
PR.
Generate encrypted bitstream: If this option is enabled, you must specify the
Encrypted Key Programming (.ekp) file, which generated when converting a
base .sof to an encrypted bitstream. The same .ekp must be used to encrypt the
PR bitstream.
When you turn on Compression, you must present each PR_DATA[15:0] word for
exactly four clock cycles. Other timing requirements shown in Figure 411 on
page 428 are listed in Table 45 for bitstream compression.
Table 45. Partial Reconfiguration Clock Requirements for Bitstream Compression
Timing Parameters
4 (exact)
80 (minimum)
80 (minimum)
DONE_to_REQ_low
8 (maximum)
Turn on the Write memory contents option only if you have M20K blocks in your PR
design that need to be initialized. When you check this box, you must to perform
double PR for regions with initialized M20K blocks. For more information, refer to
Using Double PR Cycle for Initializing M20K blocks on page 445.
437
PR Region
with Signals to
Be Probed
Brought Out
on the Ports
The Quartus II software does not support the Incremental SignalTap feature for PR
designs. After you instantiate the SignalTap II block inside the static region, you must
recompile your design. When you recompile your design, the static region may have a
modified implementation and you must also recompile your PR revisions. If you
modify an existing SignalTap II instance you must also recompile your entire design;
base revision and reconfigurable revisions.
You can use other on-chip debug features in the Quartus II software, such as the InSystem Sources and Probes or SignalProbe, to debug a PR design. As in the case of
SignalTap, In-System Sources and Probes can only be instantiated within the static
region of a PR design. If you have to probe any signal inside the PR region, you must
bring those signals to the ports of the PR region in order to monitor them within the
static region of the design.
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439
If the functionality of the static region depends on any data read out from M20K
RAMs in the static region, the design will malfunction. Figure 419 shows this
limitation.
Figure 419. Limitations for Using M20Ks in PR Regions
Stratix V Device
PR
Region
Static
Region
No Restrictions for RAM/ROM
Implementation in These M20K Columns
Use one of the following workarounds, which are applicable to both AND/OR and
SCRUB modes of partial reconfiguration:
May 2013
If this is not possible for your design, you can program the memory content for
M20K blocks with a .mif using the suggested workarounds.
Make sure your PR region extends vertically all the way through the device, in
such a way that the M20K column lies entirely inside a PR region.
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440
Figure 420 shows the LogicLock region extended as a rectangle reducing the area
available for the static region. However, you can create non-rectangular LogicLock
regions for optimally allocating the required resources for the partition. If area
saving is a concern, extend the LogicLock region to includes M20K columns
entirely.
Static
Region
Block all the M20K columns not inside a PR region, but are in columns above or
below a PR region, using Reserved LogicLock Regions as shown in Figure 421. In
this case, you may choose to under-utilize M20K resources, for gaining ROM
functionality within the PR region.
Static
Region
441
f For more information, including a list of the Stratix V devices that have this limitation,
refer to the Stratix V Errata Sheet and Guidelines.
MLAB blocks contain 640 bits of memory. The LUT RAMs in PR regions in
your design must occupy all MLAB bits, you should not use partial MLABs.
You must include control logic in your design with which you can write to all
MLAB locations used inside the PR region.
Using this control logic, write '1' at each MLAB RAM bit location in the PR
region before starting the PR process. This is to work around a false EDCRC
error during partial reconfiguration.
When using the AND-OR mode, you must also specify a .mif that sets all
MLAB RAM bits to 1 immediately after PR is complete. When using SCRUB
mode, you do not have to use a .mif.
LUT-RAMs with initialized content in MLABs are supported only when using the
SCRUB mode of partial reconfiguration, but with the following caveat.
There are no restrictions to using MLABs in the static region of your PR design.
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MLAB blocks contain 640 bits of memory. The LUT RAMs in PR regions in
your design must occupy all MLAB bits, you should not use partial MLABs.
You must include control logic in your design with which you can write to all
MLAB locations used inside PR region.
Using this control logic, write '1' at each MLAB RAM bit location in the PR
region before starting the PR process. This is to work around a false EDCRC
error during partial reconfiguration.
You must also specify a .mif that sets all MLAB RAM bits to 1 immediately
after PR is complete.
There are no restrictions to using MLABs in the static region of your PR design.
SCRUB mode
Type of memory in
PR region
Stratix V ES (1)
OK
No
OK
No
No
(1) Stratix V ES devices require the listed workarounds. For more information refer to the Stratix V ES Errata Sheet and
Guidelines in the Stratix V handbook.
(2) Stratix V production devices require the listed workarounds. For more information refer to the Stratix V Errata
Sheet and Guidelines in the Stratix V handbook.
443
ES Devices
Mode
AND/OR
SCRUB
AND/OR
While design is
running: Write
1 to all
locations before
partial
reconfiguration.
LUT-RAM
without
initialization
Suggested
Method
At compile
time: Explicitly
initialize all
memory
locations in
each new
persona to 1
via initialization
file (.mif)
SCRUB
Make sure no
spurious write
on PR entry (1)
Without
Suggested
Method
LUT-RAM
with
initialization
Suggested
Method
Without
Suggested
Method
M20K
without
initialization
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CRC Error
Not
supported
N/A
CRC Error
Make sure no
spurious write
on PR exit (1)
Make sure no
spurious write
on PR entry
Not
supported
Incorrect
results
Make sure no
spurious write
on PR exit (1)
Incorrect
results
Suggested
Method
Without
Suggested
Method
N/A
444
ES Devices
Mode
AND/OR
M20K
with
initialization
Suggested
Method
SCRUB
AND/OR
Use double PR
cycle (2)
Use double PR
cycle (2)
Make sure no
spurious write
on PR exit (1)
Make sure no
spurious write
on PR exit (1)
Without
Suggested
Method
SCRUB
Incorrect results
Note to table:
(1) Use the circuit shown in Figure 422 to create clock enable logic to safely exit partial reconfiguration without
spurious writes.
(2) Double partial reconfiguration is describe in Using Double PR Cycle for Initializing M20K blocks on page 445.
To avoid spurious writes during PR entry and exit, implement the following clock
enable circuit in the same PR region as the RAM. The circuit depends on an activehigh clear signal from the static region. Before entering PR, freeze this signal in the
same manner as all PR inputs. Your host control logic should de-assert the clear signal
as the final step in the PR process.
Figure 422. M20K/LUTRAM
M20K/LUTRAM
D
Clock Enable
Logic
SET
CLR
1
SET
CLR
SET
CLR
CE
Clear Signal to
Safely Exit PR
445
PR_READY
PR_DONE
PR_ERROR
CRC_ERROR
Figure 423 displays the second phase of a double PR cycle, where the host logic must
issue another PR_REQUEST signal after exactly seven clock cycles after the PR_DONE
signal is asserted. If the PR compression feature is enabled, the host logic must issue
another PR_REQUEST signal exactly two clock cycles after PR_DONE is asserted. The
FPGA responds with PR_READY signal to the second PR_REQUEST signal assertion.
The PR host must continue sending PR_DATA signal exactly four clock cycles after the
PR_READY signal, just as in the first PR cycle. The data on PR_DATA pins can be don't
care between the first PR_DONE signal and until four clock cycles after the PR_READY
signal is asserted for the second PR cycle.
The host must continue sending a PR_DATA signal for the second PR cycle, until it
receives the PR_DONE signal for the second request, similar to the first PR cycle. After
the PR_DONE signal is asserted for the second time, the host should de-assert the
PR_REQUEST signal and continue with other operations needed for region bring up,
such as issuing a reset to bring the region to a known state.
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Version
May 2013
13.0.0
November 2012
12.1.0
Changes
Added support for encrypted bitstreams.
Updated support for double PR.
Initial release.
This chapter describes the flow for designing HardCopy series devices in the
Quartus II software.
Altera HardCopy ASICs are the lowest risk, lowest total cost ASICs. The HardCopy
system development methodology offers fast time-to-market, low risk, and with the
Quartus II software, you can design with one set of RTL code and one set of IP for
both FPGA and ASIC implementations. This flow enables you to conduct true
hardware/software co-design and completely prepare your system for production
prior to ASIC design hand-off. Altera provides a turn-key process to convert your
design to a HardCopy ASIC for production.
In this chapter, the term FPGA refers to a Stratix II, Stratix III, or Stratix IV device,
which is the prototype device for a HardCopy II, HardCopy III, or HardCopy IV
device, respectively.
This chapter discusses the following topics:
f For more information about HardCopy series devices, refer to the respective
HardCopy device handbook, which is available on the Literature page of the Altera
website at www.altera.com.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Feedback Subscribe
52
Seamless prototyping using an FPGA for at-speed system verification and system
development, which reduces total project development time and cost
Unified design methodology for FPGA and HardCopy designs reduces the need
for ASIC development software and two sets of intellectual property, which
reduces project risk
FPGA first flowDesign the FPGA first for in-system verification, and then create
a HardCopy companion device second. Performing system verification early helps
reduce overall total project development time. The FPGA first flow is the default
flow and the rest of this chapter is based on this flow.
HardCopy first flowDesign the HardCopy device first, and then create the
FPGA companion device second for in-system verification. This method more
accurately predicts the maximum performance of the HardCopy device during
development. If you optimize your design to maximize HardCopy performance,
but cannot meet your performance requirements with the FPGA, you can still map
your design with decreased performance requirements for in-system verification.
53
Design
FPGA
First?
No
Complete FPGA
Device First Flow (1)
Select HardCopy
Device & FPGA
Companion Device
Complete HardCopy
Device First Flow (2)
In-System Verification
of FPGA Design
Compare FPGA
& HardCopy
Design Revisions
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Any
Violations?
Yes
Fix Violations
No
Create or Overwrite HardCopy
Companion Revision
Select a Larger
HardCopy Companion
Device
No
Fits in
HardCopy Device?
Yes
Compare FPGA and HardCopy Revisions
Any
Violations?
Yes
No
Design Submission & Back-End Implementation Phase
55
Any
Violations?
Yes
Fix Violations
No
Create or Overwrite FPGA
Companion Revision
In-System Verification
Any
Violations?
Yes
No
Design Submission & Back-End Implementation Phase
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HardCopy Advisor
The HardCopy Advisor provides an interactive list of tasks to help you through the
development of your FPGA prototype and HardCopy design. The following tasks
highlight the checkpoints that the HardCopy Advisor reviews, which includes the
major checkpoints in the design process, but not every step in the process.
1. Select an FPGA device.
2. Select a HardCopy companion device.
3. Set up the FPGA revision.
4. Confirm FPGA junction temperature range settings (HardCopy III and
HardCopy IV devices only).
5. Compile and check the FPGA design.
6. Create or overwrite the HardCopy companion revision.
7. Confirm HardCopy junction temperature range settings (HardCopy III and
HardCopy IV devices only).
8. Compile and check the HardCopy companion results.
9. Compare companion revisions.
10. Generate a HardCopy Handoff report.
11. Archive handoff files and send them to Altera.
h For more information about the HardCopy Advisor in the Quartus II software, refer to
About the HardCopy Advisor in Quartus II Help.
HardCopy Utilities
The HardCopy Utilities menu contains the main functions you use to develop your
HardCopy design and FPGA prototype companion revision. To access this menu in
the Quartus II software, on the Project menu, click HardCopy Utilities. Each
HardCopy Utilities menu feature is summarized in Table 51.
Table 51. HardCopy Utilities Menu Options (Part 1 of 2)
Option
Description
Restrictions
Create/Overwrite
HardCopy Companion
Revision
Compare HardCopy
Companion Revisions
57
Generate HardCopy
Handoff Report
Archive HardCopy
Handoff Files
Description
Generates a report containing
important design information
files and messages generated by
the Quartus II Compiler
Restrictions
HardCopy companion
revision
Start HardCopy
Design Readiness
Check
None
HardCopy Advisor
None
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Green
(High)
Package Resource
(1)
Orange
(Medium)
Red
(None)
Device Resources
The resource quantity is within the range of the
HardCopy device and the design can likely map if all
other resources also fit.
You still must compile the HardCopy revision to
ensure the design is able to route and close timing.
The resource quantity is within the range of the
HardCopy device; however, the resource is at risk of
exceeding the range for the HardCopy package.
Compile your design targeting the HardCopy device
as soon as possible to check if the design fits and is
able to route and migrate all other resources. You
might have to select a larger device.
The resource quantity exceeds the range of the
HardCopy device. The design cannot migrate to this
HardCopy device.
Use this report to identify potential HardCopy device candidates for your design. The
HardCopy and FPGA device packages must be compatible. A logic resource usage
greater than 100% or a ratio greater than 1:1 in a category indicates that the design will
probably not fit in that specific HardCopy device.
The HardCopy architecture consists of an array of fine-grained HCells to build logic
equivalent to FPGA adaptive logic modules (ALMs) and digital signal processing
(DSP) blocks. The DSP blocks in HardCopy devices match the functionality of the
FPGA DSP blocks, though timing of these blocks is different than the FPGA DSP
blocks because they are constructed of HCell macros.
Memory blocks in HardCopy devices and FPGAs are equivalent. Preliminary timing
reports of the HardCopy device are available in the Quartus II software. Final timing
results of the HardCopy device are provided by the Altera HardCopy Design Center
after the HardCopy back-end implementation process is complete.
h For more information about the HardCopy device resources, refer to Fitter Resources
Reports in Quartus II Help.
59
f For more information about the HardCopy device resources, refer to the respective
HardCopy series device handbook, which is available on the Literature page of the
Altera website at www.altera.com.
The report example in Figure 54 shows the resource comparisons for a design
compiled for an EP4SE230F29C2 device. Based on the report, the HC4E25FF484
device in the 484-pin FineLine BGA package is an appropriate HardCopy device. The
EP4SE230F29C2 device is rated green because the device is specified as a migration
target in the example. If the HC4E25FF484 device is not specified as a migration target
during the compilation, its package and migration compatibility is rated medium
(orange). The migration compatibilities of the other HardCopy devices are rated none
(red), because the package types are incompatible with the FPGA device.
Figure 54. HardCopy Device Resource Guide with Target Migration Enabled
For example, to select the HC4E25FF484 device as your HardCopy companion device
for the EP4SE230F29C2 FPGA, use the following the Tcl command:
set_global_assignment -name\
DEVICE_TECHNOLOGY_MIGRATION_LIST HC4E25FF484C
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Altera recommends turning on the Design Assistant to run automatically during each
compilation so that you can review the violations to determine which errors you must
fix or which you can waive, iteratively.
h For more information about the Design Assistant and its rules in the Quartus II
software, refer to About the Design Assistant in Quartus II Help.
511
To ensure that the HardCopy mapping is successful, you must make accurate I/O
assignments that include pin locations, I/O standards, drive strengths, and
capacitance loading for the design. Ensure that the I/O assignments are compatible
with all selected devices. Altera recommends assigning I/O assignments for all I/O
pins. Leaving unassigned I/O assignments may result in incompatible assignments.
When mapping between the FPGA device and a HardCopy device, the I/O pin
location must be assigned to the available common groups, called modular I/O
banks, for both devices. Because HardCopy devices have fewer I/O banks than FPGA
devices, the Quartus II software limits the I/O banks to only those available in
HardCopy devices.
f For more information about I/O banks and pins in HardCopy series devices, refer to
the respective HardCopy series device handbook, which is available on the Literature
page of the Altera website at www.altera.com.
HardCopy III I/O buffers support only the 3.0-V I/O standard with a maximum
supply voltage (VCCIO) of 3.0 V. Therefore, when specifying the I/O standard for the
Stratix III FPGA device with the HardCopy III companion device already selected,
you must choose an I/O standard with a VCCIO of 3.0 V or less. Selecting an I/O
standard that requires a VCCIO of 3.3 V results in a compilation error.
f For more information about HardCopy III I/O buffers, refer to the DC and Switching
Characteristics of HardCopy III Devices chapter of the HardCopy III Device Handbook.
HardCopy IV I/O buffers support 3.3 V I/O standards, which you can use as
transmitters or receivers in your system. The 3.3 V I/O standard can be supported by
using the bank VCCIO at 3.0 V. In this method, the clamp diode (on-chip or off-chip),
when enabled, can sufficiently clamp overshoot voltage to within the DC and AC
input voltage specification. The clamped voltage can be expressed as the sum of the
VCCIO and the diode forward voltage.
f For more information about HardCopy IV I/O buffers, refer to the DC and Switching
Characteristics of HardCopy IV Devices chapter of the HardCopy IV Device Handbook.
You must constrain the I/O standards for the design specifically for your HardCopy
device. If you do not assign an I/O standard to an I/O pin, the Quartus II software
assigns the I/O standard to 2.5 V by default, which may not be compatible with your
design. To check supported I/O standards and identify incompatible I/O settings on
the assigned I/O pins, run I/O assignment analysis by pointing to Start on the
Processing menu, and then clicking Start I/O Assignment Analysis. The Start I/O
Assignment Analysis command verifies the I/O settings and assignments.
Altera recommends verifying the correct output drive strength for the design because
the default value in the Quartus II software might not be appropriate for your
application. Assigning the right output drive strength improves signal integrity while
achieving timing requirements. In addition, the output capacitance loading for both
the output and bidirectional pins must be set in the I/O assignment for a successful
HardCopy compilation.
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Not all Physical Synthesis Optimizations settings are available when you map your
FPGA device to a HardCopy companion revision.
h For more information about setting physical synthesis optimizations for the FPGA
revision of the designs in the Quartus II software, refer to Setting up and Running the
Fitter in Quartus II Help.
Timing Settings
The TimeQuest Timing Analyzer is a complete static timing analysis tool that you use
as a sign-off tool for FPGAs and HardCopy ASICs. The TimeQuest analyzer guides
the Fitter and analyzes timing results after compilation and is the required timing
analysis tool for all Quartus II software designs.
f For more information about the TimeQuest Timing Analyzer, refer to The Quartus II
TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook and About
TimeQuest Timing Analysis in Quartus II Help.
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LogicLock Regions
LogicLock regions are flexible floorplan location constraints that help you place logic
on the target device. You can use LogicLock regions in FPGA designs targeted to
HardCopy devices, which are also passed onto the HardCopy companion revision.
When LogicLock regions are created in a HardCopy device, they start with width and
height dimensions set to (1,1), and the origin coordinates for placement are at X1_Y1
in the lower left corner of the floorplan. You must adjust the size and location of the
LogicLock regions in HardCopy devices before compiling the design.
Altera recommends that you do not use floating LogicLock regions for HardCopy
devices because floating LogicLock regions may affect the designs ability to meet
timing closure. Additionally, you must manually size and place HardCopy device
LogicLock regions in the floorplan; you cannot set the LogicLock regions to Auto.
f For more information about using LogicLock regions, refer to the Analyzing and
Optimizing the Design Floorplan chapter in volume 2 of the Quartus II Handbook.
Incremental Compilation
The Quartus II software offers incremental compilation to preserve the compilation
results for unchanged logic in your design. This feature dramatically reduces your
design iteration time by focusing new compilations only on changed design
partitions. New compilation results are then merged with the previous compilation
results from unchanged design partitions.
Quartus II incremental compilation within a single Quartus II project is supported for
the base family for both the FPGA first and HardCopy first flows. Exporting and
importing partitions is not supported in HardCopy ASIC or FPGA device
compilations when there is a migration device setting.
f For more information about using Quartus II incremental compilation, refer to the
Quartus II Incremental Compilation for Hierarchical and Team-Based Design chapter in
volume 1 of the Quartus II Handbook and About Incremental Compilation in Quartus II
Help.
515
Although you can create multiple design revisions, Altera recommends maintaining
only one FPGA revision after you create the HardCopy companion revision.
After you have successfully compiled your FPGA prototype, you can create and
compile the HardCopy companion revision of your design. You can associate only
one FPGA revision to one HardCopy companion revision. If you create more than one
revision or companion revision, set the current companion for the revision you are
working on.
h For more information about creating or setting a companion revision in the Quartus II
software, refer to Migrating a Design to a HardCopy or FPGA Device in Quartus II Help.
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Setting Check
The Setting Check report lists the results of the setting checks from the Handoff
report. The Setting Check report contains the sections described below.
Summary
The Summary section displays the number of settings that do not meet
recommendations. One of the following messages appears:
517
(1)
SIGNAL_PROBE_ENABLE ON|OFF
SIGNAL_PROBE_SOURCE ON|OFF
(2)
I/O Check
The I/O check ensures that you have assigned location assignments for the pins, I/O
standards, current strength assignments, output pin load assignments, termination
assignments, and also checks for unconnected pins.
The following message appears in the message panel during compilation when the
HCDRC detects missing I/O standard assignments:
<number> pin(s) have no explicit I/O Standard assignments provided in the
setting file and default values are being used. Please add a specific I/O
Standard assignment for these pins.
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519
Description
Sets bit stream of 0101 in
RAM.
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Default checkerboard
pattern.
520
Description
Pseudo-random pattern.
If pseudo-random seed
is not set in the
quartus.ini, the
pseudo-random pattern
defaults to
pseudo-random seed 1.
As long as the
pseudo-random seed is
fixed, then random
pattern sets in RAM is
consistent for each run,
ensuring the exact same
pattern is reproducible.
521
7. On the Assignments menu, click Settings, and then click Assembler in the
Category list. Turn on Use checkered pattern as uninitialized RAM content on
the Assembler page, or add one of the checkerboard patterns listed in Table 53 to
the revision .qsf.
8. Run the Assembler in the FPGA revision to generate a new programming file for
your FPGA.
9. Test the new programming file in your prototype environment to determine if
your design has a dependency for FPGA RAM contents initialized with zeros after
power-up and configuration.
Because the checkerboard pattern is used for testing, the patterns written in the RAM
blocks for the new programming file may not detect all cases of zero-initialized RAM
content dependencies. Some designs may detect only one bit as zero (for example, the
LSB of a memory word), so this method may not detect all cases. This checkerboard
pattern test will detect a case when a full RAM word line is expected as zeros at
startup.
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Although this flow is enabled, performing formal verification is not necessary due to
the one-to-one mapping of logic between the FPGA prototype and the HardCopy
ASIC.
To use the Conformal software with the Quartus II software project for your FPGA
design revision, you must automatically run the EDA Netlist Writer during
compilation so it can generate the necessary netlist and command files required to run
the Conformal software.
523
To automatically run the EDA Netlist Writer during the compilation of your FPGA
revision, perform the following steps:
1. On the Assignments menu, click Settings.
2. In the Category list, under EDA Tool Settings, click Formal Verification, and then
in the Tool name list, select Conformal LEC.
3. Compile your FPGA and HardCopy design revisions.
The Quartus II EDA Netlist Writer produces the netlist for the FPGA revision. You can
compare your FPGA post-compilation netlist to your RTL source code using the
scripts generated by the EDA Netlist Writer.
After compiling both the FPGA and HardCopy revisions, you can run the Compare
HardCopy Revisions command, as described in Comparing HardCopy and FPGA
Companion Revisions on page 522 to ensure that the HardCopy implementation
matches the FPGA.
f For more information about using the Cadence Encounter Conformal verification
software, refer to the Cadence Encounter Conformal Support chapter in volume 3 of the
Quartus II Handbook.
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In this small example design, you can see the placement of a DSP block constructed of
HCell macros, various logic HCell macros, and an M9K memory block. A close-up
view of this region is shown in Figure 57.
Figure 57. Close-Up View of Floorplan
HCell Macros
M9K Memory Block
525
The Altera HardCopy Design Center performs final placement and timing closure on
your HardCopy design based on the timing constraints provided in the FPGA design.
f For more information about the Altera HardCopy Design Center process, refer to the
respective HardCopy series device handbook, which is available on the Literature
page of the Altera website at www.altera.com.
One-to-one changes, which are changes that can be implemented on both FPGA
and HardCopy architectures
The following sections describe the methods for migrating each type of changes.
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527
Suggested Implementation
LUTMASK changes
Make/Delete LC_COMB
Make/Delete LC_FF
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Use the following Tcl command to run the HardCopy Netlist Writer:
execute_module -tool cdb \
-args "--generate_hardcopy_files"\
f For more information about using the Chip Planner, refer to the Engineering Change
Management with the Chip Planner chapter in volume 2 of the Quartus II Handbook.
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November 2012
Version
12.1.0
Changes
June 2012
12.0.0
November 2011
11.0.1
Template update.
May 2011
December 2010
July 2010
November 2009
March 2009
11.0.0
10.1.0
10.0.0
9.1.0
9.0.0
Added the Compiling the Design and Creating Companion Revisions section
Edited the Timing Settings section to remove support for the Classic Timing Analyzer
Editorial changes
Updated the LogicLock Regions section for updated companion revision support
Updated the Incremental Compilation section for updated companion revision support
Updated the Quartus II Software Features Supported for HardCopy Designs section
531
Version
November 2008
May 2008
8.1.0
8.0.0
Changes
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
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This chapter contains rules and guidelines for creating a floorplan with the design
separation flow, and assumes familiarity with the Quartus II incremental
compilation flow and floorplanning with the LogicLockTM feature.
The basic principle of a secure and reliable system is that critical subsystems in the
design have physical and functional independence. Systems with redundancy require
physical independence to ensure fault isolationthat a failure or corruption of any
single subsystem does not affect any other part of the system adversely. Furthermore,
if errors occur, physical independence simplifies analysis by allowing developers to
evaluate each subsystem separately.
Traditionally, systems that require redundancy implement critical IP structures using
multiple devices. The Quartus II design separation flow, used in Cyclone III LS
devices, allows you to design physically independent structures on a single device.
This functionality allows system designers to achieve a higher level of integration on a
single FPGA, and alleviates increasingly strict Size Weight and Power (SWaP)
requirements. Figure 61 shows this concept.
Figure 61. Achieving Higher Level Integration on a Single Cyclone III LS Device
Critical
Subsystem
1
Critical
Subsystem
2
Critical
Function
1
Critical
Function
2
Other subsystems
Complex System
The Quartus II design separation flow introduces the constraints necessary to create
secured regions and floorplan a secured system. When implemented in Cyclone III LS
devices, a secured region provides physical independence through controlled routing
and a boundary of unused resources. Restricting routing resources and providing a
physical guard band of unused logic array blocks (LABs) prevent faults or unintended
signals originating in one secured region from adversely affecting other design blocks
on the device.
1
The Quartus II design separation flow features require specific licensing in addition to
licensing the Quartus II software. For more information, contact your local Altera
sales representative or Altera distributor.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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62
Analyzing and Optimizing the Design Floorplan with the Chip PlannerDescribes
various attributes associated with LogicLock location constraints and introduces
the Chip Planner for creating and modifying a floorplan
63
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For more information, refer to Creating Design Partitions for the Design
Separation Flow on page 65.
4. Create a design floorplan with security attributesAfter creating design
partitions, create LogicLock location assignments and a floorplan to secure all the
entities in your design. Use the security attributes in the LogicLock Regions
window to specify the security level of each LogicLock region. These attributes
create fencing regions in your floorplan to isolate the secured LogicLock regions.
For more information, refer to Creating a Design Floorplan with Secured
Regions on page 66.
5. Assign design partitions to secured regionsAssign design partitions to secured
LogicLock regions to separate them from each other and from all other hierarchy
blocks. Refer to Using Secured Regions on page 69 for more information.
6. Add I/O pins that directly interface with a secured region as a member of the
secured regionIf a secured region interfaces with one or more I/O pins, make
the I/O pins members of the secured region. If a secured region has I/O pins as
members, that region must overlap the I/O pads. Refer to Adding I/O Pins as
Members of Secured Regions on page 69 for more information.
7. Create security routing interfaces to and from secured regionsCreate security
routing interfaces by applying the security routing interface attribute to LogicLock
regions.
You can use only routing resources in a security routing interface; you cannot
place any logic. Each security routing interface must abut one or two secured
regions. After you create an interface region for each signal or group of signals
entering or exiting a secured region, assign the signals to the appropriate routing
interfaces.
For signals routing between secured regions with different security attributes or
between a secured region and an unsecured region, you must lower the security
attribute for the signal exiting the stricter security region. For more information,
refer to Making Signal Security Assignments on page 619.
8. Assign I/O pinsAfter creating secured regions and security routing interfaces, if
the secured regions contain I/O pins as members, assign I/O pins to meet design
separation flow requirements. For example, secured regions cannot share I/O
banks. If a secured region contains I/O pins as members, the entire I/O bank is
usable only by the secured region that sinks or sources the I/O pin. For more
information, refer to Assigning I/O Pins on page 625.
9. Make design changes, set the netlist type for each design partition, and compile
the designAfter making the necessary I/O pin assignments, you complete the
design separation flow-specific steps, and you can start the iterative process of
making design changes, setting the netlist type for each design partition, and then
compiling your design until you achieve a floorplan that meets your design
requirements.
1
Subsequent sections in this chapter describes the design separation flow-specific steps
(step 1 and steps 4 through 8).
65
Register the inputs and outputs of a design partition to avoid cross-boundary logic
optimizations and to maintain timing performance along the signal path.
Minimize the number of I/O paths that cross partition boundaries to keep logic
paths in a single partition for optimization. Minimizing the number of
cross-boundary I/O paths makes partitions more independent for both logic and
placement optimization.
f For more information about guidelines for creating design partitions, refer to the Best
Practices for Incremental Compilation Partitions and Floorplan Assignments chapter in
volume 1 of the Quartus II Handbook.
When creating your design in the design separation flow, you must be aware of some
restrictions and special considerations that differ from the incremental compilation
flow. For more information about these considerations, refer to the Merging PLL
Resources and Avoiding Multiple Design Partitions With a Secured Region
sections.
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design contain no security attributes. For partitions that require shared PLL resources,
you must instantiate the PLL outside of the design partitions.
67
border of a boundary. Each secured region uses an unused boundary (or a fence) of
LABs to guard against the faults from wire resources spanning a length of one LAB
(direct link and register chain routing resources) from affecting a neighboring region.
The rules and guidelines for floorplanning in the design separation flow are similar to
those in a typical compilation flow. However, there are some special considerations
for the relative placement of secured regions in your design floorplan. Because each
secured region is a keep-out region for routing resources from other LogicLock
regions, ensure that a routing path with valid communication interfaces exists
between secured regions. Furthermore, the routing path (encapsulated in a security
routing interface) should not follow a circuitous path and must be simple enough to
meet your timing requirements.
The Fitter cannot generate a placement for LogicLock regions with security attributes.
You must manually place LogicLock regions with security attributes; that is, the size
attribute cannot be Auto, and the state attribute cannot be Floating for any LogicLock
region in a secured design.
1
f For more information about using the Chip Planner settings and options, refer to the
Analyzing and Optimizing the Design Floorplan with the Chip Planner chapter in volume 2
of the Quartus II Handbook.
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Figure 63 and Figure 64 show the design separation flow security features in the
LogicLock Regions window and the LogicLock Regions Properties dialog box.
Figure 63. Security Attribute Column Available in the Design Separation Flow
Table 61 lists a summary of the Security Attributes available for the design
separation flow.
Table 61. Security Attributes for LogicLock Regions (Part 1 of 2)
Security
Attribute
Unsecured
Description
Removes the constraint for physical isolation.
Creates a secured region. Physically isolates the LogicLock region by restricting routing resources from
leaving the region. Creates a one-LAB width border of unused logic (LABs, DSP blocks, or embedded
memory blocks) around the LogicLock region.
Applying this attribute to a LogicLock region sets the global assignment
LL_REGION_SECURITY_LEVEL 1 for the LogicLock region.
69
Description
Creates a secured region. Security attribute 2 represents a stricter level of fault isolation than security
attribute 1. For Cyclone III LS devices, implementation of security attribute 2 creates a fence that is two
units tall and one unit wide along the vertical and horizontal dimensions, respectively.
Creates a routing interface for signals entering or exiting a secured region. You may use only routing
resources (no logic) in a security routing interface.
Applying this attribute to a LogicLock region sets the global assignment
LL_SECURITY_ROUTING_INTERFACE ON for the LogicLock region.
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610
611
I/O banks along the top and bottom of the chip use only vertical routing wires to and
from the I/O Elements (IOEs). The heavy use of C4 wires from IOEs creates a
four- LAB fence between the vertical I/O banks and a secured region. Secured regions
requiring a connection to I/O in the top or bottom banks of the device optimally use
resources if you add the I/O signals as members of the secured region and overlap the
corresponding I/O pads in the floorplan. In Figure 66, Secured_Region2 is five
LABs away from the bottom of the device and Secured-Region1 is four LABs away
from the bottom of the device.
Figure 66. Vertical Fencing Near I/O Banks
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If your design routes signals to and from the configuration engine, then do not place a
secured region that directly abuts the configuration engine signal interface (along the
right side of the configuration engine) to avoid a Fitter error.
Figure 67 shows a configuration engine with a fencing region in the floorplan.
Figure 67. Configuration Engine
Configuration Engine
Configuration Engine
Signal Interface
You can overlap fencing regions between two secured regions. That is, you can
separate two adjacent secured regions by a one-row fence. The Chip Planner issues a
security warning violation if you place a LogicLock region in the boundary of a
secured region. The Chip Planner highlights security violations in red and the tooltip
of a secured region indicates the locations of all security violations. You may receive
an error if you try to compile a design with a security violation. Figure 68 shows two
regions with overlapping fences and a security violation from an unsecured region.
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Create security routing interfaces between secured regions that do not intersect
with other routing regions; secured regions and their routing edges must fit on a
single plane. A secured region must overlap any physical resources (such as I/Os,
PLLs, and CLKCTRL) that the design partition in the secured region instantiates.
Abut the secured region to the edge of the device whenever possible.
615
If a complete floorplan is impossible for all partitions in your design, you can use
empty LogicLock regions with the Reserved attribute to prevent the Fitter from
placing any logic in a region that can potentially cause a no-fit error. For the example
provided in Figure 610, you can place an empty region in the upper-left corner of
your device to prevent the Quartus II software from placing any logic that has not
been floorplanned there, as shown in Figure 611.
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Figure 611. Empty Reserved Region Preventing Fitter From Placing Logic
617
Secure
Region
Sink
Region
Source
Region
Ensuring Planarity
The Quartus II software automatically creates a fence around a security routing
interface connecting two secured regions. Because no other routing resources may
pass through a security routing interface connecting two secured regions, you must
model all secured regions as nodes in a routing graph and all security routing
interfaces as the edges, and all nodes and their edges must fit on a planar graph (that
is, none of the edges can intersect). If you have five or more secured regions on the
device, and each secured region contains signals that fan out to multiple secured
regions, a planar floorplan may not be possible. Figure 613 shows a routing graph
with five nodes. A complete graph with each pair of distinct vertices connected by an
edge is impossible without having any of the edges cross. If the topology of your
floorplan contains such a non-routable arrangement, you must rearrange your design
hierarchy to collapse related design partitions into a single design partition.
Figure 613. Non-Planar Routing Graph: Connection BD Not Possible
A
If you can model your secured regions and security routing interfaces as a planar
graph, but have a high degree of connectivity between the components, then you may
have to rearrange the shape, size, or location of the secured regions to generate a
routable floorplan. For instance, the hypothetical floorplan shown in Figure 614 does
not have a valid routing path BD (between region B and region D). The modified
floorplan in Figure 615 shows how you can achieve all the required connections on a
planar surface.
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Secure
Region
A
AB
Secure
Region
B
BE
AC
Secure
Region
C
CE
Secure
Region
E
Non-Routable
Connection BD
Connection
AD
Secure
Region
D
DE
AC
Secure
Region
C
CE
Secure
Region
A
AD
Secure
Region
D
AB
Secure
Region
B
DE
Secure
Region
E
BD
BE
You can use the Design Partition Planner for a visual representation of the
connectivity between design partitions. This tool helps you determine if you can
arrange the secured regions in your design on a planar floorplan. Figure 616 shows
the Design Partition Planner.
619
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Alternatively, you can select multiple names in the Signal list by pressing
the Ctrl key, clicking multiple names, and then clicking Edit.
The Quartus II software populates the Signals list with the names of signals
entering and exiting the secured region after analysis and synthesis and after
completing a successful partition merge.
Figure 617. Edit Security Assignments for Signal Dialog Box
2. If necessary, lower the security level of the signal by specifying the Security level.
3. Select the security routing interface for signal or signals assignment. You can
assign signals that fan-out or fan-in to multiple regions to multiple security
routing interfaces.
621
and placement and routing. Frequently, RTL signal names may not appear in the
post-fit netlist after optimization. For example, the compilation process can add tildes
(~) to nets that fan-out from a node, making it difficult to decipher which signal nets
they actually represent. Use the post-compilation filter in the node finder to add
additional signals to a security routing interface. When possible, use registered signals
as inputs into a secured region, and register the output signals from a secured design
partition.
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To honor a global promotion assignment, a clock control block that is not overlapped
by a secured region and a routing path to the clock control block must be available.
There are five clock control blocks located on each side of the device, along the
horizontal and vertical axes that run through the center of the device. Figure 618
shows the location of the clock control blocks and the PLLs for a 3CLS70 device in the
Chip Planner floorplan.
Figure 618. PLL and Clock Control Block Location on a EPC3SL70 Device
PLL 3
PLL 2
PLL 4
PLL 1
623
You can manually instantiate PLLs and clock control blocks in the design partition of
a secured region using the ALTPLL and ALTCLKCTRL megafunctions, respectively.
Instantiation of the ALTCLKCTRL megafunction in a secured partition forces the
global promotion of the signal driving the clock control block. To generate a valid
placement when you instantiate PLLs or a clock control block, the secured region
containing the physical resource must overlap a free PLL, a free clock control block, or
both.
You must be aware of certain restrictions when you instantiate a PLL in a secured
region. Secured regions with a PLL fed by an external clock pin must contain the PLL
and a valid clock pin that can drive the PLL. Each PLL has a set of dedicated clock
control blocks that it can access, located to the right (clockwise) of the PLL in the
device floorplan.
Because automatic promotion of signals onto a global resource is not allowed, you
must not place a PLL and the clock control block that the PLL drives in the same
secured region. If your design has a PLL inside of a secured region, you must assign
the PLL output to a security routing interface and then lower the security level of the
PLL output.
A secured region must not cover the clock control block associated with the PLL.
There are two sets of dedicated clock pins that can drive a PLL input. The pads for the
clock input pins are co-located with the clock control blocks. If you use the clock input
pin that is co-located with the clock control block associated with the PLL, you cannot
add the clock pin as a member of the secured region. Instead, you must either assign
the clock pin to a security routing interface that connects with the secured region, or
you can apply the LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT assignment to relax the
fitter restriction on the clock input pin.
For more information about the LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT
assignment, refer to Assigning I/O Pins on page 625.
Figure 619 shows examples of valid placement and invalid placement of secured
regions that instantiate PLLs, before applying the
LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT assignment.
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DPCLK[9:8]
CLK[11:8]
DPCLK[11:0]
Figure 619. Location of Valid and Invalid PLL, Clock Pin, and Clock Control Block Placement in a Cyclone III LS Device
2
4
4
PLL
3
PLL
2
(3)
Remote Clock from
Two Clock Pins
at Adjacent Edge
of Device (2)
(3)
Clock Control
Blocks (1)
DPCLK0
CLK[3:0]
DPCLK7
4
CLK[7:4]
DPCLK1
DPCLK6
Secured Region
Clock Control
Blocks (1)
(3)
DPCLK[11:0]
DPCLK[3:2]
DPCLK[9:8]
PLL
4
CLK[11:8]
(3)
DPCLK[5:4]
CLK[15:12]
PLL
1
2
4
4
PLL
3
PLL
2
(3)
Remote Clock from
Two Clock Pins
at Adjacent Edge
of Device (2)
(3)
Clock Control
Blocks (1)
DPCLK0
CLK[3:0]
DPCLK7
4
DPCLK1
CLK[7:4]
DPCLK6
Secured Region
Clock Control
Blocks (1)
X
(3)
(3)
3)
DPCLK[3:2]
DPCLK[5:4]
CLK[15:12]
PLL
1
PLL
4
625
You must assign I/O pins that connect to a secured region as a member of that
secured region or to a security routing interface region that abuts the secured
region.
You must ensure that secured regions with I/O pins as members do not share I/O
banks with any other region.
You must ensure that I/O pins associated with different secured regions or
security levels do not use adjacent pins.
When I/O pins directly connect to the secured region, you may add I/O pins as
members of a secured region. To add I/O pins as members of a secured region, in the
LogicLock Regions Properties dialog box, on the General tab, click Add node. If an
I/O pin is a member of a secured region, the I/O pad must be physically in the region,
and the secured region must overlap the I/O resource.
If you do not add the I/O pin as a member of the secured region, you must assign the
I/O signal to a security routing interface that abuts the secured region. This security
routing interface must connect the secured region to the root region or another
unsecured region. Explicitly lower the security level of any output signals from the
secured region that connects to I/O pins.
c I/O signals that route out to unsecured logic are no longer guaranteed to be
physically isolated from other signals in your design.
Each I/O pin is adjacent to eight other pins: four along the horizontal and vertical
axes, and four in the two diagonal axes, as shown in Figure 620.
Figure 620. Pin Adjacency
Pins D4 and D5
Set to GND
Pins E4
Eight Pins Adjacent
to Pin E4
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Pins from different I/O banks may not share an adjacent I/O pin if one of the I/O
banks contains pins that are members of a secured region. You must assign user I/O
pins that are adjacent to a signal in a secured region, which belong to a different I/O
bank than the secured signal, to GND in the Quartus II software. For example, in
Figure 620, pin E4 is assigned a signal from a secured region, and I/O banks 1 and 7
belong to different LogicLock regions. Pins D4 and D5 are assigned to GND to ensure
that no signal adjacencies exist between the I/O banks.
As a rule, you must assign all unused I/O pins to GND in the Quartus II software and
to a ground plane on the PCB. By default, the Quartus II software assigns unused pins
to GND. You can configure this option in the Unused Pins page of the Device and Pin
Options dialog box.
If you must relax a particular I/O restriction for specific signals to meet your design
requirements, you may use the LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT assignment.
The Quartus II software uses the assignment to bypass normal I/O pin checks for a
specific signal. For example, you can apply this assignment to a clock pin assigned to
one of the dedicated clock inputs.
1
f For more information about the pinouts and pin adjacencies for Cyclone III LS
devices, refer to the Cyclone III Device Pin-Out tables. For more information and
guidance about I/O assignments, refer to the Cyclone III Device Family Pin Connection
Guidelines for Cyclone III LS devices and the I/O Management chapter in volume 2 of
the Quartus II Handbook.
627
Routing Restrictions
During the overall planning of your design, you must be aware of specific design
separation flow routing restrictions, especially during the floorplanning stages. This
section discusses these routing restrictions.
Column and row interconnect routing resources on Cyclone III LS devices are
staggered, with a group of routing elements that starts at each LAB location. The LAB
location in which the wire starts drives each routing element. The routing element can
reach any LAB destination along the length of the routing element. Figure 621 shows
a set of staggered R4 interconnects.
Figure 621. Staggered R4 Interconnects
ENDPOINT
R4
Interconnects
LABs
COL
COL
COL
COL
COL
COL
COL
COL
LABs
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The Fitter disables routing wires near the edge of a secured region, in which routing is
confined in the region. Figure 622 shows the Chip Planner displaying used routing
elements in a design with secured regions, using options in the Layer Settings dialog
box and using the background color map I/O banks, with only the Global Routing
and Used Resources options turned on.
Figure 622. Chip Planner View of Used Resources
Figure 622 shows that no routing resources reach outside of LogicLock region
boundaries, except for global routing signals and signals through interface regions.
Long wires are often unusable in secured regions because their length extends beyond
the border of the region. If a secured region abuts the device boundary, you can often
attain an increase in routability, because you can use all the routing interconnects that
start inside the region and drive toward the edge of your device.
I/O pads along the top and bottom of the device can only use column interconnects to
drive into the device fabric. The shortest routing element from the I/O to core logic is
a C4 routing wire. I/O pads on the left and right sides of the device can use both C4
and R4 routing elements to reach their LAB destinations. Because the Quartus II
software restricts column I/Os from using C4 interconnects going into your device,
the Quartus II software creates a four-LAB fence around secured regions when the
boundary of the secured region is in four-LABs of the top and bottom I/O pads.
629
L/R
L/R
L/R
U/D
U/D
U/D
L/R,
U/D
U/D
U/D
U/D
L/R
L/R
L/R
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In Figure 624, HAB is both the smaller of the height of the region and the height of the
routing interface. The minimum WAB is one LAB. WBC is both the smaller width of the
region and the width of the routing interface. The minimum HBC is one LAB.
Changing WAB or HBC does not affect the values in Table 63.
Figure 624. Signals Crossing a Routing Interface
68 HAB
68 HAB
48 WBC
48 WBC
17 HAB
17 HAB
12 WBC
12 WBC
As a general guideline, keep the security routing interface channel width between the
two connecting secured regions as short as possible and the depth of the channel as
wide as possible. The channel width is the number of LABs that a security routing
interface abuts and the depth of the channel is the number of LABs a signal passes as
it goes through the routing channel.
631
In Figure 625, an optimal security interface for routing AB would have a channel
width equal to the height of secured region A (HAB) and a channel depth of one LAB
(WAB). Having a wide channel with a short depth increases the number of routing
resources available between two secured regions.
You can use the Routing Congestion task in the Chip Planner for a visual
representation of the routing utilization between secured regions. The Routing
Congestion task filters routing resources by type. Utilization of each routing resource
type is highlighted on a color gradient over the range that you specify. This tool can
help you adjust region sizes and security routing interface channel widths to help you
achieve an optimal floorplan. Figure 625 shows a design with the Routing
Congestion task in the Chip Planner and R24 routing utilization.
Figure 625. Routing Congestion
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Secure Region 1
Connection to I/O
Secure Region 2
Secure Region 4
Connection to I/O
Secure Region 3
Secure Region 5
The following steps outline a recommended design flow for creating a floorplan for
this design:
1. Create a LogicLock region for each partition that you must pack into a secured
region.
2. Set each LogicLock region with the following settings:
3. On the Processing menu, point to Start and click Start Early Timing Estimate to
run an initial placement and routing. The initial placement and routing
approximates the size of each region and the general placement of the LogicLock
regions relative to other LogicLock regions to achieve timing closure. Figure 627
shows the floorplan that the early timing estimate generates.
633
1
2
4
4. In the LogicLock Regions window, select the LogicLock regions, right-click, and
then click Set Size and Origin to Previous Fitter Results.
5. Use the Design Partition Planner to view the connectivity between the different
regions. You can experiment with the relative placement of the blocks by dragging
and dropping each design partition. The wire bundles between design partitions
help you to determine a placement that has non-overlapping routing channels.
1
You must also consider the connectivity to the I/O banks when arranging
your floorplan. You can toggle the display of the connections between the
partitions and the I/O banks in the Design Partition Planner to help you
properly allocate I/O resources and to avoid conflicts between I/O
connections and inter-partition signals. To display routing between
partitions and the I/O banks, turn on Display connections to I/O banks in
the Bundle Configuration dialog box.
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Each region that has I/O pins added as members of the LogicLock region
should overlap the I/O bank to which it is connected. You can use the I/O
bank background color map to visualize the boundaries between the I/O
banks (Figure 628).
A secured region must not cover all global resources that unsecured logic
require (such as clock pins and PLLs).
634
Figure 628. I/O Banks Layers Setting for Viewing Connectivity of LogicLock Regions to I/O Banks
8. Create security routing interfaces between each of the secured regions. Assign all
signals entering or exiting a region to a security routing interface.
Figure 629 shows the final floorplan result for this application example.
Figure 629. Final Floorplan
635
Report Panels
After the Fitter successfully places and routes your design with secured regions, the
Quartus II software generates security reports. Use the security reports to review the
secured regions, their associated routing interfaces, all inputs and outputs from each
secured region, and the I/O bank usage for each secured region. You can locate the
security reports in the Fitter section of the Compilation reports.
Description
Security Attribute
Lists the security attribute (unsecured,1, 2, or security routing interface) of the LogicLock
region.
Partition Assigned
Lists the number of inputs and fan-outs into a region. The input counts the number of unique
drivers that feed a secured region. The fan-out counts the total number of unique destinations
being fed by the input signals into the secured region. Figure 630 shows input signals and
fan-outs to a region.
Lists the number of outputs and fan-outs from a region. The output counts the number of
unique drivers sourcing a signal from the secured region. The fan-out counts the total number
of unique destinations fed by the output signal.
Secured Region A
D
CLRN
Set
D
CLRN
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Description
Interface Name
Abutting Region A
First region that the security routing interface abuts (touches the border of the secured
region).
Abutting Region B
Second region that the security routing interface abuts (touches the border of the secured
region).
Number of Signals A to B
(Total Fanout in B)
Lists the number of signal connections between region A and region B. The counts are shown
as signals and fan-outs. Signals list the number of unique drivers from region A. Fan-out lists
the number of unique destinations in region B that are fed by region A.
Number of Signals B to A
(Total Fanout in A)
Lists the number of signal connections between region B and region A. The counts are shown
as signals and fan-outs. Signals list the number of unique drivers from region B. Fan-out lists
the number of unique destinations in region A that are fed by region B.
637
Column Name
Description
I/O Bank
Associated Region
An I/O bank becomes associated with a secured LogicLock region if any portion of the I/O bank
is covered by the region. If no secured region covers an I/O bank, Unsecured Logic is
displayed, and all pins of the I/O bank are available for unsecured use.
Displays the ratio of pins with a signal assignment in the I/O bank to the number of possible I/O
pin assignments.
LL_SECURITY_ROUTING_INTERFACE
This command changes a LogicLock region assignment to a security routing interface.
Type: Boolean; (ON/OFFDefaults to OFF)
Syntax:
set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE <value> \ -section_id
<section_identifier> LL_REGION_SECURITY_ LEVEL
LL_REGION_SECURITY_LEVEL
This command identifies the security level of a LogicLock region.
Type: EnumerationDefaults to UNSECURED
UNSECURED
Syntax:
set_global_assignment -name LL_REGION_SECURITY_LEVEL <value> \
-section_id <section_identifier>
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LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE
This command assigns an I/O pin from a secured region to a security routing
interface. <value> and <section_id> denote the name of the routing interface region.
<to> specifies the name of the signal.
Type: String
Syntax:
set_instance_assignment -name \ LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE
<value> -to <to> \
-section_id <section_id>
LL_SIGNAL_SECURITY_LEVEL
This command sets the security level of a signal. The default value is the security level
of the region that generates the signal. This assignment may be used only to lower a
security level.
Type: Enumeration
UNSECURED
Syntax:
set_instance_assignment -name LL_SIGNAL_SECURITY_LEVEL <value> \
-to <to> -section_id <section_id>
November 2011
Version
12.0.0
Changes
Template update.
11.1.0
639
Version
December 2010
July 2010
10.1.0
10.0.0
Changes
Modified the former Avoiding Child Partitions section into the new Avoiding Multiple
Design Partitions With a Secured Region on page 46 section and added information
about multi-hierarchy partitions.
Updated the Making Design Separation Flow Location Assignments in the Chip Planner
on page 410 section.
Updated the Working with Global Signals on page 421 and Assigning I/O Pins on
page 625 sections with information about the
LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT assignment.
Template update.
Initial release. Content originated from AN 567: Quartus II Design Separation Flow.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
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This section provides information about Qsys. Qsys is a powerful system integration
tool which is included as part of the Quartus II software. Qsys automates the task of
capturing of integrating customized HDL components, which may include IP cores,
verification IP, and other design modules. You can use Qsys to integrate your own
components with the components that Altera or third-party developers provide. In
some cases, you can implement an entire design using components from the Qsys
component library.
This section includes the following chapters:
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Qsys is a system integration tool included as part of the Quartus II software. Qsys
captures system-level hardware designs at a high level of abstraction and automates
the task of defining and integrating customized HDL components, which may include
IP cores, verification IP, and other design modules. Qsys facilitates design reuse by
packaging and making available your custom components and systems, and
integrates your custom components with Altera and third-party developer
components.
Qsys automatically creates interconnect logic from the connectivity options you
specify, eliminating the error-prone and time-consuming task of writing HDL to
specify the system-level connections.
Qsys supports standard Avalon, AMBA AXI3 (version 1.0), AMBA AXI4
(version 2.0), and AMBA APB 3 (version 1.0) interfaces. For more information about
Avalon and AMBA interfaces, refer to the Avalon Interface Specifications and the
AMBA Protocol Specifications on the ARM website. AXI4-Lite is not supported.
Qsys provides the following advantages for system design:
f For descriptions of unique or exceptional AXI and APB support in the Qsys software,
refer to the Qsys Interconnect chapter in volume 1 of the Quartus II Handbook. For more
information about Avalon, AXI, and APB interfaces, refer to the Avalon Interface
Specifications and the AMBA Protocol Specifications on the ARM website.
ISO
9001:2008
Registered
Feedback Subscribe
72
A Qsys system can have multiple 64-bit masters, with each master establishing its
own address space. Slaves may be shared among masters and masters can map slaves
in different ways; for example, one master may interact with slave 0 at base address
0000_0000_0000, and another master may see the same slave at base address
c000_000_000.
64-bit are also supported for narrow-to-wide and wide-to-narrow transactions across
Avalon and AXI interfaces, though bursts that exceed 32-bits are legal only within the
Avalon interface. AXI3 allows bursts of 1 - 16 transfers. AXI4 allows burst lengths of
256.
Quartus II debug tools that provide access to the state of an addressable system via
the Avalon-MM interconnect are also 64-bit compatible and process within a 64-bit
address space, including a JTAG to Avalon master bridge.
DMA Controllers
DMA controllers are limited to 32-bit addressing. As a workaround, you can use the
window bridge component, as described in Ports and Bridges above.
Memory-MappedImplements a partial crossbar interconnect structure (AvalonMM, AXI, and APB) that provides concurrent paths between master and slaves.
Interconnect consists of synchronous logic and routing resources inside the FPGA,
and implementation is based on a network-on-chip architecture.
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73
ResetsConnects reset sources with reset input interfaces. If your system requires
a particular positive-edge or negative-edge synchronized reset, Qsys inserts a reset
controller to create the appropriate reset signal. If you design a system with
multiple reset inputs, the Reset Controller ORs all reset inputs and generate a
single reset output. A Reset Bridge allows you to use a reset signal in two or more
subsystems of your Qsys system.
Altera Corporation
74
Create Component
Using Component Editor, or
Manually Creating the
_hw.tcl File
Simulation at Unit-Level,
Possibly Using BFMs
Does
Simulation Give
Expected Results?
Yes
No
3
Debug Design
Generate Qsys
System
Perform System-Level
Simulation
Yes
No
Debug Design
Does
HW Testing Give
Expected Results?
Does
Simulation Give
Expected Results?
Constraint, Compile
in Quartus II Generating .sof
Yes
Qsys System Complete
No
10
Modify Design or
Constraints
In the alternative top-down design flow, you begin by designing the Qsys system, and
then define and instantiate custom Qsys components. The top-down design flow
clarifies the system requirements earlier in the design process.
Designs targeting HardCopy series devices require specific design constraints.
Consequently, if you are targeting a HardCopy series device, you must verify your
design for the HardCopy companion device.
75
You can set the IP Search Path option to specify custom and third-party components
that you want to appear in the component library. Qsys searches for component files
each time you open the tool, and locates and displays the list of available components
in the component library.
Qsys searches the directories listed in the IP Search Path for the following component
file types:
May 2013
Hardware Component Description Files (_hw.tcl) files. Each _hw.tcl file defines a
single component.
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Qsys searches some directories recursively and other directories only to a specific
depth. When a directory is recursively searched, the search stops at any directory
containing a _hw.tcl or .ipx file; subdirectories are not searched. In the following list
of search locations, a recursive descent is annotated by **. The * signifies any file.
PROJECT_DIR/*
PROJECT_DIR/ip/**/*
QUARTUS_INSTALLDIR/../ip/**/*
Complete the following steps to extend the default search path by specifying
additional directories:
1. On the Tools menu, click Options.
2. In the Category list, click IP Search Path.
3. Click Add.
4. Browse to locate additional directories and click Open to add them to your search
path.
1
You do not need to include the components specified in the IP Search Path as part of
your Quartus II project.
You want to associate your components with a specific release of the Quartus II
software.
You want to have the same components available across multiple projects.
77
<install_dir>
quartus
ip
altera
altera_components.ipx
<components>
.
.
user_components
2
component1
component1_hw.tcl
component1.v
component2
component2_hw.tcl
component2.v
In Figure 72, the circled numbers identify a typical directory structure for the
Quartus II software. For the directory structure above, Qsys performs the component
discovery algorithm described below to locate .ipx and_hw.tcl files and initiate the
component library:
1. Qsys recursively searches the <install_dir>/ip/ directory by default. The recursive
search stops when Qsys finds an .ipx file.
2. As part of the recursive search, Qsys also looks in the user_components directory
because this directory path appears as an IP Search Path in the Options dialog
box. Qsys finds the component1 directory, which contains component1_hw.tcl.
When Qsys finds that component, the recursive search ends, and no components
in subdirectories of component1 are found.
3. Qsys then searches the component2 directory, because this directory path also
appears as an IP Search Path, and discovers component2_hw.tcl. When Qsys
finds component2_hw.tcl, the recursive search ends.
1
If you save your _hw.tcl file in the <install_dir>/ip/ directory, Qsys finds your _hw.tcl
file and stops. Qsys does not conduct the component discovery algorithm just
described.
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The user_components.ipx file includes a single line of code redirecting Qsys to the
location of each user library. Example 71 shows the redirection code.
Example 71. Redirect to User Library
<library>
<path path="<user_lib_dir>/user_ip/**/*"/>
</library>
You can verify that components are available with the ip-catalog command. You can
use the ip-make-ipx command to create an .ipx file for a directory tree, which can
reduce the startup time for Qsys. The following sections describe these commands.
ipcatalog
This command displays the catalog of available components relative to the current
project directory in either plain text or XML format.
Usage
ip-catalog [--project-dir=<directory>] [--name=<value>]
[--verbose] [--xml] [--help]
Options
--xmlOptional. If set, generates the output in XML format instead of a lineand colon-delimited format.
ip-make-ipx
This command creates an ip-make-ipx (.ipx) file and is a convenient way to include a
collection of components from an arbitrary directory in the Qsys search path. You can
also edit the .ipx file to disable visibility of one or more components in the Qsys
component library.
Usage
ip-make-ipx [--source-directory=<directory>] [--output=<file>]
[--relative-vars=<value>] [--thorough-descent]
[--message-before=<value>] [--message-after=<value>] [--help]
79
Options
</library>
A <path> element contains a path attribute, which specifies the path to a directory, or
the path to another .ipx file, and can use wildcards in its definition. An asterisk
matches any file name. If you use an asterisk as a directory name, it matches any
number of subdirectories.
When searching the specified path, the following three types of files are identified:
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711
Adding Components
To add a component to your system, select the component in the Component Library,
and then click Add. A parameter editor appears allowing you to configure the
component instance.
1
You can type some or all of the components name in the Component Library search
box to help locate a particular component type. For example, you can type memory to
locate memory-mapped components, or axi to locate AXI interconnect components.
Connecting Components
When you add connections to a Qsys system, you connect the interfaces of the
modules in the system. The individual signals in each interface are connected by the
Qsys interconnect when the HDL for the system is generated. You connect interfaces
of compatible types and opposite directions. For example, you can connect a
memory-mapped master interface to a slave interface, and an Interrupt sender
interface to an Interrupt receiver interface.
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Filtering Components
You can use the Filters dialog box to filter the display of your system in the System
Contents tab. You can filter the display of your system by interface type, instance
name, or by using custom tags. For example, you can use filtering to view only
instances that include memory-mapped interfaces, instances that are connected to a
particular Nios II processor, or to temporarily hide clock and reset interfaces to
simplify the display.
h For more information about filtering components, refer to the Filters Dialog Box in
Quartus II Help.
713
In contrast, the System Contents tab displays only the exported interfaces
of Qsys subsystems included as components.
The global parameter settings that you specified on the Project Settings tab
You can use the System Inspector tab to review and change component parameters
and to review interface timing. For example, Figure 74 shows the timing for the
Avalon-MM DMA write master for the PCI Express-to-Ethernet system illustrated in
Figure 712 on page 730.
.
Figure 74. Avalon-MM Write Master Timing Waveforms Available on the Project Settings Tab
To display the timing for an interface, expand the component, and then click the
interface name.
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You can design a system where two masters access a slave at different addresses. If
you use this feature, the Base and End address columns of the System Contents tab
are labeled mixed rather than providing the address range.
Description
Device Family
Device
FIFOThis adapter uses dual-clock FIFOs for synchronization. The latency of the
FIFO-based adapter is a couple of clock cycles more than the handshaking clock crossing
component, but the FIFO-based adapter can sustain higher throughput because it
supports multiple transactions at any given time. The FIFO-based clock crossers require
more resources. The FIFO adapter is appropriate for memory-mapped transfers
requiring high throughput across clock domains.
AutoIf you select Auto, Qsys specifies the FIFO adapter for bursting links, and the
Handshake adapter for all other links.
Specifies the maximum number of pipeline stages that Qsys may insert in each command
and response path to increase the fMAX at the expense of additional latency. You can specify
between 04 pipeline stages, where 0 means that the interconnect has a combinational data
path. Choosing 3 or 4 pipeline stages may significantly increase the logic utilization of the
system. This setting is per Qsys system or subsystem, meaning that each subsystem can
have a different setting. Note that the additional latency is for both the command and
response directions for the two Qsys systems, even if you combine them into a single
Quartus II project.
Generation Id
A unique integer value that is set to a timestamp just before Qsys system generation that
Qsys uses to check for software compatibility.
715
Qsys generates a warning message if the selected device family and target device do
not match the Quartus II software project settings. Also, when you open Qsys from
within the Quartus II software, the device type in your Qsys project is replaced with
the selected device in your open Quartus II software project.
To use Tcl commands that work with instance parameters in the instance script, you
must specify the commands within a Tcl procedure called a composition callback. In
the instance script, you specify the name for the composition callback with the
following command:
set_module_property COMPOSITION_CALLBACK <name of callback procedure>
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Specify the appropriate Tcl commands inside the Tcl procedure with the following
syntax:
proc <name of procedure defined in previous command> {} {
#Tcl commands to query and set parameters go here
}
Use Tcl commands in the procedure to query the parameters of a Qsys system, or to
set the values of the parameters of the subcomponents instantiated in the system.
Table 72 describes the supported Tcl commands.
Table 72. Hardware Tcl Commands Used in Instance Scripts
Command Name
Value
get_parameters
Description
Get the names of all defined parameters (as a
space-separated list).
get_parameter_value
get_instance_parameters
<instance name>
get_instance_parameter_value
<instance name>
send_message
set_instance_parameter_value
f For more information about _hw.tcl syntax and manipulating parameters, refer to the
Component Interface Tcl Reference chapter in the Quartus II Handbook.
You can use standard Tcl commands to manipulate parameters in the script, such as
the set command to create variables, or the expr command for mathematical
manipulation of the parameter values.
Example 74 shows an instance script of a simple system that uses a parameter called
pio_width to set the width parameter of a parallel I/O (PIO) component. Note that
the script combines the get_parameter_value and set_instance_parameter_value
commands into one command using square brackets [].
Example 74. Simple Instance Script
# Request a specific version of the scripting API
package require -exact qsys 13.0
# Set the name of the procedure to manipulate parameters:
set_module_property COMPOSITION_CALLBACK compose
proc compose {} {
#Get the pio_width parameter value from this Qsys system and pass the
#value to the width parameter of the pio_0 instance
set_instance_parameter_value pio_0 width [get_parameter_value \
pio_width]
}
717
DDR3
SDRAM
Qsys System
PCIe to Ethernet Bridge
DDR3
SDRAM
Controller
PHY
Cntl
PCI Express
Subsystem
Mem
Mstr
PCIe
CSR
Mem
Slave
Embedded Cntl
Mem
Mstr
CSR
Ethernet
Subsystem
Ethernet
May 2013
Enables design reuse by allowing you to use any Qsys system as a component.
For more information about hierarchical design, refer to PCI Express Subsystem
Example on page 729.
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Because Qsys systems become components in the component library, be careful not to
give your system a name that is already is use.
719
For TrustZone-aware masters, the interconnect uses the master's AxPROT signal to
determine the security status of each transaction.
The table below summarizes secure and non-secure access between master, slave, and
memory components in Qsys. Per-access refers to allowing a TrustZone-aware master
to allow or disallow a particular access (or transactions).
Table 73.
Transaction Type
TrustZone-aware
Master
Non-TrustZone-aware
Master
Secure
Non-TrustZone-aware
Master
Non-Secure
TrustZone-aware slave/memory
OK
OK
OK
Per-access
OK
Not allowed
OK
OK
OK
Per-access
OK
Not allowed
OK
OK
If a master issues transactions that fall into the per-access or not allowed cells, as
described in the table above, your design must contain a default slave. A transaction
that violates security is rerouted to the default slave and subsequently terminated
with an error. You can connect any slave as the default that is able to respond to the
master that requires a default slave with errors. You can share the default slave
between multiple masters. Altera recommends that you have one default slave for
each domain. Altera also recommends that you use the altera_axi_default_slave
component as the default slave because this component has the required TrustZone
features.
In Qsys, you can achieve an optimized secure system by planning how you partition
your design. For example, for masters and slaves under the same hierarchy, it is
possible for a non-secure master to initiate continuous transactions resulting in
unsuccessful transfer to a secure slave. In the case of a memory aliasing, you must
carefully designate secure or non-secure address maps to maintain reliable data.
May 2013
SecureMaster issues only secure transactions. For the slave, Qsys prevents nonsecure transactions from reaching the slave, and routes them to the default slave
for the master that issued the transaction.
Secure RangesSlave only, the specified address ranges within the slave's
address span are secure; all others are not. The format is a comma-separated list of
inclusiveLow:inclusiveHigh addresses, for example, 0x0:0xfff,0x2000:0x20ff.
TrustZone-awareMaster issues either secure or non-secure transactions at runtime. The slave accepts either secure or non-secure transactions at run-time.
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After setting security options for the masters and slaves, you must identify those
masters that require a default slave before generation. To designate a slave as the
default slave, turn on Default Slave in the Systems Contents tab. A master can have
only one default slave.
Masters that support TrustZone and are connected to slaves that are compile-time
secure. This configuration requires a default slave.
Slaves that support TrustZone and are connected to masters that have compiletime secure settings. This configuration does not require a default slave.
Master connected to slaves with secure address ranges. This configuration requires
a default slave.
721
Table 74 describes the files that Qsys generates. Each time you generate your system,
Qsys overwrites these files, therefore, you should not edit Qsys-generated output
files. If you have constraints, such as board-level timing constraints, Altera
recommends that you create a separate Synopsys Design Constraints File (.sdc) and
include that file in your Quartus II project. If you need to change top-level I/O pin
names or instance name, Altera recommends you create a top-level HDL file that
instantiates the Qsys system, so that the Qsys-generated output is instantiated in your
design without any changes to the Qsys output files.
Table 74. Qsys Generated Files (Part 1 of 2)
File Name or Directory Name
Description
<qsys_design>
<qsys_design>.bsf
A Block Symbol File (.bsf) representation of the top-level Qsys system for use in
Quartus II Block Diagram Files (.bdf).
<qsys_design>.html
A report for the system, which provides a system overview including the following
information:
<qsys_design>.sopcinfo
A memory map showing the address of each slave with respect to each master to
which it is connected
Describes the components and connections in your system. This file is a complete
system description and is used by downstream tools such as the Nios II tool chain.
It also describes the parameterization of each component in the system;
consequently, you can parse its contents to get requirements when developing
software drivers for Qsys components.
This file and the system.h file generated for the Nios II tool chain include address
map information for each slave relative to each master that accesses the slave.
Different masters may have a different address map to access a particular slave
component.
/synthesis
This directory includes the Qsys-generated output files that the Quartus II software
uses to synthesize your design.
<qsys_design>.v
An HDL file for the top-level Qsys system that instantiates each component in the
system.
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Description
<qsys_design>.qip
This file lists the Quartus II software needed to compile your design. You must add
the.qip file to your Quartus II project.
<qsys_design>.sip
This file lists the files necessary for simulation with Nativelink. You must add the
.sip file to your Quartus II project.
<qsys_design>.spd
/submodules
/simulation
This directory includes the Qsys-generated output files to simulate your Qsys
design or testbench system.
<qsys_design>.v or
<qsys_design>.vhd
An HDL file for the top-level Qsys system that instantiates each submodule in the
system.
/mentor/
/aldec
/synopsys/vcs/
/synopsys/vcsmx
/cadence
Contains a shell script ncsim_setup.sh and other setup files to set up and run an
NCSIM simulation.
/testbench
<qsys_design>_tb.qsys
<qsys_design>_tb.v
<qsys_design>_tb.vhd
The top-level testbench file, which connects BFMs to the top-level interfaces of
<qsys_design>.qsys.
<system_name>_<module_name>_
<master_interface_name>.svd
Allows HPS System Debug tools to view the register maps of peripherals connected
to the HPS within a Qsys design.
723
Quartus II IP File
Qsys automatically generates an .sdc file for Qsys systems and components. In most
cases, you use TimeQuest constraints to declare false paths for signals that cross clock
domains within a component, so that the TimeQuest Timing Analyzer does not
perform setup and hold analysis for them. You can add .sdc files for custom
components, with the Add Files command on Files tab in the Component Editor.
To use Nativelink simulation integration with a Qsys system, you must add the
Quartus II Simulation IP File (.sip) file to your Quartus II project. The .sip file lists the
files necessary for simulation with Nativelink. The .sip file is stored in the synthesis
directory after generation.
1
Add the generated .qip file, not the .qsys file, to your Quartus II project.
f Refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II
Handbook for further description of the TimeQuest Timing Analyzer.
h For more information about adding files to your Quartus II project, refer to Managing
Files in a Project in Quartus II Help.
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For this system, use the following commands in your .sdc file for the TimeQuest
Timing Analyzer:
create_clock -name master_clk -period 20 [get_ports {clk}]
derive_pll_clocks
These commands create the input clock and the derived clock output of the PLL. The
TimeQuest Timing Analyzer analyzes and reports performance of the constrained
clocks in the Clocks Summary report, as shown in Figure 79.
Figure 79. Clocks Summary Report
725
Generate the Verilog or VHDL simulation model for your system to use in your
own simulation environment.
First generate a testbench system, and then modify the testbench system in Qsys
before generating its simulation model.
In most cases, you should select only one of the simulation model options, that is
generate a simulation model for the original system, or for the testbench system.
Table 75 summarizes the options on the Generation tab that correspond to the
simulation flows described above.
le
Table 75. Summary of Settings Simulation and Synthesis on Qsys Generation Tab
Simulation Setting
Create simulation
model
Value
None
Verilog
VHDL
Description
Creates simulation model files and simulation scripts. Use this option to
include the simulation model in your own custom testbench or simulation
environment. You can also use this option to generate models for a
testbench system that you have modified.
Creates a testbench Qsys system with BFM components attached to
exported Avalon and AXI3 interfaces. Includes any simulation partner
modules specified by IP cores in the system.
In Qsys 13.0, the testbench generator supports AXI interfaces and can
connect AXI3/AXI4 interfaces to Mentor Graphics AXI3/AXI4 master/slave
BFM. For more information, refer to the Mentor Verification IP (VIP) Altera
Edition (AE) document. However, BFM supports only an address width of
up to 32-bits.
Create testbench
simulation model
None
Verilog
VHDL
Creates simulation model files and simulation scripts for the testbench
Qsys system specified in the setting above. Use this option if you do not
need to modify the Qsys-generated testbench before running the
simulation.
On/Off
Top-level module
language for synthesis
Verilog
VHDL
On/Off
You can optionally create a (.bsf) file to use in schematic Block Diagram
File (.bdf) designs.
Output Directory
<directory name>
Allows you to browse and locate an alternate directory than the project
directory for each generation target.
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f For more information about using bus functional models (BFMs) and monitors to
simulate Avalon standard interfaces, including tutorials demonstrating sample
systems, refer to the Avalon Verification IP Suite User Guide. For AXI verification
protocol information, refer to the Mentor Verification IP (VIP) Altera Edition (AE)
document.
h For more information about generating system synthesis or simulation models, and a
standard Qsys testbench, refer to Generating a System for Synthesis or Simulation and
Generation Tab (Qsys) in Quartus II Help.
Modelsim Altera Edition does not support SystemVerilog assertions. If you want to
use assertion monitors, you will need to use an advanced simulator such as Mentor
Questasim, Synopsys VCS, or Cadence Incisive.
727
Figure 710 demonstrates the use of monitors with an Avalon-MM monitor between
the previously connected pcie_compiler bar1_0_Prefetchable Avalon-MM master
interface and the dma_0 control_port_slave Avalon-MM slave interface.
Figure 710. Inserting an Avalon-MM Monitor between Avalon-MM Master and Slave Interfaces
Similarly, you can insert an Avalon-ST monitor between Avalon-ST source and sink
interfaces.
Simulation Scripts
Qsys generates simulation scripts to script the simulation environment set up for
Mentor Graphics Modelsim and Questasim, Synopsys VCS and VCS MX, Cadence
Incisive Enterprise Simulator (NCSIM), and the Aldec Riviera-PRO Simulator. You
can use the scripts to compile the required device libraries and system design files in
the correct order and elaborate or load the top-level design for simulation.
The simulation scripts provide the following variables that allow flexibility in your
simulation environment:
TOP_LEVEL_NAMEIf the Qsys testbench system is not the top-level instance in your
simulation environment because you instantiate the Qsys testbench within your
own top-level simulation file, set the TOP_LEVEL_NAME variable to the top-level
hierarchy name.
QSYS_SIMDIRIf the simulation files generated by Qsys are not in the simulation
working directory, use the QSYS_SIMDIR variable to specify the directory location of
the Qsys simulation files.
Example 75 shows a simple top-level simulation HDL file for a testbench system
pattern_generator_tb, which was generated for a Qsys system called
pattern_generator. The top.sv file defines the top-level module that instantiates the
pattern_generator_tb simulation model as well as a custom SystemVerilog test
program with BFM transactions, called test_program.
Example 75. Top-level Simulation HDL File
module top();
pattern_generator_tb tb();
test_program pgm();
endmodule
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System Examples
This section includes a detailed system example that demonstrates design hierarchy
and the use of pipeline bridges, and an example that shows the use of instance
parameters to control the instantiation of subcomponents in a hierarchical system.
729
PCI Express
IP Core
CSR
M CSR
Rd
S CSR
Wr
S Tx Data
Avalon-MM PIpeline
Bridge (Qsys)
Avalon-MM PIpeline
Bridge (Qsys)
Cn
PCIe Link
(exported
to PCIe root port)
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Figure 712 shows the Qsys representation of the PCI Express subsystem.
Figure 712. Qsys Representation of the PCI Express Subsystem
Ethernet Subsystem
Qsys inserts
arbitration
logic
DDR3
Avalon-MM
Pipeline
Bridge
M
S
(Qsys)
Scatter Gather
TX Avalon-ST
Src
DMA
S CSR
Cn
Snk
Ethernet
Triple Speed
Ethernet
M
Scatter Gather
DMA
Snk
CSR S
RX Avalon-ST
Src
CSR
Cn
Calibration
Avalon-MM Pipeline
Bridge (Qsys)
S
CSR
731
Qsys System
Qsys inserts
arbitration and
Clock crossing
logic
(125 MHz-200MHz)
DDR3
SDRAM
400 MHz
DDR3
SDRAM
Controller
C
PCI Express
Subsystem
125 MHz
PCIe link Cn
CSR S
Avalon-MM
PIpeline
Bridge (Qsys)
M
S
to CPU
200 MHz
M DDR3
CSR
125 MHz
Calibration Cn
Ethernet
Subsystem
125 MHz
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Altera Corporation
Ethernet Cn
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Figure 716 shows the Qsys representation of the PCI Express-to-Ethernet Bridge
example.
Figure 716. Qsys Representation of the Complete PCI Express to Ethernet Bridge
Pipeline Bridges
The PCI Express to Ethernet bridge example system uses several pipeline bridges.
These bridges must be configured to accommodate the address range of all of
connected components, including the components in the originating subsystem and
the components in the next higher level of the system hierarchy. As the name
suggests, the pipeline bridge inserts a pipeline stage between the connected
components. Altera recommends registering signals at the subsystem interface level
for the following reasons:
Registering interface signals raises the potential frequency, or fMAX, of your design
at the expense of an additional cycle of latency, which might adversely affect
system throughput.
The Quartus II incremental compilation feature can achieve better fMAX results if
the subsystem boundary is registered.
f For more information about optimizing a Qsys design for performance using bridges
and other techniques, refer to Optimizing System Performance for Qsys in volume 1 of
the Quartus II Handbook.
1
AXI bridge components are not available in the Quartus II software, but you can
connect AXI interfaces with other bridge types. Connections between AXI and Avalon
interfaces are made without requiring the use of explicitly instantiated bridges; the
interconnect provides all necessary bridging logic.For more information about AXI
support, refer to the Qsys System Design Components chapter in volume 1 of the
Quartus II Handbook.
733
To satisfy the design requirements for this example, you define an instance parameter
in my_system.qsys that is set by the higher-level system, and then define an instance
script to specify how the values of the parameters of the My_IP components
instantiated in my_system.qsys are affected by the value set on the instance
parameter.
To do this, in Qsys, open the my_system.qsys Qsys system that instantiates the two
instances of the My_IP components. On the Instance Parameters tab, create a
parameter called system_id. For this example, you can set this parameter to be of type
Integer and choose 0 as the default value.
Next, you provide a Tcl Instance Script that defines how the value of the system_id
parameter should affect the parameters of comp0 and comp1 subcomponents in
my_system.qsys.
The example script in Example 76gets the value of the parameter system_id from the
top-level system and saves it as top_id, and then increments the value by 1 and 2. The
script then uses the new calculated values to set the MY_SYSTEM_ID parameter in the
My_IP component for the instances comp0 and comp1. The script uses informational
messages to print the status of the parameter settings when the my_system.qsys
system is added to the higher-level system.
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You can click Preview Instance to see a parameters panel that allows you to modify
the parameter value interactively and see the effect of the scripts in the message panel
which can be useful for debugging the script. In this example, if you change the
parameter value in the Preview screen, the component generates messages to report
the top-level ID parameter value and the parameter values used for the two instances
of the component.
h For more information on creating a parameter on the Instance Parameters tab, refer to
Working with Instance Parameters in Qsys in Quartus II Help.
735
For more information about Qsys utilities and scripting, including examples, refer to
the Altera Wiki Qsys Scripts page.
May 2013
<1st arg file>Required. The name of the .qsys system file to generate.
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You must provide a package version for the qsys-script. If you do not specify the
--package-version=<value> qsys-script command, you must then provide a Tcl
script and request the system scripting API directly with the package require -exact
qsys <version> command.
The following is a list of options that you can use with the qsys-script utility:
739
Full Description
page 741
page 741
page 741
auto_assign_base_addresses <instance>
page 742
auto_assign_irqs <instance>
page 742
auto_connect <element>
page 742
create_system [<name>]
page 742
page 743
page 743
get_composed_connections <instance>
page 743
page 744
page 744
page 744
page 745
get_composed_instances <instance>
page 745
page 745
page 745
get_connection_parameters <connection>
page 746
get_connection_properties
page 746
page 746
get_connections [<element>]
page 746
page 747
get_instance_assignments <instance>
page 747
page 747
page 747
page 748
page 750
page 748
page 749
page 749
get_instance_interface_properties
page 749
page 749
get_instance_interfaces <instance>
page 750
page 750
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Full Description
page 750
get_instance_parameters <instance>
page 750
page 751
get_instance_properties
page 751
page 751
get_instances
page 751
page 752
get_interface_ports <interface>
page 752
get_interface_properties
page 752
page 752
get_interfaces
page 753
get_module_properties
page 753
get_module_property <property>
page 753
get_parameter_properties
page 753
get_port_properties
page 754
get_project_properties
page 754
get_project_property <property>
page 758
load_system <file>
page 754
lock_avalon_base_address <instance.interface>
page 755
preview_insert_avalon_streaming_adapters
page 755
remove_connection <connection>
page 755
remove_instance <instance>
page 755
remove_interface <interface>
page 756
save_system [<file>]
page 756
page 756
page 757
page 757
page 757
page 758
page 753
page 758
page 759
unlock_avalon_base_address <instance.interface>
page 759
upgrade_sopc_system <filename>
page 759
validate_connection <connection>
page 760
validate_instance <instance>
page 760
page 760
validate_system
page 760
741
Interface properties work differently for qsys scripting than with _hw.tcl scripting. In
_hw.tcl, interfaces do not distinguish between properties and parameters; in qsys
scripting, properties and parameters are unique.
add_connection
This command connects interfaces using an appropriate connection type. Interface
names consist of a child instance name, followed by the name of an interface provided
by that module, for example, mux0.out is the interface out on the instance named
mux0.
add_connection
Usage
Returns
None
Arguments
start
end (optional)
Example
add_instance
This command adds an instance of a component, referred to as a child or child
instance, to the system.
add_instance
Usage
Returns
None
Arguments
Example
name
Specifies a unique local name that you can use to manipulate the instance. This
name is used in the generated HDL to identify the instance.
type
version
(optional)
The required version of the specified instance type. If no version is specified, the
latest version is used.
add_interface
This command adds an interface to your system, which you can use to export an
interface from within the system. You specify the exported interface with the
command set_interface_property EXPORT_OF <instance.interface>.
add_interface
Usage
Returns
None
Arguments
Example
May 2013
name
The name of the interface that will be exported from the system
type
direction
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742
auto_assign_base_addresses
This command assigns base addresses to memory-mapped interfaces on an instance
in the system. Instance interfaces that are locked with lock_avalon_base_address
command keep their addresses during address auto-assignment.
auto_assign_base_addresses
Usage
auto_assign_base_addresses <instance>
Returns
None
Arguments
instance
Example
auto_assign_base_addresses sdram
auto_assign_irqs
This command assigns interrupt numbers to all connected interrupt senders on an
instance in the system.
auto_assign_irqs
Usage
auto_assign_irqs <instance>
Returns
None
Arguments
instance
Example
auto_assign_irqs sdram
auto_connect
This command creates connections from an instance or instance interface to matching
interfaces in other instances in the system. For example, Avalon-MM slaves are
connected to Avalon-MM masters.
auto_connect
Usage
auto_connect <element>
Returns
None
Arguments
element
Example
auto_connect sdram
auto_connect uart_0.s1
create_system
This command replaces the current system in the system script with a new system
with the specified name.
create_system
Usage
create_system [<name>]
Returns
None
Arguments
name (optional)
Example
create_system my_new_system_name
743
get_composed_connection_parameter_value
This command returns the value of a parameter in a connection in the subsystem, for
an instance that contains a subsystem.
get_composed_connection_parameter_value
Usage
Returns
String
instance
childConnection
parameter
Arguments
Example
get_composed_connection_parameters
This command returns a list of parameters on a connection in the subsystem, for an
instance that contains a subsystem.
get_composed_connection_parameters
Usage
Returns
String[]
Arguments
instance
childConnection
Example
get_composed_connections
This command returns a list of all connections in a subsystem, for an instance that
contains a subsystem.
get_composed_connections
Usage
get_composed_connections <instance>
Returns
String[]
A list of connection names in the subsystem. These connection names will not be
qualified with the instance name.
Arguments
instance
Example
get_composed_connections subsystem_0
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get_composed_instance_assignment
This command returns the value of an assignment on an instance of a subsystem, for
an instance that models a subsystem.
get_composed_instance_assignment
Usage
Returns
String
instance
childInstance
key
Arguments
Example
get_composed_instance_assignments
This command returns a list of assignments on an instance of a subsystem, for an
instance that contains a subsystem.
get_composed_instance_assignments
Usage
Returns
String[]
Arguments
instance
childInstance
Example
get_composed_instance_parameter_value
This command returns the value of a parameters on an instance in a subsystem, for an
instance that contains a subsystem.
get_composed_instance_parameter_value
Usage
Returns
String
instance
childInstance
parameter
Arguments
Example
745
get_composed_instance_parameters
This command returns a list of parameters on an instance of a subsystem, for an
instance that contains a subsystem.
get_composed_instance_parameters
Usage
Returns
String[]
Arguments
instance
childInstance
Example
get_composed_instances
This command returns a list of child instances in the subsystem, for an instance that
contains a subsystem.
get_composed_instances
Usage
get_composed_instances <instance>
Returns
String[]
Arguments
instance
Example
get_composed_instances subsystem_0
get_connection_parameter_property
This command returns the value of a parameter property in a connection.
get_connection_parameter_property
Usage
Returns
various
connection
parameter
property
Arguments
Example
get_connection_parameter_value
This command gets the value of a parameter on the connection. Parameters represent
aspects of the connection that can be modified once the connection is created, such as
the base address for an Avalon-MM connection.
get_connection_parameter_value
Usage
Returns
various
Arguments
connection
parameter
Example
May 2013
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get_connection_parameters
This command returns a list of parameters found on a connection. The list of
connection parameters is the same for all connections of the same type.
get_connection_parameters
Usage
get_connection_parameters <connection>
Returns
String[]
Arguments
connection
Example
get_connection_parameters cpu.data_master/dma0.csr
get_connection_properties
This command returns a list of properties found on a connection. The list of
connection properties is the same for all connections, regardless of type.
get_connection_properties
Usage
get_connection_properties
Returns
String[]
Arguments
None
Example
get_connection_properties
get_connection_property
This command returns the value of a connection property.
get_connection_property
Usage
Returns
String
Arguments
connection
property
Example
get_connections
This command returns a list of connections in the system if no element is specified. If
a child instance is specified, for example cpu, all connections to any interface on the
instance are returned. If an interface on a child instance is specified, for example
cpu.instruction_master, only connections to that interface are returned.
get_connections
Usage
get_connections [<element>]
Returns
String[]
A list of connections
Arguments
element
(optional)
get_connections
Example
get_connections cpu
get_connections cpu.instruction_master
747
get_instance_assignment
This command returns the value of an assignment on a child instance.
get_instance_assignment
Usage
Returns
String
Arguments
instance
key
Example
get_instance_assignments
This command returns a list of assignment keys for any assignments defined for the
instance.
get_instance_assignments
Usage
get_instance_assignments <instance>
Returns
String[]
Arguments
instance
Example
get_instance_assignments sdram
get_instance_interface_assignment
This command returns the value of an assignment on an interface of a child instance.
get_instance_interface_assignment
Usage
Returns
String
instance
interface
key
Arguments
Example
get_instance_interface_assignments
This command returns the value of an assignment on an interface of a child instance.
get_instance_interface_assignments
Usage
Returns
String[]
Arguments
instance
interface
Example
May 2013
get_instance_interface_assignments sdram s1
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748
get_instance_interface_parameter_property
This command returns the property value on a parameter in an interface of a child
instance.
get_instance_interface_parameter_property
Usage
Returns
various
instance
interface
parameter
property
Arguments
Example
get_instance_interface_parameter_value
This command returns the value of a parameter of an interface in a child instance.
get_instance_interface_parameter_value
Usage
Returns
various
instance
interface
parameter
Arguments
Example
get_instance_interface_parameters
This command returns a list of parameters for an interface in a child instance.
get_instance_interface_parameters
Usage
Returns
String[]
Arguments
instance
interface
Example
get_instance_interface_parameters uart_0 s0
749
get_instance_interface_port_property
This command returns the property value of a port in the interface of a child instance.
get_instance_interface_port_property
Usage
Returns
various
instance
interface
port
property
Arguments
Example
get_instance_interface_ports
This command returns a list of ports in an interface of a child instance.
get_instance_interface_ports
Usage
Returns
String[]
Arguments
instance
interface
Example
get_instance_interface_ports uart_0 s0
get_instance_interface_properties
This command returns a list of properties that you can be query for an interface in a
child instance.
get_instance_interface_properties
Usage
get_instance_interface_properties
Returns
String[]
Arguments
None
Example
get_instance_interface_properties
get_instance_interface_property
This command returns the property value for an interface in a child instance.
get_instance_interface_property
Usage
Returns
String
instance
interface
property
Arguments
Example
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get_instance_interfaces
This command returns a list of interfaces in a child instance.
get_instance_interfaces
Usage
get_instance_interfaces <instance>
Returns
String[]
Arguments
instance
Example
get_instance_interfaces uart_0
get_instance_parameter_property
This command returns the value of a property on a parameter in a child instance.
get_instance_parameter_property
Usage
Returns
various
instance
parameter
property
Arguments
Example
get_instance_parameter_value
This command returns the value of a property in a child instance.
get_instance_parameter_value
Usage
Returns
various
Arguments
instance
parameter
Example
get_instance_parameters
This command returns a list of parameters in a child instance.
get_instance_parameters
Usage
get_instance_parameters <instance>
Returns
String[]
Arguments
instance
Example
get_instance_parameters uart_0
751
get_instance_port_property
This command returns the value of a property of a port contained by an interface in a
child instance.
get_instance_port_property
Usage
Returns
various
instance
port
property
Arguments
Example
get_instance_properties
This command returns a list of properties for a child instance.
get_instance_properties
Usage
get_instance_properties
Returns
String[]
Arguments
None
Example
get_instance_properties
get_instance_property
This command returns the value of a property for a child instance.
get_instance_property
Usage
Returns
String
Arguments
instance
property
Example
get_instances
This command returns a list of the instance names for all child instances in the system.
get_instances
Usage
get_instances
Returns
String[]
Arguments
None
Example
get_instances
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get_interface_port_property
This command returns the value of a property of a port contained by one of the toplevel exported interfaces.
get_interface_port_property
Usage
Returns
various
interface
port
property
Arguments
Example
get_interface_ports
This command returns the names of all of the ports that have been added to an
interface.
get_interface_ports
Usage
get_interface_ports <interface>
Returns
String[]
Arguments
interface
Example
get_interface_ports export_clk_out
get_interface_properties
This command returns the names of all the available interface properties. The list of
interface properties is the same for all interface types.
get_interface_properties
Usage
get_interface_properties
Returns
String[]
Arguments
None
Example
get_interface_properties
get_interface_property
This command returns the value of a property from the specified interface.
get_interface_property
Usage
Returns
various
Arguments
interface
property
Example
753
get_interfaces
This command returns a list of top-level interfaces in the system.
get_interfaces
Usage
get_interfaces
Returns
String[]
Arguments
None
Example
get_interfaces
get_module_properties
This command returns the properties that you can manage for the top-level module.
get_module_properties
Usage
get_module_properties
Returns
String[]
Arguments
None
Example
get_module_properties
get_module_property
This command returns the value of a top-level system property.
get_module_property
Usage
get_module_property <property>
Returns
String
Arguments
property
Example
get_module_property NAME
get_parameter_properties
This command returns a list of properties that you can query on parameters. These
properties can be queried on any parameter, such as parameters on instances,
interfaces, instance interfaces, and connections.
get_parameter_properties
Usage
get_parameter_properties
Returns
String[]
Arguments
None
Example
get_parameter_properties
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get_port_properties
This command returns a list of properties that you can query on ports.
get_port_properties
Usage
get_port_properties
Returns
String[]
Arguments
None
Example
get_port_properties
get_project_properties
This command returns a list of properties that you can query for the Quartus II
project.
get_project_properties
Usage
get_project_properties
Returns
String[]
Arguments
None
Example
get_project_properties
get_project_property
This command returns the value of a Quartus II project property.
get_project_property
Usage
get_project_property <property>
Returns
String
Arguments
property
Example
get_project_property DEVICE_FAMILY
load_system
This command loads a Qsys system from a file, and uses the system as the current
system for scripting commands.
load_system
Usage
load_system <file>
Returns
None
Arguments
file
Example
load_system example.qsys
755
lock_avalon_base_address
This command prevents the memory-mapped base address from being changed for
connections to an interface on an instance when the auto_assign_base_addresses or
auto_assign_system_base_addresses commands are run.
lock_avalon_base_address
Usage
lock_avalon_base_address <instance.interface>
Returns
None
Arguments
instance.interface
Example
lock_avalon_base_address sdram.s1
preview_insert_avalon_streaming_adapters
This command runs the adapter insertion for Avalon-ST connections, which adapt
connections with mismatched configuration, such as mismatched data widths.
preview_insert_avalon_streaming_adapters
Usage
preview_insert_avalon_streaming_adapters
Returns
None
Arguments
None
Example
preview_insert_avalon_streaming_adapters
remove_connection
This command removes a connection from the system.
remove_connection
Usage
remove_connection <connection>
Returns
None
Arguments
connection
Example
remove_connection cpu.data_master/sdram.s0
remove_instance
This command removes a child instance from the system.
remove_instance
Usage
remove_instance <instance>
Returns
None
Arguments
instance
Example
remove_instance cpu
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remove_interface
This command removes an exported top-level interface from the system.
remove_interface
Usage
remove_interface <interface>
Returns
None
Arguments
interface
Example
remove_interface clk_out
save_system
This command saves the current in-memory system to the named file. If the file is not
specified, the system saves to the same file that was opened with the load_system
command.
save_system
Usage
save_system [<file>]
Returns
None
Arguments
file (optional)
Example
save_system
save_system example.qsys
send_message
This command sends a message to the user of the script. The message text is normally
interpreted as HTML. You can use the <b> element to provide emphasis.
send_message
Usage
Returns
None
The following message levels are supported:
Arguments
level
message
Example
757
set_connection_parameter_value
This command sets the parameter value for a connection.
set_connection_parameter_value
Usage
Returns
None
Arguments
Example
connection
The connection
parameter
value
set_instance_parameter_value
This command set the parameter value for a child instance. Derived parameters and
SYSTEM_INFO parameters for the child instance can not be set with this command.
set_instance_parameter_value
Usage
Returns
None
Arguments
Example
instance
parameter
value
set_instance_property
This command sets the property value of a child instance. Most instance properties
are read-only and can only be set by the instance itself. The primary use for this
command is to update the ENABLED parameter, which includes or excludes a child
instance when generating the system.
set_instance_property
Usage
Returns
None
Arguments
Example
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instance
property
value
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set_interface_property
This command sets the property value on an exported top-level interface. This
command is used to set the EXPORT_OF property to specify which interface of a child
instance is exported by the top-level interface.
set_interface_property
Usage
Returns
None
Arguments
Example
interface
property
value
set_module_property
This command sets the system property value, such as the name of the system using
the NAME property.
set_module_property
Usage
Returns
None
Arguments
property
value
Example
set_project_property
This command sets the project property value, such as the device family.
set_project_property
Usage
Returns
None
Arguments
property
value
Example
759
set_validation_property
This command sets a property that affects how and when validation is run during
system scripting. To disable system validation after each scripting command, set
AUTOMATIC_VALIDATION to false.
set_validation_property
Usage
Returns
None
Arguments
property
value
Example
unlock_avalon_base_address
This command allows the memory-mapped base address to be changed for
connections to an interface on an instance when the auto_assign_base_addresses or
auto_assign_system_base_addresses commands are run.
unlock_avalon_base_address
Usage
unlock_avalon_base_address <instance.interface>
Returns
None
Arguments
instance.interface
Example
unlock_avalon_base_address sdram.s1
upgrade_sopc_system
This command loads the specified .sopc file, which then upgrades the file as a
Qsys-compatible system. Some child instances and interconnect are replaced so that
the system functions in Qsys. You must save the new Qsys-compatible system with
the save_system command.
upgrade_sopc_system
Usage
upgrade_sopc_system <filename>
Returns
None
Arguments
filename
Example
upgrade_sopc_system old_system.sopc
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The path to the .sopc file being upgraded. The upgrade will move the .sopc file and
related generation files to a backup directory.
760
validate_connection
This command validates the specified connection, and returns the during validation
messages.
validate_connection
Usage
validate_connection <connection>
Returns
String[]
Arguments
connection
Example
validate_connection cpu.data_master/sdram.s1
validate_instance
This command validates the specified child instance, and returns the validation
messages.
validate_instance
Usage
validate_instance <instance>
Returns
String[]
Arguments
instance
Example
validate_instance cpu
validate_instance_interface
This command validates an interface on a child instance, and returns the validation
messages.
validate_instance_interface
Usage
Returns
String[]
Arguments
instance
interface
Example
validate_system
This command validates the system, and returns the validation messages.
validate_system
Usage
validate_system
Returns
String[]
Arguments
None
Example
validate_system
761
Version
May 2013
13.0.0
November 2012
June 2012
12.1.0
12.0.0
November 2011
May 2011
11.1.0
11.0.0
December 2010
10.1.0
Changes
Added Using Instance Parameters and Example Hierarchical System Using Parameters.
Initial release.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
m
May 2013
For more information about the benefits of using Qsys, refer to Five Reasons to Switch
from SOPC Builder to Qsys on the Webcasts and Videos page of the Altera website.
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This chapter describes the structure of Qsys components, with an emphasis on using
the Qsys Component Editor to create the Hardware Component Description File
(_hw.tcl), which describe and package components that you can use in a Qsys system.
Qsys supports standard Avalon, AMBA AXI3 (version 1.0), AMBA AXI4
(version 2.0), and AMBA APB 3 (version 1.0) interfaces. For more information about
Avalon and AMBA interfaces, refer to the Avalon Interface Specifications and the
AMBA Protocol Specifications on the ARM website. AXI4-Lite is not supported.
This chapter uses the Demo AXI Memory example available on the Qsys Design
Examples page of the Altera web site.
f For Tcl command reference information, refer to the Component Interface Tcl Reference
chapter in volume 1 of the Quartus II Handbook.
Qsys Components
A Qsys component includes the following elements:
Information about the component type, such as name, version, and author.
Constraint files (.sdc or Quartus) that define the component for synthesis and
simulation.
Component Interfaces
Components can have any number of interfaces in any combination. For example, a
component might provide both an Avalon-ST source port for high-throughput data,
and a memory-mapped slave port for register configuration.
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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82
Static Components
You implement a static component using the same HDL files for all instances of the
component. If the top-level HDL module is parameterized, instances may have
unique behavior, depending on the parameter values.
Generated Components
A generated component's fileset callback allows an instance of the component to
create unique HDL design files based on the instance's parameter values.
83
For example, you can write a fileset callback to include a control and status interface
based on the value of a parameter. The callback overcomes a limitation of HDL
languages, which do not allow runtime parameters.
1
For information about defining fileset callback procedures, refer to Controlling File
Generation Dynamically with Parameters and a Fileset Callback on page 827.
Composed Components
Composed components are subsystems constructed from instances of other
components. You can use a composition callback to manage the subsystem in a
composed component.
For information about creating a composed component, refer to Creating a
Composed Component or Subsystem on page 828.
<component_directory>/
<hdl>/Contains the component HDL design files, for example .v, .sv, or .vhd
files that contain the top-level module, along with any required constraint files.
Component Versions
Qsys systems support multiple versions of the same component within the same
system; you can create and maintain multiple versions of the same component.
If you have multiple _hw.tcl files for components with the same NAME module
properties and different VERSION module properties, both versions of the
component are available.
If multiple versions of the component are available in the Qsys Component Library,
you can add a specific version of a component by right-clicking the component, and
then selecting Add version <version_number>.
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DiscoveryDuring the discovery phase, Qsys reads the _hw.tcl file to identify
information that appears in the Qsys Component Library, such as the component's
name, version, and documentation URLs. Each time you open Qsys, the tool
searches for the following file types using the default search locations and entries
in the IP Search Path:
85
ElaborationDuring the elaboration phase, Qsys queries the component for its
interface information. Elaboration is triggered when an instance of a component is
added to a system, when its parameters are changed, or when a system property
changes. You can use callback procedures that run during the elaboration phase to
dynamically control interfaces, signals, and HDL files based on the values of
parameters. For example, interfaces defined with static declarations can be
enabled or disabled during elaboration. When elaboration is complete, the
component's interfaces and design logic must be completely defined.
Specify the SystemVerilog, Verilog HDL, or VHDL files, and constraint files that
define the component for synthesis and simulation.
Create an HDL template for a component by first defining its parameters, signals,
and interfaces.
In a Qsys system, the interfaces of a component are connected within the system, or
exported as top-level signals from the system.
If you are creating the component using an existing HDL file, the order in which the
tabs appear in the Component Editor reflects the recommended design flow for
component development. You can use the Prev and Next buttons at the bottom of the
Component Editor window to guide you through the tabs.
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If the component is not based on an existing HDL file, enter the parameters, signals,
and interfaces first, and then return to the Files tab to create the top-level HDL file
template. When you click Finish, Qsys creates the component _hw.tcl file with the
details provided on the Component Editor tabs.
After the component is saved, it is available in the Qsys Component Library.
If you require features in the component that are not supported by the Component
Editor, such as callback procedures, you can use the Component Editor to create the
_hw.tcl file, and then manually edit the file to complete the component definition.
Subsequent sections of this chapter document the hw.tcl commands that are
generated by the Component Editor, as well as some of the advanced features that
you can add with your own hw.tcl commands.
f For full syntax and details about all hw.tcl commands, refer to the Component Interface
Tcl Reference chapter in volume 1 of the Quartus II Handbook.
Altera recommends that you save _hw.tcl files and their associated files in an
ip/<class-name> directory within your Quartus II project directory.
f You can publish component information for use by software, such as a C compiler and
a board support package (BSP) generator. For information on how to publish
hardware component information for embedded software tools, refer to the Publishing
Component Information to Embedded Software chapter in the Nios II Software Developers
Handbook.
Editing a Component
In Qsys, you make changes to a component by right-clicking the component in the
Component Library, and then clicking Edit. After making changes, click Finish to
save the changes to the _hw.tcl file. You can open the _hw.tcl file in a text editor to
view the hardware Tcl for the component. If you edit the _hw.tcl file to use advanced
features, you cannot use the Component Editor to make further changes without
over-writing the original file.
1
You cannot use the Component Editor to edit components installed with the
Quartus II software, such as Altera-provided components. If you edit the HDL for a
component and change the interface to the top-level module, you must edit the
component to reflect the changes you made to the HDL.
h For more information about the procedures for creating components in the
Component Editor, refer to Creating Qsys Components in Quartus II Help.
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NameSpecifies the name used in the _hw.tcl filename, as well as in the top-level
module name when you create a synthesis wrapper file for a non HDL-based
component.
Display nameIdentifies the component in the parameter editor, which you use
to configure and instance of the component, and also appears in the Component
Library under Project and on the System Contents tab.
IconAllows you to enter the relative path to an icon file (.gif, .jpg, or .pgn
format) that represents the component and appears as the header in the parameter
editor for the component. The default image is the Altera MegaCore function icon.
To specify an Internet file, begin your path with http://, for example:
http://mydomain.com/datasheets/my_memory_controller.html.
To specify a file in the file system, begin your path with file:/// for Linux, and
file://// for Windows; for example (Windows):
file:////company_server/datasheets/ my_memory_controller.pdf.
The Display name, Group, Description, Created By, Icon, and Documentation
entries are optional.
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Figure 81 shows an example of the Component Type tab with the component
information.
Figure 81. Component Type Tab in the Component Editor
When you use the Component Editor to create a component, it writes this basic
component information in the _hw.tcl file. Example 81 shows the component
hardware Tcl code related to the entries for the Component Type tab in Figure 81.
The package require command specifies the ACDS version that Qsys uses to create
the _hw.tcl file, and ensures compatibility with this version of the Qsys API in future
ACDS releases.
The component defines its basic information with various module properties using
the set_module_property command. For example, set_module_property NAME
specifies the name of the component, while set_module_property VERSION allows
you to specify the version of the component. When you apply a version to the _hw.tcl
file, it allows the file to behave exactly the same way in future releases of the
Quartus II software.
Example 81. Hardware Tcl Commands Created from the Component Type Tab in the Component Editor
#
# request TCL package from ACDS 13.0
#
package require -exact qsys 13.0
#
# module demo_axi_memory
#
set_module_property DESCRIPTION "Demo AXI-3 memory with optional Avalon-ST port"
set_module_property NAME demo_axi_memory
set_module_property VERSION 1.0
set_module_property GROUP "My Components"
set_module_property AUTHOR Altera
set_module_property DISPLAY_NAME "Demo AXI Memory"
f For more information about _hw.tcl syntax and advanced features that you can add to
a component definition, refer to the Component Interface Tcl Reference chapter in
volume 1 of the Quartus II Handbook.
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A component must specify an HDL file as the top-level file, which contains the
top-level module. The Synthesis Files list might also include supporting HDL files,
such as timing constraints, or other files required to successfully synthesize and
compile in the Quartus II software. The synthesis files for a component are copied to
the generation output directory during Qsys system generation.
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Figure 82 indicates the demo_axi_memory.sv file as the top-level file for the
component in the Synthesis Files section on the Files tab.
Figure 82. Using HDL Files to Define a Component
At this stage in the Component Editor flow, you cannot add or remove parameters or
signals created from a specified HDL file without editing the HDL file itself.
Example 82 shows the component hardware Tcl code related to the entries for the
Files Type tab in the Synthesis Files section in Figure 82.
811
The synthesis files are added to a fileset with the name QUARTUS_SYNTH and type
QUARTUS_SYNTH. The top-level module is used to specify the TOP_LEVEL fileset property.
Each synthesis file is individually added to the fileset. If the source files are saved in a
different directory from the working directory where the _hw.tcl is located, you can
use standard fixed or relative path notation to identify the file location for the PATH
variable.
Example 82. Hardware Tcl Commands Created from the Files Tab - Synthesis FIles Section of the Component Editor
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL demo_axi_memory
add_fileset_file demo_axi_memory.sv SYSTEM_VERILOG PATH demo_axi_memory.sv
add_fileset_file single_clk_ram.v VERILOG PATH single_clk_ram.v
f For more information about _hw.tcl syntax and advanced features that you can add to
a component definition, refer to the Component Interface Tcl Reference chapter in
volume 1 of the Quartus II Handbook.
Specifying an interface name with <interface name> is optional if you have only one
interface of each type in the component definition. For interfaces with only one signal,
such as clock and reset inputs, the <interface type prefix> is also optional. When the
Component Editor recognizes a valid prefix and signal type for a signal, it
automatically assigns an interface and signal type to the signal based on the naming
convention. If no interface name is specified for a signal, you can choose an interface
name on the Interfaces tab in the Component Editor.
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Interface Type
asi
aso
avm
Avalon-MM master
avs
Avalon-MM slave
axm
AXI master
axs
AXI slave
apm
APB master
aps
APB slave
coe
Conduit
csi
cso
inr
Interrupt receiver
ins
Interrupt sender
ncm
ncs
rsi
rso
tcm
Avalon-TC master
tcs
Avalon-TC slave
Refer to the Avalon Interface Specifications or the AMBA Protocol Specification for the
signal types available for each interface type.
813
Figure 83 shows the files specified for simulation on the Files tab.
Figure 83. Specifying the Simulation Output Files
Example 83 shows the component hardware Tcl code related to the entries for the
Files Type tab in the Simulation Files section.
Example 83. Hardware Tcl Commands Created from the Files Tab - Simulation Files Section of the Component Editor
add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL demo_axi_memory
add_fileset_file single_clk_ram.v VERILOG PATH single_clk_ram.v
add_fileset_file verbosity_pkg.sv SYSTEM_VERILOG PATH verification_lib/verbosity_pkg.sv
add_fileset_file demo_axi_memory.sv SYSTEM_VERILOG PATH demo_axi_memory.sv
add_fileset SIM_VHDL SIM_VHDL "" ""
set_fileset_property SIM_VHDL TOP_LEVEL demo_axi_memory
set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file demo_axi_memory.sv SYSTEM_VERILOG PATH demo_axi_memory.sv
add_fileset_file single_clk_ram.v VERILOG PATH single_clk_ram.v
add_fileset_file verbosity_pkg.sv SYSTEM_VERILOG PATH verification_lib/verbosity_pkg.sv
f For more information about _hw.tcl syntax and advanced features that you can add to
a component definition, refer to the Component Interface Tcl Reference chapter in
volume 1 of the Quartus II Handbook.
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The Parameters tab in the Component Editor allows you specify the parameters that
are used to configure instances of the component in a Qsys system. You can specify
various properties for each parameter that describe how the parameter is displayed
and used. You can also specify a range of allowed values that are checked during the
Validation phase. The Parameters table displays the HDL parameters that are
declared in the top-level HDL module. If you have not yet created the top-level HDL
file, the parameters that you create on the Parameters tab are included in the top-level
synthesis file template created from the Files tab.
When the component includes HDL files, the parameters match those defined in the
top-level module, and you cannot be add or remove them on the Parameters tab. To
add or remove the parameters, edit your HDL source, and then re-analyze the file.
If you used the Component Editor to create a top-level template HDL file for
synthesis, you can remove the newly-created file from the Synthesis Files list on the
Files tab, make your parameter changes, and then re-analyze the top-level synthesis
file.
You can use the Parameters table to specify the following information about each
parameter:
Default ValueSets the default value used in new instances of the component.
EditableSpecifies whether or not the user can edit the parameter value.
TooltipAllows you to add a description of the parameter that appears when the
user of the component points to the parameter in the parameter editor.
815
On the Parameters tab, you can click Preview the GUI at any time to see how the
declared parameters appear in the parameter editor. Figure 84 shows parameters
with their default values defined, with checks in the Editable column indicating that
users of this component are allowed to modify the parameter value. Editable
parameters cannot contain computed expressions. You can group parameters under a
common heading or section in the parameter editor with the Group column, and a
tooltip helps users of the component understand the function of the parameter.
Various parameter properties allow you to customize the components parameter
editor, such as using radio buttons for parameter selections, or displaying an image.
Figure 84. Parameters Tab in the Components Editor
If a parameter <n> defines the width of a signal, the signal width must follow the
format: <n-1>:0.
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Example 84 shows the component hardware Tcl code related to the entries for the
Parameters tab in Figure 84. In this example, the first add_parameter command
includes commonly-specified properties. The set_parameter_property command
specifies each property individually. The Tooltip column on the Parameters tab maps
to the DESCRIPTION property, and there is an additional unused UNITS property created
in the code. The HDL_PARAMETER property specifies that the value of the parameter is
specified in the HDL instance wrapper when creating instances of the component.
The Group column in the Parameters tab maps to the display items section with the
add_display_item commands.
Example 84. Hardware Tcl Commands Created from the Parameters Tab in the Component Editor
#
# parameters
#
add_parameter AXI_ID_W INTEGER 4 "Width of ID fields"
set_parameter_property AXI_ID_W DEFAULT_VALUE 4
set_parameter_property AXI_ID_W DISPLAY_NAME AXI_ID_W
set_parameter_property AXI_ID_W TYPE INTEGER
set_parameter_property AXI_ID_W UNITS None
set_parameter_property AXI_ID_W DESCRIPTION "Width of ID fields"
set_parameter_property AXI_ID_W HDL_PARAMETER true
add_parameter AXI_ADDRESS_W INTEGER 12
set_parameter_property AXI_ADDRESS_W DEFAULT_VALUE 12
add_parameter AXI_DATA_W INTEGER 32
...
#
# display items
#
add_display_item "AXI Port Widths" AXI_ID_W PARAMETER ""
If an AXI slave's ID bit width is smaller than the formula, the AXI slave response
might not reach AXI masters. The formula of an AXI slave ID bit width is calculated as
follows:
maximum_master_id_width_in_the_interconnect +
log2(number_of_masters_in_the_same_interconnect)
For example, if an AXI slave connects to three AXI masters and the maximum AXI
master ID length of the three masters is 5 bits, then the AXI slave ID is 7 bits, then:
5 bits + 2 bits (log2(3 masters)) = 7
f For more information about _hw.tcl syntax and advanced features that you can add to
a component definition, refer to the Component Interface Tcl Reference chapter in
volume 1 of the Quartus II Handbook.
817
The ALLOWED_RANGES property is a list of valid ranges, where each range is a single
value, or a range of values defined by a start and end value. Table 82 shows
examples of the ALLOWED_RANGES property. For a parameter editor GUI example of the
LLOWED_RANGES property, refer to Parameter Editor Illustrating Parameter
Declarations on page 819. Refer to the Declaring Parameters in hw.tcl, including
Allowed Ranges and a Derived Parameter on page 819 for an hw.tcl code example
that uses the ALLOWED_RANGES property.
Table 82. ALLOWED_RANGES Property
ALLOWED_RANGES
Meaning
{a b c}
a or b or c
{1 2 4 8 16}
1, 2, 4, 8, or 16
{1:3}
1 through 3, inclusive
{1 2 3 7:10}
1, 2, 3, or 7 through 10 inclusive
Types of Parameters
Qsys uses the following parameter types: user parameters, system information
parameters, and derived parameters.
User Parameters
User parameters are parameters that users of a component can control, and appear in
the parameter editor for instances of the component. User parameters map directly to
parameters in the component HDL, such as AXI_DATA_W in Example 85 on page 819,
or control commands in an elaboration callback, such as ENABLE_STREAM_OUTPUT, also
in Example 85.
You then set the name of the clock interface as the SYSTEM_INFO argument:
set_parameter_property <param> SYSTEM_INFO_ARG <clkname>
Derived Parameters
Derived parameter values are calculated from other parameters during the
Elaboration phase, and are specified in the hw.tcl file with the DERIVED property. For
example, you can derive a clock period parameter from a data rate parameter.
Derived parameters are sometimes used to perform operations that are difficult to
perform in HDL, such as using logarithmic functions to determine the number of
address bits that a component requires.
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Altera Corporation
818
819
In the parameter editor, the AXI_NUMBYTES parameter value is not editable, because its
value is based on another parameter value.
Example 85. Declaring Parameters in hw.tcl, including Allowed Ranges and a Derived Parameter
add_parameter
set_parameter_property
set_parameter_property
set_parameter_property
set_parameter_property
set_parameter_property
set_parameter_property
AXI_ADDRESS_W
AXI_ADDRESS_W
AXI_ADDRESS_W
AXI_ADDRESS_W
AXI_ADDRESS_W
AXI_ADDRESS_W
AXI_ADDRESS_W
add_parameter
set_parameter_property
set_parameter_property
set_parameter_property
set_parameter_property
set_parameter_property
set_parameter_property
AXI_DATA_W
AXI_DATA_W
AXI_DATA_W
AXI_DATA_W
AXI_DATA_W
AXI_DATA_W
AXI_DATA_W
add_parameter
set_parameter_property
set_parameter_property
set_parameter_property
set_parameter_property
set_parameter_property
set_parameter_property
AXI_NUMBYTES
AXI_NUMBYTES
AXI_NUMBYTES
AXI_NUMBYTES
AXI_NUMBYTES
AXI_NUMBYTES
AXI_NUMBYTES
add_parameter
set_parameter_property
Source Port"
set_parameter_property
source (default), or hide
set_parameter_property
...
INTEGER
DISPLAY_NAME
DESCRIPTION
UNITS
ALLOWED_RANGES
HDL_PARAMETER
GROUP
INTEGER
DISPLAY_NAME
DESCRIPTION
UNITS
ALLOWED_RANGES
HDL_PARAMETER
GROUP
INTEGER
DERIVED
DISPLAY_NAME
DESCRIPTION
UNITS
HDL_PARAMETER
GROUP
12
"AXI Slave Address Width"
"Address width.
bits
4:16
true
"AXI Port Widths"
32
"Data Width"
"Width of data buses."
bits
{8 16 32 64 128 256 512 1024}
true
"AXI Port Widths"
4
true
"Data Width in bytes; Data Width/8"
"Number of bytes in one word"
bytes
true
"AXI Port Widths"
ENABLE_STREAM_OUTPUT BOOLEAN
true
ENABLE_STREAM_OUTPUT DISPLAY_NAME "Include Avalon Streaming
ENABLE_STREAM_OUTPUT DESCRIPTION
the interface"
ENABLE_STREAM_OUTPUT GROUP
f For more information about _hw.tcl syntax and advanced features that you can add to
a component definition, refer to the Component Interface Tcl Reference chapter in
volume 1 of the Quartus II Handbook.
Figure 85 shows how the parameter editor GUI generated from Example 85.
Figure 85. Parameter Editor Illustrating Parameter Declarations
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820
For more information about _hw.tcl syntax and advanced features that you can add to
a component definition, refer to the Component Interface Tcl Reference chapter in
volume 1 of the Quartus II Handbook.
821
The Interface column allows you assign a signal to an interface. Each signal must
belong to an interface and be assigned a legal signal type for that interface. To create a
new interface of a specific type, select new <interface type> from the list; this new
interface then become available in the list for subsequent signal assignments. You can
highlight all of the signals in an interface and then select an Interface from the list to
apply the Interface name to each signal in the interface.
You edit the interface name on the Interface tab; you cannot edit the interface name
on the Signals tab.
Figure 86 shows the altera_axi_slave selection available for the axs_awaddr signal.
Figure 86. Signals Tab in the Components Editor
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Altera Corporation
822
Example 87 shows the component hardware Tcl code related to the entries for the
Signals tab in Figure 86.
Example 87. Hardware Tcl Commands Created from the Signals Tab
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
add_interface_port
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
altera_axi_slave
f For more information about _hw.tcl syntax and advanced features that you can add to
a component definition, refer to the Component Interface Tcl Reference chapter in
volume 1 of the Quartus II Handbook.
823
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Altera Corporation
824
Example 88 shows the component hardware Tcl code related to the entries for the
Interfaces tab in Figure 87. In this example, each interface is created with the
add_interface command. You specify the properties of each interface with the
set_interface_property command. The interface's signals are specified with the
add_interface_port command.
Example 88. Hardware Tcl Commands Created from the Signals and Interfaces Tabs
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
add_interface_port reset reset_n reset_n Input 1
#
# connection point streaming
#
add_interface streaming avalon_streaming start
set_interface_property streaming associatedClock clock
set_interface_property streaming associatedReset reset
set_interface_property streaming dataBitsPerSymbol 8
set_interface_property streaming errorDescriptor ""
set_interface_property streaming firstSymbolInHighOrderBits true
set_interface_property streaming maxChannel 0
set_interface_property streaming readyLatency 0
set_interface_property streaming ENABLED true
add_interface_port streaming aso_data data Output 8
add_interface_port streaming aso_valid valid Output 1
add_interface_port streaming aso_ready ready Input 1
#
# connection point slave
#
add_interface slave axi end
set_interface_property slave
set_interface_property slave
set_interface_property slave
set_interface_property slave
set_interface_property slave
set_interface_property slave
set_interface_property slave
associatedClock clock
associatedReset reset
readAcceptanceCapability 1
writeAcceptanceCapability 1
combinedAcceptanceCapability 1
readDataReorderingDepth 1
ENABLED true
825
readIssuingCapability
readAcceptanceCapability
writeIssuingCapability
writeAcceptanceCapability
combinedIssuingCapability
combinedAcceptanceCapability
readDataReorderingDepth
f For more information about _hw.tcl syntax and advanced features that you can add to
a component definition, refer to the Component Interface Tcl Reference chapter in
volume 1 of the Quartus II Handbook.
May 2013
Altera Corporation
826
f For more information about _hw.tcl syntax and advanced features that you can add to
a component definition, refer to the Component Interface Tcl Reference chapter in
volume 1 of the Quartus II Handbook.
elaborate
proc elaborate {} {
#Optionally disable the Avalon- ST data output
if { [ get_parameter_value ENABLE_STREAM_OUTPUT ] == "false" } {
set_port_property aso_data
termination true
set_port_property aso_valid
termination true
set_port_property aso_ready
termination true
set_port_property aso_ready
termination_value 0
}
# Calculate the Data Bus Width in bytes
set bytewidth_var [ expr [ get_parameter_value AXI_DATA_W] /8 ]
set_parameter_value AXI_NUMBYTES $bytewidth_var
}
f For more information about _hw.tcl syntax and advanced features that you can add to
a component definition, refer to the Component Interface Tcl Reference chapter in
volume 1 of the Quartus II Handbook.
827
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Altera Corporation
828
f For more information about _hw.tcl syntax and advanced features that you can add to
a component definition, refer to the Component Interface Tcl Reference chapter in
volume 1 of the Quartus II Handbook.
829
Static commandsIn the main static part of the _hw.tcl file, you can use
composition commands such as add_instance,
set_instance_parameter_value, and add_connection to create and
parameterize subcomponent instances.
A composition callback replaces the validation and elaboration phases. HDL for the
subsystem is generated by generating all of the subcomponents and the top-level that
combines them.
To connect instances of your component, you must define the component's interfaces.
Unlike an HDL-based component, a composed component does not directly specify
the signals that are exported. Instead, interfaces of submodules are chosen as the
external interface, and each internal interface's ports are connected through the
exported interface.
Exporting an interface means that you are making the interface visible from the
outside of your component, instead of connecting it internally. You can set the
EXPORT_OF property of the externally visible interface from the main program or the
composition callback, to indicate that it is an exported view of the submodule's
interface.
Exporting an interface is different than defining an interface. An exported interface is
an exact copy of the subcomponents interface, and you are not allowed to change
properties on the exported interface. For example, if the internal interface is a 32-bit or
64-bit master without bursting, then the exported interface is the same. An interface
on a subcomponent cannot be exported and also connected within the subsystem.
When you create an exported interface, the properties of the exported interface are
copied from the subcomponents interface without modification. Ports are copied
from the subcomponents interface with only one modification; the names of the
exported ports on the composed component are chosen to ensure that they are
unique.
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Altera Corporation
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Figure 88 shows a block diagram for the composed component in Example 812.
Figure 88. Top-Level of a Composed Component
my_component
reset
clk
altera
reset
bridge
altera
clock
bridge
slave
my_regs_microcore
my_phy_microcore
pins
Example 812 provides an example of a composed _hw.tcl file that instantiates two
subcomponents. It connects the components, and also connects the clocks and resets.
Note that clock and reset bridge components are required to allow both
subcomponents to see common clock and reset inputs.
Example 812. Composed _hw.tcl File with Two Subcomponents
package require -exact qsys 13.0
set_module_property name my_component
add_instance clk altera_clock_bridge
add_instance phy my_phy_microcore
add_interface clk clock end
add_instance reset altera_reset_bridge
set_interface_property clk EXPORT_OF clk.in_clk
add_instance regs my_regs_microcore
set_instance_property_value reset synchronous_edges deassert
add_interface reset reset end
set_interface_property reset EXPORT_OF reset.in_reset
add_interface pins conduit end
set_interface_property pins EXPORT_OF phy.pins
add_interface slave avalon slave
set_interface_property slave EXPORT_OF regs.slave
add_connection clk.out_clk reset.clk
add_connection clk.out_clk phy.clk
add_connection reset.out_reset phy.clk_reset
add_connection
add_connection
add_connection
add_connection
clk.out_clk regs.clk
reset.out_reset regs.reset
phy.output regs.input
regs.output phy.input
831
f For more information about _hw.tcl syntax and advanced features that you can add to
a component definition, refer to the Component Interface Tcl Reference chapter in
volume 1 of the Quartus II Handbook.
Static commandsIn the main static part of the _hw.tcl file, you can use instance
commands such as add_hdl_instance and set_instance_parameter_value to
create and parameterize subcomponent instances.
Design Guidelines
When instantiating multiple nested components, you must create a unique variation
name for each component with the add_hdl_instance command. Prefixing a variation
name with the parent component name can prevent conflicts in a system. The
variation name can be the same across multiple parent components if the generated
parameterization of the nested component is exactly the same.
1
If you do not adhere to the above naming variation guidelines, Qsys validation-time
errors occur, which are often difficult to debug.
A component is either generated or static. Generated components change their
generation output (RTL) based on their parameterization. Static components always
generate the same output, regardless of their parameterization.
If a component is generated, then any component that might instantiate it with
multiple parameter sets must also be considered generated, since its RTL, changes
with its parameterization. This case has an effect that propagates up to the top level of
a design.
Furthermore, components that instantiate static components must have only static
children. Additionally, any design file that is static between all parameterizations of a
component can only instantiate other static design files. Like the generated rule
above, this propagates down the hierarchy.
In order to promote standard and predictable results when generating both generated
and static components, Altera recommends the following best-practices:
May 2013
Altera Corporation
832
Different file names with the same entity names, results in same entity conflicts at
compilation-time.
Different contents with the same file name, results in overwriting other instances
of the component, and results in either compile-time conflicts or unexpected
behavior.
Generated components that generate files not based on the output name and that
have different content, results in either compile-time conflicts, or unexpected
behavior.
Version
May 2013
13.0.0
November 2012
12.1.0
June 2012
12.0.0
November 2011
11.1.0
May 2011
11.0.0
December 2010
10.1.0
Changes
Added the demo_axi_memory example with screen shots and example _hw.tcl code.
Template update.
Added many interface templates for Nios custom instructions and Avalon-TC interfaces.
Initial release.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
9. Qsys Interconnect
May 2013
QII51021-13.0.0
QII51021-13.0.0
Memory-Mapped Interfaces
This section describes the implementation and structure of the Qsys interconnect for
memory-mapped interfaces. Content pertains to both Avalon and AXI memorymapped interfaces, unless noted otherwise.
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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92
Any number of components with master and slave interfaces. The master-to-slave
relationship can be one-to-one, one-to-many, many-to-one, or many-to-many.
Components with different interface properties and signals. Qsys adapts the
component interfaces so that interfaces with the following differences can be
connected:
Avalon and AXI interfaces that use active-high and active-low signalling
AXI signals are active high, except for the reset signal.
93
Figure 91 illustrates the Qsys interconnect for an Avalon-MM system with multiple
masters.
Figure 91. Qsys interconnectExample System
PCB
Instruction
M
Master
Network
Interface
S
Control
Qsys Design
in Altera FPGA
Processor
DMA Controller
Data
M
Master
Network
Interface
Interconnect
Read
M
Write
M
Master
Network
Interface
Master
Network
Interface
Response Switch
(Avalon-ST)
Command Switch
(Avalon-ST)
Slave
Network
Interface
Slave
Network
Interface
Slave
Network
Interface
Slave
Network
Interface
Data
Memory
DDR3
Controller
Tri-State
Controller
Tri-State
Conduit
TCM
TCM
TCS
TCS
Instruction
Memory
Tri-State Conduit
Pin Sharer & Bridge
DDR3 Chip
Ethernet
MAC/PHY
Chip
Flash
Memory
Chip
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94
Table 91 describes the fields of the Qsys packet that encapsulate the memorymapped master commands and memory-mapped slave responses.
Table 91. Qsys Packet Format (Part 1 of 2)
Field
Address
Description
Specifies the byte address for the lowest byte in the current cycle. There are no restrictions
on address alignment.
Encodes the run-time size of the transaction.
Size
Address Sideband
In conjunction with address, this field describes the segment of the payload that contains
valid data for a beat within the packet.
Carries address sideband signals. The interconnect passes this field from master to slave.
This field is valid for each beat in a packet, even though it is only produced and consumed
by an address cycle.
Up to 8-bit sideband signals are supported for both read and write address channels.
Cache
Transaction (Exclusive)
Transaction (Posted)
Data
For command packets, carries the data to be written. For read response packets, carries the
data that has been read.
Specifies which symbols are valid. AXI can issue or accept any byteenable pattern. For
compatibility with Avalon, Altera recommends that you use the following legal values for 32bit data transactions between Avalon masters and slaves:
Byteenable
Source_ID
Destination_ID
Response
Thread ID
Byte count
The number of bytes remaining in the transaction, including this beat. Number of bytes
requested by the packet.
95
Description
The burstwrap value specifies the wrapping behavior of the current burst. The burstwrap
value is of the form 2<n>-1. The following types are defined:
Variable wrapVariable wrap bursts can wrap at any integer power of 2 value. When the
burst reaches the wrap boundary, it wraps back to the previous burst boundary so that
only the low order bits are used for addressing. For example, a burst starting at address
0x1C, with a burst wrap boundary of 32 bytes and a burst size of 20 bytes, would write to
addresses 0x1C, 0x0, 0x4, 0x8, and 0xC.
For a burst wrap boundary of size <m>, Burstwrap = <m> - 1, or for this case
Burstwrap = (32 - 1) = 31 which is 25 -1.
For AXI masters, the burstwrap boundary value (m) based on the different AXBURST:
Burstwrap
SequentialSequential bursts increment the address for each transfer in the burst. For
sequential bursts, the Burstwrap field is set to all 1s. For example, with a 6-bit
Burstwrap field, the value for a sequential burst is 6'b111111 or 63, which is 26 - 1.
For Avalon masters, Qsys adaptation logic sets a hardwired value for the burstwrap field,
according the declared master burst properties. For example, for a master that declares
sequential bursting, the burstwrap field is set to ones. Similarly, masters that declare burst
have their burstwrap field set to the appropriate constant value.
AXI masters choose their burst type at run-time, depending on the value of the AW or
ARBURST signal. The interconnect calculates the burstwrap value at run-time for AXI
masters.
Access level protection. When the lowest bit is 0, the packet has normal access. When the
lowest bit is 1, the packet has privileged access. For Avalon-MM interfaces, this field maps
directly to the privileged access signal, which allows an memory-mapped master to write to
an on-chip memory ROM instance. The other bits in this field support AXI secure accesses.
Protection
QoS (Quality of Service Signaling) is a 4-bit field that is part of the AXI4 interface that carries
QoS information for the packet from the AXI master to the AXI slave.
QoS
Transactions from AXI3 and Avalon masters have the default value 4'b0000, that indicates
that they are not participating in the QoS scheme. QoS values are dropped for slaves that do
not support QoS.
Carries data sideband signals for the packet. On a write command, the data sideband
directly maps to WUSER. On a read response, the data sideband directly maps to RUSER. On a
write response, the data sideband directly maps to BUSER.
Data sideband
Name
Definition
PKT_TRANS_READ
PKT_TRANS_COMPRESSED_READ
PKT_TRANS_WRITE
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Name
Definition
PKT_TRANS_POSTED
PKT_TRANS_LOCK
The fields of the Qsys packet format are variable length to minimize the resources
used. However, if the majority of components in a design have a single data width, for
example 32 bits, and a single component has a data width of 64 bits, Qsys inserts a
width adapter to accommodate 64-bit transfers.
Interconnect Domains
A group of connected memory-mapped masters and slaves is called an interconnect
domain. The components in a single interconnect domain share the same packet
format. The following two examples illustrate this point.
Component 1
64-bit
Avalon-MM
Master
64-bit
Avalon-MM
Master
16-bit
Avalon-MM
Master
Domain 1
Domain 2
64-bit
Avalon-MM
Slave
64-bit
Avalon-MM
Slave
16-bit
Avalon-MM
Slave
16-bit
Avalon-MM
Slave
Command Network
Response Network
97
When there are AXI interfaces in the domain, width adapters are automatically placed
on the network boundaries, for example, they are treated as part of the network
interface modules. As a result, the switches for a particular AXI domain have a
common data width.
In Figure 93, the 16-bit Avalon master connects through a 1:4 adapter, then a 4:1
adapter to reach its 16-bit slaves.
Figure 93. One Domain with 1:4 and 4:1 Width Adapters
Single Domain with 1:4 & 4:1 Width Adapters
64-Bit
Avalon-MM
Master
M
1:4
S
64-Bit
Avalon-MM
Slave
64-Bit
Avalon-MM
Master
M
4:1
16-Bit
Avalon-MM
Master
M
16-Bit
Avalon-MM
Slave
16-Bit
Avalon-MM
Slave
S
64-Bit
Avalon-MM
Slave
Qsys Transformations
Figure 94 provides a detailed view of the transformation that occurs when you
generate a Qsys system with memory-mapped master and slave components. The
memory-mapped master and slave components connect to network interface modules
that encapsulate the transaction in Avalon-ST packets. The memory-mapped
interfaces have no information about the encapsulation or the function of the layer
transporting the packets and simply operate in accordance with memory-mapped
protocol, using the read and write signals and transfers as defined in the Avalon or
AXI interface specification.
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98
Avalon-ST
Master
Interface
Master
Network
Interface
Master
Interface
Master
Network
Interface
Avalon-ST
Network
(Command)
Avalon-ST
Network
(Response)
Avalon-MM or AXI
Slave
Network
Interface
Slave
Interface
Slave
Network
Interface
Slave
Interface
The Qsys components that implement the blocks shaded grey in Figure 94 are
described in Master Network Interfaces on page 98 and Slave Network
Interfaces on page 911.
99
Avalon network interfaces drive default values for the QoS and BUSER, WUSER, and
RUSER packet fields in the master agent, and drop the packet fields in the slave agent.
Figure 95 shows the Avalon-MM Master network interface.
Figure 95. Avalon-MM Master Network Interface
Router
Master
Interface
Translator
Agent
Limiter
Avalon-ST
Network
(Response)
An AXI4 master supports INCR bursts up to 256 beats, QoS signals, and Data Sideband
signals. Figure 96 shows the AXI Master Network Interface.
Figure 96. AXI Master Network Interface
Master
Interface
AXI
Translator
AXI
Master
Agent
Write Command
Router
Router
Limiter
Avalon-ST
Network
(Command)
Write Response
Read Response
Limiter
Avalon-ST
Network
(Response)
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Inserts wait states to prevent an Avalon-MM master from reading invalid data
Altera Corporation
910
AXI Translator
AXI4 allows some signals to be omitted from interfaces. The translator bridges
between these incomplete AXI4 interfaces and the complete AXI4 interface on the
network interfaces. The AXI translator is inserted for both AXI4 master and slave, and
performs the following functions:
Drives default values as defined in the AMBA Protocol Specifications for missing
signals.
APB Translator
An APB peripheral does not require pslverr signals to support additional signals for
the APB debug interface. The APB translator is inserted for both the master and slave
and performs the following functions:
Sets the response value default to OKAY if the APB slave does not have a pslverr
signal.
Turns on or off additional signals between the APB debug interface, which is used
with HPS (Altera SoCs Hard Processor System).
911
Memory-Mapped Router
The Memory-Mapped Router routes command packets from the master to the slave,
and response packets from the slave to the master. For master command packets, the
router uses the address to set the Destination_ID and Avalon-ST channel. For the
slave response packet, the router uses the Destination_ID to set the Avalon-ST
channel. The demultiplexers use the Avalon-ST channel to route the packet to the
correct destination.
An AXI4 slave supports up to 256 beat INCR bursts, QoS signals, and data sideband
signals. Figure 97 shows an Avalon slave network interface.
Figure 97. Avalon-MM Slave Network Interface
Slave Network Interface
Avalon-ST
Network
(Command)
Overflow Error
Command
Waitrequest
Agent
Avalon-ST
Network
(Response)
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Altera Corporation
Translator
Slave
Interface
Response
912
Network Interface
Avalon-ST
Network
(Command)
Write Command
Read Command
AXI
Agent
Avalon-ST
Network
(Response)
AXI
Translator
Slave
Interface
Write Response
Read Response
Supports Avalon-MM slaves that operate using fixed timing and or slaves that use
the readdatavalid signal to identify valid data.
Translates the read, write, and chipselect signals into the representation that the
Avalon-ST slave response network uses.
AXI Translator
AXI4 allows some signals to be omitted from interfaces. The translator bridges
between these incomplete AXI4 interfaces and the complete AXI4 interface on the
network interfaces. The AXI translator is inserted for both AXI4 master and slave, and
performs the following functions:
Drives default values as defined in the AMBA Protocol Specifications for missing
signals.
913
Arbitration
When multiple masters contend for access to a slave, Qsys automatically inserts
arbitration logic which grants access in fairness-based, round-robin order.
In a fairness-based arbitration scheme, each master has an integer value of transfer
shares with respect to a slave. One share represents permission to perform one
transfer. The default arbitration scheme is equal share round-robin that grants equal,
sequential access to all requesting masters. You can change the arbitration scheme to
weighted round-robin by specifying a relative number of arbitration shares to the
masters that access a particular slave. AXI slaves have separate arbitration for their
independent read and write channels, and the Arbitration Shares setting affects both
the read and write arbitration. To display arbitration settings, right-click an instance
on the System Contents tab, and then click Show Arbitration Shares.
Figure 99 illustrates arbitration shares indicated in the Connections column.
Figure 99. Arbitration Settings on the System Contents Tab
Arbitration Timing
Figure 910 illustrates the arbitration timing. As this figure illustrates, a device can
drive valid data in the granted cycle. Figure 910 shows the following sequence of
events:
1. In cycle one, the arbiter grants a request. The granted device drives valid data in
cycles one and two.
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Altera Corporation
914
2. In cycle 4, the arbiter grants a request. The granted device drives valid data in
cycles 4 and 5.
3. In cycle 6, the arbiter grants a request. The granted device drives valid data in
cycles 6and 7.
4. At the positive edge of cycle 3, a grant signal is not present, although there is a
request signal asserted. Therefore, cycle3 does not contain valid data.
Figure 910. Arbitration Timing
1
clock
request
grant
data[31:0]
Arbitration Rules
This section describes the rules by which the arbiter grants access to masters.
Fairness-Based Shares
In a fairness-based arbitration scheme, each master-to-slave connection provides a
transfer share count. This count is a request for the arbiter to grant a specific number
of transfers to this master before giving control to a different master. One share
represents permission to perform one transfer.
For example, for two masters that continuously attempt to perform back-to-back
transfers to a slave, the arbiter grants Master 1 access for three transfers, and Master 2
for four transfers. This cycle repeats indefinitely. Figure 911 shows each masters
transfer request output, wait request input (which is driven by the arbiter logic), and
the current master with control of the slave.
Figure 911. Arbitration of Continuous Transfer Requests from Two Masters
clk
M1_transfer_request
M1_waitrequest
M2_transfer_request
M2_waitrequest
Current_Master
Master 1
Master 2
Master 1
Master 2
Master 1
915
If a master stops requesting transfers before it exhausts its shares, it forfeits all of its
remaining shares, and the arbiter grants access to another requesting master, as
shown in Figure 914. After completing one transfer, Master 2 stops requesting for
one clock cycle. As a result, the arbiter grants access back to Master 1, which gets a
replenished supply of shares.
Figure 912. Arbitration of Two Masters with a Gap in Transfer Requests
clk
M1_transfer_request
M1_waitrequest
M2_transfer_request
M2_waitrequest
Current_Master
Master 1
Master 2
Master 1
Master 2
Master 1
Master 2
Round-Robin Scheduling
When multiple masters contend for access to a slave, the arbiter grants shares in
round-robin order. Round-robin scheduling drives a request interface according to
space available and data available credit interfaces. At every slave transfer, only
requesting masters are included in the arbitration.
Burst Transfers
For burst transfer arbitration, there is a one-to-one relationship between a single share
and a transaction, so that arbitration shares are respected during burst transactions.
For example, for an arbitration share of 3, a master is granted 3 burst transactions.
Once a burst begins between a master-slave pair, arbiter logic does not allow any
other master to access the slave until the burst completes.
Arbitration Examples
Figure 913 illustrates the timing for two Avalon-MM masters continuously accessing
a single Avalon-MM slave to perform back-to-back transfers. Master 1 has three
shares and Master 2 has four shares. The arbiter grants Master 1 access for three
transfers, then Master 2 for four transfers. This cycle repeats indefinitely.
Figure 913. Arbitration of Continuous Transfer Requests from Two Masters
clk
M1_transfer_request
M1_waitrequest
M2_transfer_request
M2_waitrequest
Current_Master
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Altera Corporation
Master 1
Master 2
Master 1
Master 2
Master 1
916
If a master stops requesting transfers before it exhausts its shares, it forfeits all of its
remaining shares, and the arbiter grants access to another requesting master as
Figure 914 illustrates. After completing one transfer, Master 2 stops requesting for
one clock cycle. As a result, the arbiter grants access back to Master 1, which gets three
shares.
Figure 914. Arbitration of Two Masters with a Gap in Transfer Requests
clk
M1_transfer_request
M1_waitrequest
M2_transfer_request
M2_waitrequest
Current_Master
Master 1
Master 2
Master 1
Master 2
Master 1
Master 2
Memory-Mapped Arbiter
The input to the Memory-Mapped Arbiter is the command packet for all masters
requesting access to a particular slave. The arbiter outputs the channel number for the
selected master. This channel number controls the output of a multiplexer that selects
the slave device. Figure 915 illustrates this logic.
917
In Figure 915, four Avalon-MM masters connect to four Avalon-MM slaves. In each
cycle, an arbiter positioned in front of each Avalon-MM slave selects among the
requesting Avalon-MM masters.
Figure 915. Arbitration Logic
Logic included in the Avalon-ST Command Network
Command
packet for
master 0
Master 0
Arbiter
for
slave 0
Master 1
Command
packet for
master 1
Selected request
Arbiter
Arbiter
for
for
slave
slave 1
1
Selected request
Master 2
Arbiter
for
slave 2
Command
packet for
master 2
Master 3
Command
packet for
master 3
Selected request
Arbiter
for
slave 3
Selected request
= Pipeline stage, masters 0-3
If you specified a Limit interconnect pipeline stages to parameter greater than zero
on the Qsys Project Settings tab, the output of the Arbiter is registered. Registering
this output reduces the amount of combinational logic between the master and
interconnect, increasing the fMAX of the system.
Width Adaptation
Qsys width adaptation converts between Avalon memory-mapped master and slaves
with different data and byte enable widths, and manages the run-time size
requirements of AXI. Width adaptation for AXI to Avalon interfaces is also supported.
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Altera Corporation
918
byteenable_in[3:0]
wide_data[31:0]
Adapter
Output
08
C
AABBCCDD
addr_out[7:0]
08
09
0A
0B
byteenable_out[3:0]
DD
CC
BB
AA
narrow_data[7:0]
write
919
Behavior
If the transaction size is less than or equal to the output width, the burst is unmodified.
Otherwise, it is converted to an incrementing burst with a larger length and size equal to the
output width.
If the resulting burst is unsuitable for the slave, the burst is converted to multiple sequential
bursts of the largest allowable lengths. For example, for a 2:1 downsizing ratio, an INCR9
burst is converted into INCR16 + INCR2 bursts. This is true if the maximum burstcount a
slave can accept is 16, which is the case for AXI3 slaves. Avalon slaves have a maximum
burstcount of 64.
Incrementing
If the transaction size is less than or equal to the output width, the burst is unmodified.
Otherwise, it is converted to a wrapping burst with a larger length, with a size equal to the
output width.
Wrapping
If the resulting burst is unsuitable for the slave, the burst is converted to multiple sequential
bursts of the largest allowable lengths; respecting wrap boundaries. For example, for a 2:1
downsizing ratio, a WRAP16 burst is converted into two or three INCR bursts, depending on
the address.
If the transaction size is less than or equal to the output width, the burst is unmodified.
Otherwise, it is converted into repeated sequential bursts over the same addresses. For
example, for a 2:1 downsizing ratio, a FIXED single burst is converted into an INCR2 burst.
Fixed
Behavior
Incrementing
The burst (and its response) passes through unmodified. Data and write strobes are placed
in the correct output segment.
Wrapping
Fixed
Burst Transfers
Avalon-MM and AXI burst transactions grant a master uninterrupted access to a slave
for a specified number of transfers. The master specifies the number of transfers when
it initiates the burst. Once a burst begins between a master and slave pair, arbiter logic
is locked until the burst completes. For burst masters, the length of the burst is the
number of cycles that the master has access to the slave, and the selected arbitration
shares have no effect.
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920
AXI masters can issue burst types that Avalon cannot accept, for example, fixed
bursts. In this case, the burst adapter converts the fixed burst into a sequence of
transactions to the same address.
For AXI4 slaves, Qsys allows 256-beat INCR bursts, though you must ensure that
256-beat narrow-sized INCR bursts are shortened to 16-beat narrow-sized INCR bursts
for AXI3 slaves.
Avalon-MM masters always issue addresses that are aligned to the size of the transfer.
However, in some cases, when a narrow-to-wide width adaptation is used, the
resulting address may be unaligned. In the case of unaligned addresses, the burst
adapter issues the maximum possible sized bursts, with appropriate byte enables, to
bring the burst-in-progress up to an aligned slave address. Then, it completes the
burst on aligned addresses.
The burst adapter supports variable wrap or sequential burst types to accommodate
the different properties of memory-mapped masters. Some bursting masters can issue
more than one burst type.
Burst adaptation is available for Avalon to Avalon, Avalon to AXI, and AXI to Avalon
connections, and AXI to AXI connections
For AXI4 to AXI3 connections, Qsys follows an AXI4 256 burst length to AXI3 16 burst
length.
Table 95 and Table 96 specify the behavior when converting between AXI and
Avalon burst types.
921
Table 95 describes behavior when converting from AXI and Avalon burst types.
Table 95. Burst Adaptation: AXI to Avalon
Burst Type
Behavior
Sequential Slave
Bursts that exceed slave_max_burst_length are converted to multiple sequential bursts
of a length less than or equal to the slave_max_burst_length. Otherwise, the burst is
unconverted. For example, for an Avalon slave with a maximum burst length of 4, an INCR7
burst is converted to INCR4 + INCR3.
Incrementing
Wrapping Slave
Bursts that exceed the slave_max_burst_length are converted to multiple sequential
bursts of length less than or equal to the slave_max_burst_length. Bursts that exceed
the wrapping boundary are converted to multiple sequential bursts that respect the slave's
wrapping boundary.
Sequential Slave
A WRAP burst is converted to multiple sequential bursts. The sequential bursts are less than
or equal to the max_burst_length and respect the transaction's wrapping boundary
Wrapping
Wrapping Slave
If the WRAP transaction's boundary matches the slave's boundary, then the burst passes
through. Otherwise, the burst is converted to sequential bursts that respect both the
transaction and slave wrap boundaries.
Fixed
Fixed bursts are converted to sequential bursts of length 1 that repeatedly access the same
address. Refer to Table 93 on page 919 for the downsizing behavior for fixed bursts.
Narrow
Table 96 describes behavior when converting from Avalon to AXI burst types.
Table 96. Burst Adaptation: Avalon to AXI
Burst Type
Definition
Sequential
Bursts of length greater than16 are converted to multiple INCR bursts of a length less than
or equal to16. Bursts of length less than or equal to16 are not converted.
Wrapping
Only Avalon masters with alwaysBurstMaxBurst = true are supported. The WRAP burst
is passed through if the length is less than or equal to16. Otherwise, it is converted to two or
more INCR bursts that respect the transaction's wrap boundary.
Streaming Interfaces
High bandwidth components with streaming data typically use Avalon-ST interfaces
for the high throughput datapath. These components can also use memory-mapped
connection interfaces to provide an access point for control. In contrast to the
memory-mapped interconnect, which you can use to create a wide variety of
topologies, the Avalon-ST interconnect always creates a point-to-point connection
between a single data source and data sink, as Figure 917 illustrates.
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Altera Corporation
922
The data source in the Rx Interface transfers data to the data sink in the FIFO.
The data source in the FIFO transfers data to the Tx Interface data sink.
In Figure 917, the memory-mapped interface allows a processor to access the data
source, FIFO, or data sink to provide system control.
Figure 917. Use of the Memory-Mapped and Avalon-ST Interfaces
Control Plane Memory Mapped Intefaces
RAM
Processor
Control
Slave
Timer
Control
Slave
Data Source
Control
Slave
Data Sink
FIFO
(Rx Interface )
Data
Data
Source
Source
UART
ready
valid
channel
data
Data
Sink
(Tx Interface )
Data
Source
ready
valid
channel
data
Data
Sink
If your source and sink interfaces have different formats, for example, a 32-bit source
and an 8-bit sink, Qsys automatically inserts the necessary adapters, which are then
visible in the System Contents tab. For more information, refer to Avalon-ST
Adapters on page 924.
Figure 918 illustrates the simplest system example with an Avalon-ST connection
between the source and sink. This source-sink pair includes only the data signal. The
sink must be able to receive data as soon as the source interface comes out of reset.
Figure 918. Interconnect for a Simple Avalon Streaming Source-Sink Pair
Data Source
data
Data Sink
923
Figure 919 illustrates a more extensive interface that includes signals indicating the
start and end of packets, channel numbers, error conditions, and back pressure.
Figure 919. Avalon Streaming Interface for Packet Data
Data Source
ready
valid
channel
startof packet
endofpacket
empty
error
data
Data Sink
All data transfers using Avalon-ST interconnect occur synchronously to the rising
edge of the associated clock interface. Throughput and frequency of a system depends
on the components and how they are connected.
f AXI streaming components are not available in Qsys, version 13.0. For details about
the Avalon-ST interface protocol, refer to the Avalon Interface Specification.
The Qsys Component Library includes a number of Avalon-ST components that you
can use to create datapaths, including datapaths whose input and output streams
have different properties. Generated systems that include memory-mapped master
and slave components may also use these Avalon-ST components because the
generation process creates an interconnect whose structure resembles a network
topology as Qsys Transformations on page 97 describes. The following sections
introduce the Avalon-ST components.
Avalon-ST Multiplexer
The Avalon-ST Multiplexer accepts data on its Avalon-ST sink interface and
multiplexes the data for transmission on its Avalon-ST source interface. You can
parameterize the multiplexer to append channel information on the source to indicate
which sink is driving the source data. The multiplexer includes internal arbitration
logic which selects between inputs using a round-robin arbitration algorithm.
Figure 920 illustrates the Avalon-ST multiplexer. Among the parameters that you can
specify are the option to use packet scheduling, which guarantees that the multiplexer
only changes inputs at the end of a packet.
Figure 920. Avalon-ST Multiplexer
Avalon-ST Source0
Avalon-ST Source1
Avalon-ST Source2
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Altera Corporation
Snk
Snk
Src
Avalon-ST Source
Snk
924
Avalon-ST Demultiplexer
The Avalon-ST Demultiplexer accepts channelized data on its sink interface, and
transmits the data on one of its source interfaces. The channel bits of the source stream
indicate which port the drives the output data. Figure 921 illustrates the Multiplexer.
Among the parameters that you can specify are the number of output ports and the
width of the channel signal.
Figure 921. Avalon-ST Demultiplexer
Src
Avalon-ST Source0
Src
Avalon-ST Source1
Src
Avalon-ST Source2
Avalon-ST Adapters
Qsys automatically adds Avalon-ST adapters between two components during
system generation when it detects mismatched interfaces. If you connect mismatched
Avalon-ST sources and sinks, for example, a 32-bit source and an 8-bit sink, Qsys
inserts the appropriate adapter type, as described below, to connect the mismatched
interfaces. After generation, you can view the inserted adapters with the Show
System With Qsys Fabric Components command on the System menu. Qsys reports
the mismatched interfaces and inserted adapter with informational messages.
You can turn off the auto-inserted adapters feature by adding the
qsys_enable_avalon_streaming_transform=off command to the quartus.ini file.
When you turn off the auto-inserted adapters feature, if mismatched interfaces are
detected during system generation, Qsys does not insert adapters and reports the
mismatched interface with an error message.
1
The auto-inserted adapters feature does not work for video IP core connections.
Qsys includes the following adapter types:
Timing Adapter
Channel Adapter
Error Adapter
925
If the adaptation is from a wider to a narrower interface, a beat of data at the input
corresponds to multiple beats of data at the output. If the input error signal is
asserted for a single beat, it is asserted on output for multiple beats.
If the adaptation is from a narrow to a wider interface, multiple input beats are
required to fill a single output beat, and the output error is the logical OR of the
input error signal.
Figure 922 shows a data format adapter that allows a connection between a 128-bit
input data stream and three 32-bit output data streams.
Figure 922. Avalon Streaming Interconnect with Data Format Adapter
128 Bits
128 Bits
128-Bit RX
Interface
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Altera Corporation
Data
Format
Adapter
32 Bits
32-Bit TX
Interface
32-Bit TX
Interface
128 Bits
Data
Format
Adapter
32 Bits
128 Bits
Data
Format
Adapter
32 Bits
32-Bit TX
Interface
926
Timing Adapter
The timing adapter allows you to connect component interfaces that require a
different number of cycles before driving or receiving data. This adapter inserts a
FIFO buffer between the source and sink to buffer data or pipeline stages to delay the
back pressure signals. You can also use the timing adapter to connect interfaces that
support the ready signal, and those that do not. The timing adapter treats all signals
other than the ready and valid signals as payload, and simply drives them from the
source to the sink. Table 98 outlines the adaptations that the timing adapter provides.
Table 98. Timing Adapter Adaptations
Condition
Adaptation
In this case, the source can respond to backpressure, but the sink never needs
to apply it. The ready input to the source interface is connected directly to
logical 1.
The sink may apply backpressure, but the source is unable to respond to it.
There is no logic that the adapter can insert that prevents data loss when the
source asserts valid but the sink is not ready. The adapter provides simulation
time error messages and an error indication if data is ever lost. The user is
presented with a warning, and the connection is allowed.
The source responds to ready assertion or deassertion faster than the sink
requires it. A number of pipeline stages equal to the difference in ready latency
are inserted in the ready path from the sink back to the source, causing the
source and the sink to see the same cycles as ready cycles.
Channel Adapter
The channel adapter provides adaptations between interfaces that have different
support for the channel signal, the maximum number of channels supported, or
channel-related parameters. The adaptations for the channel adapter are described in
Table 99.
Table 99. Channel Adapter
Condition
You are given a warning at generation time. The adapter provides a simulation error
and signals an error for data for any channel from the source other than 0.
You are given a warning, and the channel inputs to the sink are all tied to a logical 0.
927
Error Adapter
The error adapter ensures that per-bit-error information provided by the source
interface is correctly connected to the sink interfaces input error signal. Matching
error conditions processed by the source and sink are connected. If the source has an
error condition that is not supported by the sink, the signal is left unconnected; the
adapter provides a simulation error message and an error indication if this error is
ever asserted. If the sink has an error condition that is not supported by the source, the
sinks input is tied to zero.
Table 910 describes the available options for the error adapter on the Parameter
Settings page of the configuration wizard.
.
Description
Input Interface Parameters
Type the width of the error signal. Valid values are 031 bits. Type 0 if
the error signal is not used.
Type the description for each of the error bits. Separate the description
fields by commas. For a connection to be made, the description of the
error bits in the source and sink must match. Refer to Error Adapter on
page 927 for the adaptations that can be made when the bits do not
match.
Output Interface Parameters
Type the width of the error signal. Valid values are 031 bits. Type 0 if
you do not need to send error values.
Type the description for each of the error bits. Separate the description
fields by commas. For a connection to be made, the description of the
error bits in the source and sink must match. Refer to Error Adapter on
page 927 for the adaptations that can be made when the bits do not
match.
Common to Input and Output Interfaces
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Altera Corporation
928
Description
Ready Latency
When the ready signal is used, the value for ready_latency indicates
the number of cycles between when the ready signal is asserted and when
valid data is driven.
Turn this option on if the cycle that includes the endofpacket signal can
include empty symbols. This signal is not necessary if the number of
symbols per beat is 1.
Interrupt Interfaces
Using individual requests, the interrupt logic can process up to 32 IRQ inputs
connected to each interrupt receiver. With this logic, the interrupt sender connected to
interrupt receiver_0 is the highest priority with sequential receivers being
successively lower priority. You can redefine the priority of interrupt senders by
instantiating the IRQ mapper component. For more information refer to the IRQ
Mapper on page 931.
You can define the interrupt sender interface as asynchronous with no associated
clock or reset interfaces; the properties associatedClock and associatedReset can
thus be left undefined for Avalon masters and slaves. AXI masters and slaves are
required to specify associatedClock and associatedReset.
For clock crossing adaption on interrupts, Qsys inserts a synchronizer, which is
clocked with the interrupt end point interface clock when the corresponding starting
point interrupt interface has no clock or a different clock (than the end point). Qsys
inserts the adapter if there is any kind of mismatch between the start and end points.
929
Figure 923 shows an example of the interrupt controller mapping the IRQs on four
senders to irq[31:0] on a receiver.
Figure 923. IRQ Mapping Using Software Priority
Sender
1
irq
Interrupt
Controller
Sender
2
irq
Sender
3
irq
irq0
irq1
irq2
irq3
irq4
irq5
irq6
Receiver
irq31
Sender
4
irq
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Altera Corporation
930
Figure 924 shows an example of IRQ mapping using the encoded interrupt scheme.
Figure 924. IRQ Mapping Using Hardware Priority
Interrupt Handling Logic
Sender
1
irq
Sender
2
irq
Sender
3
irq
irq
Receiver
Sender
4
irq
irq0
irq1
irq2
irq3
irq4
irq5
irq6
irqnumber [5..0]
Priority
Encoder
irq63
IRQ Bridge
IRQ Mapper
IRQ Bridge
The IRQ Bridge allows you to route interrupt wires between Qsys subsystems. These
interrupts are routed to the IRQ receiver bridge in the CPU Subsystem.
1
Nios II BSP tools do not fully support the IRQ Bridge. Interrupts connected via an IRQ
Bridge will not appear in the generated system.h file.
931
In Figure 925, the Peripheral Subsystem has three interrupt senders that are exported
to the top level of the subsystem.
Figure 925. Qsys IRQ Bridge Application
Top-Level Qsys System
3-bit bus
IR
export
export
export
IRQ Bridge
export
IS
IS
IS
Interrupt
Sender 1
Interrupt
Sender 2
Interrupt
Sender 3
IS
Interrupt
Sender 4
IS
Peripheral Subsystem
4-bit bus
IR
CPU Subsystem
IS
Interrupt Sender
IR
Nios II
Processor
Interrupt Receiver
IRQ Mapper
Qsys inserts the IRQ Mapper automatically during generation. The IRQ Mapper
converts individual interrupt wires to a bus, and then maps the appropriate IRQ
priority number onto the bus.
By default, the interrupt sender connected to the receiver0 interface of the IRQ
mapper is the highest priority, and sequential receivers are successively lower
priority. You can modify the interrupt priority of each IRQ wire by modifying the IRQ
priority number in Qsys under the IRQ column. The modified priority is reflected in
the IRQ_MAP parameter for the auto-inserted IRQ Mapper.
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Altera Corporation
932
Figure 926 shows the IRQ column in Qsys and the default interrupt priority
allocated for the CPU subsystem shown in Figure 925 above.
Figure 926. Qsys IRQ Column
933
Clock Interfaces
You can use the Clock Settings tab to define external clock sources, for example an
oscillator on your board. The Clock Source parameters allows you to set the
following options:
Clock frequencyThe frequency of the output clock from this clock source.
Clock frequency is known When turned on, the clock frequency is known.
When turned off, the frequency is set from outside the system.
1
If turned off, system generation may fail because the components do not
receive the necessary clock information. For best results, turn this option on
before system generation.
NoneThe reset is asserted and deasserted asynchronously. You can use this
setting if you have internal synchronization circuitry that matches the reset
required for the IP in the system.
Reset Interfaces
You can choose to create a single global reset domain by selecting Create Global
Reset Network on the System menu. If your design requires more than one reset
domain, you can implement your own reset logic and connectivity.
The Component Library includes a reset controller and a reset bridge to implement
the reset functionality. You can also design your own reset logic.
1
May 2013
If you design your own reset circuitry you must carefully consider situations which
might result in system lockup. For example, if an Avalon-MM slave is reset in the
middle of a transaction, the Avalon-MM master might wait forever.
Altera Corporation
934
Reset Controller
The Reset Controller has the following parameters that you can specify to customize
its behavior:
NoneThe reset is asserted and deasserted asynchronously. You can use this
setting if you have designed internal synchronization circuitry that matches the
reset style required for the IP in the system.
There is a mismatch between the reset sources synchronous edges and the reset
sinks synchronous edges
Reset Bridge
The Reset Bridge allows you to use a reset signal in two or more subsystems of your
Qsys system. You can connect one reset source to local components, and export one or
more to other subsystems, as required. The Reset Bridge parameters are used to
describe the incoming reset and include the following options:
Active low resetWhen turned on, reset is asserted low.
935
Qsys supports multiple reset sink connections to a single reset source interface.
However, there are situations in composed systems where an internally generated
reset must be exported from the composed system in addition to being used to
connect internal components. In this situation, you must declare one reset output
interface as an export, and use another reset output to connect internal components.
Conduits
You can use the conduit interface type for interfaces that do not fit any of the other
interface types, and to group any arbitrary collection of signals. Like other interface
types, you can export or connect conduit interfaces. The PCI Express-to-Ethernet
Bridge Example System shown in Figure 715 on page 731 in the Creating a System
With Qsys chapter is an example of the use of the conduit interface for export.
You can declare an associated clock interface for conduit interfaces in the same way as
memory-mapped interfaces with the associatedClock.
To connect two conduit interfaces inside Qsys, the following conditions must be met:
The interfaces must match exactly with the same signal roles and widths.
To connect a conduit output to more than one input conduit interface, you can create a
custom component. The custom component could have one input that connects to
two outputs, and you can use this component between other conduits that you want
to connect.
f For more information about the Avalon Conduit interface, refer to the Avalon Interface
Specifications.
Address Decoding
Address decoding logic forwards appropriate addresses to each slave. Address
decoding logic simplifies component design in the following ways:
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Changing the system memory map does not involve manually editing HDL.
address [M..0]
Master
Port
Address
Decoding
Logic
read/write
address [S..0]
read/write
address [T..2]
Slave
Port 1
(8-bit)
Slave
Port 2
(32-bit)
937
In Qsys, the base addresses are controlled by the Base setting of active components on
the System Contents tab, as shown in Figure 928.
Figure 928. Base Settings in Qsys Address Decoding
Datapath Multiplexing
Datapath multiplexing logic drives the writedata signal from the granted master to
the selected slave, and the readdata signal from the selected slave back to the
requesting master. Qsys generates separate datapath multiplexing logic for every
master in the system.
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Figure 929 shows a block diagram of the datapath multiplexing logic for one master
and two slaves.
Figure 929. Block Diagram of Datapath Multiplexing Logic
readdata1
Slave
Port 1
address
Data
Path
Multiplexer
readdata
Master
Port
writedata
control
Slave
Port 2
readdata2
read/write
Wait-State
Insertion
Logic
read/write
wait request
Master
Port
address
Slave
Port
data
939
Interconnect Pipelining
If you set the Limit interconnect pipeline stages to parameter to a value greater than
0 on the Project Settings tab, Qsys automatically inserts Avalon-ST pipeline stages
when you generate your design. The pipeline stages increase the fMAX of your design
by reducing the combinational logic depth. The cost is additional latency and logic.
The insertion of pipeline stages depends upon the existence of certain interconnect
components. For example, in a single-slave system, no multiplexer exists; therefore
multiplexer pipelining does not occur. In an extreme case, of a single-master to
single-slave system, no pipelining occurs, regardless of the value of Limit
interconnect pipeline stages to.
Figure 931 shows the placement of up to four potential pipeline stages inserted by
Qsys before the input to the demultiplexer, at the output of the multiplexer, between
the arbiter and the multiplexer, and at the outputs of the demultiplexer.
Figure 931. Pipeline Placement in Arbitration Logic
Logic included in the Avalon-ST Command Network
Command
packet for
master 0
Master 0
Arbiter
for
slave 0
Master 1
Command
packet for
master 1
Selected request
Arbiter
Arbiter
for
for
slave
slave 1
1
Selected request
Master 2
Arbiter
for
slave 2
Command
packet for
master 2
Master 3
Command
packet for
master 3
Selected request
Arbiter
for
slave 3
Selected request
= Pipeline stage, masters 0-3
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940
For more information about pipelined Avalon-MM Interfaces, refer to the Optimizing
Qsys System Performance chapter in volume 1 of the Quartus II Handbook.
Read this section in conjunction with the AMBA Protocol Specifications for AXI3 on the
ARM website.
AXI3 Channels
Read and Write Address Channels
All signals are allowed with the following limitations:
Cache Support
AWCACHE and ARCACHE are passed to an AXI slave unmodified.
Bufferable
The interconnect treats AXI transactions as non-bufferable; all responses must come
from the terminal slave. When connecting to Avalon-MM slaves, since they do not
have write responses, the following exceptions applies:
For Avalon-MM slaves, the write response are generated by the slave agent once
the write transaction is accepted by the slave. The following limitation exists for an
Avalon bridge:
For an Avalon bridge, the response is generated before the write reaches the
endpoint; users must be aware of this limitation and avoid multiple paths past the
bridge to any endpoint slave, or only perform bufferable transactions to an Avalon
bridge.
941
Cacheable (Modifiable)
The interconnect acknowledges the cacheable (modifiable) attribute of AXI
transactions. It does not change the address, burst length, or burst size of nonmodifiable transactions, with the following exceptions:
AXI read and write transactions might be treated as modifiable when the
destination is an Avalon slave. The AXI transaction might be split into multiple
Avalon transactions if the slave is unable to accept the transaction, which might
occur because of burst lengths, narrow sizes, or burst types.
All other bits, for example, read allocate or write allocate, are ignored because the
interconnect does not perform caching.
By default, transactions issued by Avalon masters are treated as non-bufferable and
non-cacheable, with the allocate bits tied low. Qsys provides compile-time options to
control the cache behavior of Avalon transactions on a per-master basis.
Security Support
TrustZone refers to the security extension of the ARM architecture, which includes the
concept of "secure" and "non-secure" transactions, and a protocol for processing
between the designations. TrustZone security support is a part of the Qsys 13.0
interconnect.
The interconnect passes the AWPROT and ARPROT signals to the endpoint slave without
modification. It does not use or modify the PROT bits.
f For more information about secure systems and the TrustZone feature, refer to the
Creating a System With Qsys chapter in volume 1 of the Quartus II Handbook.
Atomic Accesses
Exclusive accesses are supported for AXI slaves by passing the lock, transaction ID,
and response signals from master to slave, with the limitation that slaves that do not
reorder responses.
Avalon slaves do not support exclusive accesses, and always return OKAY as a
response.
Locked accesses are also not supported.
Response Signaling
Full response signalling is supported. Avalon slaves always return OKAY as a response.
Ordering Model
Qsys interconnect provides responses in the same order as the commands were
issued.
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To prevent reordering, for slaves that accept reordering depths greater than 0, Qsys
does not transfer the transaction ID from the master, but provides a constant
transaction ID of 0. For slaves that do not reorder, Qsys allows the transaction ID to be
transferred to the slave.
To avoid cyclic dependencies, Qsys supports a single outstanding slave scheme for
both reads and writes. Changing the targeted slave before all responses have returned
stalls the master, regardless of transaction ID.
Data Buses
Narrow bus transfers are supported.
AXI write strobes can have any pattern that is compatible with the address and size
information. Altera recommends that transactions to Avalon slaves follow Avalon
byteenable limitations for maximum compatibility.
1
Byte 0 is always bits [7:0] in the interconnect, following AXI's and Avalon's byte
(address) invariance scheme.
Unaligned transfers are aligned if downsizing occurs. For example, when downsizing
to a bus width narrower than that required by the transaction size, AWSIZE or ARSIZE,
the transaction must be modified.
943
Qsys always assumes that the byteenable is asserted based on the size of the
command, not the address of the command. For example, for a 32-bit AXI master that
issues a read command with unaligned address starting at address 0x01, and a
burstcount of 2 to a 32-bit avalon slave, are treated as having a starting address of
0x00.
Read this section in conjunction with the AMBA Protocol Specifications for AXI4 on the
ARM website.
Burst Support
Qsys supports for INCR bursts up to 256 beats. Qsys converts long bursts to multiple
bursts in a packet with each burst having a length less than or equal to MAX_BURST
when going to AXI3 or Avalon slaves.
For narrow-sized transfers, bursts with Avalon slaves as destinations are shortened to
multiple non-bursting transactions in order to transmit the correct address to the
slaves, since Avalon slaves always perform full-sized datawidth transactions.
Bursts with AXI3 slaves as destinations are shortened to multiple bursts, with each
burst length less than or equal to 16. Bursts with AXI4 slaves as destinations are not
shortened.
QoS
Qsys routes 4-bit QoS signals (Quality of Service Signaling) on the read and write
address channels directly from the master to the slave.
Transactions from AXI3 and Avalon masters have a default value of 4'b0000, which
indicates that the transactions are not part of the QoS flow. QoS values are not used
for slaves that do not support QoS.
For Qsys 13.0, there are no programmable QoS registers or compile-time QoS options
for a master that overrides its real or default value.
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Regions
For Qsys 13.0, there is no support for the optional regions feature. AXI4 slaves with
AXREGION signals are allowed. AXREGION signals are driven with the default value of
0x0, and are limited to one entry in a master's address map.
Data packing is not supported when any master or slave is an AXI3, AXI4, or APB
component.
For example, for a read/write command with a 32-bit master connected to a 64-bit
slave, and a transaction of 2 burstcounts, Qsys sends 2 separate read/write
commands to access the 64-bit data width of the slave. Data packing is only supported
if the system does not contain AXI3, AXI4, or APB masters or slaves.
Ordering Model
Out of order support is not implemented in Qsys, version 13.0. Qsys processes AXI
slaves as device non-bufferable memory types.
The following describes the required behavior for the device non-bufferable memory
type:
945
Locked Transactions
Locked transactions are not supported for Qsys, version 13.0.
Memory Types
For AXI4, Qsys processes transactions as though the endpoint is a device memory
type. For device memory types, using non-bufferable transactions to force previous
bufferable transactions to finish is irrelevant, because Qsys interconnect always
identifies transactions as being non-bufferable.
Mismatched Attributes
There are rules for how multiple masters issue cache values to a shared memory
region. The interconnect meets requirements as long as cache signals are not modified.
Signals
Qsys supports up to 64-bits for the BUSER, WUSER and RUSER sideband signals. AXI4
allows some signals to be omitted from interfaces by aligning them with the default
values as defined in the AMBA Protocol Specifications on the ARM website.
Read this section in conjunction with the AMBA Protocol Specifications for APB on the
ARM website.
Bridges
With APB, you cannot use bridge components that use multiple PSELx in Qsys. As a
workaround, you can group PSELx, and then send the packet to the slave directly.
Altera recommends as an alternative that you instantiate the APB bridge and all the
APB slaves in Qsys. You should then connect the slave side of the bridge to any high
speed interface and connect the master side of the bridge to the APB slaves. Qsys
creates the interconnect on either side of the APB bridge and creates only one PSEL
signal.
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Alternatively, you can connect a bridge to the APB bus outside of Qsys. Use an
Avalon/AXI bridge to export the Avalon/AXI master to the top-level, and then
connect this Avalon/AXI interface to the slave side of the APB bridge. Alternatively,
instantiate the APB bridge in Qsys and export APB master to the
top- level, and from there connect to APB bus outside of Qsys.
Burst Adaptation
APB is a non-bursting interface. Therefore, for any AXI or Avalon master with
bursting support, a burst adapter is inserted before the slave interface and the burst
transaction is translated into a series of non-bursting transactions before reaching the
APB slave.
Width Adaption
Qsys allows different data width connections with APB. When connecting a wider
master to a narrower APB slave, the width adapter converts the wider transactions to
a narrower transaction to fit the APB slave data width.
1
APB does not support Write Strobe. Therefore, when connecting a narrower
transaction to a wider APB slave, the slave cannot determine which byte lane to write,
so the data at the slave might be overwritten or corrupted.
Error Response
Error responses are returned to the master. Qsys performs error mapping if the master
is an AXI3 or AXI4 master, for example, RRESP/BRESP= SLVERR. For the case when the
slave does not use SLVERR signal, an OKAY response is sent back to master by default.
May 2013
November 2012
Version
13.0.0
12.1.0
Changes
Moved Address Span Extender to the Qsys System Design Components chapter in
volume 1 of the Quartus II Handbook.
June 2012
12.0.0
Added Avalon-ST.
November 2011
11.0.1
Template update.
May 2011
11.0.0
December 2010
10.1.0
Initial release.
May 2013
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For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
Altera Corporation
948
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9001:2008
Registered
Feedback Subscribe
102
AXI streaming and bridge components are not available in the Quartus II software,
version 12.1.
103
Figure 101 shows how to implement a set of four output registers to support
software read back from logic.
Figure 101. Example of Control and Status Registers (CSR) in a Slave Component
Avalon-MM
Slave Port
Read Multiplexer
readdata[31:0]
EN
read
address[1:0]
Register File
D
Decode
2:4
User
Logic
EN
0
D
EN
1
D
address[1:0]
EN
2
D
EN
write
EN
writedata[31:0]
The decoder enables the appropriate 32-bit or 64-bit register for writes. For reads, the
address bits drive the multiplexer selection bits. The read signal registers the data
from the multiplexer, adding a pipeline stage so that the component can achieve a
higher clock frequency. This component has write wait states and one read wait state.
Alternatively, if you want high throughput, you might set both the read and write
wait states to zero, and then specify a read latency of one, because the component also
supports pipelined reads.
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104
Plan shared resourcesFor example, determine the best location for shared
resources in the system hierarchy. For example, if two subsystems share resources,
you should add the components that use those resources to a higher-level system
for easy access.
Plan how much latency you might add to your systemWhen you add a
pipeline bridge between subsystems, you might add more latency to the overall
system. You can reduce the added latency by parameterizing the pipeline bridge
with zero cycles of latency.
Figure 102 shows an example of two Nios II processor subsystems with shared
resources for message passing. Bridges in each subsystem export the Nios II data
master to the top-level system that includes the mutex (mutual exclusion component)
and shared memory component (which could be another on-chip RAM, or a
controller for an off-chip RAM device).
Figure 102. Message Passing Between Subsystems
Top-Level System
Subsystem
Subsystem
Nios II
Processor
Nios II
Processor
M
Pipeline Bridges
Arbiter
Arbiter
Arbiter
Arbiter
On-Chip
Memory
PIO
UART
Mutex
Shared
Memory
On-Chip
Memory
PIO
UART
If a design contains one or more identical functional units, the functional unit can be
defined as a subsystem and instantiated multiple times within a top-level system. You
can also design systems that process multiple data channels by instantiating the same
subsystem for each channel. This approach is easier to maintain than a larger, non
hierarchical system. In addition, such systems are easier to scale because you can
calculate the required resources as a simple multiple of the subsystem requirements.
105
Figure 103 shows a design with three subsystems, each processing a unique channel.
Figure 103. Multi Channel System
Channel 1 System
Channel 2 System
Channel N System
Nios II
Processor
M
Arbiter
S
On-Chip
Memory
Input Data
Stream
Input Data
Stream
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106
Nios II
Processor
M
DMA
Engine
M
Arbiter
Arbiter
External Memory
Controller
External Memory
Controller
Dual-Port On-Chip
Memory
PCI Express
Interface
In this Avalon example, the DMA engine operates with Avalon-MM read and write
masters. However, an AXI DMA interface typically has only one master, because in
the AXI standard the write and read channels on the master are independent and can
process transactions simultaneously.
107
Figure 105 shows an AXI example where the DMA engine operates with a single
master, because in AXI the write and read channels on the master are independent
and can process transactions simultaneously. This example shows concurrency
between the read and write channels, with the yellow lines representing concurrent
data paths.
Figure 105. AXI Multi Master Parallel Access
Nios II
Processor
M
DMA
Engine
M
Read
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Write
Arbiter
Arbiter
External Memory
Controller
External Memory
Controller
Dual-Port On-Chip
Memory
PCI Express
Interface
108
Compute
Engine 1
Data Channel 1
Host 2
Compute
Engine 2
Data Channel 2
Arbiter
Host 3
Compute
Engine 3
Data Channel 3
Host 4
Compute
Engine 4
Data Channel 4
Compute
Engine 1
Data Channel 1
Host 2
Compute
Engine 2
Data Channel 2
Host 3
Compute
Engine 3
Data Channel 3
Host 4
Compute
Engine 4
Data Channel 4
109
In this example, the DMA engine operates with Avalon-MM write and read masters.
An AXI DMA typically has only one master, because in AXI the write and read
channels on the master are independent and can process transactions simultaneously.
Figure 107. Single or Dual DMA Channels
Single DMA Channel
Maximum of One Read & One Write Per Clock Cycle
DMA
Engine
M
Read
Buffer 1
Read
Buffer 2
Write
Buffer 1
Write
Buffer 2
DMA
Engine 2
DMA
Engine 1
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Altera Corporation
Read
Buffer 1
Write
Buffer 1
Read
Buffer 2
Write
Buffer 2
1010
For more information about the Limit interconnect pipeline stages to parameter,
refer to the Qsys Interconnect chapter in volume 1 of the Quartus II Handbook.
AXI bridges are not supported in the Quartus II software, version 12.1; however, you
can use Avalon bridges between AXI interfaces, and between Avalon domains. Qsys
automatically creates interconnect logic between the AXI and Avalon interfaces, so
you do not have to explicitly instantiate bridges between these domains. For more
discussion about the benefits and disadvantages of shared and separate domains,
refer to the Qsys Interconnect chapter in volume 1 of the Quartus II Handbook.
An Avalon bridge has an Avalon-MM slave interface and an Avalon-MM master
interface. You can have many components connected to the bridge slave interface, or
many components connected to the bridge master interface, or a single component
connected to a single bridge slave or master interface. You can configure the data
width of the bridge, which can affect how Qsys generates bus sizing logic in the
interconnect. Both interfaces support Avalon-MM pipelined transfers with variable
latency, and can also support configurable burst lengths.
Transfers to the bridge slave interface are propagated to the master interface, which
connects to components downstream from the bridge. When you need greater control
over the interconnect pipelining, you can use bridges instead of using the Limit
Interconnect Pipeline Stages to parameter.
1011
Master-to-Slave
Signals
Master-to-Slave
Pipeline
D
Master-to-Slave
Signals
ENA
waitrequest
Pipeline
Wait Request
Logic
waitrequest
Connects to an
Avalon-MM
Slave Interface
Slave-to-Master
Signals
Altera Corporation
Master
I/F
Slave
I/F
May 2013
waitrequest
Connects to an
Avalon-MM
Master Interface
Slave-to-Master
Signals
Slave-to-Master
Pipeline
1012
Master 1
Master 2
Master 3
Master 4
arb
arb
Pipeline Bridge
Pipeline Bridge
arb
S
Shared
Slave
Read Data
Write Data &
Control Signals
1013
When you use a FIFO clock crossing bridge for the clock domain crossing, you add
data buffering. Buffering allows pipelined read masters to post multiple reads to the
bridge, even if the slaves downstream from the bridge do not support pipelined
transfers.
Separate Component Frequencies
You can use of a clock crossing bridge to place high and low frequency components in
separate clock domains. If you limit the fast clock domain to the portion of your
design that requires high performance, you might achieve a higher fMAX for this
portion of the design.
For example, the majority of processor peripherals included in embedded designs do
not need to operate at high frequencies, therefore you do not need to use a highfrequency clock for these components. When you compile a design with the
Quartus II software, compilation may take more time when the clock frequency
requirements are difficult to meet because the Fitter needs more time to place registers
to achieve the required fMAX. To reduce the amount of effort that the Fitter uses on low
priority and low performance components, you can place these behind a clock
crossing bridge operating at a lower frequency, allowing the Fitter to increase the
effort placed on the higher priority and higher frequency data paths.
Reduced Concurrency
The amount of logic generated for the interconnect often increases as the system
becomes larger because Qsys creates arbitration logic for every slave interface that is
shared by multiple master interfaces. Qsys inserts multiplexer logic between master
interfaces that connect to multiple slave interfaces if both support read data paths.
Most embedded processor designs contain components that are either incapable of
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Altera Corporation
1014
Concurrency
M
No Concurrency
M
Arbiter
S
Bridge
Arbiter
Arbiter
Arbiter
1015
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1016
Increased Latency
Adding a bridge to your design has an effect on the read latency between the master
and the slave. Depending on the system requirements and the type of master and
slave, this latency increase may or may not be acceptable in your design.
Acceptable Latency Increase
For a pipeline bridge, a cycle of latency is added for each pipeline option that is
enabled. The buffering in the clock crossing bridge also adds latency. If you use a
pipelined or burst master that posts many read transfers, the increase in latency does
not impact performance significantly because the latency increase is very small
compared to the length of the data transfer.
For example, if you use a pipelined read master such as a DMA controller to read data
from a component with a fixed read latency of four clock cycles, but only perform a
single word transfer, the overhead is three clock cycles out of the total four, assuming
there is no additional pipeline latency in the Qsys interconnect. The read throughput
is only 25%. Figure 1011 shows this type of low-efficiency read transfer.
Figure 1011. Low-Efficiency Read Transfer
Read Latency
Read Latency
Overhead
Overhead
clk
address
A0
A1
read
waitrequest
readdata
D0
D1
However, if 100 words of data are transferred without interruptions, the overhead is
three cycles out of the total of 103 clock cycles, corresponding to a read efficiency of
approximately 97% when there is no additional pipeline latency in the interconnect.
Adding a pipeline bridge to this read path adds two extra clock cycles of latency. The
transfer requires 105 cycles to complete, corresponding to an efficiency of
approximately 94%. Although the efficiency decreased by 3%, adding the bridge
1017
might increase the fMAX by 5%, for example, and in that case, if the clock frequency can
be increased, the overall throughput would improve. As the number of words
transferred increases, the efficiency increases to nearly 100%, whether or not a
pipeline bridge is present. Figure 1012 shows this type of high-efficiency read
transfer.
Figure 1012. High Efficiency Read Transfer
Read Latency
Overhead
clk
address
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D1
D2
D3
D4
D5
D6
read
waitrequest
readdatavalid
readdata
D7
D8
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
read
waitrequest
readdatavalid
readdata
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D4
D5
D6
D7
1018
Adding a clock crossing bridge allows the memory to operate at 125 MHz in this
example. However, this increase in frequency is negated by the increase in latency for
the following reasons, as shown in Figure 1014. If the clock crossing bridge adds six
clock cycles of latency at 100 MHz, then the memory continues to operate with a read
latency of four clock cycles; consequently, the first read from memory takes 100 ns,
and each successive word takes 10 ns because reads arrive at the frequency of the
processor, which is 100 MHz. In total, eight reads complete after 170 ns. Although the
memory operates at a higher clock frequency, the frequency at which the master
operates limits the throughput.
Figure 1014. Processor System: Eight Reads with Ten Cycles Latency
170 ns
100 ns
clk
address
A0 A1 A2 A3 A4 A5 A6 A7
read
waitrequest
readdatavalid
readdata
D0 D1 D2 D3 D4 D5 D6 D7
Limited Concurrency
Placing an bridge between multiple master and slave interfaces limits the number of
concurrent transfers your system can initiate. This limitation is the same as connecting
multiple master interfaces to a single slave interface. The slave interface of the bridge
is shared by all the masters and, as a result, Qsys creates arbitration logic. If the
components placed behind a bridge are infrequently accessed, this concurrency
limitation might be acceptable.
Bridges can have a negative impact on system performance if you use them
inappropriately. For example, if multiple memories are used by several masters, you
should not place the memory components behind a bridge. The bridge limits memory
performance by preventing concurrent memory accesses. Placing multiple memory
components behind a bridge can cause the separate slave interfaces to appear as one
large memory to the masters accessing the bridge; all masters must access the same
slave interface.
1019
Figure 1015 shows a memory subsystem with one bridge that acts as a single slave
interface for the Avalon-MM Nios II and DMA masters, which results in a bottleneck
architecture. The bridge acts as a bottleneck between the two masters and the
memories. An AXI DMA typically has only one master, because in the AXI standard
the write and read channels on the master are independent and can process
transactions simultaneously.
Figure 1015. Inappropriate Use of a Bridge in a Hierarchical System
Nios II
Processor
M
DMA
M
Arbiter
Qsys Subsystem
Bottleneck
S
Bridge
M
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DDR
SDRAM
DDR
SDRAM
DDR
SDRAM
DDR
SDRAM
1020
If the fMAX of your memory interfaces is low and you want to use a pipeline bridge
between subsystems, you can place each memory behind its own bridge, which
increases the fMAX of the system without sacrificing concurrency, as Figure 1016
shows.
Figure 1016. Efficient Memory Pipelining Without a Bottleneck in a Hierarchical System
Subsystem
Nios II
Processor
DMA
M
Arbiter
Arbiter
Arbiter
Arbiter
Bridge
Bridge
Bridge
Bridge
DDR
SDRAM
DDR
SDRAM
DDR
SDRAM
DDR
SDRAM
Subsystem
1021
Figure 1017 shows how address translation functions. In this example, the Nios II
processor connects to a bridge located at base address 0x1000, a slave connects to the
bridge master interface at an offset of 0x20, and the processor performs a write
transfer to the fourth 32-bit or 64-bit word within the slave. Nios II drives the address
0x102C to interconnect, which is within the address range of the bridge. The bridge
master interface drives 0x2C, which is within the address range of the slave, and the
transfer completes.
Figure 1017. Avalon Bridge Address Translation
Nios II Processor
M
Bridge
0x102C
0x2C
Peripheral
M
0x2C
0xC
Base = 0x1000
Address
Decoder
Base = 0x20
Address Translation
Address Translation
Address Coherency
To simplify the system design, all masters should access slaves at the same location. In
many systems, a processor passes buffer locations to other mastering components,
such as a DMA controller. If the processor and DMA controller do not access the slave
at the same location, Qsys must compensate for the differences.
In Figure 1018, a Nios II processor and DMA controller access a slave interface
located at address 0x20. The processor connects directly to the slave interface. The
DMA controller connects to a pipeline bridge located at address 0x1000, which then
connects to the slave interface. Because the DMA controller accesses the pipeline
bridge first, it must drive 0x1020 to access the first location of the slave interface.
Because the processor accesses the slave from a different location, you must maintain
two base addresses for the slave device.
Figure 1018. Slave at Different Addresses, Complicating the Software
Nios II Processor
M
Peripheral
0x20
Arbiter
Address
Decoder
Base = 0x20
Masters Drive
Different Addresses
DMA
0x0
Bridge
M
0x1020
0x20
0x20
Base = 0x1000
Address Translation
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Altera Corporation
1022
To avoid the requirement for two addresses, you can add an additional bridge to the
system, set its base address to 0x1000, and then disable all the pipelining options in
the second bridge so that the bridge has minimal impact on system timing and
resource utilization. Because this second bridge has the same base address as the
original bridge, the DMA controller connects to both the processor and DMA
controller and accesses the slave interface with the same address range, as shown in
Figure 1019.
Figure 1019. Address Translation Corrected With Bridge
Address Translation
Nios II Processor
M
Bridge
0x1020
0x20
Peripheral
0x20
Arbiter
0x0
Base = 0x1000
Address
Decoder
Base = 0x20
DMA
Bridge
M
0x1020
0x20
0x20
Base = 0x1000
Address Translation
1023
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1024
If your system includes a bridge, you must set the Maximum Pending Reads
parameter on the bridge as well. To allow maximum throughput, this value should be
equal to or greater than the Maximum Pending Reads value for the connected slave
that has the highest value. As described in Changing the Response Buffer Depth on
page 1015, you can limit the maximum pending reads of a slave and reduce the
buffer depth by reducing the parameter value on the bridge if the high throughput is
not required. If you do not know the Maximum Pending Reads value for all your
slave components, you can monitor the number of reads that are pending during
system simulation while running the hardware. To use this method, set the Maximum
Pending Reads parameter to a high value and use a master that issues read requests
on every clock, such as a DMA. Then, reduce the number of maximum pending reads
of the bridge until the bridge reduces the performance of any masters accessing the
bridge.
Arbitration lock
Sequential addressing
Burst adapters
1025
Arbitration Lock
When a master posts a burst transfer, the arbitration is locked for that master;
consequently, the bursting master should be capable of sustaining transfers for the
duration of the locked period. If, after the fourth write, the master deasserts the write
(Avalon-MM write or AXI wvalid) signal for fifty cycles, all other masters continue to
wait for access during this stalled period.
To avoid wasted bandwidth, your master designs should wait until a full burst
transfer is ready before requesting access to a slave device. Alternatively, you can
avoid wasted bandwidth by posting burstcounts equal to the amount of data that is
ready. For example, if you create a custom bursting write master with a maximum
burstcount of eight, but only three words of data are ready, you can simply present a
burstcount of three. This strategy does not result in optimal use of the system
bandwidth if the slave is capable of handling a larger burst; however, this strategy
prevents stalling and allows access for other masters in the system.
Avalon-MM Sequential Addressing
An Avalon-MM burst transfer includes a base address and a burstcount. The
burstcount represents the number of words of data to be transferred, starting from
the base address and incrementing sequentially. Burst transfers are common for
processors, DMAs, and buffer processing accelerators; however, sometimes when a
master must access non-sequential addresses. Consequently, a bursting master must
set the burstcount to the number of sequential addresses, and then reset the
burstcount for the next location.
The arbitration share algorithm has no restrictions on addresses; therefore, your
custom master can update the address it presents to the interconnect for every read or
write transaction.
f AXI has different burst types than the Avalon interface. For more information about
AXI burst types, refer to the Qsys Interconnect chapter in volume 1 of the Quartus II
Handbook, and the AMBA AXI Protocol Specification on the ARM website.
Burst Adapters
Qsys allows you to create systems that mix bursting and non-bursting master and
slave interfaces. This design strategy allows you to connect bursting master and slave
interfaces that support different maximum burst lengths, and Qsys generates burst
adapters when appropriate.
Qsys inserts a burst adapter whenever a master interface burst length exceeds the
burst length of the slave interface, or if the master issues a burst type that the slave
cannot support. For example, if you connect an AXI master to an Avalon slave, a burst
adapter is inserted.
Qsys assigns non-bursting masters and slave interfaces a burst length of one. The
burst adapter divides long bursts into shorter bursts. As a result, the burst adapter
adds logic to the address and burstcount paths between the master and slave
interfaces.
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Altera Corporation
1026
Slave
No pipeline
The Qsys interconnect does not instantiate logic to handle pipeline latency.
No pipeline
The Qsys interconnect forces the master to wait through any slave-side latency
cycles. This master-slave pair gains no benefits from pipelining, because the
master waits for each transfer to complete before beginning a new transfer.
However, while the master is waiting, the slave can accept transfers from a
different master.
Pipelined
No pipeline
The Qsys interconnect carries out the transfer as if neither master nor slave were
pipelined, causing the master to wait until the slave returns data. An example of
a non-pipeline slave is an asynchronous off-chip interface.
1027
Slave
Pipelined
The Qsys interconnect allows the master to capture data at the exact clock cycle
when data from the slave is valid, to enable maximum throughput. An example
of a fixed latency slave is an on-chip memory.
Pipelined
Pipelined with
variable latency
The slave asserts a signal when its readdata is valid, and the master captures
the data. The master-slave pair can achieve maximum throughput if the slave
has variable latency. Examples of variable latency slaves include SDRAM and
FIFO memories.
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Altera Corporation
1028
f For more information about the example in Figure 1020, refer to the write master
design in the Avalon Memory-Mapped Master Templates on the Altera website.
Figure 1020. Avalon Bursting Write Master
start_address[31:0]
go
d
load
increment_address
master_address[31:0]
Up
Counter
0 s
D
VCC
count enable
byteenable[3:0]
EN
burst_begin
done
transfer_length[31:0]
go
d
load
increment_address
length[31:0]
master_burstcount[2:0]
Down
Counter
count enable
Tracking Logic/
State Machine
fifo_used[]
burst_begin
burst_count[2:0]
write
increment_address
waitrequest
user_data[31:0]
user_data_full
full
user_data_write
write
used[]
Look-Ahead FIFO
read acknowledge
writedata[31:0]
increment_address
1029
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Altera Corporation
1030
1031
Figure 1021 shows a system with a mix of components with different burst
capabilities. It includes a Nios II/e core, a Nios II/f core, and an external processor,
which off-loads some processing tasks to the Nios II/f core.
Figure 1021. Mixed Bursting System
64
B
1
M
8
Host Processor
Interface
64
B
1
B
1
8
B
Arbiter
Arbiter
Arbiter
Arbiter
Arbiter
2
PIO
System ID
Timer
Mutex
DDR
SDRAM
Burst Adapter
64
B
2
Qsys automatically inserts burst adapters to compensate for burst length mismatches.
The adapters reduce bursts to a single transfer, or the length of two transfers. For the
external processor interface connecting to DDR SDRAM, a burst of 64 words is
divided into 32 burst transfers, each with a burst length of two.
When you generate a system, Qsys inserts burst adapters based on maximum
burstcount values; consequently, the interconnect logic includes burst adapters
between masters and slave pairs that do not require bursting, if the master is capable
of bursts. In Figure 1021, Qsys inserts a burst adapter between the Nios II processors
and the timer, system ID, and PIO peripherals. These components do not support
bursting and the Nios II processor performs only single word read and write accesses
to these components.
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1032
To reduce the number of adapters, you can add pipeline bridges, as Figure 1022
shows. The pipeline bridge between the Nios II/f core and the peripherals that do not
support bursts eliminates three burst adapters from Figure 1021. A second pipeline
bridge between the Nios II/f core and the DDR SDRAM, with its maximum burst size
set to eight, eliminates another burst adapter.
Figure 1022. Mixed Bursting System with Bridges
Host Processor
Interface
64
8
64
64
B
1
B
1
Bridge
Bridge
M
8
B
2
Arbiter
Arbiter
Arbiter
Arbiter
Arbiter
2
PIO
System ID
Timer
Mutex
DDR
SDRAM
Burst Adapter
1033
Allows each memory-mapped port to operate in only one clock domain, which
reduces design complexity of components.
Enable masters to access any slave without communication with the slave clock
domain.
A clock domain adapter consists of two finite state machines (FSM), one in each clock
domain, that use a simple hand-shaking protocol to propagate transfer control signals
(read_request, write_request, and the master waitrequest signals) across the clock
boundary.
Figure 1023 shows illustrates a clock domain adapter between one master and one
slave.
Figure 1023. Block Diagram of Clock Crossing Adapter
Receiver Clock Domain
CDC Logic
control
waitrequest
Receiver
Port
Receiver
Handshake
FSM
transfer
request
Synchronizer
Synchronizer
acknowledge
control
Sender
Handshake
FSM
waitrequest
Sender
Port
address
readdata
readdata
writedata & byte enable
The synchronizer blocks in Figure 1023 use multiple stages of flipflops to eliminate
the propagation of metastable events on the control signals that enter the handshake
FSMs. The CDC logic works with any clock ratio.
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1034
The typical sequence of events for a transfer across the CDC logic is described as
follows:
1. Master asserts address, data, and control signals.
2. The master handshake FSM captures the control signals, and immediately forces
the master to wait.
1
The FSM uses only the control signals, not address and data. For example,
the master simply holds the address signal constant until the slave side has
safely captured it.
3. Master handshake FSM initiates a transfer request to the slave handshake FSM.
4. The transfer request is synchronized to the slave clock domain.
5. The slave handshake FSM processes the request, performing the requested
transfer with the slave.
6. When the slave transfer completes, the slave handshake FSM sends an
acknowledge back to the master handshake FSM.
7. The acknowledge is synchronized back to the master clock domain.
8. The master handshake FSM completes the transaction by releasing the master
from the wait condition.
Transfers proceed as normal on the slave and the master side, without a special
protocol to handle crossing clock domains. From the perspective of a slave, there is
nothing different about a transfer initiated by a master in a different clock domain.
From the perspective of a master, a transfer across clock domains simply requires
extra clock cycles. Similar to other transfer delay cases (for example, arbitration delay
or wait states on the slave side), the Qsys forces the master to wait until the transfer
terminates. As a result, pipeline master ports do not benefit from pipelining when
performing transfers to a different clock domain.
Qsys automatically determines where to insert CDC logic based on the system
contents and the connections between components, and places CDC logic to maintain
the highest transfer rate for all components. Qsys evaluates the need for CDC logic for
each master and slave pair independently, and generates CDC logic wherever
necessary.
Four additional master clock cycles, due to the master-side clock synchronizer
Four additional slave clock cycles, due to the slave-side clock synchronizer
One additional clock in each direction, due to potential metastable events as the
control signals cross clock domains
1035
Systems that require a higher performance clock should use the Avalon-MM clock
crossing bridge instead of the automatically inserted CDC logic. The clock crossing
bridge includes a buffering mechanism, so that multiple reads and writes can be
pipelined. After paying the initial penalty for the first read or write, there is no
additional latency penalty for pending reads and writes, increasing throughput by up
to four times, at the expense of added logic resources.
Qsys does not support AXI standard low power extensions in the current version of
the QII software.
PIOs
Timers
EPCS controller
By reducing the clock frequency of the components connected to the bridge, you
reduce the dynamic power consumption of your design. Dynamic power is a function
of toggle rates and decreasing the clock frequency decreases the toggle rate.
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1036
Figure 1024. Reducing Power Utilization Using a Bridge to Separate Clock Domains
Nios II
Processor
M
Arbiter
Arbiter
DDR
SDRAM
On-Chip
Memory
Arbiter
200 MHz
S
Clock
Crossing
Bridge
M
5 MHz
PIO
UART
System ID
Timer
PLL
SPI
EPCS
Controller
S
Tristate
Conduit
M
Low-Frequency Components
S
Flash
Qsys automatically inserts clock crossing adapters between master and slave
interfaces that operate at different clock frequencies. You can choose the type of clock
crossing adapter in the Qsys Project Settings tab. There are three types of clock
crossing adapter types available in Qsys, as described below. Adapters do not appear
in the Qsys Connection column because you do not insert them.
1037
AutoQsys specifies the appropriate FIFO adapter for bursting links and the
Handshake adapter for all other links.
Throughput
Because the clock crossing bridge uses FIFOs to implement the clock crossing logic, it
buffers transfers and data. Clock crossing adapters are not pipelined, so that each
transaction is blocking until the transaction completes. Blocking transactions may
lower the throughput substantially; consequently, if you want to reduce power
consumption without limiting the throughput significantly, you should use the clock
crossing bridge or the FIFO clock crossing adapter. However, if the design simply
requires single read transfers, a clock crossing adapter is preferable because the
latency is lower.
Resource Utilization
The clock crossing bridge requires few logic resources besides on-chip memory. The
number of on-chip memory blocks used is proportional to the address span, data
width, buffering depth, and bursting capabilities of the bridge. The clock crossing
adapter does not use on-chip memory and requires a moderate number of logic
resources. The address span, data width, and the bursting capabilities of the clock
crossing adapter determine the resource utilization of the device.
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Inserting bridges
Altera Corporation
1038
There is no direct AXI equivalent for waitrequest and burstcount, though the
AMBA Protocol Specification implies that ready (the equivalent of Avalon-MM
waitrequest) cannot depend combinatorially on AXI valid. Therefore, Qsys typically
buffers AXI component boundaries (at least for the ready signal).
For slave interfaces, the interconnect manages the begintransfer signal, which is
asserted during the first clock cycle of any read or write transfer. If your waitrequest
is one clock cycle late, you can logically OR your waitrequest and the begintransfer
signals to form a new waitrequest signal that is properly synchronized, as shown in
Figure 1025.
Remaining
Component
Logic
readdata
read
waitrequest
ready
(synchronous)
begintransfer
1039
Inserting Bridges
You can use bridges to reduce toggle rates, if you do not want to modify the
component by using boundary registers or clock enables. A bridge acts as a repeater
where transfers to the slave interface are repeated on the master interface. If the
bridge is not accessed, the components connected to its master interface are also not
accessed. The master interface of the bridge remains idle until a master accesses the
bridge slave interface.
Bridges can also reduce the toggle rates of signals that are inputs to other master
interfaces. These signals are typically readdata, readdatavalid, and waitrequest.
Slave interfaces that support read accesses drive the readdata, readdatavalid, and
waitrequest signals. A bridge inserts either a register or clock crossing FIFO between
the slave interface and the master to reduce the toggle rate of the master input signals.
Disabling Logic
There are typically two types of low power modes: volatile and non-volatile. A
volatile low power mode holds the component in a reset state. When the logic is
reactivated, the previous operational state is lost. A non-volatile low power mode
restores the previous operational state. This section discusses using either softwarecontrolled or hardware-controlled sleep modes to disable a component in order to
reduce power consumption.
May 2013
Altera Corporation
1040
f For more information about the mutex core, refer to the Mutex Core chapter of the
Embedded Peripherals IP User Guide.
q
count
= 0?
reset
Down
Counter
read
write
wake
load
waitrequest
count enable
sleep_n
busy
f For more information on reducing power utilization, refer to Power Optimization in the
Quartus II Handbook.
Design Examples
The following examples illustrate the resolution of Qsys system design challenges.
Design Requirements
You must carefully design the logic for the control and data paths of pipelined read
masters. The control logic must extend a read cycle whenever the waitrequest signal
is asserted. This logic must also control the master address, byteenable, and read
signals. To achieve maximum throughput, pipelined read masters should post reads
continuously as long as waitrequest is deasserted. While read is asserted, the address
presented to the interconnect is stored.
1041
The data path logic includes the readdata and readdatavalid signals. If your master
can accept data on every clock cycle, you can register the data with the readdatavalid
as an enable bit. If your master cannot process a continuous stream of read data, it
must buffer the data in a FIFO. The control logic must stop issuing reads when the
FIFO reaches a predetermined fill level to prevent FIFO overflow.
f Refer to the Avalon Interface Specifications to learn more about the signals that
implement an Avalon pipelined read master.
May 2013
Altera Corporation
1042
Figure 1027 shows a pipeline read master that stores data in a FIFO.
Figure 1027. Pipelined Read Master
start_address[31:0]
go
d
load
increment_address
master_address[31:0]
Up
Counter
VCC
count enable
byteenable[3:0]
done
transfer_length[31:0]
go
d
load
increment_address
length[31:0]
read
Down
Counter
increment_address
count enable
Tracking Logic/
State Machine
readdatavalid
fifo_used[]
waitrequest
user_data[31:0]
user_data_empty
empty
user_data_read
read acknowledge
used[]
Look-Ahead FIFO
d
write
writedata[31:0]
readdatavalid
When the go bit is asserted, the master registers the start_address and
transfer_length signals. The master begins issuing reads continuously on the next
clock until the length register reaches zero. In this example, the word size is four
bytes so that the address always increments by four and the length decrements by
four. The read signal remains asserted unless the FIFO fills to a predetermined level.
The address register increments and the length register decrements if the length has
not reached 0 and a read is posted.
The master posts a read transfer every time the read signal is asserted and the
waitrequest is deasserted. The master issues reads until the entire buffer has been
read or waitrequest is asserted. An optional tracking block monitors the done bit.
When the length register reaches zero, some reads are outstanding. The tracking logic
prevents assertion of done until last read completes. The tracking logic monitors the
number of reads posted to the interconnect so that it does not exceed the space
remaining in the readdata FIFO. This logic includes a counter that verifies the
following conditions are met:
When the length register and the tracking logic counter reach zero, all the reads have
completed and the done bit is asserted. The done bit is important if a second master
overwrites the memory locations that the pipelined read master accesses. This bit
guarantees that the reads have completed before the original data is overwritten.
1043
Multiplexer Examples
You can combine adapters with streaming components to create datapaths whose
input and output streams have different properties. The following sections provide
examples of datapaths in which the output stream is higher performance than the
input stream. Figure 1028 shows an output with double the throughput of each
interface with a corresponding doubling of the clock frequency. Figure 1029 doubles
the data width. Figure 1030 boosts the frequency of a stream by 10% by multiplexing
input data from two sources.
Data Source
input
src
100 MHz
Dual Clk
sink
src
200 MHz
sink
src
On - Chip FIFO
Data Source
input
Memory
src
100 MHz
sink
output
200 MHz
Dual Clk
sink
src
200 MHz
sink
Data Source
input
src
8 bits
sink
@ 100 MHz
Data Format
Adapter
src
16 bits
sink
@ 100 MHz
src
16 bits
@ 100 MHz
Data Source
input
May 2013
Altera Corporation
src
8 bits
sink
@ 100 MHz
Data Format
Adapter
sink
src
16 bits
sink
@ 100 MHz
1044
30 %
channel utilization
8 bits
@ 100 MHz
src
On -Chip FIFO
Memory Dual Clk
sink
src
27 .3%
sample rate
110 MHz
100 %
channel
utilization
sink
src
On - Chip FIFO
Memory Dual Clk
Data Source
input
8 bits
@ 100 MHz
src
sink
sink
src
72 .7%
sample rate
110 MHz
output
110 MHz
sink
80 %
channel utilization
Conclusion
Recommendations presented in this chapter may improve your systems maximum
clock frequency, concurrency and throughput, logic utilization, or even power
utilization. When you design a Qsys system, use your knowledge of the design intent
and goals to further optimize system performance beyond the automated
optimization available within Qsys.
Version
Changes
May 2013
13.0.0
November 2012
12.1.0
June 2012
12.0.0
November 2011
11.1.0
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive
This chapter contains descriptions of Tcl commands and indicates the Qsys phases
during which it is available: in the main static body of the program (main), or during
the elaboration, composition, and fileset callback phases, or any combination.
Table 111 summarizes the commands and provides a reference to the full description.
Qsys supports standard Avalon, AMBA AXI3 (version 1.0), AMBA AXI4
(version 2.0), and AMBA APB 3 (version 1.0) interfaces. For more information about
Avalon and AMBA interfaces, refer to the Avalon Interface Specifications and the
AMBA Protocol Specifications on the ARM website. AXI4-Lite is not supported.
f For more information about procedures for creating component _hw.tcl files in the
Qsys Component Editor, and supported interface standards, refer to the Creating Qsys
Components and the Qsys Interconnect chapters in volume 1 of the Quartus II Handbook.
If you are developing a component to work with the Nios II processor, refer to the
Publishing Component Information to Embedded Software chapter, which describes how to
publish hardware component information for embedded software tools, such as a C
compiler and a Board Support Package (BSP) generator.
This section provides a reference for hardware Tcl commands, as follows:
(1)
(Part 1 of 3)
Command
Full Description
Module Definition
add_documentation_link <title> <fileOrUrl>
page 114
get_module_assignment <moduleName>
page 116
get_module_assignments
page 114
get_module_ports
page 115
get_module_properties
page 115
get_module_property <propertyName>
page 115
page 115
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Feedback Subscribe
112
(1)
(Part 2 of 3)
Command
Full Description
page 116
page 116
page 117
Parameters
add_parameter <parameterName> <parameterType> [<defaultValue> <description>]
page 118
decode_address_map <address_map_XML_string>
page 119
get_parameters
page 1110
get_parameter_properties
page 1110
page 1111
get_parameter_value <parameterName>
page 1111
get_string <identifier>
page 1111
load_strings <fileName>
page 1112
page 1111
page 1111
Display Items
add_display_item <groupName> <id> <type> [<additionalInfo>]
page 1118
get_display_items
page 1120
get_display_item_properties
page 1120
page 1120
page 1121
page 1122
page 1123
get_interfaces <interfaceName>
page 1123
page 1124
get_interface_assignments
page 1124
get_interface_ports [<interfaceName>]
page 1124
page 1125
get_port_properties
page 1126
page 1126
page 1124
page 1127
page 1128
Composition
add_connection <startInterface> <endInterface>[<type>]
page 1130
get_connections
page 1131
get_connection_parameters <instanceName>
page 1131
(1)
113
(Part 3 of 3)
Command
Full Description
page 1131
page 1130
get_instance_interfaces <instanceName>
page 1132
page 1132
page 1132
page 1133
get_instances
page 1132
get_instance_parameters <instanceName>
page 1133
page 1135
page 1132
page 1133
page 1136
page 1136
page 1137
Fileset Generation
add_fileset <filesetName> <filesetKind> <callbackProcName> [<displayName>]
page 1137
page 1139
create_temp_file <fileName>
page 1139
page 1140
Miscellaneous
page 1140
page 1140
get_device_family_displayname <device_family>
page 1140
set_qip_strings <qip_strings>
page 1141
Module Definition
This section provides information about the commands that you use to define and
query a module.
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114
add_documentation_link
This command allows you to link to documentation for your component.
add_documentation_link
Callback
availability
Main
Usage
Returns
None
title
fileOrUrl
A path to the component documentation, using a syntax that provides the entire
URL, not a relative path. For example: http://www.mydomain.com/my_
memory_controller.html or file:///datasheet.txt.
Arguments
Example
get_module_assignment
This command returns the value of an assignment. You can use the
get_module_assignment and set_module_assignment and the
get_interface_assignment and set_interface_assignment commands to provide
information about hardware components to embedded software tools and
applications.
get_module_assignment
Callback
availability
Usage
get_module_assignment <name>
Returns
String
Arguments
name
Example
get_module_assignment embeddedsw.CMacro.colorSpace
get_module_assignments
This command returns names of the module assignments.
get_module_assignments
Callback
availability
Usage
get_module_assignments
Returns
String
Arguments
None
Example
get_module_assignments
115
get_module_ports
This command returns a list of the names of all the ports that are currently defined.
get_module_ports
Callback
availability
Usage
get_module_ports
Returns
String
Example
get_module_ports
get_module_properties
This command returns the names of all the available module properties as a list of
strings. You can use the get_module_property and set_module_property commands
to get and set values of individual properties. The value returned by this command is
always the same for a particular version of Qsys.
get_module_properties
Callback
availability
Usage
get_module_properties
Returns
List of strings
Arguments
None
Example
get_module_properties
get_module_property
This command returns the value of a single module property.
get_module_property
Callback
availability
Usage
get_module_property <propertyName>
Returns
Arguments
propertyName
Example
package
The package command allows you to specify a particular version of the Qsys software
to avoid software compatibility issues. You must use the package command at the
beginning of your _hw.tcl file. When used, the component files behave as if they are
interpreted by the version of the Qsys software that you specify.
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116
package
Callback
availability
Usage
Returns
None
Arguments
version
Example
send_message
This command sends a message to the user of the component. The message text is
normally interpreted as HTML. The <b> element can be used to provide emphasis. If
you do not want the message text to be interpreted as HTML, then pass a list such as
{info text} as the message level.
send_message
Callback
availability
Usage
Returns
None
The following message levels are supported:
Arguments
messageLevel
messageText
set_module_assignment
This command sets the value of the specified assignment.
set_module_assignment
Callback
availability
Usage
Returns
None
117
set_module_assignment
Arguments
Example
name
value
set_module_property
This command allows you to set the values for module properties.
set_module_property
Callback
availability
Main
Usage
Returns
None
Arguments
Example
propertyName
propertyValue
Table 112 lists the available module properties, their use, and the phases in which
they can be set.
Property
Type
Can Be Set
Description
AUTHOR
String
Main program
COMPOSITION_CALLBACK
String
String
DESCRIPTION
String
Main program
DISPLAY_NAME
String
Main program
EDITABLE
Boolean
Main program
ELABORATION_CALLBACK
String
Main program
GROUP
String
Main program
ICON_PATH
String
Main program
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Altera Corporation
118
Property
Type
Can Be Set
Description
INTERNAL
Boolean
Main program
NAME
String
Main program
OPAQUE_ADDRESS_MAP
String
Main program
VERSION
String
Main program
Parameters
Parameters allow users of your component to affect its operation in the same manner
as Verilog HDL parameters or VHDL generics.
add_parameter
This command adds a parameter to your component. Most of the parameter types are
found in the C programming language or HDL. However, the string_list and
integer_list parameters that are used to create tables in GUIs require some
explanation.
Example 111. Creating Tables Using the string_list and integer_list Parameter Types
add_parameter names STRING_LIST
add_parameter counts INTEGER_LIST
add_display_item "" myTable GROUP TABLE
add_display_item myTable names PARAMETER
add_display_item myTable counts PARAMETER
119
add_parameter
Callback
availability
Main
Usage
Returns
String
Arguments
Example
parameterName
A name that you, the component author, choose for your parameter.
parameterType
defaultValue
The value for this parameter if the parameter's value is never explicitly set.
description
decode_address_map
This utility function converts an XMLformatted address map into a list of Tcl lists.
Each inner list is in the correct format for conversion to an array. The XML code
describing each slave includes: its name, start address, and end address + l.
Figure 111 shows a portion of a Qsys system with three slave devices.
Figure 111. Qsys System with Three Avalon-MM Slaves
Example 112 shows the XML code that describes the address map for the master that
accesses these slaves. The format of the XML string provided may differ from that
described here; it may have different white space between the elements and could
include additional attributes or elements. Using the decode_address_map command to
decode the XML representing an masters address map is easier and ensures that your
code will work with future versions of the XML address map.
1
Altera recommends that you use the code provided in the description of
Example 112 to enumerate over the components within an address map, rather than
writing your own parser.
May 2013
Altera Corporation
1110
decode_address_map
Callback
availability
Usage
decode_address_map <address_map_XML_string>
Returns
List of Tcl lists, each one suitable for passing to array set
Arguments
address_map_
XML_string
Example
get_parameters
This command returns the names of all parameters that have been previously defined
by add_parameter as a space-separated list.
get_parameters
Callback
availability
Usage
get_parameters
Returns
List of strings
Arguments
None
Example
get_parameter_properties
This command returns a list of all the available parameter properties as a list of
strings. The get_parameter_property and set_parameter_property commands are
used to get and set the values of these properties, respectively.
get_parameter_properties
Callback
availability
Usage
get_parameter_properties
Returns
List of strings
Arguments
None
Example
1111
get_parameter_property
This command returns a single parameter property.
get_parameter_property
Callback
availability
Usage
Returns
string, boolean, or units, depending on property. Refer to Table 113 on page 1114.
Arguments
Example
parameterName
propertyName
get_parameter_value
This command returns the current value of a parameter defined previously with the
add_parameter command.
get_parameter_value
Callback
availability
Elaboration
Usage
get_parameter_value <parameterName>
Returns
String
Arguments
parameterName
Example
(1),
Note:
(1) If AFFECTS_ELABORATION=false for a given parameter, get_parameter_value is not available for that parameter from the elaboration
callback. If AFFECTS_GENERATION=false then it is not available from the generation callback.
get_string
This command returns the value of an externalized string previously loaded by the
load_strings command.
Example 113. get_string
package require -exact qsys <version>
load_strings test.properties
set_module_property NAME test
set_module_property VERSION [get_string VERSION]
set_module_property DISPLAY_NAME [get_string DISPLAY_NAME]
add_parameter firepower INTEGER 0 ""
set_parameter_property firepower DISPLAY_NAME [get_string PARAM_DISPLAY_NAME]
set_parameter_property firepower TYPE INTEGER
set_parameter_property firepower DESCRIPTION [get_string PARAM_DESCRIPTION]
DISPLAY_NAME = Trogdor!
VERSION = 1.0
PARAM_DISPLAY_NAME = Firepower
PARAM_DESCRIPTION = The amount of force to use when breathing fire.
May 2013
Altera Corporation
1112
get_string
Availability
Usage
get_string <identifier>
Returns
string
Arguments
identifier
Example
get_string MY_STRING
load_strings
This command loads strings from an external .properties file. The format of the
properties file is in the Java Properties File format.
Example 114. load_strings
package require -exact qsys 12.1
load_strings test.properties
set_module_property NAME test
set_module_property VERSION [get_string VERSION]
set_module_property DISPLAY_NAME [get_string DISPLAY_NAME]
add_parameter firepower INTEGER 0 ""
set_parameter_property firepower DISPLAY_NAME [get_string PARAM_DISPLAY_NAME]
set_parameter_property firepower TYPE INTEGER
set_parameter_property firepower DESCRIPTION [get_string PARAM_DESCRIPTION]
DISPLAY_NAME = Trogdor!
VERSION = 1.0
PARAM_DISPLAY_NAME = Firepower
PARAM_DESCRIPTION = The amount of force to use when breathing fire.
load_strings
availability
Usage
load_strings <path>
Returns
none
Arguments
path
Example
load_strings_my_externalized_strings.properties
1113
set_parameter_property
This command sets a single parameter property.
set_parameter_property
Callback
availability
Usage
Returns
Arguments
Example
parameterName
propertyName
Specifies the property of parameterName that is being set, refer to Table 113
on page 1114 for a list of properties.
value
set_parameter_value
This command sets a parameter value. The values of derived parameters can be set
from the elaboration callback.
set_parameter_value
Callback
availability
Usage
Returns
None
Arguments
Example
May 2013
parameterName
value
Altera Corporation
1114
AFFECTS_ELABORATION
AFFECTS_GENERATION
AFFECTS_VALIDATION
Type/
Default
Boolean, true
Boolean, refer to
description
Boolean, refer to
description
Can Be Set
Description
Main program
Main program
Main program
ALLOWED_RANGES
String,""
Main program
DEFAULT_VALUE
String or
Boolean
Main program
DERIVED
Boolean, false
Elaboration
callback
1115
Type/
Default
Can Be Set
Description
DESCRIPTIONA tooltip description of the parameter
that appears in the parameter editor.
DESCRIPTION
String, ""
Main program
LONG_DESCRIPTION
DISPLAY_NAME
String,""
Main program
DISPLAY_UNITS
String, ""
Main program
ENABLED
Boolean, true
Main program
and elaboration
callbacks
HDL_PARAMETER
Boolean,false
Main program
Main program
NEW_INSTANCE_VALUE
String, ""
String, ""
Main program
set_parameter_property my_parameter
SYSTEM_INFO <info-type> [<arg>]
Refer to Table 114 for descriptions of the
<info_type> argument. You can use the
SYSTEM_INFO property to set the SYSTEM_INFO_TYPE
and SYSTEM_INFO_ARG properties at the same time.
SYSTEM_INFO_ARG
String, ""
Main program
SYSTEM_INFO_TYPE
Various
Main program
Main program
TYPE
May 2013
String, ""
Altera Corporation
1116
Type/
Default
Can Be Set
Description
Sets the units of the parameter. The following values
are possible:
UNITS
String, ""
Main program
NONE
ADDRESS
BITS
BITSPERSECOND
BYTES
CYCLES
GIGABYTES
GIGABITSPERSECOND
GIGAHERTZ
HERTZ
KILOBYTES
KILOHERTZ
KILOBITSPERSECOND
MEGABYTES
MEGABITSPERSECOND
MEGAHERTZ
MICROSECONDS
MILLISECONDS
NANOSECONDS
PERCENT
PICOSECONFDS
SECONDS
Boolean, true
Main program
elaboration,
callbacks
WIDTH
String, ""
Main program
1117
ADDRESS_MAP
Type of
Parameter
String
Description
Assigns an XML-formatted string describing the address map to the
parameter you specify.
set_parameter_property <my_parameter> SYSTEM_INFO
{ADDRESS_MAP <my_avalon-mm_master>}
ADDRESS_WIDTH
Integer
Assigns an integer to the parameter you specify that is the number of bits
an master must drive to address all of its slaves, using byte addresses.
set_parameter_property <my_parameter> SYSTEM_INFO
{ADDRESS_WIDTH <my_avalon-mm_master>}
CLOCK_DOMAIN
Integer
CLOCK_RATE
Integer or
String
CLOCK_RESET_INFO
String
Specifies the name of the modules clock or reset sink interface. (Specifies
the clock sink interface for designs that use a global reset.)
CUSTOM_INSTRUCTION_
SLAVES
String
DEVICE_FAMILY
String
Assigns the family name (not the specific device part number) of the
currently selected device to the parameter you specify.
set_parameter_property <my_parameter> SYSTEM_INFO
{DEVICE_FAMILY}
DEVICE_FEATURES
String
INTERRUPTS_USED
Integer or
string
Creates a mask indicating which bits of the interrupt receiver vector are
connected to an interrupt sender. This mask is assigned to the parameter
you specify. You can use this interrupt mask to optimize logic that handles
interrupts.
set_parameter_property <my_parameter> SYSTEM_INFO
(INTERRUPTS_USED <my_interrupt_receiver>}
May 2013
Altera Corporation
1118
SYSTEM_INFO Type
Description
Assigns an integer to the parameter you specify that is the data width of the
widest slave connected to the specified master.
MAX_SLAVE_DATA_WIDTH
Integer
set_parameter_property <my_parameter> SYSTEM_INFO
{MAX_SLAVE_DATA_WIDTH <my_avalon_mm_master>}
RESET_DOMAIN
Integer
TRISTATECONDUIT_MASTERS
String
Specifies the name or names of the modules interfaces that are tri-state
conduit slaves.
Returns an XML string containing information about the Avalon-TC
masters connected to the specified Avalon-TC slave interface on a given
component. The returned string may include all of the following
information:
TRISTATECONDUIT_INFO
String
UNIQUE_ID
String
Display Items
You specify your component GUI using the display commands.
add_display_item
You can use this command to specify the following aspects of component display:
You can create logical groups for a components parameters. For example, you
might want to create separate groups for the components timing, size, and
simulation parameters. A component displays the groups and parameters in the
order that you specify the display items for them in the _hw.tcl file.
1119
You can create a button by adding a display item of type action. The display item
includes the name of the callback to run when the action is performed.
add_display_item
Callback
availability
Main
Usage
Returns
String
groupName
id
type
groupa group. If the groupName is also defined, the new group is a child of
the groupName group. If groupName is an empty string, the group is
top-level.
actionan action defined by a callback procedure when you click the button
labeled by actionName.
Provides extra information required for display items. The following examples
illustrate how you use the additionalInfo argument for the various types:
Arguments
additionalInfo
Examples
May 2013
Altera Corporation
1120
get_display_items
This command returns a list of all items to be displayed as part of the
parameterization GUI.
get_display_items
Callback
availability
Usage
get_display_items
Returns
List of strings
Arguments
None
Example
get_display_items
get_display_item_properties
This command returns a list of properties that can be set on display items.
get_display_item_properties
Callback
availability
Main
Usage
get_display_item_properties
Returns
List of strings
Arguments
None
Example
get_display_item_properties
get_display_item_property
This command returns the value of a property that can be set on a display item.
get_display_item_property
Callback
availability
Main
Usage
Returns
String
Arguments
Example
itemName
The name of the display item whose property value is being retrieved.
propertyName
1121
set_display_item_property
This command sets the value of a property of a display item that is part of the
parameterization GUI.
set_display_item_property
Callback
availability
Main
Usage
Returns
String
Arguments
itemName
The name of the display item whose property value is being set.
propertyName
value
Type
Default
Can Be Set
Main
program
String
Description
For an ACTION display item, updates the
description /tooltip for the action button.
Provides a hint about how to display a
parameter. The following values are possible:
DISPLAY_HINT
Main
program
String,""
true
Main
program and
elaboration
callbacks
ENABLED
Boolean
GROUP
String, ""
Main
PATH
String
Main
program
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Altera Corporation
1122
TEXT
VISIBLE
Type
Default
Can Be Set
Description
string
Main
program and
elaboration
callbacks
Boolean
Main
program
elaboration,
callbacks
true
add_interface
This command adds an interface to your module. As the component author, you
choose the name of the interface. By default, interfaces are enabled. You can set the
interface property ENABLED to false to disable a component interface. If an interface is
disabled, it is hidden and its ports are automatically terminated to their default
values. Active high signals are terminated to 0, and active low signals are terminated
1.
add_interface (Part 1 of 2)
Callback
availability
Usage
Returns
String
interfaceName
Arguments
interfaceType and
direction
Interface Type
Direction
avalon
master, slave
axi
master, slave
tristate_conduit
master, slave
avalon_streaming
source, sink
interrupt
sender, receiver
conduit
end
clock
source, sink
reset
source,sink
nios_custom_instruction
slave
(1)
1123
add_interface (Part 2 of 2)
Example
Notes:
(1) The terms master, source, and start are interchangeable. The terms slave, sink, and end are interchangeable.
add_interface_port
This command adds a port to an interface on your module. The name must match the
name of a signal on the top-level module in the HDL of your component. The port
width and direction must be set by the end of the elaboration phase. The port width
can be set with one of the following mechanisms:
A constant width set in the main program and updated in the elaboration callback.
add_interface_port
Callback
availability
Usage
Returns
String
Arguments
Example
interfaceName
portName
The name of the port that matches a signal name on the top-level module in the
component's HDL files.
portRole
The role of this port within the interface. Port roles are referred to as signal
types in the Avalon Interface Specification. Refer to the Avalon Interface
Specifications for the signal types available for each interface type.
direction
width_expr
The port's width expression. In simple cases, this is just the width of the port in
bits.
get_interfaces
This command returns the names of all interfaces that have been previously defined
by add_interface as a space-separated list.
get_interfaces
Callback
availability
Usage
get_interfaces
Returns
List of strings
Arguments
None
Example
May 2013
Altera Corporation
1124
get_interface_assignment
This command returns the value of the specified name for the specified interface.
get_interface_assignment
Callback
availability
Usage
Returns
String
Arguments
Example
interfaceName
name
get_interface_assignment s1 embeddedsw.configuration.isFlash
get_interface_assignments
This command returns the value of all interface assignments for the specified
interface.
get_interface_assignments
Callback
availability
Usage
get_interface_assignments <interfaceName>
Returns
String
Arguments
interfaceName
Example
get_interface_assignments s1
get_interface_ports
This command returns the names of all of the ports that have been added to a given
interface. If the interface name is omitted, all ports for all interfaces are returned.
get_interface_ports
Callback
availability
Usage
get_interface_ports [<interfaceName>]
Returns
String
Arguments
interfaceName
Example
get_interface_ports mm_slave
The name of the interface whose ports you want to list (optional).
1125
get_interface_properties
This command returns the names of all the available interface properties for the
specified interface as a space separated list.
get_interface_properties
Callback
availability
Usage
get_interface_properties <interfaceName>
Returns
List of strings
Arguments
interfaceName
Example
get_interface_properties mm_slave
f The properties available for each interface type are different. Refer to the Avalon
Interface Specifications for more information about interface properties. The interface
properties that are common to all interface types are listed below in Table 116.
get_interface_property
This command returns the value of a single interface property from the specified
interface.
get_interface_property
Callback
availability
Usage
Returns
string, boolean, or units, depending on property. Refer to Table 116 on page 1128 and the
Avalon Interface Specifications for more information about interface properties
Arguments
Example
May 2013
interfaceName
propertyName
Altera Corporation
1126
get_port_properties
This command returns a list of all available port properties.
get_port_properties
Callback
availability
Usage
get_port_properties <portName>
Returns
String, boolean, or units, depending on property. Refer to Table 117 on page 1129 for more
information.
Arguments
portName
The name of the port whose properties are required. The following port properties are
supported:
Refer to Table 117 for a description of these properties.
Example
get_port_properties mm_slave
get_port_property
This command returns the value of single port property for the specified port.
get_port_property
Callback
availability
Usage
Returns
Arguments
Example
portName
propertyName
1127
set_interface_assignment
This command sets the value of the specified assignment for the specified interface.
set_interface_assignment
Callback
availability
Usage
Returns
None
Arguments
Example
interfaceName
name
value
set_interface_assignment s1 embeddedsw.configuration.isFlash 1
f For more information about the use of the set_interface_assignment command, refer
to the Publishing Component Information to Embedded Software chapter in the Nios II
Software Developers Handbook.
set_interface_property
This command sets a single interface property for an interface.
set_interface_property
Callback
availability
Usage
Returns
String
Arguments
Example
interfaceName
propertyName
The name of the property whose value you want to set, which is ENABLED or a
name from Table 116 on page 1128.
value
f The properties available for each interface type are different. The ENABLED property
applies to all interface types. Refer to the Avalon Interface Specifications for a
description of other properties.
May 2013
Altera Corporation
1128
set_port_property
This command sets a single port property.
set_port_property
Callback
availability
Usage
Returns
String, boolean, or units, depending on property. Refer to Table 117 on page 1129.
Arguments
Example
portName
propertyName
value
EXPORT_OF
Type
String
Description
For composed _hwl.tcl files, the EXPORT_OF property
indicates which interface of a child instance is to be
exported through this interface. Before using this
command, you must have created the border interface
using add_interface. The interface to be exported is
of the form <instanceName.interfaceName>.
SVD_ADDRESS_GROUP <int>
SVD_ADDRESS_OFFSET
Boolean
Integer
Integer
1129
Type
Description
input, output,
bidir
TERMINATION
boolean
TERMINATION_VALUE
integer
VHDL_TYPE
std_logic
std_logic_vector
auto
indicates the type of a VHDL port. The default value, auto, selects
std_logic if the width is fixed at 1, and std_logic_vector
otherwise.
WIDTH_VALUE
integer
The width of the port in bits. Cannot be set directly. Any changes
must be set through the WIDTH_EXPR property.
DIRECTION
string
DRIVEN_BY
integer, input
ROLE
string
Interface Specifications.
Specifies a split or join from the component definition in the Qsys
component library and the instantiation in a Qsys system.
FRAGMENT_LIST
string
May 2013
Altera Corporation
1130
Composition
This section describes the commands that allow you to build a component by
combining instances of other components. It also includes commands to query the
child instances in the component.
add_instance
The add_instance command adds an instance of a component, referred to as a child
or child module, to the component. You can use this command to create components
that are composed of other components.
add_instance
Callback
availability
Usage
Returns
String
Arguments
instanceName
Specifies a unique local name that you can use to manipulate the module. This
name is used in the generated HDL to identify the module.
type
The type refers to a module available in the component library, for example
altera_avalon_uart.
version
Example
add_connection
This command connects the named interfaces on child instances together using an
appropriate connection type. Both interface names consist of a child instance name,
followed by the name of an interface provided by that module. For example,
mux0.out is the interface named out on the instance named mux0. The command
returns the name of the newly added connection in start.point/end.point
format. Be careful to connect the start to the end, and not the other way around.
add_connection
Callback
availability
Usage
Returns
String
Arguments
Example
end.interface
kind
Indicates the interface type. For a list of interface types refer to add_interface
on page 1122.
name
Specifies the name of the connection. If omitted, the name is of the form
start-module.start-interface/end-module.end-interface.
1131
get_connections
This command returns a list of connections. If no argument is specified, all
connections in the component are returned. If a child instance is specified, all
connections to interfaces on the instance are returned. If an interface on a child
instance is specified, only connections to that interface are returned.
get_connections
Callback
availability
Usage
Returns
List of strings
Arguments
None
Example
get_connections cpu.instruction_master
get_connection_parameters
This command gets the names of all parameters for the connection specified.
get_connection_parameters
Callback
availability
Usage
get_connection_parameters <connectionName>
Returns
List of strings
Arguments
connectionName
Example
get_connection_parameters cpu0.data_master/dma0.csr
get_connection_parameter_value
This command gets the value of a parameter on the connection.
get_connection_parameter_value
Callback
availability
Usage
Returns
String
Arguments
connectionName
parameterName
Example
May 2013
get_connection_parameters cpu0.data_master/dma0.csr
Altera Corporation
1132
get_instances
This command lists the instance names of all child modules in the component.
get_instances
Callback
availability
Usage
get_instances
Returns
List of strings
Arguments
None
Example
get_instances
get_instance_interfaces
This command returns the names of all of the interfaces of a child module. The
interfaces can change when the parameterization of the module changes.
get_Instance_interfaces
Callback
availability
Usage
get_instance_interfaces <instanceName>
Returns
String
Arguments
instanceName
Example
get_instance_interfaces my_ColorSpaceConverter
get_instance_interface_ports
This command returns a list of the names of the ports on the specified interface.
get_Instance_interface_ports
Callback
availability
Usage
Returns
List of Strings
Arguments
instanceName
interfaceName
Example
get_instance_interface_properties
This command returns the names of all of the properties of the specified interface.
get_Instance_interface_properties
Callback
availability
Usage
1133
get_Instance_interface_properties
Returns
String
Arguments
instanceName
interfaceName
Example
get_instance_interface_properties my_ColorSpaceConverter
inputInterface
get_instance_interface_property
This command returns the value of a property associated with the specified module
interface.
get_Instance_interface_property
Callback
availability
Usage
Returns
String
Arguments
instanceName
interfaceName
propertyName
Example
get_instance_parameters
This command gets the parameters for an existing instance where the return value is
an array of key/value pairs. It omits parameters that are derived and those that have
the SYSTEM_INFO parameter property set.
get_Instance_parameters
Callback
availability
Usage
get_instance_parameters <instanceName>
Returns
List of strings
Arguments
instanceName
Examples
get_instance_parameters pixel_converter
Specifies the name of the instance whose parameters are being retrieved.
See Also
get_instance_parameter_value, get_instances,
set_instance_parameter_value
get_instance_parameter_property
This command returns the names of the specified instance parameter property.
May 2013
Altera Corporation
1134
get_Instance_parameter_property
Callback
availability
Usage
Returns
String, boolean, or units, depending on property. Refer to Table 113 on page 1114.
Arguments
instanceName
parameterName
propertyName
Example
1135
get_instance_parameter_value
This command returns the value of a parameter in a child instance. You cannot use
this command to get the value of parameters whose values are derived or those that
are defined using the SYSTEM_INFO parameter property.
get_instance_parameter_value
Callback
availability
Usage
Returns
String, boolean, or units, depending on property. Refer to Table 113 on page 1114.
Arguments
Examples
instanceName
parameterName
Notes
You can use this command with instances created by the add_instance
command.
See Also
get_instance_parameters, get_instances,
set_instance_parameter_value
May 2013
Altera Corporation
1136
get_instance_port_property
This command returns a information about the port property specified.
get_instance_port_property
Callback
availability
Usage
Returns
String
Arguments
instanceName
portName
Specifies a port.
property
Specifies the property for which information is being retrieved. Not all port
properties are visible from the parent. Those which are visible are ROLE,
DIRECTION, WIDTH, WIDTH_EXPR and VHDL_TYPE.
Example
set_connection_parameter_value
This command sets a property of the connection. The start and end are each interface
names of the format <instance>.<interface>. Connection parameters depend
on the type of connection, for memory-mapped they include base addresses and
arbitration priorities.
set_connection_parameter_value
Callback
availability
Usage
Returns
None
Arguments
connName
parameterName
parameterValue
Example
1137
set_instance_parameter_value
This command sets the value of a parameter for a child instance. Derived parameters
and SYSTEM_INFO parameters for the child instance can not be set using this command.
set_instance_parameter_value
Callback
availability
Usage
Returns
None
Arguments
instanceName
parameterName
parameterValue
Examples
Notes
You can use this command with instances created by the add_instance
command.
See Also
get_instance_parameter_value, get_instances
Fileset Generation
This section covers the commands that create files to define the component and
provide information to downstream tools.
add_fileset
This command adds a generation fileset for a particular target as specified by
<filesetKind>. This target (SIM_VHDL, SIM_VERILOG, QUARTUS_SYNTH, or
EXAMPLE_DESIGN) is called by Qsys when the specified generation target is requested.
You may define multiple filesets for each kind of fileset. The specified callback
procedure must have a single argument. The value of this argument is a generated
name which must be used in the top-level module or entity declaration of your
component. To override this generated name, you may set the fileset property
TOP_LEVEL.
May 2013
Altera Corporation
1138
Overriding the generated name is only possible if all parameterizations of a core yield
identical HDL
add_fileset
Callback
availability
Main
Usage
Returns
String
filesetName
filesetKind
Arguments
Example
SIM_VHDL
SIM_VERILOG
QUARTUS_SYNTH
EXAMPLE_DESIGN
calbackProcName
A string identifying the name of the callback procedure. If you add files in the
global section, you can then specify a blank callback procedure.
displayName
1139
add_fileset_file
This command adds an output file for the generation directory. You can specify source
file locations using either an absolute path or a path that is relative to the components
_hw.tcl file.
add_fileset_file
Callback
availability
Fileset
Usage
Returns
String
fileDestination
Specifies the output file for the file after Qsys generation.
Files support the following kinds:
fileKind
Arguments
VERILOG
SYSTEM_VERILOG
SYSTEM_VERILOG_INCLUDE
VHDL
SDC
MIF
HEX
DAT
OTHER
contentsOrPath
When the fileSource is PATH, specifies the file to be copied to filePath. When
the fileSource is TEXT, specifies the text string to be stored in the file.
Example
create_temp_file
This command creates a temporary file which can be manipulated inside the fileset
callbacks of a_hw.tcl file. This temporary file can serve as a scratch pad or can be
included in the generation output if it is included using the add_fileset_file
command.
create_temp_file
Callback
availability
Fileset
Usage
create_temp_file <fileName>
Returns
String
Arguments
fileName
Example
May 2013
Altera Corporation
1140
set_fileset_property
Allows a user to set the properties of a fileset.
set_fileset_property
Callback availability
Fileset Generation
Usage
Returns
String
Arguments
Example
filename
filesetProperty
TOP_LEVEL
Miscellaneous
check_device_family_equivalence
This command returns 1 if the device family is equivalent to one of the families in the
list, and returns 0 if the device family is not equivalent to any families.
check_device_equivalence
Callback
availability
Usage
Returns
1 or 0
Based on equivalence.
deviceName
deviceList
Arguments
Example
get_device_family_displayname
This command returns the display name of a given device family.
get_device_family_displayname
Callback
availability
Usage
get_device_family_displayname <deviceName>
Returns
Arguments
Example
1141
set_qip_strings
This command places strings in the Quartus II IP File (.qip) file. The .qip file contains
paths to the files for an IP core. You add the .qip file to your Quartus II project in the
under Files in the Settings dialog box. Successive calls to set_qip_strings are not
additive, they replace the previously declared value.
set_qip_strings
Callback
availability
Main, elaboration
Usage
Returns
Arguments
qip Entries
%entityName%
The generated name of the entity replaces this macro when the string is written
to the .qip file.
%libraryName%
The compilation library this component was compiled into is inserted in place of
this marco inside the .qip file.
Macros
Example
Table 118.
For complete AXI interface specifications, refer to the AMBA Protocol Specifications on
the ARM website
Direction
Width
araddr
Output
1 to 64
arburst
Output
arcache
Output
arid
Output
1 to 18
arlen
Output
arlock
Output
arprot
Output
arready
Input
arsize
Output
aruser
Output
1 to 64
arvalid
Output
awaddr
Output
1 to 64
May 2013
Altera Corporation
1142
Table 118.
altera_axi_master
(Part 2 of 2)
Name
Direction
Width
awburst
Output
awcache
Output
awid
Output
1 to 18
awlen
Output
awlock
Output
awprot
Output
awready
Input
awsize
Output
awuser
Output
1 to 64
awvalid
Output
bid
Input
1 to 18
bready
Output
bresp
Input
bvalid
Input
rdata
Input
rid
Input
1 to 18
rlast
Input
rready
Output
rresp
Input
rvalid
Input
wdata
Output
wid
Output
1 to 18
wlast
Output
wready
Input
wstrb
Output
wvalid
Output
Table 119.
Direction
Width
araddr
Input
1 to 64
arburst
Input
arcache
Input
arid
Input
1 to 18
arlen
Input
arlock
Input
arprot
Input
arready
Output
arsize
Input
Table 119.
altera_axi_slave
1143
(Part 2 of 2)
Name
Direction
Width
aruser
Input
1 to 64
arvalid
Input
awaddr
Input
1 to 64
awburst
Input
awcache
Input
awid
Input
1 to 18
awlen
Input
awlock
Input
awprot
Input
awready
Output
awsize
Input
awuser
Input
1 to 64
awvalid
Input
bid
Output
1 to 18
bready
Input
bresp
Output
bvalid
Output
rdata
Output
rid
Output
1 to 18
rlast
Output
rready
Input
rresp
Output
rvalid
Output
wdata
Input
wid
Input
1 to 18
wlast
Input
wready
Output
wstrb
Input
wvalid
Input
Width
paddr
[1:32]
psel
penable
pwrite
May 2013
Altera Corporation
Direction
(APB master)
Direction
(APB Slave)
Required
Output
Input
Yes
[1:16]
Output
Input
Yes
Output
Input
Yes
Output
Input
Yes
1144
Direction
(APB master)
Width
Direction
(APB Slave)
Required
pwdata
[1:32]
Output
Input
Yes
prdata
[1:32]
Input
Output
Yes
pslverr
Input
Output
No
pready
Input
Output
Yes
paddr31
Output
Input
No
Width
Direction
Description
Fundamental Signals
address
begintransfer
1-32
Master
Slave
Master
Slave
1145
Width
Direction
Description
Enables specific byte lane(s) during transfers on ports of width
greater than 8 bits. Each bit in byteenable corresponds to a
byte in writedata and readdata. The master bit <n> of
byteenable indicates whether byte <n> is being written to.
During writes, byteenables specify which bytes are being
written to; other bytes should be ignored by the slave. During
reads, byteenables indicates which bytes the master is reading.
Slaves that simply return readdata with no side effects are free
to ignore byteenables during reads. If an interface does not
have a byteenable signal, the transfer proceeds as if all
byteenables are asserted.
byteenable
byteenable_n
1, 2, 4, 8,
16, 32, 64,
128
Master
Slave
When more than one bit of the byteenable signal is asserted, all
asserted lanes are adjacent. The number of adjacent lines must
be a power of 2, and the specified bytes must be aligned on an
address boundary for the size of the data. For example, the
following values are legal for a 32-bit slave:
1111
0011
1100
0001
0010
0100
1000
debugaccess
read
read_n
readdata
write
Master
Slave
Master
Slave
write_n
writedata
May 2013
Master
Slave
Altera Corporation
Master
Slave
1146
Width
Direction
Description
Wait-State Signals
lock
Master
Slave
waitrequest
waitrequest_n
Slave
Master
readdatavalid
readdatavalid_n
Slave
Master
1147
Width
Direction
Description
Burst Signals
111
burstcount
Master
Slave
beginbursttransfer
Master
Slave
Width
Direction
Description
Fundamental Signals
1128
channel
data
14096
Source
Sink
1256
Source
Sink
error
ready
May 2013
Source
Sink
Altera Corporation
Sink
Source
The channel number for data being transferred on the current cycle.
If an interface supports the channel signal, it must also define the
maxChannel parameter.
The data signal from the source to the sink, typically carries the bulk of
the information being transferred.
The contents and format of the data signal is further defined by
parameters.
A bit mask used to mark errors affecting the data being transferred in the
current cycle. A single bit in error is used for each of the errors
recognized by the component, as defined by the errorDescriptor
property.
Asserted high to indicate that the sink can accept data. ready is asserted
by the sink on cycle <n> to mark cycle <n + readyLatency> as a ready
cycle, during which the source may assert valid and transfer data.
Sources without a ready input cannot be backpressured, and sinks
without a ready output never need to backpressure.
1148
Width
Source
Sink
valid
Direction
Description
Asserted by the source to qualify all other source to sink signals. On ready
cycles where valid is asserted, the data bus and other source to sink
signals are sampled by the sink, and on other cycles are ignored.
Sources without a valid output implicitly provide valid data on every
cycle that they are not being backpressured, and sinks without a valid
input expect valid data on every cycle that they are not backpressuring.
Packet Transfer Signals
empty
18
Source
Sink
Indicates the number of symbols that are empty during cycles that contain
the end of a packet. The empty signal is not used on interfaces where there
is one symbol per beat. If endofpacket is not asserted, this signal is not
interpreted.
Source
Sink
Source
Sink
endofpacket
startofpacket
write
Width
1-32
Direction
Req
d
In
No
In
No
chipselect_n
outputenable
outputenable_n
data
Address lines to the slave port. Specifies a byte offset into the
slaves address space.
Read-request signal. Not required if the slave port never
outputs data.
If present, data must also be used.
Write-request signal. Not required if the slave port never
receives data from a master.
In
No
In
No
In
Yes
No
write_n
chipselect
Description
8,16, 32,
64, 128,
256, 512,
1024
Bidir
1149
Width
Direction
Req
d
Description
Enables specific byte lane(s) during transfers.
Each bit in byteenable corresponds to a byte lane in data.
During writes, byteenables specify which bytes the master is
writing to the slave. During reads, byteenables indicates which
bytes the master is reading. Slaves that simply return data
with no side effects are free to ignore byteenables during
reads.
byteenable
byteenable_n
2, 4, 8,16,
32, 64,
128
In
No
When more than one byte lane is asserted, all asserted lanes
are guaranteed to be adjacent. The number of adjacent lines
must be a power of 2, and the specified bytes must be aligned
on an address boundary for the size of the data. The are legal
values for a 32-bit slave:
1111writes full 32 bits
0011writes lower 2 bytes
1100writes upper 2 bytes
0001writes byte 0 only
0010writes byte 1 only
0100writes byte 2 only
1000writes byte 3 only
writebyteenable
2,4,8,16,
In
32, 64,128
No
writebyteenable_n
begintransfer
No
In
May 2013
Altera Corporation
1150
Width
Direction
Required
Description
The meaning of request depends on the state of the grant
signal, as the following rules dictate.
1. When request is asserted and grant is deasserted,
request is requesting access for the current cycle.
Master
Slave
request
Yes
grant
Slave
Master
Yes
<name>_in
11024
Slave
Master
No
<name>_out
11024
Master
Slave
No
<name>_outen
Master
Slave
No
Width
Direction
Required
Input
Yes
clk
Description
A clock signal. Provides synchronization for internal logic and for
other interfaces.
Width
1
Direction
Output
Required
Yes
Description
An output clock signal.
1151
Width
In, out or
bidirectional
<n>
export
Direction
Description
A conduit interface consists of one or more signals of arbitrary width of direction
input or output. Compatible conduit interfaces can be connected inside the Qsys
system, exported to the next level of the hierarchical design, or to the top-level of
the Qsys system.
Width
Direction
Required
Output
Yes
Description
Interrupt Request. A slave asserts irq when it needs to be serviced.
Width
Direction
Required
132
Input
Yes
Description
irq is an <n>-bit vector, where each bit corresponds directly to one
IRQ sender, with no inherent assumption of priority.
Version
May 2013
13.0.0
November 2012
12.1.0
June 2012
12.0.0
November 2011
May 2013
11.1.0
Altera Corporation
Changes
Added the demo_axi_memory example with screen shots and example _hw.tcl code.
Template update.
1152
Version
May 2011
11.0.0
December 2010
10.1.0
Changes
Initial release.
f For more information about Tcl syntax, refer to the Tcl Developer Xchange website.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
This chapter describes components and IP cores that you can use to design your Qsys
systems. The Qsys interfaces define components appropriate for streaming highspeed data, reading and writing registers and memory, and controlling off-chip
devices.
Qsys supports standard Avalon, AMBA AXI3 (version 1.0), AMBA AXI4
(version 2.0), and AMBA APB 3 (version 1.0) interfaces. For more information about
Avalon and AMBA interfaces, refer to the Avalon Interface Specifications and the
AMBA Protocol Specifications on the ARM website. AXI4-Lite is not supported.
Bridges
Qsys provides bridge components to provide flexibility and control in your system
implementation. You can use bridges to control the topology of a Qsys system.
Bridges are not end points for data, but rather affect the way data is transported
between components. By inserting bridges between masters and slaves, you control
system topology, which in turn affects the interconnect that Qsys generates.
You can also use bridges to separate components in different clock domains and to
isolate clock domain crossing logic.
This section describes the following bridge components:
Clock Bridge
AXI bridge components are not available in the Quartus II software, but you can
connect AXI interfaces with other bridge types.
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Feedback Subscribe
122
Structure of a Bridge
A bridge has one slave interface and one master interface, as shown in Figure 121. In
Qsys, one or more masters interfaces from other components connect to the bridge
slave; then, the bridge master connects to one or more slave interfaces on other
components. In Figure 121, all three masters have logical connections to all three
slaves, although physically each master connects only to the bridge.
Figure 121. Example of Bridge in an Qsys System
M1
M2
M3
S
Bridge
M
S1
S2
S3
Master
Slave
Transfers initiated to the bridges slave propagate to the bridge master in the same
order in which they are initiated on the bridge slave.
123
Figure 122 shows an Avalon-MM pipeline bridge between Avalon-MM and AXI
networks.
Figure 122. Connecting Avalon and AXI Interfaces
Shared Avalon & AXI Domain
Avalon-MM
AXI
AXI
Network
Avalon-MM
AXI
Avalon-MM
AXI
AXI
Network
AXI
Avalon-MM
Network
Avalon-MM
AXI
Avalon-MM
Avalon-MM
Clock Bridge
The Clock Bridge allows you to connect a clock source to multiple clock input
interfaces. You can use this bridge to connect a clock source that's outside the Qsys
system through an exported interface to multiple clock input interfaces in the system.
Figure 123 illustrates the use of a clock bridge.
Figure 123. Clock Bridge
External Clock from PCB
Export
CIn
Clock Bridge
COut
CIn
PIO
CIn
DMA
Qsys System
May 2013
Altera Corporation
124
f You can use the Avalon-MM Clock Crossing Bridge to bridge between AXI Masters
and Slaves of different clock domains. For more information about Handshake and
FiFO clock crossing types, refer to the Creating a System With Qsys chapter in volume 1
of the Quartus II Handbook.
1
The Avalon-MM Clock Clocking Bridge core is implemented to work with the Qsys
interconnect. If you migrate a Qsys design that was created with an older version of
Qsys or SOPC Builder, and that includes an Avalon-MM Clock Crossing Bridge, Qsys
automatically updates your design to the current version.
XAUI PHY
Xcvr
S
Avalon-MM
Pipeline
Bridge (Qsys)
Interleave
M
Interconnect
Transceiver
Reconfiguration
Controller
Low Latency
Controller
PMA
Ch
Cntl
PCS
Alt_PMA
Because the Avalon-MM slave interface is exported to the pins of the device, having a
single Avalon-MM slave port (rather than separate ports for each Avalon-MM slave
device) reduces the pin count of the FPGA.
125
Burst Properties
For read commands, when the Address Span Extender must propagate byteenables to
prevent read side-effects, the Burstcount Width option should be set to 1. If
Burstcount Width is set greater than 1, the read burst command is expressed in a
single cycle, and assumes all byteenables are asserted on every cycle.
May 2013
Altera Corporation
126
Tri-state Components
The tri-state interface type allows you to design Qsys subsystems that connect to tristate devices on your PCB. The following three components implement the tri-state
conduit functionality:
You can use these components to implement pin sharing, convert between
unidirectional and bidirectional signals, and create tri-state controllers for devices
whose interfaces can be described using the tri-state signal types.
f For more information about the tri-state signal types, refer to the Avalon Tri-state
Conduit Interfaces chapter in the Avalon Interface Specifications, and the Avalon Tri-State
Conduit Components Use Guide.
Figure 125 illustrates the typical use of tri-state components, and includes two
Generic Tri-state Conduit Controllers. The first is customized to control a flash
memory. The second is customized to control an off-chip SSRAM. The Tri-state
Conduit Pin Sharer multiplexes between these two controllers, and the Tri-state
Conduit Bridge converts between an on-chip encoding of tri-state signals and true
bidirectional signals.
Figure 125. Tri-state Conduit System to Control Off-Chip SRAM and Flash Devices
TCS
M
Nios II
Processor
M
Generic Tri-state
Controller
Parameterized
for 8 MByte
S
TCM
x16 Flash
TCS
Avalon-MM Master
TCM
Avalon-TC Master
Avalon-MM Slave
TCS
Avalon-TC Slave
Cn
Tri-state
Conduit TCM
Pin
Sharer
TCS
Tri-state
Conduit
Bridge
Cn
SSRAM
Cn
Flash
Cn
Conduit
127
By default, the Tri-state Conduit Pin Sharer and Tri-State Conduit Bridge present byte
addresses. Each address location in many memory devices contains more than one
byte of data. In the example in Figure 125, the flash device operates on 16-bit words
and must ignore the least-significant bit of the Avalon-MM address. The SSRAM
memory operates on 32-bit words and must ignore the two, low-order memory bits.
Because neither device requires a byte address, addr[0] is not routed on the PCB.
Figure 126 shows addr[0]as unconnected.
Figure 126. Address Connections from Qsys System to PCB
PCB
Qsys
Address Map
2 MByte SSRAM
(32-bit word)
PCB_Addr[19:1]
16 MBytes
Unused
A[18:0]
10 MBytes
Tristate Conduit
Bridge
Addr[23]
Addr[22:1]
Addr[0]
8 MBytes
PCB_Addr[21:0]
2 MByte SSRAM
(32-bit word)
PCB_Addr[21:0]
8 MByte Flash
(16-bit word)
8 MByte Flash
(16-bit word)
A[21:0]
In this example design, the flash device responds to address range 0 MBytes to
8 MBytes-1. The SSRAM responds to address range 8 MBytes to 10 MBytes-1. The
PCB schematic for the PCB connects addr[20:2] to addr[18:0] of the SSRAM device
because the SSRAM responds to 32-bit word address. The 8 MByte flash device
accesses 16-bit words; consequently, the schematic does not connect addr[0]. The
chipselect signals select between the two devices.
1
May 2013
If you create a custom tri-state conduit master with word-aligned addresses, the
Tri-state Conduit Pin Sharer does nothing to change or align the address signals.
Altera Corporation
128
129
Tri-state master interface usually connects to the tri-state conduit slave interface of
the tri-state conduit pin sharer.
If the widths of shared signals differ, the signals are aligned on their 0th bit and the
higher-order pins are driven to 0 whenever the smaller signal has control of the bus.
Unshared signals always propagate through the pin sharer. The tri-state conduit pin
sharer uses the round-robin arbiter to select between tri-state conduit controllers.
1
May 2013
All tri-state conduit components connected to a given pin sharer must be in the same
clock domain.
Altera Corporation
1210
Table 121. Test Pattern Generator Estimated Resource Utilization and Performance Values
Altera Corporation
Cyclone II
Stratix
No. of
Channels
Datawidth
(No. of
8-bit
Symbols
Per Beat)
Packet
Support
fMAX
(MHz)
ALM
Count
Memory
(bits)
fMAX
(MHz)
Logic
Cells
Memory
(bits)
fMAX
(MHz)
Logic
Cells
Memory
(bits)
Yes
284
233
560
206
642
560
202
642
560
No
293
222
496
207
572
496
245
561
496
32
Yes
276
270
912
210
683
912
197
707
912
32
No
323
227
848
234
585
848
220
630
848
16
Yes
298
361
560
228
867
560
245
896
560
16
No
340
330
496
230
810
496
228
845
496
32
16
Yes
295
410
912
209
954
912
224
956
912
32
16
No
269
409
848
219
842
848
204
912
848
May 2013
Table 121 provides estimated resource utilization and performance values for the test pattern generator core.
Table 122 provides estimated resource utilization and performance values for the test pattern checker core.
Table 122. Test Pattern Checker Estimated Resource Utilization and Performance Values
Packet
Support
fMAX
(MHz)
ALM
Count
Memory
(bits)
fMAX
(MHz)
Logic
Cells
Memory
(bits)
fMAX
(MHz)
Logic
Cells
Memory
(bits)
Yes
270
271
96
179
940
174
744
96
No
371
187
32
227
628
229
663
32
32
Yes
185
396
3616
111
875
3854
105
795
3616
32
No
221
363
3520
133
686
3520
133
660
3520
16
Yes
253
462
96
185
1433
166
1323
96
Cyclone II
Stratix
16
No
277
306
32
218
1044
192
1004
32
32
16
Yes
182
582
3616
111
1367
3584
110
1298
3616
32
16
No
218
473
3520
129
1143
3520
126
1074
3520
1211
No. of
Channels
Datawidth
(No. of
8-bit
Symbols
Per Beat)
1212
TEST PATTERN
GENERATOR
Avalon-ST
Source
command
Avalon-MM
Slave Port
Avalon-MM
Slave Port
data_out
The data pattern is calculated as: Symbol Value = Symbol Position in Packet XOR Data
Error Mask. Data that is not organized in packets is a single stream with no beginning
or end.
The test pattern generator has a throttle register that is set via the Avalon-MM control
interface. The value of the throttle register is used in conjunction with a pseudorandom number generator to throttle the data generation rate.
Command Interface
The command interface is a 32-bit Avalon-MM write slave that accepts data
generation commands. It is connected to a 16-element deep FIFO, thus allowing a
master peripheral to drive a number of commands into the test pattern generator.
The command interface maps to the following registers: cmd_lo and cmd_hi. The
command is pushed into the FIFO when the register cmd_lo (address 0) is addressed.
When the FIFO is full, the command interface asserts the waitrequest signal. You can
create errors by writing to the register cmd_hi (address 1). The errors are cleared when
0 is written to this register, or its respective fields. See page Test Pattern Generator
Command Registers on page 1217 for more information about the register fields.
1213
Output Interface
The output interface is an Avalon-ST interface that optionally supports data packets.
You can configure the output interface to align with your system requirements.
Depending on the incoming stream of commands, the output data may contain
interleaved packet fragments for different channels. To keep track of the current
symbols position within each packet, the test pattern generator maintains an internal
state for each channel.
Functional Parameter
The functional parameter allows you to configure the test pattern generator as a
whole system. The Throttle Seed is the starting value for the throttle control random
number generator. Altera recommends a value that is unique to each instance of the
test pattern generator and checker cores in a system.
Output Interface
You can configure the output interface of the test pattern generator with the following
parameters:
Data Bits Per SymbolThe bits per symbol is related to the width of readdata
and writedata signals, which must be a multiple of the bits per symbol.
1
If you change only bits per symbol, and do not change the data width, you
will get errors.
Data Symbols Per BeatThe number of symbols (words) that are transferred per
beat. Valid values are 1 to 256.
Error Signal Width (bits)The width of the error signal on the output interface.
Valid values are 0 to 31. A value of 0 indicates that the error signal is not used.
May 2013
Altera Corporation
1214
data_in
Avalon-ST
Sink
Avalon-MM
Slave Port
TEST PATTERN
CHECKER
The test pattern checker detects exceptions and reports them to the control interface
via a 32-element deep internal FIFO. Possible exceptions are data error, missing startof-packet (SOP), missing end-of-packet (EOP), and signalled error.
As each exception occurs, an exception descriptor is pushed into the FIFO. If the same
exception occurs more than once consecutively, only one exception descriptor is
pushed into the FIFO. All exceptions are ignored when the FIFO is full. Exception
descriptors are deleted from the FIFO after they are read by the control and status
interface.
Input Interface
The input interface is an Avalon-ST interface that optionally supports data packets.
You can configure the input interface to align with your system requirements.
Incoming data may contain interleaved packet fragments. To keep track of the current
symbols position, the test pattern checker maintains an internal state for each
channel.
Functional Parameter
The functional parameter allows you to configure the test pattern checker as a whole
system. The Throttle Seed is the starting value for the throttle control random
number generator. Altera recommends a unique value for each instance of the test
pattern generator and checker cores in a system.
Input Parameters
You can configure the input interface of the test pattern checker using the following
parameters:
1215
Data Bits Per SymbolThe bits per symbol is related to the width of readdata
and writedata signals, which must be a multiple of the bits per symbol.
1
If you change only bits per symbol, and do not change the data width, you
will get errors.
Data Symbols Per BeatThe number of symbols (words) that are transferred per
beat. Valid values are 1 to 32.
Error Signal Width (bits)The width of the error signal on the input interface.
Valid values are 0 to 31. A value of 0 indicates that the error signal is not used.
This instruction does not apply if you use the Nios II command-line tools.
Software Files
The following software files define the low-level access to the hardware, and provide
the routines for the HAL device drivers.
1
May 2013
Altera Corporation
1216
Register Maps
This section describes the register maps for the test pattern generator and checker
cores.
Test Pattern Generator Control and Status Registers
Table 123 shows the offset for the test pattern generator control and status registers.
Each register is 32 bits wide.
Table 123. Test Pattern Generator Control and Status Register Map
Offset
Register Name
base + 0
status
base + 1
control
base + 2
fill
Name
Access
Description
[15:0]
ID
RO
[23:16]
NUMCHANNELS
RO
[30:24]
NUMSYMBOLS
RO
SUPPORTPACKETS
RO
[31]
Name
ENABLE
[7:1]
Access
RW
Description
Setting this bit to 1 enables the test pattern generator core.
Reserved
1217
Name
[16:8]
Access
Description
RW
Specifies the throttle value which can be between 0256, inclusively. This
value is used in conjunction with a pseudorandom number generator to
throttle the data generation rate.
THROTTLE
RW
SOFT RESET
When this bit is set to 1, all internal counters and statistics are reset. Write
0 to this bit to exit reset.
[31:18]
Reserved
Name
[0]
Access
Description
RO
BUSY
[6:1]
Reserved
[15:7]
RO
FILL
[31:16]
Reserved
Register Name
base + 0
cmd_lo
base + 1
cmd_hi
Table 128 describes the cmd_lo register bits. The command is pushed into the FIFO
only when the cmd_lo register is addressed.
Table 128. cmd_lo Field Descriptions
Bit(s)
Name
Access
Description
[15:0]
SIZE
RW
The segment size in symbols. Except for the last segment in a packet, the size
of all segments must be a multiple of the configured number of symbols per
beat. If this condition is not met, the test pattern generator core inserts
additional symbols to the segment to ensure the condition is fulfilled.
[29:16]
CHANNEL
RW
The channel to send the segment on. If the channel signal is less than 14 bits
wide, the low order bits of this register are used to drive the signal.
[30]
SOP
RW
Set this bit to 1 when sending the first segment in a packet. This bit is ignored
when data packets are not supported.
[31]
EOP
RW
Set this bit to 1 when sending the last segment in a packet. This bit is ignored
when data packets are not supported.
May 2013
Altera Corporation
1218
Name
Access
Description
[15:0]
SIGNALLED
ERROR
RW
Specifies the value to drive the error signal. A non-zero value creates a
signalled error.
[23:16]
DATA ERROR
RW
The output data is XORed with the contents of this register to create data
errors. To stop creating data errors, set this register to 0.
[24]
SUPRESS SOP
RW
[25]
SUPRESS EOP
RW
Set this bit to 1 to suppress the assertion of the endofpacket signal when
the last segment in a packet is sent.
Register Name
base + 0
status
base + 1
control
base + 2
base + 3
Reserved
base + 4
base + 5
exception_descriptor
base + 6
indirect_select
base + 7
indirect_count
Name
Access
Description
[15:0]
ID
RO
[23:16]
NUMCHANNELS
RO
[30:24]
NUMSYMBOLS
RO
SUPPORTPACKETS
RO
[31]
Name
ENABLE
[7:1]
Access
RW
Description
Setting this bit to 1 enables the test pattern checker.
Reserved
1219
Name
[16:8]
THROTTLE
Access
Description
RW
Specifies the throttle value which can be between 0256, inclusively. This
value is used in conjunction with a pseudorandom number generator to
throttle the data generation rate.
Setting THROTTLE to 0 stops the test pattern generator core. Setting it to
256 causes the test pattern generator core to run at full throttle. Values
between 0256 result in a data rate proportional to the throttle value.
[17]
SOFT RESET
RW
When this bit is set to 1, all internal counters and statistics are reset. Write
0 to this bit to exit reset.
[31:18]
Reserved
Name
Access
Description
[0]
DATA ERROR
RO
[1]
MISSINGSOP
RO
[2]
MISSINGEOP
RO
[7:3]
Reserved
[15:8]
SIGNALLED
ERROR
RO
[23:16]
[31:24]
Reserved
CHANNEL
RO
Bits Name
[7:0]
Access
INDIRECT
CHANNEL
RW
INDIRECT ERROR
RO
[15:8]
[31:16]
Description
Reserved
Bits Name
Access
Description
[15:0]
INDIRECT
PACKET COUNT
RO
[31:16]
INDIRECT
SYMBOL COUNT
RO
May 2013
Altera Corporation
1220
API functions are currently not available from the interrupt service routine (ISR).
data_source_reset()
Prototype:
Thread-safe:
No.
Include:
<data_source_util.h>
Parameters:
Returns:
void.
Description:
This function resets the test pattern generator core including all internal counters and FIFOs. The
control and status registers are not reset by this function.
data_source_init()
Prototype:
Thread-safe:
No.
Include:
<data_source_util.h>
Parameters:
Returns:
1Initialization is successful.
0Initialization is unsuccessful.
Description:
This function performs the following operations to initialize the test pattern generator core:
n Resets and disables the test pattern generator core.
n Sets the maximum throttle.
n Clears all inserted errors.
data_source_get_id()
Prototype:
Thread-safe:
Yes.
Include:
<data_source_util.h>
Parameters:
Returns:
Description:
data_source_get_supports_packets()
Prototype:
Thread-safe:
Yes.
Include:
<data_source_util.h>
Parameters:
Returns:
1221
This function checks if the test pattern generator core supports data packets.
data_source_get_num_channels()
Prototype:
Thread-safe:
Yes.
Include:
<data_source_util.h>
Parameters:
Returns:
Description:
This function retrieves the number of channels supported by the test pattern generator core.
data_source_get_symbols_per_cycle()
Prototype:
Thread-safe:
Yes.
Include:
<data_source_util.h>
Parameters:
Returns:
Description:
This function retrieves the number of symbols transferred by the test pattern generator core in each
beat.
data_source_set_enable()
Prototype:
Thread-safe:
No.
Include:
<data_source_util.h>
Parameters:
Returns:
void.
Description:
This function enables or disables the test pattern generator core. When disabled, the test pattern
generator core stops data transmission but continues to accept commands and stores them in the
FIFO
data_source_get_enable()
Prototype:
Thread-safe:
Yes.
Include:
<data_source_util.h>
Parameters:
Returns:
Description:
May 2013
Altera Corporation
1222
data_source_set_throttle()
Prototype:
Thread-safe:
No.
Include:
<data_source_util.h>
Parameters:
Returns:
void.
Description:
This function sets the throttle value, which can be between 0256 inclusively. The throttle value,
when divided by 256 yields the rate at which the test pattern generator sends data.
data_source_get_throttle()
Prototype:
Thread-safe:
Yes.
Include:
<data_source_util.h>
Parameters:
Returns:
Description:
data_source_is_busy()
Prototype:
Thread-safe:
Yes.
Include:
<data_source_util.h>
Parameters:
Returns:
Description:
This function checks if the test pattern generator is busy. The test pattern generator core is busy
when it is sending data or has data in the command FIFO to be sent.
data_source_fill_level()
Prototype:
Thread-safe:
Yes.
Include:
<data_source_util.h>
Parameters:
Returns:
Description:
This function retrieves the number of commands currently in the command FIFO.
May 2013
Altera Corporation
1223
1224
data_source_send_data()
Prototype:
Thread-safe:
No.
Include:
<data_source_util.h>
Parameters:
Returns:
Always returns 1.
Description:
data_sink_reset()
Prototype:
Thread-safe:
No.
Include:
<data_sink_util.h>
Parameters:
Returns:
void.
Description:
This function resets the test pattern checker core including all internal counters.
1225
data_sink_init()
Prototype:
Thread-safe:
No.
Include:
<data_sink_util.h>
Parameters:
Returns:
1Initialization is successful.
0Initialization is unsuccessful.
Description:
This function performs the following operations to initialize the test pattern checker core:
n Resets and disables the test pattern checker core.
n Sets the throttle to the maximum value.
data_sink_get_id()
Prototype:
Thread-safe:
Yes.
Include:
<data_sink_util.h>
Parameters:
Returns:
Description:
data_sink_get_supports_packets()
Prototype:
Thread-safe:
Yes.
Include:
<data_sink_util.h>
Parameters:
Returns:
Description:
This function checks if the test pattern checker core supports data packets.
data_sink_get_num_channels()
Prototype:
Thread-safe:
Yes.
Include:
<data_sink_util.h>
Parameters:
Returns:
Description:
This function retrieves the number of channels supported by the test pattern checker core.
May 2013
Altera Corporation
1226
data_sink_get_symbols_per_cycle()
Prototype:
Thread-safe:
Yes.
Include:
<data_sink_util.h>
Parameters:
Returns:
Description:
This function retrieves the number of symbols received by the test pattern checker core in each
beat.
data_sink_set enable()
Prototype:
Thread-safe:
No.
Include:
<data_sink_util.h>
Parameters:
Returns:
void.
Description:
data_sink_get_enable()
Prototype:
Thread-safe:
Yes.
Include:
<data_sink_util.h>
Parameters:
Returns:
Description:
data_sink_set_throttle()
Prototype:
Thread-safe:
No.
Include:
<data_sink_util.h>
Parameters:
Returns:
void.
Description:
This function sets the throttle value, which can be between 0256 inclusively. The throttle value,
when divided by 256 yields the rate at which the test pattern checker receives data.
1227
data_sink_get_throttle()
Prototype:
Thread-safe:
Yes.
Include:
<data_sink_util.h>
Parameters:
Returns:
Description:
data_sink_get_packet_count()
Prototype:
Thread-safe:
No.
Include:
<data_sink_util.h>
Parameters:
Returns:
Description:
This function retrieves the number of data packets received on a given channel.
data_sink_get_symbol_count()
Prototype:
Thread-safe:
No.
Include:
<data_sink_util.h>
Parameters:
Returns:
Description:
data_sink_get_error_count()
Prototype:
Thread-safe:
No.
Include:
<data_sink_util.h>
Parameters:
Returns:
Description:
May 2013
Altera Corporation
1228
data_sink_get_exception()
Prototype:
Thread-safe:
Yes.
Include:
<data_sink_util.h>
Parameters:
Returns:
Description:
This function retrieves the first exception descriptor in the exception FIFO and pops it off the FIFO.
data_sink_exception_is_exception()
Prototype:
Thread-safe:
Yes.
Include:
<data_sink_util.h>
Parameters:
exceptionException descriptor
Returns:
1Indicates an exception.
0No exception.
Description:
data_sink_exception_has_data_error()
Prototype:
Thread-safe:
Yes.
Include:
<data_sink_util.h>
Parameters:
exceptionException descriptor.
Returns:
Description:
data_sink_exception_has_missing_sop()
Prototype:
Thread-safe:
Yes.
Include:
<data_sink_util.h>
Parameters:
exceptionException descriptor.
Returns:
1Missing SOP.
0Other exception types.
Description:
1229
data_sink_exception_has_missing_eop()
Prototype:
Thread-safe:
Yes.
Include:
<data_sink_util.h>
Parameters:
exceptionException descriptor.
Returns:
1Missing EOP.
0Other exception types.
Description:
data_sink_exception_signalled_error()
Prototype:
Thread-safe:
Yes.
Include:
<data_sink_util.h>
Parameters:
exceptionException descriptor.
Returns:
Description:
This function retrieves the value of the signalled error from the exception.
data_sink_exception_channel()
Prototype:
Thread-safe:
Yes.
Include:
<data_sink_util.h>
Parameters:
exceptionException descriptor.
Returns:
Description:
This function retrieves the channel number on which a given exception occurred.
Splitter Core
The Avalon-ST Splitter Core allows you to replicate transactions from an Avalon-ST
source interface to multiple Avalon-ST sink interfaces. This core support from 1 to 16
outputs.
May 2013
Altera Corporation
1230
Avalon-ST
Splitter Core
Output 0
Out_Data
Avalon-ST
Source N
Clock
Avalon-ST
Source 0
In_Data
Avalon-ST
Sink
Output N
The Avalon-ST Splitter core copies input signals from the input interface to the
corresponding output signals of each output interface without altering the size or
functionality. This include all signals except for the ready signal. The core includes a
clock signal to determine the Avalon-ST interface and clock domain where the core
resides. Because the clock signal is unused internally, latency is not introduced when
using this core.
Backpressure
The Avalon-ST Splitter core integrates with backpressure by AND-ing the ready
signals from the output interfaces and sending the result to the input interface. As a
result, if an output interface deasserts the ready signal, the input interface receives the
deasserted ready signal, as well. This functionality ensures that backpressure on the
output interfaces is propagated to the input interface.
When the Qualify Valid Out parameter is set to 1, the Out_Valid signals on all other
output interfaces are gated when backpressure is applied from one output interface.
In this case, when any output interface deasserts its ready signal, the Out_Valid
signals on the other output interfaces are deasserted, as well.
When the Qualify Valid Out parameter is set to 0, the output interfaces have a
non-gated Out_Valid signal when backpressure is applied. In this case, when an
output interface deasserts its ready signal, the Out_Valid signals on the other output
interfaces are not affected.
Because the logic is combinational, the core introduces no latency.
Interfaces
The Avalon-ST Splitter core supports streaming data, with optional packet, channel,
and error signals. The core propagates backpressure from any output interface to the
input interface.
1231
Property
Backpressure
Ready latency = 0.
Data Width
Configurable.
Channel
Supported (optional).
Error
Supported (optional).
Packet
Supported (optional).
Parameters
Table 1218 describes the parameters that you can configure for the Splitter core.
Table 1218. Configurable Parameters
Legal
Values
Parameter
Default
Value
Description
Number Of Outputs
1 to 16
0 or 1
Data Width
1512
1512
The number of bits per symbol for the input and output interfaces.
For example, byte-oriented interfaces have 8-bit symbols.
Use Packets
0 or 1
Use Channel
0 or 1
Channel Width
0-8
Max Channels
0-255
Use Error
0 or 1
Error Width
031
Delay Core
The Avalon-ST Delay Core provides a solution to delay Avalon-ST transactions by a
constant number of clock cycles. This core supports up to 16 clock cycle delays.
May 2013
Altera Corporation
1232
Avalon-ST
Delay Core
Avalon-ST
Source
In_Data
Avalon-ST
Sink
Out_Data
Clock
The Delay core adds a delay between the input and output interfaces. The core accepts
transactions presented on the input interface and reproduces them on the output
interface N cycles later without changing the transaction.
The input interface delays the input signals by a constant N number of clock cycles to
the corresponding output signals of the output interface. The Number Of Delay
Clocks parameter defines the constant N, which must be between 0 and 16. The
change of the In_Valid signal is reflected on the Out_Valid signal exactly N cycles
later.
Reset
The Avalon-ST Delay core has a reset signal that is synchronous to the clk signal.
When the core asserts the reset signal, the output signals are held at 0. After the
reset signal is deasserted, the output signals are held at 0 for N clock cycles. The
delayed values of the input signals are then reflected at the output signals after N clock
cycles.
Interfaces
The Delay core supports streaming data, with optional packet, channel, and error
signals. This core does not support backpressure.
Table 1219 shows the Delay core properties.
Table 1219. Properties of Avalon-ST Interfaces
Feature
Property
Backpressure
Not supported.
Data Width
Configurable.
Channel
Supported (optional).
Error
Supported (optional).
Packet
Supported (optional).
1233
Parameters
Table 1220 describes the parameters that you can configure for the Delay core.
Table 1220. Configurable Parameters
Legal
Values
Parameter
Default
Value
Description
0 to 16
Data Width
1512
1512
The number of bits per symbol for the input and output
interfaces. For example, byte-oriented interfaces have 8-bit
symbols.
Use Packets
0 or 1
Use Channel
0 or 1
Channel Width
0-8
Max Channels
0-255
Use Error
0 or 1
Error Width
031
May 2013
Altera Corporation
1234
Figure 1213 shows the block diagram of the Avalon-ST Round Robin Scheduler.
Avalon-ST
Round-Robin
Scheduler
Avalon-ST Sink
Request
(Channel_select)
Avalon-MM
Write Master
Logic Registers
Memory
M512/M4K/
M-RAM
fMAX
(MHz)
0/0/0
> 125
12
25
17
0/0/0
> 125
24
62
30
0/0/0
> 125
Number of
Channels
ALUTs
Table 1222 shows the resource utilization and performance data for a Stratix III
device (EP3SL340F1760C3). The performance of Stratix IV devices is similar to
Stratix III devices.
Table 1222. Resource Utilization and Performance Data for Stratix III Devices
Logic Registers
Memory
M9K/M144K/
MLAB
fMAX
(MHz)
0/0/0
> 125
12
25
17
0/0/0
> 125
24
67
30
0/0/0
> 125
Number of
Channels
ALUTs
Table 1223 shows the resource utilization and performance data for a Cyclone III
device (EP3C120F780I7).
Table 1223. Resource Utilization and Performance Data for Cyclone III Devices (Part 1 of 2)
Number of
Channels
Total Logic
Elements
Total Registers
Memory M9K
fMAX
(MHz)
12
> 125
1235
Table 1223. Resource Utilization and Performance Data for Cyclone III Devices (Part 2 of 2)
Number of
Channels
Total Logic
Elements
Total Registers
Memory M9K
fMAX
(MHz)
12
32
17
> 125
24
71
30
> 125
Interfaces
The following interfaces are available in the Avalon-ST Round Robin Scheduler core:
Request Interface
Property
Backpressure
Not supported
Data Width
Channel
Error
Not supported
Packet
Not supported
Request Interface
The Request Interface is an Avalon-MM write master interface that requests data from
a specific channel. The Avalon-ST Round Robin Scheduler cycles through the
channels it supports and schedules data to be read.
Operations
If a particular channel is almost full, the Round Robin Scheduler will not schedule
data to be read from that channel in the source component. The scheduler only
requests 1 beat of data from a channel at each transaction. To request 1 beat of data
from channel n, the scheduler writes the value 1 to address (4 n). For example, if the
scheduler is requesting data from channel 3, the scheduler writes 1 to address 0xC. At
every clock cycle, the scheduler requests data from the next channel. Therefore, if the
scheduler starts requesting from channel 1, at the next clock cycle, it requests from
channel 2. The scheduler does not request data from a particular channel if the
almost-full status for the channel is asserted. In this case, one clock cycle is used
without a request transaction.
The Avalon-ST Round Robin Scheduler cannot determine if the requested component
is able to service the request transaction. The component asserts waitrequest when it
cannot accept new requests.
May 2013
Altera Corporation
1236
Table 1225 shows the list of ports for the Round Robin Scheduler.
Table 1225. Ports for the Avalon-ST Round Robin Scheduler
Signal
Direction
Description
In
Clock reference.
reset_n
In
Out
request_write
Out
request_writedata
Out
In
almost_full_valid
In
almost_full_channel
(Channel_Width1:0)
In
almost_full_data (log2
Max_Channels1:0)
In
request_waitrequest
Avalon-ST Almost-Full Status Interface
Parameters
Table 1226 describes the parameters that you can configure for the Round Robin
Scheduler.
Table 1226. Parameters for Avalon-ST Round Robin Scheduler Component
Parameters
Values
Description
Number of channels
232
01
Specifies whether the almost-full interface is used. If the interface is not used, the
core always requests data from the next channel at the next clock cycle.
The SPI Slave to Avalon Master Bridge and JTAG to Avalon Master Bridge are
examples of how Packets to Transactions Converter core is used. For more
information, refer to the Avalon Interface Specifications.
1237
data_out
Avalon-MM Master
Avalon
Packets to
Transactions
Converter
Avalon-ST
Source
data_in
Avalon-ST
Sink
Avalon-MM
Slave
Component
Interfaces
Table 1227 shows the properties of Avalon-ST interfaces.
Table 1227. Properties of Avalon-ST Interfaces
Feature
Property
Backpressure
Ready latency = 0.
Data Width
Channel
Not supported.
Error
Not used.
Packet
Supported.
The Avalon-MM master interface supports read and write transactions. The data
width is set to 32 bits, and burst transactions are not supported.
Operation
The Packets to Transactions Converter core receives streams of packets on its AvalonST sink interface and initiates Avalon-MM transactions. Upon receiving transaction
responses from Avalon-MM slaves, the core transforms the responses to packets and
returns them to the requesting components via its Avalon-ST source interface. The
core does not report Avalon-ST errors.
May 2013
Altera Corporation
1238
Field
Description
Transaction code
Reserved
[3:2]
Size
Transaction size in bytes. For write transactions, the size indicates the size of
the data field. For read transactions, the size indicates the total number of
bytes to read.
[7:4]
Address
[n:8]
Data
Transaction code
Reserved
Size
[4:2]
Supported Transactions
Table 1229 lists the Avalon-MM transactions supported by the Packets to
Transactions Converter core.
Table 1229. Transaction Supported
Transaction
Code
Avalon-MM Transaction
Description
0x00
Writes data to the given address until the total number of bytes written
to the same word address equals to the value specified in the size
field.
0x04
0x10
Reads 32 bits of data from the given address until the total number of
bytes read from the same address equals to the value specified in the
size field.
0x14
Reads the number of bytes specified in the size field starting from the
given address.
0x7f
No transaction.
No transaction is initiated. You can use this transaction type for testing
purposes. Although no transaction is initiated on the Avalon-MM
interface, the core still returns a response packet for this transaction
code.
The Packets to Transactions Converter core can process only a single transaction at a
time. The ready signal on the core's Avalon-ST sink interface is asserted only when the
current transaction is completely processed.
1239
No internal buffer is implemented on the data paths. Data received on the Avalon-ST
interface is forwarded directly to the Avalon-MM interface and vice-versa. Asserting
the waitrequest signal on the Avalon-MM interface backpressures the Avalon-ST sink
interface. In the opposite direction, if the Avalon-ST source interface is backpressured,
the read signal on the Avalon-MM interface is not asserted until the backpressure is
alleviated. Backpressuring the Avalon-ST source in the middle of a read could result
in data loss. In this cases, the core returns the data that is successfully received.
A transaction is considered complete when the core receives an EOP. For write
transactions, the actual data size is expected to be the same as the value of the size
property. Whether or not both values agree, the core always uses the EOP to
determine the end of data.
Malformed Packets
The following are examples of malformed packets:
May 2013
Altera Corporation
1240
Scheduling
Size
Data Width
(Cycles)
Cyclone II
Stratix
fMAX
(MHz)
ALM
Count
fMAX
(MHz)
Logic Cells
fMAX
(MHz)
Logic Cells
500
31
420
63
422
80
500
36
417
60
422
58
32
451
43
364
68
360
49
401
150
257
233
228
298
32
356
151
219
207
211
123
16
262
333
174
533
170
284
16
32
310
337
161
471
157
277
500
23
400
48
422
52
500
30
420
52
422
56
11
292
275
197
397
182
287
16
262
295
182
441
179
224
Table 1231 provides estimated resource utilization for six different configurations of
the demultiplexer. The core operating frequency varies with the device, the number of
interfaces, and the size of the datapath.
Table 1231. Demultiplexer Estimated Resource Usage
Stratix II
(Approximate LEs)
Stratix II GX
(Approximate LEs)
Cyclone II
No. of Inputs
Data Width
(Symbols per
Beat)
fMAX
(MHz)
ALM Count
fMAX
(MHz)
Logic Cells
fMAX
(MHz)
Logic Cells
500
53
400
61
399
44
15
349
171
235
296
227
273
16
363
171
233
294
231
290
500
85
392
97
381
71
15
352
247
213
450
210
417
16
328
280
218
451
222
443
1241
Multiplexer
The Avalon-ST multiplexer takes data from a variety of input data interfaces, and
multiplexes the data onto a single output interface. The multiplexer includes a roundrobin scheduler that selects from the next input interface that has data. Each input
interface has the same width as the output interface, so that the other input interfaces
are backpressured when the multiplexer is carrying data from a different input
interface.
The multiplexer includes an optional channel signal that allows each input interface
to carry channelized data. When the channel signal is enabled on an input interfaces,
the multiplexer adds log2 (num_input_interfaces) bits to make the output channel
signal. Then the output channel signal has all of the bits of the input channel, plus the
bits required to indicate the originating cycle of data. These bits are appended to
either the most or least significant bits of the output channel signal.
Figure 1215 shows a diagram of an Avalon-ST Multplexer.
Figure 1215. Multiplexer
data_in_n
sink
...
sink
...
data_in0
src
data_out
sink
sink
The scheduler processes one input interface at a time, selecting it for transfer. Once an
input interface has been selected, data from that input interface is sent until one of the
following scenarios occurs:
The input interface has no more data to send and valid is deasserted on a ready
cycle.
Input Interfaces
Each input interface is an Avalon-ST data interface that optionally supports packets.
The input interfaces are identical; they have the same symbol and data widths, error
widths, and channel widths.
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1242
Output Interface
The output interface carries the multiplexed data stream with data from the inputs.
The symbol, data, and error widths are the same as the input interfaces. The width of
the channel signal is the same as the input interfaces, with the addition of the bits
needed to indicate the origin of the data.
You can configure the following parameters for the output interface:
Data Bits Per SymbolThe bits per symbol is related to the width of readdata
and writedata signals, which must be a multiple of the bits per symbol.
1
If you change only bits per symbol, and do not change the data width, you
will get errors.
Data Symbols Per BeatThe number of symbols (words) that are transferred per
beat (transfer). Valid values are 1 to 32.
Channel Signal Width (bits)The number of bits used for the channel signal for
input interfaces. A value of 0 indicates that input interfaces do not have channels.
A value of 4 indicates that up to 16 channels share the same input interface. The
input channel can have a width between 0 to 31 bits. A value of 0 means that the
optional channel signal is not used.
Error Signal Width (bits)The width of the error signal for input and output
interfaces. A value of 0 means the error signal is not used.
Multiplexer Parameters
You can configure the following parameters for the multiplexer:
Scheduling Size (Cycles)The number of cycles that are sent from a single
channel before changing to the next channel.
Use Packet SchedulingWhen this parameter is turned on, the multiplexer only
switches the selected input interface on packet boundaries. Therefore, packets on
the output interface are not interleaved.
Use high bits to indicate source portWhen this parameter is turned on, the high
bits of the output channel signal are used to indicate the origin of the input
interface of the data. For example, if the input interfaces have 4-bit channel signals,
and the multiplexer has 4 input interfaces, the output interface has a 6-bit channel
signal. If this parameter is turned on, bits [5:4] of the output channel signal
indicate origin of the input interface of the data, and bits [3:0] are the channel bits
that were presented at the input interface.
1243
Demultiplexer
That Avalon-ST demultiplexer takes data from a channelized input data interface and
provides that data to multiple output interfaces, where the output interface selected
for a particular transfer is specified by the input channel signal. The data is delivered
to the output interfaces in the same order it is received at the input interface,
regardless of the value of channel, packet, frame, or any other signal. Each of the
output interfaces has the same width as the input interface; each output interface is
idle when the demultiplexer is driving data to a different output interface. The
demultiplexer uses log2 (num_output_interfaces) bits of the channel signal to select
the output for the data; the remainder of the channel bits are forwarded to the
appropriate output interface unchanged.Figure 1216 shows a diagram of an AvalonST Demultplexer.
Figure 1216. Demultiplexer
sink
src
data_out0
...
data_in
sink
...
src
sink
data_out_n
channel
Input Interface
Each input interface is an Avalon-ST data interface that optionally supports packets.
You can configure the following parameters for the input interface:
Data Bits Per SymbolThe bits per symbol is related to the width of readdata
and writedata signals, which must be a multiple of the bits per symbol.
1
May 2013
If you change only bits per symbol, and do not change the data width, you
will get errors.
Data Symbols Per BeatThe number of symbols (words) that are transferred per
beat (transfer). Valid values are 1 to 32.
Channel Signal Width (bits)The number of bits used for the channel signal for
output interfaces. A value of 0 means that output interfaces do not use the optional
channel signal.
Error Signal Width (bits)The width of the error signal for input and output
interfaces. A value of 0 means the error signal is not unused.
Altera Corporation
1244
Output Interfaces
Each output interface carries data from a subset of channels from the input interface.
Each output interface is identical; all have the same symbol and data widths, error
widths, and channel widths. The symbol, data, and error widths are the same as the
input interface. The width of the channel signal is the same as the input interface,
without the bits that were used to select the output interface.
Parameters
You can configure the following parameters for the demultiplexer:
High channel bits select outputWhen this option is turned on, the high bits of
the input channel signal are used by the demultiplexing function and the low
order bits are passed to the output. When this option is turned off, the low order
bits are used and the high order bits are passed through.
Figure 1217 illustrates the significance of the location of signals; for example,
there is one input interface and two output interfaces. If the low-order bits of the
channel signal select the output interfaces, the even channels goes to channel 0,
and the odd channels goes to channel 1. If the high-order bits of the channel signal
select the output interface, channels 0 to 7 goes to channel 0 and channels 8 to 15
goes to channel 1.
sink
data_out_n
src channel<3..0>
1245
data_in
Sink
Register 0
data_out
Source
Register 1
data_in
Sink
Source
data_out
Register 0
Full?
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Altera Corporation
1246
Avalon-ST
Data
Sink
in
Avalon-ST
Single-Clock
FIFO
Avalon-ST
Status
Source
Avalon-ST
Data
Source
out
Avalon-ST
Status
Source
almost_empty
almost_full
in_csr
out_csr
Avalon-MM
Slave
in
Avalon-ST
Data
Sink
Avalon-MM
Slave
Avalon-ST
Dual-Clock
FIFO
Clock A
Avalon-ST
Data
Source
out
Clock B
Interfaces
This section describes the interfaces implemented in the FIFO cores.
Property
Backpressure
Ready latency = 0.
Data Width
Configurable.
1247
Property
Channel
Error
Configurable.
Packet
Configurable.
Operating Modes
The FIFO operating modes are as follows:
Store and forward modeThis mode applies only to the single-clock FIFO
core. The core asserts the valid signal on the out interface only when a full
packet of data is available at the interface. In this mode, you can also enable the
drop-on-error feature by setting the drop_on_error register to 1. When this
feature is enabled, the core drops all packets received with the in_error signal
asserted.
Cut-through modeThis mode applies only to the single-clock FIFO core. The
core asserts the valid signal on the out interface to indicate that data is
available for consumption when the number of entries specified in the
cut_through_threshold register are available in the FIFO buffer.
To use the store and forward or cut-through mode, turn on the Use store and forward
parameter to include the csr interface (Avalon-MM slave). Set the
cut_through_threshold register to 0 to enable the store and forward mode, and then
set the register to any value greater than 0 to enable the cut-through mode. The nonzero value specifies the minimum number of FIFO entries that must be available
before the data is ready for consumption. Setting the register to 1 provides you with
the default mode.
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Altera Corporation
1248
Fill Level
You can obtain the fill level of the FIFO buffer via the optional Avalon-MM control
and status interface. Turn on the Use fill level parameter (Use sink fill level and Use
source fill level in the dual-clock FIFO core) and read the fill_level register.
The dual-clock FIFO core has two fill levels, one in each clock domain. Due to the
latency of the clock crossing logic, the fill levels reported in the input and output clock
domains may be different at any given instance. In both cases, the fill level may report
badly for the clock domain; that is, the fill level is reported high in the input clock
domain, and low in the output clock domain.
The dual-clock FIFO has an output pipeline stage to improve fMAX. This output stage is
accounted for when calculating the output fill level, but not when calculating the
input fill level. Therefore, the best measure of the amount of data in the FIFO is given
by the fill level in the output clock domain, while the fill level in the input clock
domain represents the amount of space available in the FIFO (available space = FIFO
depth input fill level).
Thresholds
You can use almost-full and almost-empty thresholds as a mechanism to prevent FIFO
overflow and underflow. This feature is available only in the single-clock FIFO core.
To use the thresholds, turn on the Use fill level, Use almost-full status, and Use
almost-empty status parameters. You can access the almost_full_threshold and
almost_full_threshold registers via the csr interface and set the registers to an
optimal value for your application. See Table 1234 on page 1249 for the register
description.
You can obtain the almost-full and almost-empty statuses from almost_full and
almost_empty interfaces (Avalon-ST status source). The core asserts the almost_full
signal when the fill level is equal to or higher than the almost-full threshold. Likewise,
the core asserts the almost_empty signal when the fill level is equal to or lower than
the almost-empty threshold.
Parameters
Table 1233 describes the parameters that you can configure for the Single-Clock and
Dual-Clock FIFO cores.
Table 1233. Configurable Parameters (Part 1 of 2)
Parameter
Legal Values
Description
132
132
Error width
032
FIFO depth
132
The FIFO depth. An output pipeline stage is added to the FIFO to increase
performance, which increases the FIFO depth by one.
Use packets
Turn on this parameter to enable data packet support on the Avalon-ST data
interfaces.
1249
Legal Values
Channel width
132
Description
The width of the channel signal.
Turn on this parameter to include the Avalon-MM control and status register
interface.
Turn on this parameter to include the Avalon-MM control and status register
interface in the input clock domain.
Turn on this parameter to include the Avalon-MM control and status register
interface in the output clock domain.
Write pointer
synchronizer length
28
The length of the write pointer synchronizer chain. Setting this parameter to a
higher value leads to better metastability while increasing the latency of the
core.
Read pointer
synchronizer length
28
The length of the read pointer synchronizer chain. Setting this parameter to a
higher value leads to better metastability.
Max Channel
1255
Register Description
The csr interface in the Avalon-ST Single Clock FIFO core provides access to registers.
Table 1234 describes the registers.
Table 1234. Register Description for Avalon-ST Single-Clock FIFO (Part 1 of 2)
32-Bit
Word Offset
Name
Access
Reset
Description
fill_level
Reserved
almost_full_threshold
RW
FIFO depth1
almost_empty_threshold
RW
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Altera Corporation
1250
Name
cut_through_threshold
Access
Reset
Description
RW
drop_on_error
RW
The in_csr and out_csr interfaces in the Avalon-ST Dual Clock FIFO core reports the
FIFO fill level. Table 1235 describes the fill level.
Table 1235. Register Description for Avalon-ST Dual-Clock FIFO
32-Bit Word
Offset
0
Name
fill_level
Access
Reset
Value
Description
24-bit FIFO fill level. Bits 24 to 31 are unused.
f For more information about the Avalon interfaces, refer to the Avalon Interface
Specifications or the Avalon Memory-Mapped Design Optimizations chapter in the
Embedded Design Handbook.
Version
May 2013
13.0.0
November 2012
12.1.0
Changes
For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
When designing for large and complex FPGAs, your design and coding styles can
impact your quality of results significantly. Designs reflecting synchronous design
practices behave predictably reliably, even when re-targeted to different device
families or speed grades. Using recommended HDL coding styles ensures that
synthesis tools can infer the optimal device hardware to implement your design.
Following best practices when creating your design hierarchy and logic provides the
most flexibility when partitioning the design for incremental compilation, and leads
to the best results. If you create floorplan location assignments to control the
placement of different design blocks (useful in team-based designs so each designer
can target a different area of the device floorplan), following best practices is
important to maintaining good design performance.
This section presents design and coding style recommendations in the following
chapters:
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Use this chapter when setting up your design hierarchy and determining the
interfaces between logic blocks in your design, as well as if/when you create a
design floorplan. You can also use this chapter to make changes to a design that
was not originally set up to take advantage of incremental compilation, because it
provides tips on changing a design to work better with an incremental design
flow.
This chapter provides design recommendations for Altera devices and describes the
Quartus II Design Assistant, which helps you check your design for violations of
Alteras design recommendations.
Current FPGA applications have reached the complexity and performance
requirements of ASICs. In the development of complex system designs, good design
practices have an enormous impact on the timing performance, logic utilization, and
system reliability of a device. Well-coded designs behave in a predictable and reliable
manner even when retargeted to different families or speed grades. Good design
practices also aid in successful design migration between FPGA and HardCopy or
ASIC implementations for prototyping and production.
For optimal performance, reliability, and faster time-to-market when designing with
Altera devices, you should adhere to the following guidelines:
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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9001:2008
Registered
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132
Before an active clock edge, you must ensure that the data input has been stable
for at least the setup time of the register.
After an active clock edge, you must ensure that the data input remains stable for
at least the hold time of the register.
When you specify all of your clock frequencies and other timing requirements, the
Quartus II TimeQuest Timing Analyzer reports actual hardware requirements for the
setup times (tSU) and hold times (tH) for every pin in your design. By meeting these
external pin requirements and following synchronous design techniques, you ensure
that you satisfy the setup and hold times for all registers in your device.
1
To meet setup and hold time requirements on all input pins, any inputs to
combinational logic that feed a register should have a synchronous relationship with
the clock of the register. If signals are asynchronous, you can register the signals at the
inputs of the device to help prevent a violation of the required setup and hold times.
133
When you violate the setup or hold time of a register, you might oscillate the output,
or set the output to an intermediate voltage level between the high and low levels
called a metastable state. In this unstable state, small perturbations such as noise in
power rails can cause the register to assume either the high or low voltage level,
resulting in an unpredictable valid state. Various undesirable effects can occur,
including increased propagation delays and incorrect output states. In some cases, the
output can even oscillate between the two valid states for a relatively long period of
time.
h For information about timing requirements and analysis in the Quartus II software,
refer to About TimeQuest Timing Analysis in Quartus II Help.
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134
Design Guidelines
When designing with HDL code, you should understand how a synthesis tool
interprets different HDL design techniques and what results to expect. Your design
techniques can affect logic utilization and timing performance, as well as the designs
reliability. This section describes basic design techniques that ensure optimal
synthesis results for designs targeted to Altera devices while avoiding several
common causes of unreliability and instability. Altera recommends that you design
your combinational logic carefully to avoid potential problems and pay attention to
your clocking schemes so that you can maintain synchronous functionality and avoid
timing problems.
Combinational Loops
Combinational loops are among the most common causes of instability and
unreliability in digital designs. Combinational loops generally violate synchronous
design principles by establishing a direct feedback loop that contains no registers. You
should avoid combinational loops whenever possible. In a synchronous design,
feedback loops should include registers. For example, a combinational loop occurs
when the left-hand side of an arithmetic expression also appears on the right-hand
side in HDL code. A combinational loop also occurs when you feed back the output of
a register to an asynchronous pin of the same register through combinational logic, as
shown in Figure 131.
Figure 131. Combinational Loop Through Asynchronous Control Pin
D
Logic
CLRN
Use recovery and removal analysis to perform timing analysis on asynchronous ports,
such as clear or reset in the Quartus II software.
h If you are using the TimeQuest Timing Analyzer, refer to Specifying Timing Constraints
and Exceptions (TimeQuest Timing Analyzer) in Quartus II Help for details about how
TimeQuest analyzer performs recovery and removal analysis.
135
Combinational loops are inherently high-risk design structures for the following
reasons:
Combinational loops can cause endless computation loops in many design tools.
Most tools break open combinational loops to process the design. The various
tools used in the design flow may open a given loop in a different manner,
processing it in a way that is inconsistent with the original design intent.
Latches
A latch is a small circuit with combinational feedback that holds a value until a new
value is assigned. You can implement latches with the Quartus II Text Editor or Block
Editor. It is common for mistakes in HDL code to cause unintended latch inference;
Quartus II Synthesis issues a warning message if this occurs.
Unlike other technologies, a latch in FPGA architecture is not significantly smaller
than a register. The architecture is not optimized for latch implementation and latches
generally have slower timing performance compared to equivalent registered
circuitry.
Latches have a transparent mode in which data flows continuously from input to
output. A positive latch is in transparent mode when the enable signal is high (low for
negative latch). In transparent mode, glitches on the input can pass through to the
output because of the direct path created. This presents significant complexity for
timing analysis. Typical latch schemes use multiple enable phases to prevent long
transparent paths from occurring. However, timing analysis cannot identify these safe
applications.
The TimeQuest analyzer analyzes latches as synchronous elements clocked on the
falling edge of the positive latch signal by default, and allows you to treat latches as
having nontransparent start and end points. Be aware that even an instantaneous
transition through transparent mode can lead to glitch propagation. The TimeQuest
analyzer cannot perform cycle-borrowing analysis.
Due to various timing complexities, latches have limited support in formal
verification tools. Therefore, you should not rely on formal verification for a design
that includes latches.
1
Avoid using latches to ensure that you can completely analyze the timing
performance and reliability of your design.
Delay Chains
You require delay chains when you use two or more consecutive nodes with a single
fan-in and a single fan-out to cause delay. Inverters are often chained together to add
delay. Delay chains are sometimes used to resolve race conditions created by other
asynchronous design practices.
May 2013
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136
Delays in PLD designs can change with each placement and routing cycle. Effects
such as rise and fall time differences and on-chip variation mean that delay chains,
especially those placed on clock paths, can cause significant problems in your design.
Refer to Hazards of Asynchronous Design on page 133 for examples of the kinds
of problems that delay chains can cause. Avoid using delay chains to prevent these
kinds of problems.
In some ASIC designs, delays are used for buffering signals as they are routed around
the device. This functionality is not required in FPGA devices because the routing
structure provides buffers throughout the device.
Using a Register
Trigger
Clock
Pulse
Q
CLRN
In Figure 132, a trigger signal feeds both inputs of a 2-input AND gate, but the
design adds inverts to create a delay chain to one of the inputs. The width of the pulse
depends on the time differences between path that feeds the gate directly, and the
path that goes through the delay chain. This is the same mechanism responsible for
the generation of glitches in combinational logic following a change of input values.
This technique artificially increases the width of the glitch.
As also shown in Figure 132, a registers output drives the same registers
asynchronous reset signal through a delay chain. The register resets itself
asynchronously after a certain delay.
The width of pulses generated in this way are difficult for synthesis and
place-and-route to determine, set, or verify. The actual pulse width can only be
determined after placement and routing, when routing and propagation delays are
known. You cannot reliably create a specific pulse width when creating HDL code,
and it cannot be set by EDA tools. The pulse may not be wide enough for the
application under all PVT conditions. Also, the pulse width changes if you change to
a different device. Additionally, verification is difficult because static timing analysis
cannot verify the pulse width.
137
Trigger Signal
Clock
In Figure 133, the pulse width is always equal to the clock period. This pulse
generator is predictable, can be verified with timing analysis, and is easily moved to
other architectures, devices, or speed grades.
Clocking Schemes
Like combinational logic, clocking schemes have a large effect on the performance
and reliability of a design. Avoid using internally generated clocks (other than PLLs)
wherever possible because they can cause functional and timing problems in the
design. Clocks generated with combinational logic can introduce glitches that create
functional problems, and the delay inherent in combinational logic can lead to timing
problems.
1
Specify all clock relationships in the Quartus II software to allow for the best
timing-driven optimizations during fitting and to allow correct timing analysis. Use
clock setting assignments on any derived or internal clocks to specify their
relationship to the base clock.
Use global device-wide, low-skew dedicated routing for all internally-generated
clocks, instead of routing clocks on regular routing lines. For more information, refer
to Clock Network Resources on page 1323.
Avoid data transfers between different clocks wherever possible. If you require a data
transfer between different clocks, use FIFO circuitry. You can use the clock uncertainty
features in the Quartus II software to compensate for the variable delays between
clock domains. Consider setting a clock setup uncertainty and clock hold uncertainty
value of 10% to 15% of the clock delay.
The following sections provide specific examples and recommendations for avoiding
clocking scheme problems.
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Altera Corporation
138
Clock
Generation
Logic
Registering the output of combinational logic ensures that glitches generated by the
combinational logic are blocked at the data input of the register.
Divided Clocks
Designs often require clocks that you create by dividing a master clock. Most Altera
FPGAs provide dedicated phase-locked loop (PLL) circuitry for clock division. Using
dedicated PLL circuitry can help you to avoid many of the problems that can be
introduced by asynchronous clock division logic.
When you must use logic to divide a master clock, always use synchronous counters
or state machines. Additionally, create your design so that registers always directly
generate divided clock signals, as described in Internally Generated Clocks, and
route the clock on global clock resources. To avoid glitches, do not decode the outputs
of a counter or a state machine to generate clock signals.
Ripple Counters
To simplify verification, avoid ripple counters in your design. In the past, FPGA
designers implemented ripple counters to divide clocks by a power of two because
the counters are easy to design and may use fewer gates than their synchronous
counterparts. Ripple counters use cascaded registers, in which the output pin of one
register feeds the clock pin of the register in the next stage. This cascading can cause
problems because the counter creates a ripple clock at each stage. These ripple clocks
must be handled properly during timing analysis, which can be difficult and may
require you to make complicated timing assignments in your synthesis and placement
and routing tools.
139
You can often use ripple clock structures to make ripple counters out of the smallest
amount of logic possible. However, in all Altera devices supported by the Quartus II
software, using a ripple clock structure to reduce the amount of logic used for a
counter is unnecessary because the device allows you to construct a counter using one
logic element per counter bit. You should avoid using ripple counters completely.
Multiplexed Clocks
Use clock multiplexing to operate the same logic function with different clock sources.
In these designs, multiplexing selects a clock source, as shown in Figure 135. For
example, telecommunications applications that deal with multiple frequency
standards often use multiplexed clocks.
Figure 135. Multiplexing Logic and Clock Sources
Multiplexed Clock Routed
on Global Clock Resource
Clock 1
Clock 2
Select Signal
Adding multiplexing logic to the clock signal can create the problems addressed in
the previous sections, but requirements for multiplexed clocks vary widely,
depending on the application. Clock multiplexing is acceptable when the clock signal
uses global clock routing resources and if the following criteria are met:
The clock multiplexing logic does not change after initial configuration
The design uses multiplexing logic to select a clock for testing purposes
If the design switches clocks in real time with no reset signal, and your design cannot
tolerate a temporarily incorrect response, you must use a synchronous design so that
there are no timing violations on the registers, no glitches on clock signals, and no race
conditions or other logical problems. By default, the Quartus II software optimizes
and analyzes all possible paths through the multiplexer and between both internal
clocks that may come from the multiplexer. This may lead to more restrictive analysis
than required if the multiplexer is always selecting one particular clock. If you do not
require the more complete analysis, you can assign the output of the multiplexer as a
base clock in the Quartus II software, so that all register-to-register paths are analyzed
using that clock.
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Altera Corporation
1310
Gated Clocks
Gated clocks turn a clock signal on and off using an enable signal that controls gating
circuitry, as shown in Figure 136. When a clock is turned off, the corresponding clock
domain is shut down and becomes functionally inactive.
Figure 136. Gated Clock
D
Clock
Gating Signal
Gated Clock
You can use gated clocks to reduce power consumption in some device architectures
by effectively shutting down portions of a digital circuit when they are not in use.
When a clock is gated, both the clock network and the registers driven by it stop
toggling, thereby eliminating their contributions to power consumption. However,
gated clocks are not part of a synchronous scheme and therefore can significantly
increase the effort required for design implementation and verification. Gated clocks
contribute to clock skew and make device migration difficult. These clocks are also
sensitive to glitches, which can cause design failure.
Use dedicated hardware to perform clock gating rather than an AND or OR gate. For
example, you can use the clock control block in newer Altera devices to shut down an
entire clock network. Dedicated hardware blocks ensure that you use global routing
with low skew, and avoid any possible hold time problems on the device due to logic
delay on the clock line.
From a functional point of view, you can shut down a clock domain in a purely
synchronous manner using a synchronous clock enable signal. However, when using
a synchronous clock enable scheme, the clock network continues toggling. This
practice does not reduce power consumption as much as gating the clock at the source
does. In most cases, use a synchronous scheme such as those described in
Synchronous Clock Enables. For improved power reduction when gating clocks
with logic, refer to Recommended Clock-Gating Methods on page 1311.
1311
Data
Enable
Clock
Gating Signal
Enable
In the technique shown in Figure 138, a register generates the enable signal to ensure
that the signal is free of glitches and spikes. The register that generates the enable
signal is triggered on the inactive edge of the clock to be gated. Use the falling edge
when gating a clock that is active on the rising edge, as shown in Figure 138. Using
this technique, only one input of the gate that turns the clock on and off changes at a
time. This prevents glitches or spikes on the output. Use an AND gate to gate a clock
that is active on the rising edge. For a clock that is active on the falling edge, use an
OR gate to gate the clock and register the enable command with a positive
edge-triggered register.
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When using this technique, pay close attention to the duty cycle of the clock and the
delay through the logic that generates the enable signal because you must generate
the enable command in one-half the clock cycle. This situation might cause problems
if the logic that generates the enable command is particularly complex, or if the duty
cycle of the clock is severely unbalanced. However, careful management of the duty
cycle and logic delay may be an acceptable solution when compared with problems
created by other methods of gating clocks.
Ensure that you apply a clock setting to the gated clock in the TimeQuest analyzer. As
shown in Figure 138 on page 1311, apply a clock setting to the output of the AND
gate. Otherwise, the timing analyzer might analyze the circuit using the clock path
through the register as the longest clock path and the path that skips the register as
the shortest clock path, resulting in artificial clock skew.
In certain cases, converting the gated clocks to clock enables may help reduce glitch
and clock skew, and eventually produce a more accurate timing analysis. You can set
the Quartus II software to automatically convert gated clocks to clock enables by
turning on the Auto Gated Clock Conversion option. The conversion applies to two
types of gated clocking schemes: single-gated clock and cascaded-gated clock. The
TimeQuest analyzer supports this option for Arria II, Arria II GX, Cyclone II,
Cyclone III, Cyclone IV, HardCopy series, Stratix II, Stratix II GX, Stratix III,
Stratix IV, and Stratix V devices.
f For information about the settings and limitations of this option, refer to the Auto
Gated Clock Conversion section of the Quartus II Integrated Synthesis chapter in
volume 1 of the Quartus II Handbook.
1313
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1314
Register duplicationThis technique is most useful where registers have high fanout, or where the fan-out is in physically distant areas of the device. Review the
netlist optimizations report and consider manually duplicating registers
automatically added by physical synthesis. You can also locate the original and
duplicate registers in the Chip Planner. Compare their locations, and if the fan-out
is improved, modify the code and turn off register duplication to save compile
time.
Apply False Path constraints to all asynchronous clock domain crossings or resets
in the design. This technique prevents overconstraining and the Fitter focuses only
on critical paths to reduce compile time. However, over constraining timing
critical clock domains can sometimes provide better timing results and lower
compile times than physical synthesis.
Overconstrain rather than using physical synthesis when the slack improvement
from physical synthesis is near zero. Overconstrain the frequency requirement on
timing critical clock domains by using setup uncertainty.
1315
For high-speed and high-bandwidth designs, optimize speed by reducing bus width
and wire usage. To reduce wire use, move the data as little as possible. For example, if
a block of logic functions on a few bits of a word, store inactive bits in a fifo or
memory. Memory is cheaper and denser than registers and reduces wire usage.
Power Optimization
The total FPGA power consumption is comprised of I/O power, core static power,
and core dynamic power. Knowledge of the relationship between these components is
fundamental in calculating the overall total power consumption. You can use various
optimization techniques and tools to minimize power consumption when applied
during FPGA design implementation. The Quartus II software offers power-driven
compilation features to fully optimize device power consumption. Power-driven
compilation focuses on reducing your designs total power consumption using
power-driven synthesis and power-driven placement and routing.
f For more information about power-driven compilation flow and low-power design
guidelines, refer to the Power Optimization chapter in volume 2 of the Quartus II
Handbook.
f For more information about power optimization techniques available for Stratix III
devices, refer to AN 437: Power Optimization in Stratix III FPGAs. For more information
about power optimization techniques available for Stratix IV devices, refer to AN 514:
Power Optimization in Stratix IV FPGAs. For more information about power
optimization techniques available for Stratix V devices, refer to Reducing Power
Consumption and Increasing Bandwidth on 28-nm FPGAs white paper.
h Additionally, you can use the Quartus II PowerPlay suite of power analysis and
optimization tools to help you during the design process by delivering fast and
accurate estimations of power consumption. For more information about the
Quartus II PowerPlay suite of power analysis and optimization tools, refer to About
Power Estimation and Analysis in Quartus II Help.
Metastability
Metastability in PLD designs can be caused by the synchronization of asynchronous
signals. You can use the Quartus II software to analyze the mean time between
failures (MTBF) due to metastability, thus optimizing the design to improve the
metastability MTBF. A high metastability MTBF indicates a more robust design.
f For more information about how to ensure complete and accurate metastability
analysis, refer to the Managing Metastability With the Quartus II Software chapter in
volume 1 of the Quartus II Handbook.
h For more information about viewing metastability reports, refer to Viewing
Metastability Reports in Quartus II Help.
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Incremental Compilation
The incremental compilation feature in the Quartus II software allows you to partition
your design hierarchy, separately compile partitions, and reuse the results for
unchanged partitions. Incremental compilation flows require more up-front planning
than flat compilations, and generally require you to be more rigorous about following
good design practices than flat compilations.
f For more information about incremental compilation and floorplan assignments, refer
to the Best Practices for Incremental Compilation Partitions and Floorplan Assignments
chapter in volume 1 of the Quartus II Handbook.
h For more information about incremental compilation, refer to About Incremental
Compilation in Quartus II Help.
1317
Figure 139 shows the Quartus II software design flow with the Design Assistant.
Figure 139. Quartus II Design Flow with the Design Assistant
Design Files
Pre-Synthesis
Netlist
Design Assistant
Golden Rules (1)
Post-Synthesis
Netlist
Synthesis
(Logic Synthesis &
Technology Mapping)
Design Assistant
Fitter
Timing Analysis
Post-Fitting
Netlist
Custom
Rules (2)
The Design Assistant analyzes your design netlist at different stages of the
compilation flow and may yield different warnings or errors, even though the netlists
are functionally the same. Your pre-synthesis, post-synthesis, and post-fitting netlists
might be different due to optimizations performed by the Quartus II software. For
example, a warning message in a pre-synthesis netlist may be removed after the
netlist has been synthesized into a post-synthesis or post-fitting netlist.
The exact operation of the Design Assistant depends on when you run it:
When you run the Design Assistant after running a full compilation or fitting, the
Design Assistant performs a post-fitting analysis on the design.
When you run the Design Assistant after performing Analysis and Synthesis, the
Design Assistant performs post-synthesis analysis on the design.
When you start the Design Assistant after performing Analysis and Elaboration,
the Design Assistant performs a pre-synthesis analysis on the design. You can also
perform pre-synthesis analysis with the Design Assistant using the command-line.
You can use the -rtl option with the quartus_drc executable, as shown in the
following example:
quartus_drc <project_name> --rtl=on r
h For more information about Design Assistant settings, refer to About the Design
Assistant and Design Assistant Page (Settings Dialog Box) in Quartus II Help.
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Custom Rules
In addition to the existing design rules that the Design Assistant offers, you can also
create your own rules and specify your own reporting format in a text file (with any
file extension) with the XML format. You then specify the path to that file in the
Design Assistant settings page and run the Design Assistant for violation checking.
Refer to the following location to locate the file that contains the default rules for the
Design Assistant:
<Quartus II install path>\quartus\libraries\design-assistant\da_golden_rule.xml
h For more information about how to set the file path to your custom rules, refer to
Custom Rules Settings Dialog Box in Quartus II Help. For more information about the
basics of writing custom rules, the Design Assistant settings, and coding examples on
how to check for clock relationship and node relationship in a design, refer to Creating
Custom Design Assistant Rules in Quartus II Help. To specify the rules that you want
the Design Assistant to use when checking for violations, refer to Design Assistant Page
(Settings Dialog Box) in Quartus II Help.
1319
In Example 131, the possible SR latch structures are specified in the rule definition
section. Codes defined in the <AND></AND> block are tied together, meaning that each
statement in the block must be true for the block to be fulfilled (AND gate similarity).
In the <OR></OR> block, as long as one statement in the block is true, the block is
fulfilled (OR gate similarity). If no <AND></AND> or <OR></OR> blocks are specified, the
default is <AND></AND>.
The <FORBID></FORBID> section contains the undesirable condition for the design,
which in this case is the SR latch structures. If the condition is fulfilled, the Design
Assistant highlights a rule violation.
The following examples are the undesired conditions from Example 131 with their
equivalent block diagrams (Figure 1310 and Figure 1311):
<AND>
<NODE_RELATIONSHIP FROM_NAME="NODE_1" FROM_TYPE="NAND" TO_NAME="NODE_2"
TO_TYPE="NAND" />
<NODE_RELATIONSHIP FROM_NAME="NODE_2" FROM_TYPE="NAND" TO_NAME="NODE_1"
TO_TYPE="NAND" />
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</AND>
<AND>
<NODE_RELATIONSHIP FROM_NAME="NODE_1" FROM_TYPE="NOR" TO_NAME="NODE_2" TO_TYPE="NOR" />
<NODE_RELATIONSHIP FROM_NAME="NODE_2" FROM_TYPE="NOR" TO_NAME="NODE_1" TO_TYPE="NOR" />
</AND>
1321
There is no logic between the register output of the transmitting clock domain and
the cascaded registers in the receiving asynchronous clock domain
The codes differentiate the clock domains. ASYN means asynchronous, and !ASYN means
non-asynchronous. This notation is useful for describing nodes that are in different
clock domains. The following lines from Example 132 state that NODE_2 and NODE_3 are
in the same clock domain, but NODE_1 is not.
<NODE_RELATIONSHIP FROM_NAME="NODE_1" TO_NAME="NODE_2" TO_PORT="D_PORT"
CLOCK_RELATIONSHIP="ASYN" />
<NODE_RELATIONSHIP FROM_NAME="NODE_2" TO_NAME="NODE_3" TO_PORT="D_PORT"
CLOCK_RELATIONSHIP="!ASYN" />
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The next line of code states that NODE_2 and NODE_3 have a clock relationship of either
sequential edge or asynchronous.
<CLOCK_RELATIONSHIP NAME="SEQ_EDGE|ASYN" NODE_LIST="NODE_2, NODE_3" />
The <FORBID></FORBID> section contains the undesirable condition for the design,
which in this case is the undesired configuration of the synchronizer. If the condition
is fulfilled, the Design Assistant highlights a rule violation.
The following examples are the undesired conditions from Example 132 with their
equivalent block diagrams (Figure 1312 and Figure 1313):
Example 133.
<NODE_RELATIONSHIP FROM_NAME="NODE_1" TO_NAME="NODE_2" TO_PORT="D_PORT"
CLOCK_RELATIONSHIP="ASYN" />
<NODE_RELATIONSHIP FROM_NAME="NODE_2" TO_NAME="NODE_3" TO_PORT="D_PORT"
CLOCK_RELATIONSHIP="!ASYN" />
<NODE_RELATIONSHIP FROM_NAME="NODE_1" TO_NAME="NODE_2" TO_PORT="D_PORT"
REQUIRED_THROUGH="YES" THROUGH_TYPE="COMB" CLOCK_RELATIONSHIP="ASYN" />
Example 134.
<NODE_RELATIONSHIP FROM_NAME="NODE_1" TO_NAME="NODE_2" TO_PORT="D_PORT"
CLOCK_RELATIONSHIP="ASYN" />
<NODE_RELATIONSHIP FROM_NAME="NODE_2" TO_NAME="NODE_3" TO_PORT="D_PORT"
CLOCK_RELATIONSHIP="!ASYN" />
<CLOCK_RELATIONSHIP NAME="SEQ_EDGE|ASYN" NODE_LIST="NODE_2, NODE_3" />
1323
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1324
Reset Resources
ASIC designs may use local resets to avoid long routing delays. Take advantage of the
device-wide asynchronous reset pin available on most FPGAs to eliminate these
problems. This reset signal provides low-skew routing across the device.
The following are three types of resets used in synchronous circuits:
Synchronous Reset
Asynchronous Reset
Synchronous Reset
The synchronous reset ensures that the circuit is fully synchronous. You can easily
time the circuit with the Quartus II TimeQuest analyzer. Because clocks that are
synchronous to each other launch and latch the reset signal, the data arrival and data
required times are easily determined for proper slack analysis. The synchronous reset
is easier to use with cycle-based simulators.
There are two methods by which a reset signal can reach a register; either by being
gated in with the data input, as shown in Figure 1314, or by using an LAB-wide
control signal (synclr), as shown in Figure 1315. If you use the first method, you risk
adding an additional gate delay to the circuit to accommodate the reset signal, which
causes increased data arrival times and negatively impacts setup slack. The second
method relies on dedicated routing in the LAB to each register, but this is slower than
an asynchronous reset to the same register.
Figure 1314. Synchronous Reset
reset_n
data
AND2
DFF
inst1
PRN
Q
out
clock
CLRN
inst
1325
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0
labclk2
labclk1
labclkena0
labclkena1
labclr1
syncload
labclkena2
labclr0
synclr
Consider two types of synchronous resets when you examine the timing analysis of
synchronous resetsexternally synchronized resets and internally synchronized
resets. Externally synchronized resets are synchronized to the clock domain outside
the FPGA, and are not very common. A power-on asynchronous reset is dual-rank
synchronized externally to the system clock and then brought into the FPGA. Inside
the FPGA, gate this reset with the data input to the registers to implement a
synchronous reset.
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PRN
Q
PRN
Q
FPGA
clock
reset_n
CLRN
data_a
CLRN
clock
INPUT
VCC
INPUT
VCC
AND2
lc 1
OUTPUT
out_a
INPUT
VCC
AND2
data_b
DFF
PRN
D
Q
INPUT
VCC
lc 2
CLRN
reg1
DFF
PRN
D
Q
OUTPUT
out_b
CLRN
reg2
Example 135 shows the Verilog equivalent of the schematic. When you use
synchronous resets, the reset signal is not put in the sensitivity list.
Example 135. Verilog Code for Externally Synchronized Reset
module sync_reset_ext (
input
clock,
input
reset_n,
input
data_a,
input
data_b,
output out_a,
output out_b
);
reg
reg1, reg2
assign
assign
out_a
out_b
= reg1;
= reg2;
//
sync_reset_ext
1327
Example 136 shows the constraints for the externally synchronous reset. Because the
external reset is synchronous, you only need to constrain the reset_n signal as a
normal input signal with set_input_delay constraint for -max and -min.
Example 136. SDC Constraints for Externally Synchronous Reset
# Input clock - 100 MHz
create_clock [get_ports {clock}] \
-name {clock} \
-period 10.0 \
-waveform {0.0 5.0}
# Input constraints on low-active reset
# and data
set_input_delay 7.0 \
-max \
-clock [get_clocks {clock}] \
[get_ports {reset_n data_a data_b}]
set_input_delay 1.0 \
-min \
-clock [get_clocks {clock}] \
[get_ports {reset_n data_a data_b}]
More often, resets coming into the device are asynchronous, and must be
synchronized internally before being sent to the registers. Figure 1317 shows an
internally synchronized reset.
Figure 1317. Internally Synchronized Reset
DFF
reset_n
INPUT
VCC
DFF
PRN
Q
CLRN
reg3
data_a
INPUT
VCC
clock
INPUT
VCC
PRN
Q
CLRN
reg4
AND2
lc 1
AND2
data_b
INPUT
VCC
lc 2
DFF
PRN
D
Q
OUTPUT
out_a
CLRN
reg1
DFF
PRN
D
Q
OUTPUT
out_b
CLRN
reg2
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Altera Corporation
1328
Example 137 shows the Verilog equivalent of the schematic. Only the clock edge is in
the sensitivity list for a synchronous reset.
Example 137. Verilog Code for Internally Synchronous Reset
module sync_reset (
input
clock,
input
reset_n,
input
data_a,
input
data_b,
output out_a,
output out_b
);
reg
reg
reg1, reg2
reg3, reg4
assign
assign
assign
out_a
out_b
rst_n
= reg1;
= reg2;
= reg4;
always @ (posedge
begin
if (!rst_n)
begin
reg1
reg2
end
else
begin
reg1
reg2
end
end
clock)
<= 1bo;
<= 1b0;
<= data_a;
<= data_b;
1329
The SDC constraints are similar to the external synchronous reset, except that the
input reset cannot be constrained because it is asynchronous and should be cut with a
set_false_path statement (as shown in Example 138) to avoid these being
considered as unconstrained paths.
Example 138. SDC Constraints for Internally Synchronized Reset
# Input clock - 100 MHz
create_clock [get_ports {clock}] \
-name {clock} \
-period 10.0 \
-waveform {0.0 5.0}
# Input constraints on data
set_input_delay 7.0 \
-max \
-clock [get_clocks {clock}] \
[get_ports {data_a data_b}]
set_input_delay 1.0 \
-min \
-clock [get_clocks {clock}] \
[get_ports {data_a data_b}]
# Cut the asynchronous reset input
set_false_path \
-from [get_ports {reset_n}] \
-to [all_registers]
An issue with synchronous resets is their behavior with respect to short pulses (less
than a period) on the asynchronous input to the synchronizer flipflops. This can be a
disadvantage because the asynchronous reset requires a pulse width of at least one
period wide to guarantee that it is captured by the first flipflop. However, this can
also be viewed as an advantage in that this circuit increases noise immunity. Spurious
pulses on the asynchronous input have a lower chance of being captured by the first
flipflop, so the pulses do not trigger a synchronous reset. In some cases, you might
want to increase the noise immunity further and reject any asynchronous input reset
that is less than n periods wide to debounce an asynchronous input reset.
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1330
Figure 1318 shows the necessary modifications that you should make to the
internally synchronized reset.
Figure 1318. Internally Synchronized Reset with Pulse Extender
n Pulse Extender Flip-Flops
Synchronizer Flip-Flops
DFF
reset_n
INPUT
VCC
DFF
PRN
Q
CLRN
reg3
data_a
DFF
PRN
Q
CLRN
reg4
BNAND2
DFF
PRN
Q
CLRN
reg5
PRN
Q
CLRN
regn
lc 3
AND2
INPUT
VCC
lc 1
clock
OUTPUT
out_a
OUTPUT
out_b
INPUT
VCC
AND2
data_b
DFF
PRN
D
Q
INPUT
VCC
lc 2
CLRN
reg1
DFF
PRN
D
Q
CLRN
reg2
Many designs have more than one clock signal. In these cases, use a separate reset
synchronization circuit for each clock domain in the design. When you create
synchronizers for PLL output clocks, these clock domains are not reset until you lock
the PLL and the PLL output clocks are stable. If you use the reset to the PLL, this reset
does not have to be synchronous with the input clock of the PLL. You can use an
asynchronous reset for this. Using a reset to the PLL further delays the assertion of a
synchronous reset to the PLL output clock domains when using internally
synchronized resets.
Asynchronous Reset
Asynchronous resets are the most common form of reset in circuit designs, as well as
the easiest to implement. Typically, you can insert the asynchronous reset into the
device, turn on the global buffer, and connect to the asynchronous reset pin of every
register in the device. This method is only advantageous under certain
circumstancesyou do not need to always reset the register. Unlike the synchronous
reset, the asynchronous reset is not inserted in the data path, and does not negatively
impact the data arrival times between registers. Reset takes effect immediately, and as
soon as the registers receive the reset pulse, the registers are reset. The asynchronous
reset is not dependent on the clock.
However, when the reset is deasserted and does not pass the recovery (tSU) or
removal (tH) time check (the TimeQuest analyzer recovery and removal analysis
checks both times), the edge is said to have fallen into the metastability zone.
Additional time is required to determine the correct state, and the delay can cause the
setup time to fail to register downstream, leading to system failure. To avoid this, add
a few follower registers after the register with the asynchronous reset and use the
output of these registers in the design. Use the follower registers to synchronize the
1331
data to the clock to remove the metastability issues. You should place these registers
close to each other in the device to keep the routing delays to a minimum, which
decreases data arrival times and increases MTBF. Ensure that these follower registers
themselves are not reset, but are initialized over a period of several clock cycles by
flushing out their current or initial state.
Figure 1319 shows a schematic example of this circuit.
Figure 1319. Asynchronous Reset with Follower Registers
DFF
DFF
data_a
PRN
D
Q
PRN
D
Q
INPUT
VCC
CLRN
CLRN
reg1
reset_n
INPUT
VCC
clock
INPUT
VCC
reg2
DFF
D
PRN
Q
OUTPUT
out_a
CLRN
reg3
Example 139 shows the equivalent Verilog code. The active edge of the reset is now
in the sensitivity list for the procedural block, which infers a clock enable on the
follower registers with the inverse of the reset signal tied to the clock enable. The
follower registers should be in a separate procedural block as shown using nonblocking assignments.
Example 139. Verilog Code of Asynchronous Reset with Follower Registers
module async_reset (
input
clock,
input
reset_n,
input
data_a,
output
out_a,
);
reg
assign
out_a
= reg3;
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Altera Corporation
1332
The asynchronous reset is susceptible to noise, and a noisy asynchronous reset can
cause a spurious reset. You must ensure that the asynchronous reset is debounced and
filtered. You can easily enter into a reset asynchronously, but releasing a reset
asynchronously can lead to potential problems (also referred to as reset removal)
with metastability, including the hazards of unwanted situations with synchronous
circuits involving feedback.
1333
Figure 1320 shows a method for implementing the synchronized asynchronous reset.
You should use synchronizer registers in a similar manner as synchronous resets.
However, the asynchronous reset input is gated directly to the CLRN pin of the
synchronizer registers and immediately asserts the resulting reset. When the reset is
deasserted, logic 1 is clocked through the synchronizers to synchronously deassert
the resulting reset.
Figure 1320. Schematic of Synchronized Asynchronous Reset
VCC
DFF
PRN
D
Q
CLRN
reg3
DFF
D
PRN
Q
CLRN
reg4
DFF
data_a
clock
INPUT
VCC
INPUT
VCC
PRN
Q
OUTPUT
out_a
CLRN
reset_n
INPUT
VCC
reg1
DFF
data_b
INPUT
VCC
PRN
Q
OUTPUT
out_b
CLRN
reg2
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1334
Example 1311 shows the equivalent Verilog code. Use the active edge of the reset in
the sensitivity list for the blocks in Figure 1320.
Example 1311. Verilog Code for Synchronized Asynchronous Reset
module sync_async_reset (
input
clock,
input
reset_n,
input
data_a,
input
data_b,
output
out_a,
output
out_b
);
reg
reg
reg1, reg2;
reg3, reg4;
assign
assign
assign
out_a
out_b
rst_n
= reg1;
= reg2;
= reg4;
// sync_async_reset
To minimize the metastability effect between the two synchronization registers, and to
increase the MTBF, the registers should be located as close as possible in the device to
minimize routing delay. If possible, locate the registers in the same logic array block
(LAB). The input reset signal (reset_n) must be excluded with a set_false_path
command, so the reset that comes from the synchronization register (rst_n) can be
timed in the TimeQuest analyzer with recovery and removal Analysis.
1335
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1336
You should check how you specify the memory in your HDL code when you use
read-during-write behavior. The HDL code that describes the read returns either the
old data stored at the memory location, or the new data being written to the memory
location.
In some cases, when the device architecture cannot implement the memory behavior
described in your HDL code, the memory block is not mapped to the dedicated RAM
blocks, or the memory block is implemented using extra logic in addition to the
dedicated RAM block. Implement the read-during-write behavior using single-port
RAM in Arria GX devices and the Cyclone and Stratix series of devices to avoid this
extra logic implementation.
f For Verilog HDL and VHDL examples and guidelines for inferring RAM functions
that match the dedicated memory architecture in Altera devices, refer to the
Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook.
In many synthesis tools, you can specify that the read-during-write behavior is not
important to your design; if, for example, you never read and write from the same
address in the same clock cycle. For Quartus II integrated synthesis, add the synthesis
attribute ramstyle=no_rw_check to allow the software to choose the
read-during-write behavior of a RAM, rather than using the read-during-write
behavior specified in your HDL code. Using this type of attribute prevents the
synthesis tool from using extra logic to implement the memory block and, in some
cases, can allow memory inference when it would otherwise be impossible.
f For details about using the ramstyle attribute, refer to the Quartus II Integrated
Synthesis chapter in volume 1 of the Quartus II Handbook. For information about the
synthesis attributes in other synthesis tools, refer to your synthesis tool
documentation, or to the appropriate chapter in the Synthesis section in volume 1 of
the Quartus II Handbook.
Conclusion
Following the design practices described in this chapter can help you to consistently
meet your design goals. Asynchronous design techniques may result in incomplete
timing analysis, may cause glitches on data signals, and may rely on propagation
delays in a device leading to race conditions and unpredictable results. Taking
advantage of the architectural features in your FPGA device can also improve the
quality of your results.
Version
May 2013
13.0.0
Changes
June 2012
12.0.0
November 2011
11.0.1
Template update.
1337
Version
May 2011
11.0.0
December 2010
July 2010
10.1.0
Changes
Added information to Reset Resources on page 1324.
Title changed from Design Recommendations for Altera Devices and the Quartus II
Design Assistant.
Removed duplicated content and added references to Quartus II Help for Custom
Rules on page 915.
Removed duplicated content and added references to Quartus II Help for Design
Assistant settings, Design Assistant rules, Enabling and Disabling Design Assistant
Rules, and Viewing Design Assistant reports.
10.0.0
November 2009
9.1.0
March 2009
9.0.0
No change to content.
Updated Figure 59 on page 513; added custom rules file to the flow
November 2008
May 2008
8.1.0
8.0.0
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
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Altera Corporation
1338
Inferring Multiplier and DSP Functions from HDL Code on page 145
f For additional guidelines about structuring your design, refer to the Design
Recommendations for Altera Devices and the Quartus II Design Assistant chapter in
volume 1 of the Quartus II Handbook. For additional handcrafted techniques you can
use to optimize design blocks for the adaptive logic modules (ALMs) in many Altera
devices, including a collection of circuit building blocks and related discussions, refer
to the Advanced Synthesis Cookbook.
f The Altera website also provides design examples for other types of functions and to
target specific applications. For more information about design examples, refer to the
Design Examples page and the Reference Designs page on the Altera website.
For style recommendations, options, or HDL attributes specific to your synthesis tool
(including Quartus II integrated synthesis and other EDA tools), refer to the tool
vendors documentation or the appropriate chapter in the Synthesis section in
volume 1 of the Quartus II Handbook.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
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142
143
h You can use any of the standard features of the Quartus II Text Editor to modify the
HDL design or save the template as an HDL file to edit in your preferred text editor.
For more information about inserting a template with the Quartus II Text Editor, refer
to About the Quartus II Text Editor in Quartus II Help.
June 2012
Creating a Netlist File for Other Synthesis ToolsYou can optionally create a
netlist file instead of a wrapper file.
Altera Corporation
144
Description
<output file>.v|.vhd|.tdf
<output file>.inc
<output file>.cmp
<output file>.bsf
<output file>_inst.v|.vhd|.tdf
HDL Instantiation Template for the language of the variation fileSample instantiation of
the Verilog HDL module, VHDL entity, or AHDL subdesign.
<output file>_bb.v
Black box Verilog HDL Module DeclarationHollow-body module declaration that can
be used in Verilog HDL designs to specify port directions when instantiating the
megafunction as a black box in third-party synthesis tools.
<output file>_syn.v
145
Because your synthesis tool may call the Quartus II software in the background to
generate this netlist, turning on the Generate Netlist option might be optional.
f For information about support for timing and resource estimation netlists in your
synthesis tool, refer to the tool vendors documentation or the appropriate chapter in
the Synthesis section in volume 1 of the Quartus II Handbook.
Altera recommends that you use the MegaWizard Plug-In Manager for complex
megafunctions such as PLLs, transceivers, and LVDS drivers. For details about using
the MegaWizard Plug-In Manager, refer to Instantiating Megafunctions Using the
MegaWizard Plug-In Manager on page 144.
f For synthesis tool features and options, refer to your synthesis tool documentation or
the appropriate chapter in the Synthesis section in volume 1 of the Quartus II Handbook.
f For more design examples involving advanced multiply functions and complex DSP
functions, refer to the DSP Design Examples page on the Altera website.
June 2012
Altera Corporation
146
Example 141 and Example 142 show Verilog HDL code examples, and
Example 143 and Example 144 show VHDL code examples, for unsigned and
signed multipliers that synthesis tools can infer as a megafunction or DSP block
atoms. Each example fits into one DSP block element. In addition, when register
packing occurs, no extra logic cells for registers are required.
1
The signed declaration in Verilog HDL is a feature of the Verilog 2001 Standard.
Example 141. Verilog HDL Unsigned Multiplier
module unsigned_mult (out, a, b);
output [15:0] out;
input [7:0] a;
input [7:0] b;
assign out = a * b;
endmodule
Example 142. Verilog HDL Signed Multiplier with Input and Output Registers (Pipelining = 2)
module signed_mult (out, clk, a, b);
output [15:0] out;
input clk;
input signed [7:0] a;
input signed [7:0] b;
reg signed [7:0] a_reg;
reg signed [7:0] b_reg;
reg signed [15:0] out;
wire signed [15:0] mult_out;
assign mult_out = a_reg * b_reg;
always @ (posedge clk)
begin
a_reg <= a;
b_reg <= b;
out <= mult_out;
end
endmodule
147
Example 143. VHDL Unsigned Multiplier with Input and Output Registers (Pipelining = 2)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY unsigned_mult IS
PORT (
a: IN UNSIGNED (7 DOWNTO 0);
b: IN UNSIGNED (7 DOWNTO 0);
clk: IN STD_LOGIC;
aclr: IN STD_LOGIC;
result: OUT UNSIGNED (15 DOWNTO 0)
);
END unsigned_mult;
ARCHITECTURE rtl OF unsigned_mult IS
SIGNAL a_reg, b_reg: UNSIGNED (7 DOWNTO 0);
BEGIN
PROCESS (clk, aclr)
BEGIN
IF (aclr ='1') THEN
a_reg <= (OTHERS => '0');
b_reg <= (OTHERS => '0');
result <= (OTHERS => '0');
ELSIF (clk'event AND clk = '1') THEN
a_reg <= a;
b_reg <= b;
result <= a_reg * b_reg;
END IF;
END PROCESS;
END rtl;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY signed_mult IS
PORT (
a: IN SIGNED (7 DOWNTO 0);
b: IN SIGNED (7 DOWNTO 0);
result: OUT SIGNED (15 DOWNTO 0)
);
END signed_mult;
ARCHITECTURE rtl OF signed_mult IS
BEGIN
result <= a * b;
END rtl;
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148
f For details about advanced DSP block features, refer to the appropriate device
handbook. For more design examples of DSP functions and inferring advanced
features in the multiply-add and multiply-accumulate circuitry, refer to the DSP
Design Examples page and AN639: Inferring Stratix V DSP Blocks for FIR Filtering
Applications on Alteras website.
The Verilog HDL and VHDL code samples in Example 145 through Example 148 on
pages 149 through 1412 infer multiply-accumulators and multiply-adders with
input, output, and pipeline registers, as well as an optional asynchronous clear signal.
Using the three sets of registers provides the best performance through the function,
with a latency of three. You can remove the registers in your design to reduce the
latency.
149
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1410
1411
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1412
0);
0);
0);
0);
DOWNTO 0)
1413
f For synthesis tool features and options, refer to your synthesis tool documentation or
the appropriate chapter in the Synthesis section in volume 1 of the Quartus II Handbook.
Alteras dedicated memory architecture offers a number of advanced features that can
be easily targeted using the MegaWizard Plug-In Manager, as described in
Instantiating Altera Megafunctions in HDL Code on page 143. The coding
recommendations in the following sections provide portable examples of generic
HDL code that infer the appropriate megafunction. However, if you want to use some
of the advanced memory features in Altera devices, consider using the megafunction
directly so that you can control the ports and parameters easily.
You can also use the Quartus II templates provided in the Quartus II software as a
starting point. For more information, refer to Inserting a Template with the
Quartus II Text Editor on page 142. Table 142 lists the full designs for RAMs and
ROMs available in the Quartus II templates.
f Most of these designs can also be found on the Design Examples page on the Altera
website.
Table 142. RAM and ROM Full Designs from the Quartus II Templates (Part 1 of 2)
Language
VHDL
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1414
Table 142. RAM and ROM Full Designs from the Quartus II Templates (Part 2 of 2)
Language
Verilog HDL
Single-Port RAM
Single-Port RAM with Initial Contents
Simple Dual-Port RAM (single clock)
Simple Dual-Port RAM (dual clock)
True Dual-Port RAM (single clock)
True Dual-Port RAM (dual clock)
Single-Port ROM
Dual-Port ROM
System Verilog
If your design contains a RAM block that your synthesis tool does not recognize and
infer, the design might require a large amount of system memory that can potentially
cause compilation problems.
When you use a formal verification flow, Altera recommends that you create RAM
blocks in separate entities or modules that contain only the RAM logic. In certain
formal verification flows, for example, when using Quartus II integrated synthesis,
the entity or module containing the inferred RAM is put into a black box
automatically because formal verification tools do not support RAM blocks. The
Quartus II software issues a warning message when this situation occurs. If the entity
or module contains any additional logic outside the RAM block, this logic cannot be
verified because it also must be treated as a black box for formal verification.
The following sections present several guidelines for inferring RAM functions that
match the dedicated memory architecture in Altera devices, and then provide
recommended HDL code for different types of memory logic.
1415
Memory read occurs in a Verilog always block with a clock signal or a VHDL
clocked process. The recommended coding style for synchronous memories is to
create your design with a registered read output.
Memory read occurs outside a clocked block, but there is a synchronous read
address (that is, the address used in the read statement is registered). This type of
logic is not always inferred as a memory block, or may require external bypass
logic, depending on the target device architecture.
The synchronous memory structures in Altera devices can differ from the structures
in other vendors devices. For best results, match your design to the target device
architecture.
Later sections provide coding recommendations for various memory types. All of
these examples are synchronous to ensure that they can be directly mapped into the
dedicated memory architecture available in Altera FPGAs.
f For additional information about the dedicated memory blocks in your specific
device, refer to the appropriate Altera device family data sheet on the Altera website
at www.altera.com.
June 2012
Altera Corporation
1416
Example 149 shows an example of undesirable code where there is a reset signal that
clears part of the RAM contents. Avoid this coding style because it is not supported in
Altera memories.
Example 149. Verilog RAM with Reset Signal that Clears RAM Contents: Not Supported in
Device Architecture
module clear_ram
(
input clock, reset, we,
input [7:0] data_in,
input [4:0] address,
output reg [7:0] data_out
);
reg [7:0] mem [0:31];
integer i;
always @ (posedge clock or posedge reset)
begin
if (reset == 1'b1)
mem[address] <= 0;
else if (we == 1'b1)
mem[address] <= data_in;
data_out <= mem[address];
end
endmodule
1417
Example 1410 shows an example of undesirable code where the reset signal affects
the RAM, although the effect may not be intended. Avoid this coding style because it
is not supported in Altera memories.
Example 1410. Verilog RAM with Reset Signal that Affects RAM: Not Supported in Device
Architecture
module bad_reset
(
input clock,
input reset,
input we,
input [7:0] data_in,
input [4:0] address,
output reg [7:0] data_out,
input d,
output reg q
);
reg [7:0] mem [0:31];
integer i;
always @ (posedge clock or posedge reset)
begin
if (reset == 1'b1)
q <= 0;
else
begin
if (we == 1'b1)
mem[address] <= data_in;
data_out <= mem[address];
q <= d;
end
end
endmodule
In addition to reset signals, other control logic can prevent memory logic from being
inferred as a memory block. For example, you cannot use a clock enable on the read
address registers in Stratix devices because doing so affects the output latch of the
RAM, and therefore the synthesized result in the device RAM architecture would not
match the HDL description. You can use the address stall feature as a read address
clock enable in Stratix II, Cyclone II, Arria GX, and other newer devices to avoid
this limitation. Check the documentation for your device architecture to ensure that
your code matches the hardware available in the device.
June 2012
Altera Corporation
1418
Synthesis tools map an HDL design into the target device architecture, with the goal
of maintaining the functionality described in your source code. Therefore, if your
source code specifies unsupported read-during-write behavior for the device RAM
blocks, the software must implement the logic outside the RAM hardware in regular
logic cells.
One common problem occurs when there is a continuous read in the HDL code, as in
the following examples. You should avoid using these coding styles:
//Verilog HDL concurrent signal assignment
assign q = ram[raddr_reg];
-- VHDL concurrent signal assignment
q <= ram(raddr_reg);
When a write operation occurs, this type of HDL implies that the read should
immediately reflect the new data at the address, independent of the read clock.
However, that is not the behavior of synchronous memory blocks. In the device
architecture, the new data is not available until the next edge of the read clock.
Therefore, if the synthesis tool mapped the logic directly to a synchronous memory
block, the device functionality and gate-level simulation results would not match the
HDL description or functional simulation results. If the write clock and read clock are
the same, the synthesis tool can infer memory blocks and add extra bypass logic so
that the device behavior matches the HDL behavior. If the write and read clocks are
different, the synthesis tool cannot reliably add bypass logic, so the logic is
implemented in regular logic cells instead of dedicated RAM blocks. The examples in
the following sections discuss some of these differences for read-during-write
conditions.
In addition, the MLAB feature in certain device logic array blocks (LABs) does not
easily support old data or new data behavior for a read-during-write in the dedicated
device architecture. Implementing the extra logic to support this behavior
significantly reduces timing performance through the memory.
1
For best performance in MLAB memories, your design should not depend on the read
data during a write operation.
In many synthesis tools, you can specify that the read-during-write behavior is not
important to your design; for example, if you never read from the same address to
which you write in the same clock cycle. For Quartus II integrated synthesis, add the
synthesis attribute ramstyle set to "no_rw_check" to allow the software to choose the
read-during-write behavior of a RAM, rather than use the behavior specified by your
HDL code. In some cases, this attribute prevents the synthesis tool from using extra
logic to implement the memory block, or can allow memory inference when it would
otherwise be impossible.
Synchronous RAM blocks require a synchronous read, so Quartus II integrated
synthesis packs either data output registers or read address registers into the RAM
block. When the read address registers are packed into the RAM block, the read
address signals connected to the RAM block contain the next value of the read
address signals indexing the HDL variable, which impacts which clock cycle the read
and the write occur, and changes the read-during-write conditions. Therefore, bypass
logic may still be added to the design to preserve the read-during-write behavior,
even if the "no_rw_check" attribute is set.
1419
f For more information about attribute syntax, the no_rw_check attribute value, or
specific options for your synthesis tool, refer to your synthesis tool documentation or
the appropriate chapter in the Synthesis section in volume 1 of the Quartus II Handbook.
The next section describes how you control the logic implementation in the Altera
device, and the following sections provide coding recommendations for various
memory types. Each example describes the read-during-write behavior and addresses
the support for the memory type in Altera devices.
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1420
The read-during-write behavior in these examples is to read the old data at the
memory address. Refer to Check Read-During-Write Behavior on page 1417 for
details. Altera recommends that you use the Old Data Read-During-Write coding
style for most RAM blocks as long as your design does not require the RAM locations
new value when you perform a simultaneous read and write to that RAM location.
For best performance in MLAB memories, use the appropriate attribute so that your
design does not depend on the read data during a write operation.
If you require that the read-during-write results in new data, refer to Single-Clock
Synchronous RAM with New Data Read-During-Write Behavior on page 1421.
The simple dual-port RAM code samples in Example 1411 and Example 1412 map
directly into Altera synchronous memory.
Single-port versions of memory blocks (that is, using the same read address and write
address signals) can allow better RAM utilization than dual-port memory blocks,
depending on the device family.
Example 1411. Verilog HDL Single-Clock Simple Dual-Port Synchronous RAM with Old Data
Read-During-Write Behavior
module single_clk_ram(
output reg [7:0] q,
input [7:0] d,
input [6:0] write_address, read_address,
input we, clk
);
reg [7:0] mem [127:0];
always @ (posedge clk) begin
if (we)
mem[write_address] <= d;
q <= mem[read_address]; // q doesn't get d in this clock cycle
end
endmodule
1421
Example 1412. VHDL Single-Clock Simple Dual-Port Synchronous RAM with Old Data
Read-During-Write Behavior
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY single_clock_ram IS
PORT (
clock: IN STD_LOGIC;
data: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
write_address: IN INTEGER RANGE 0 to 31;
read_address: IN INTEGER RANGE 0 to 31;
we: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END single_clock_ram;
ARCHITECTURE rtl OF single_clock_ram IS
TYPE MEM IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL ram_block: MEM;
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (we = '1') THEN
ram_block(write_address) <= data;
END IF;
q <= ram_block(read_address);
-- VHDL semantics imply that q doesn't get data
-- in this clock cycle
END IF;
END PROCESS;
END rtl;
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Altera Corporation
1422
Example 1413. Verilog HDL Single-Clock Simple Dual-Port Synchronous RAM with New Data
Read-During-Write Behavior
module single_clock_wr_ram(
output reg [7:0] q,
input [7:0] d,
input [6:0] write_address, read_address,
input we, clk
);
reg [7:0] mem [127:0];
always @ (posedge clk) begin
if (we)
mem[write_address] = d;
q = mem[read_address]; // q does get d in this clock cycle if
// we is high
end
endmodule
Example 1413 is similar to Example 1411, but Example 1413 uses a blocking
assignment for the write so that the data is assigned immediately.
An alternative way to create a single-clock RAM is to use an assign statement to read
the address of mem to create the output q, as shown in the following coding style
example. By itself, the code describes new data read-during-write behavior. However,
if the RAM output feeds a register in another hierarchy, a read-during-write results in
the old data. Synthesis tools may not infer a RAM block if the tool cannot determine
which behavior is described, such as when the memory feeds a hard hierarchical
partition boundary. For this reason, avoid using this alternate type of coding style:
reg [7:0] mem [127:0];
reg [6:0] read_address_reg;
always @ (posedge clk) begin
if (we)
mem[write_address] <= d;
read_address_reg <= read_address;
end
assign q = mem[read_address_reg];
1423
The VHDL sample in Example 1414 uses a concurrent signal assignment to read
from the RAM. By itself, this example describes new data read-during-write behavior.
However, if the RAM output feeds a register in another hierarchy, a read-during-write
results in the old data. Synthesis tools may not infer a RAM block if the tool cannot
determine which behavior is described, such as when the memory feeds a hard
hierarchical partition boundary.
Example 1414. VHDL Single-Clock Simple Dual-Port Synchronous RAM with New Data
Read-During-Write Behavior
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY single_clock_rw_ram IS
PORT (
clock: IN STD_LOGIC;
data: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
write_address: IN INTEGER RANGE 0 to 31;
read_address: IN INTEGER RANGE 0 to 31;
we: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END single_clock_rw_ram;
ARCHITECTURE rtl OF single_clock_rw_ram IS
TYPE MEM IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL ram_block: MEM;
SIGNAL read_address_reg: INTEGER RANGE 0 to 31;
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (we = '1') THEN
ram_block(write_address) <= data;
END IF;
read_address_reg <= read_address;
END IF;
END PROCESS;
q <= ram_block(read_address_reg);
END rtl;
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1424
The code samples in Example 1415 and Example 1416 show Verilog HDL and
VHDL code that infers dual-clock synchronous RAM. The exact behavior depends on
the relationship between the clocks.
Example 1415. Verilog HDL Simple Dual-Port, Dual-Clock Synchronous RAM
module dual_clock_ram(
output reg [7:0] q,
input [7:0] d,
input [6:0] write_address, read_address,
input we, clk1, clk2
);
reg [6:0] read_address_reg;
reg [7:0] mem [127:0];
always @ (posedge clk1)
begin
if (we)
mem[write_address] <= d;
end
always @ (posedge clk2) begin
q <= mem[read_address_reg];
read_address_reg <= read_address;
end
endmodule
1425
Read new dataThis mode matches the behavior of synchronous memory blocks.
Read old dataThis mode is supported only in device families that support
M144, M9k, and MLAB memory blocks.
When a read and write operation occurs on different ports for the same address (also
known as mixed port), the read operation may behave as follows:
Read dont careThis behavior is supported on different ports in simple dualport mode by synchronous memory blocks for all device families except Arria,
Arria GX, Cyclone, Cyclone II, HardCopy, HardCopy II, MAX, Stratix, and
Stratix II device families.
The Verilog HDL single-clock code sample in Example 1417 maps directly into
Altera synchronous memory. When a read and write operation occurs on the same
port for the same address, the new data being written to the memory is read. When a
read and write operation occurs on different ports for the same address, the old data
in the memory is read. Simultaneous writes to the same location on both ports results
in indeterminate behavior.
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1426
A dual-clock version of this design describes the same behavior, but the memory in
the target device will have undefined mixed port read-during-write behavior because
it depends on the relationship between the clocks.
Example 1417. Verilog HDL True Dual-Port RAM with Single Clock
module true_dual_port_ram_single_clock
(
input [(DATA_WIDTH-1):0] data_a, data_b,
input [(ADDR_WIDTH-1):0] addr_a, addr_b,
input we_a, we_b, clk,
output reg [(DATA_WIDTH-1):0] q_a, q_b
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 6;
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @ (posedge clk)
begin // Port A
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
q_a <= ram[addr_a];
end
always @ (posedge clk)
begin // Port b
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
else
q_b <= ram[addr_b];
end
endmodule
If you use the following Verilog HDL read statements instead of the if-else
statements in Example 1417, the HDL code specifies that the read results in old data
when a read operation and write operation occurs at the same time for the same
address on the same port or mixed ports. This mode is supported only in device
families that support M144, M9k, and MLAB memory blocks.
always @ (posedge clk)
begin // Port A
if (we_a)
ram[addr_a] <= data_a;
q_a <= ram[addr_a];
end
always @ (posedge clk)
begin // Port B
1427
if (we_b)
ram[addr_b] <= data_b;
q_b <= ram[addr_b];
end
The VHDL single-clock code sample in Example 1418 maps directly into Altera
synchronous memory. When a read and write operation occurs on the same port for
the same address, the new data being written to the memory is read. When a read and
write operation occurs on different ports for the same address, the old data in the
memory is read. Simultaneous write operations to the same location on both ports
results in indeterminate behavior.
A dual-clock version of this design describes the same behavior, but the memory in
the target device will have undefined mixed port read-during-write behavior because
it depends on the relationship between the clocks.
Example 1418. VHDL True Dual-Port RAM with Single Clock (Part 1 of 2)
library ieee;
use ieee.std_logic_1164.all;
entity true_dual_port_ram_single_clock is
generic (
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
port (
clk : in std_logic;
addr_a: in natural range 0 to 2**ADDR_WIDTH - 1;
addr_b: in natural range 0 to 2**ADDR_WIDTH - 1;
data_a: in std_logic_vector((DATA_WIDTH-1) downto 0);
data_b: in std_logic_vector((DATA_WIDTH-1) downto 0);
we_a: in std_logic := '1';
we_b: in std_logic := '1';
q_a : out std_logic_vector((DATA_WIDTH -1) downto 0);
q_b : out std_logic_vector((DATA_WIDTH -1) downto 0)
);
end true_dual_port_ram_single_clock;
architecture rtl of true_dual_port_ram_single_clock is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
type memory_t is array((2**ADDR_WIDTH - 1) downto 0) of word_t;
-- Declare the RAM signal.
shared variable ram : memory_t;
June 2012
Altera Corporation
1428
Example 1419. VHDL True Dual-Port RAM with Single Clock (Part 2 of 2)
begin
process(clk)
begin
if(rising_edge(clk)) then -- Port A
if(we_a = '1') then
ram(addr_a) <= data_a;
-- Read-during-write on the same port returns NEW data
q_a <= data_a;
else
-- Read-during-write on the mixed port returns OLD data
q_a <= ram(addr_a);
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then -- Port B
if(we_b = '1') then
ram(addr_b) <= data_b;
-- Read-during-write on the same port returns NEW data
q_b <= data_b;
else
-- Read-during-write on the mixed port returns OLD data
q_b <= ram(addr_b);
end if;
end if;
end process;
end rtl;
1429
Refer to the Quartus II Templates for parameterized examples that you can use for
supported combinations of read and write widths, and true dual port RAM examples
with two read ports and two write ports for mixed-width writes and reads.
Example 1420. SystemVerilog Mixed-Width RAM with Read Width Smaller than Write Width
module mixed_width_ram
// 256x32 write and 1024x8 read
(
input [7:0] waddr,
input [31:0] wdata,
input we, clk,
input [9:0] raddr,
output [7:0] q
);
logic [3:0][7:0] ram[0:255];
always_ff@(posedge clk)
begin
if(we) ram[waddr] <= wdata;
q <= ram[raddr / 4][raddr % 4];
end
endmodule : mixed_width_ram
Example 1421. SystemVerilog Mixed-Width RAM with Read Width Larger than Write Width
module mixed_width_ram
// 1024x8 write and 256x32 read
(
input [9:0] waddr,
input [31:0] wdata,
input we, clk,
input [7:0] raddr,
output [9:0] q
);
logic [3:0][7:0] ram[0:255];
always_ff@(posedge clk)
begin
if(we) ram[waddr / 4][waddr % 4] <= wdata;
q <= ram[raddr];
end
endmodule : mixed_width_ram
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1430
Example 1422. VHDL Mixed-Width RAM with Read Width Smaller than Write Width
library ieee;
use ieee.std_logic_1164.all;
package ram_types is
type word_t is array (0 to 3) of std_logic_vector(7 downto 0);
type ram_t is array (0 to 255) of word_t;
end ram_types;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ram_types.all;
entity mixed_width_ram is
port (
we, clk : in std_logic;
waddr
: in integer range 0 to 255;
wdata
: in word_t;
raddr
: in integer range 0 to 1023;
q
: out std_logic_vector(7 downto 0));
end mixed_width_ram;
architecture rtl of mixed_width_ram is
signal ram : ram_t;
begin -- rtl
process(clk, we)
begin
if(rising_edge(clk)) then
if(we = '1') then
ram(waddr) <= wdata;
end if;
q <= ram(raddr / 4 )(raddr mod 4);
end if;
end process;
end rtl;
1431
Example 1423. VHDL Mixed-Width RAM with Read Width Larger than Write Width
library ieee;
use ieee.std_logic_1164.all;
package ram_types is
type word_t is array (0 to 3) of std_logic_vector(7 downto 0);
type ram_t is array (0 to 255) of word_t;
end ram_types;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ram_types.all;
entity mixed_width_ram is
port (
we, clk : in std_logic;
waddr
: in integer range 0 to 1023;
wdata
: in std_logic_vector(7 downto 0);
raddr
: in integer range 0 to 255;
q
: out word_t);
end mixed_width_ram;
architecture rtl of mixed_width_ram is
signal ram : ram_t;
begin -- rtl
process(clk, we)
begin
if(rising_edge(clk)) then
if(we = '1') then
ram(waddr / 4)(waddr mod 4) <= wdata;
end if;
q <= ram(raddr);
end if;
end process;
end rtl;
June 2012
Altera Corporation
1432
Refer to the Quartus II Templates for parameterized examples that you can use for
different address widths, and true dual port RAM examples with two read ports and
two write ports.
Example 1424. SystemVerilog Simple Dual-Port Synchronous RAM with Byte Enable
module byte_enabled_simple_dual_port_ram
(
input we, clk,
input [5:0] waddr, raddr, // address width = 6
input [3:0] be,
// 4 bytes per word
input [31:0] wdata, // byte width = 8, 4 bytes per word
output reg [31:0] q // byte width = 8, 4 bytes per word
);
// use a multi-dimensional packed array
//to model individual bytes within the word
logic [3:0][7:0] ram[0:63];// # words = 1 << address width
always_ff@(posedge clk)
begin
if(we) begin
if(be[0]) ram[waddr][0] <= wdata[7:0];
if(be[1]) ram[waddr][1] <= wdata[15:8];
if(be[2]) ram[waddr][2] <= wdata[23:16];
if(be[3]) ram[waddr][3] <= wdata[31:24];
end
q <= ram[raddr];
end
endmodule
1433
Example 1425. VHDL Simple Dual-Port Synchronous RAM with Byte Enable
library ieee;
use ieee.std_logic_1164.all;
library work;
entity byte_enabled_simple_dual_port_ram is
port (
we, clk : in std_logic;
waddr, raddr : in integer range 0 to 63
be
: in std_logic_vector (3 downto
wdata
: in std_logic_vector(31 downto
q
: out std_logic_vector(31 downto
end byte_enabled_simple_dual_port_ram;
;
0);
0);
0) );
-----
address width = 6
4 bytes per word
byte width = 8
byte width = 8
June 2012
Certain device memory types do not support initialized memory, such as the M-RAM
blocks in Stratix and Stratix II devices.
Altera Corporation
1434
There are slight power-up and initialization differences between dedicated RAM
blocks and the MLAB memory due to the continuous read of the MLAB. Altera
dedicated RAM block outputs always power-up to zero and are set to the initial value
on the first read. For example, if address 0 is pre-initialized to FF, the RAM block
powers up with the output at 0. A subsequent read after power-up from address 0
outputs the pre-initialized value of FF. Therefore, if a RAM is powered up and an
enable (read enable or clock enable) is held low, the power-up output of 0 is
maintained until the first valid read cycle. The MLAB is implemented using registers
that power-up to 0, but are initialized to their initial value immediately at power-up
or reset. Therefore, the initial value is seen, regardless of the enable status. The
Quartus II software maps inferred memory to MLABs when the HDL code specifies
an appropriate ramstyle attribute.
Quartus II integrated synthesis supports the ram_init_file synthesis attribute that
allows you to specify a Memory Initialization File (.mif) for an inferred RAM block.
f For information about the ram_init_file attribute, refer to the Quartus II Integrated
Synthesis chapter in volume 1 of the Quartus II Handbook. For information about
synthesis attributes in other synthesis tools, refer to the tool vendors documentation.
In Verilog HDL, you can use an initial block to initialize the contents of an inferred
memory. Quartus II integrated synthesis automatically converts the initial block into a
.mif file for the inferred RAM. Example 1426 shows Verilog HDL code that infers a
simple dual-port RAM block and corresponding .mif file.
Example 1426. Verilog HDL RAM with Initialized Contents
module ram_with_init(
output reg [7:0] q,
input [7:0] d,
input [4:0] write_address, read_address,
input we, clk
);
reg [7:0] mem [0:31];
integer i;
initial begin
for (i = 0; i < 32; i = i + 1)
mem[i] = i[7:0];
end
always @ (posedge clk) begin
if (we)
mem[write_address] <= d;
q <= mem[read_address];
end
endmodule
Quartus II integrated synthesis and other synthesis tools also support the $readmemb
and $readmemh commands so that RAM initialization and ROM initialization work
identically in synthesis and simulation. Example 1427 shows an initial block that
initializes an inferred RAM block using the $readmemb command.
1435
f Refer to the Verilog Language Reference Manual (LRM) 1364-2001 Section 17.2.8 or the
example in the Templates for the Quartus II software for details about the format of
the ram.txt file.
Example 1427. Verilog HDL RAM Initialized with the readmemb Command
reg [7:0] ram[0:15];
initial
begin
$readmemb("ram.txt", ram);
end
June 2012
Altera Corporation
1436
If you use Quartus II integrated synthesis, you can direct the software to infer ROM
blocks for all sizes with the Allow Any ROM Size for Recognition option in the
More Analysis & Synthesis Settings dialog box.
Some synthesis tools provide options to control the implementation of inferred ROM
blocks for Altera devices with synchronous memory blocks. For example, Quartus II
integrated synthesis provides the romstyle synthesis attribute to specify the type of
memory block or to specify the use of regular logic instead of a dedicated memory
block.
f For details about using the romstyle attribute, refer to the Quartus II Integrated
Synthesis chapter in volume 1 of the Quartus II Handbook. For information about
synthesis attributes in other synthesis tools, refer to the appropriate chapter in the
Synthesis section in volume 1 of the Quartus II Handbook.
1
1437
The ROM code examples in Example 1429 through Example 1432 on pages 1437
through 1439 map directly to the Altera memory architecture.
Example 1429. Verilog HDL Synchronous ROM
module sync_rom (clock, address, data_out);
input clock;
input [7:0] address;
output [5:0] data_out;
reg [5:0] data_out;
always @ (posedge clock)
begin
case (address)
8'b00000000: data_out
8'b00000001: data_out
...
8'b11111110: data_out
8'b11111111: data_out
endcase
end
endmodule
= 6'b101111;
= 6'b110110;
= 6'b000001;
= 6'b101010;
June 2012
Altera Corporation
1438
1439
1;
1;
downto 0);
downto 0)
June 2012
Altera Corporation
1440
Have equally spaced taps that are at least three registers apart
When you use a formal verification flow, Altera recommends that you create shift
register blocks in separate entities or modules containing only the shift register logic,
because you might have to treat the entity or module as a black box during formal
verification.
1
If the registered bus width is one (W = 1), the software infers ALTSHIFT_TAPS if
the number of taps times the length between each tap is greater than or equal to 64
(N L 64).
If the registered bus width is greater than one (W > 1), the software infers
ALTSHIFT_TAPS if the registered bus width times the number of taps times the
length between each tap is greater than or equal to 32 (W N L 32).
If the length between each tap (L) is not a power of two, the software uses more logic
to decode the read and write counters. This situation occurs because for different sizes
of shift registers, external decode logic that uses logic elements (LEs) or ALMs is
required to implement the function. This decode logic eliminates the performance and
utilization advantages of implementing shift registers in memory.
1441
The registers that the software maps to the ALTSHIFT_TAPS megafunction and places
in RAM are not available in a Verilog HDL or VHDL output file for simulation tools
because their node names do not exist after synthesis.
1
If your design uses a shift enable signal to infer a shift register, the shift register will
not be implemented into MLAB memory, but can use only dedicated RAM blocks.
June 2012
Altera Corporation
1442
1443
June 2012
Altera Corporation
sr_tap_one = sr[15];
sr_tap_two = sr[31];
sr_tap_three = sr[47];
sr_out = sr[63];
1444
Example 1436. VHDL 8-Bit Wide, 64-Bit Long Shift Register with Evenly Spaced Taps
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY shift_8x64_taps IS
PORT (
clk: IN STD_LOGIC;
shift: IN STD_LOGIC;
sr_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
sr_tap_one: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sr_tap_two : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sr_tap_three: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sr_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END shift_8x64_taps;
ARCHITECTURE arch OF shift_8x64_taps IS
SUBTYPE sr_width IS STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE sr_length IS ARRAY (63 DOWNTO 0) OF sr_width;
SIGNAL sr: sr_length;
BEGIN
PROCESS (clk)
BEGIN
IF (clk'EVENT and clk = '1') THEN
IF (shift = '1') THEN
sr(63 DOWNTO 1) <= sr(62 DOWNTO 0);
sr(0) <= sr_in;
END IF;
END IF;
END PROCESS;
sr_tap_one <= sr(15);
sr_tap_two <= sr(31);
sr_tap_three <= sr(47);
sr_out <= sr(63);
END arch;
1445
If your design uses a preset signal on a device that does not support presets in the
register architecture, your synthesis tool may convert the preset signal to a clear
signal, which requires synthesis to perform an optimization referred to as NOT gate
push-back. NOT gate push-back adds an inverter to the input and the output of the
register so that the reset and power-up conditions will appear to be high, and the
device operates as expected. In this case, your synthesis tool may issue a message
informing you about the power-up condition. The register itself powers up low, but
the register output is inverted, so the signal that arrives at all destinations is high.
Due to these effects, if you specify a non-zero reset value, you may cause your
synthesis tool to use the asynchronous clear (aclr) signals available on the registers to
implement the high bits with NOT gate push-back. In that case, the registers look as
though they power up to the specified reset value.
When an asynchronous load (aload) signal is available in the device registers, your
synthesis tools can implement a reset of 1 or 0 value by using an asynchronous load of
1 or 0. When the synthesis tool uses a load signal, it is not performing NOT gate
push-back, so the registers power up to a 0 logic level.
f For additional details, refer to the appropriate device family handbook or the
appropriate handbook on the Altera website.
Designers typically use an explicit reset signal for the design, which forces all registers
into their appropriate values after reset. Altera recommends this practice to reset the
device after power-up to restore the proper state.
You can make your design more stable and avoid potential glitches by synchronizing
external or combinational logic of the device architecture before you drive the
asynchronous control ports of registers.
f For additional information about good synchronous design practices, refer to the
Design Recommendations for Altera Devices and the Quartus II Design Assistant chapter in
volume 1 of the Quartus II Handbook.
June 2012
Setting the Power-Up Level to a logic level of high for a large design entity could
degrade the quality of results due to the number of inverters that are required. In
some situations, issues are caused by enable signal inference or secondary control
logic inference. It may also be more difficult to migrate such a design to an ASIC or a
HardCopy device.
Altera Corporation
1446
You can simulate the power-up behavior in a functional simulation if you use
initialization.
f The Power-Up Level option and the altera_attribute assignment are described in
the Quartus II Integrated Synthesis chapter in volume 1 of the Quartus II Handbook.
Some synthesis tools can also read the default or initial values for registered signals
and implement this behavior in the device. For example, Quartus II integrated
synthesis converts default values for registered signals into Power-Up Level settings.
When the Quartus II software reads the default values, the synthesized behavior
matches the power-up state of the HDL code during a functional simulation.
For example, the code samples in Example 1437 and Example 1438 both infer a
register for q and set its power-up level to high.
Example 1437. Verilog Register with High Power-Up Value
reg q = 1b1; //q has a default value of 1
always @ (posedge clk)
begin
q <= d;
end
There may also be undeclared default power-up conditions based on signal type. If
you declare a VHDL register signal as an integer, Quartus II synthesis attempts to use
the left end of the integer range as the power-up value. For the default signed integer
type, the default power-up value is the highest magnitude negative integer
(100001). For an unsigned integer type, the default power-up value is 0.
1
If the target device architecture does not support two asynchronous control signals,
such as aclr and aload, you cannot set a different power-up state and reset state. If
the NOT gate push-back algorithm creates logic to set a register to 1, that register will
power-up high. If you set a different power-up condition through a synthesis
assignment or initial value, the power-up level is ignored during synthesis.
1447
To make the most efficient use of the signals in the device, your HDL code should
match the device architecture as closely as possible. The control signals have a certain
priority due to the nature of the architecture, so your HDL code should follow that
priority where possible.
Your synthesis tool can emulate any control signals using regular logic, so achieving
functionally correct results is always possible. However, if your design requirements
are flexible in terms of which control signals are used and in what priority, match your
design to the target device architecture to achieve the most efficient results. If the
priority of the signals in your design is not the same as that of the target architecture,
extra logic may be required to implement the control signals. This extra logic uses
additional device resources and can cause additional delays for the control signals.
In addition, there are certain cases where using logic other than the dedicated control
logic in the device architecture can have a larger impact. For example, the clock enable
signal has priority over the synchronous reset or clear signal in the device
architecture. The clock enable turns off the clock line in the LAB, and the clear signal is
synchronous. Therefore, in the device architecture, the synchronous clear takes effect
only when a clock edge occurs.
If you code a register with a synchronous clear signal that has priority over the clock
enable signal, the software must emulate the clock enable functionality using data
inputs to the registers. Because the signal does not use the clock enable port of a
register, you cannot apply a Clock Enable Multicycle constraint. In this case, following
the priority of signals available in the device is clearly the best choice for the priority
of these control signals, and using a different priority causes unexpected results with
an assignment to the clock enable signal.
1
The priority order for secondary control signals in Altera devices differs from the
order for other vendors devices. If your design requirements are flexible regarding
priority, verify that the secondary control signals meet design performance
requirements when migrating designs between FPGA vendors and try to match your
target device architecture to achieve the best results.
The signal order is the same for all Altera device families, although, as noted
previously, not all device families provide every signal. The following priority order is
observed:
1. Asynchronous Clear, aclrhighest priority
2. Asynchronous Load, aload
3. Enable, ena
4. Synchronous Clear, sclr
5. Synchronous Load, sload
6. Data In, datalowest priority
The following examples provide Verilog HDL and VHDL code that creates a register
with the aclr, aload, and ena control signals.
June 2012
MAX 3000 and MAX 7000 devices include a dedicated preset signal, which has
second priority after aclr, and is not included in the following examples.
Altera Corporation
1448
The Verilog HDL example (Example 1439) does not have adata on the sensitivity list,
but the VHDL example (Example 1440) does. This is a limitation of the Verilog HDL
languagethere is no way to describe an asynchronous load signal (in which q
toggles if adata toggles while aload is high). All synthesis tools should infer an aload
signal from this construct despite this limitation. When they perform such inference,
you may see information or warning messages from the synthesis tool.
Example 1439. Verilog HDL D-Type Flipflop (Register) with ena, aclr, and aload Control Signals
module dff_control(clk, aclr, aload, ena, data, adata, q);
input clk, aclr, aload, ena, data, adata;
output q;
reg q;
always @ (posedge clk or posedge aclr or posedge aload)
begin
if (aclr)
q <= 1'b0;
else if (aload)
q <= adata;
else if (ena)
q <= data;
end
endmodule
Example 1440. VHDL D-Type Flipflop (Register) with ena, aclr, and aload Control Signals (Part 1
of 2)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dff_control IS
PORT (
clk: IN STD_LOGIC;
aclr: IN STD_LOGIC;
aload: IN STD_LOGIC;
adata: IN STD_LOGIC;
ena: IN STD_LOGIC;
data: IN STD_LOGIC;
q: OUT STD_LOGIC
);
END dff_control;
1449
Example 1440. VHDL D-Type Flipflop (Register) with ena, aclr, and aload Control Signals (Part 2
of 2)
ARCHITECTURE rtl OF dff_control IS
BEGIN
PROCESS (clk, aclr, aload, adata)
BEGIN
IF (aclr = '1') THEN
q <= '0';
ELSIF (aload = '1') THEN
q <= adata;
ELSE
IF (clk = '1' AND clk'event) THEN
IF (ena ='1') THEN
q <= data;
END IF;
END IF;
END IF;
END PROCESS;
END rtl;
Creating many registers with different sload and sclr signals can make packing the
registers into LABs difficult for the Quartus II Fitter because the sclr and sload
signals are LAB-wide signals. In addition, using the LAB-wide sload signal prevents
the Fitter from packing registers using the quick feedback path in the device
architecture, which means that some registers cannot be packed with other logic.
Synthesis tools typically restrict use of sload and sclr signals to cases in which there
are enough registers with common signals to allow good LAB packing. Using the
look-up table (LUT) to implement the signals is always more flexible if it is available.
Because different device families offer different numbers of control signals, inference
of these signals is also device-specific. For example, because Stratix II devices have
more flexibility than Stratix devices with respect to secondary control signals,
synthesis tools might infer more sload and sclr signals for Stratix II devices.
If you use these additional control signals, use them in the priority order that matches
the device architecture. To achieve the most efficient results, ensure the sclr signal
has a higher priority than the sload signal in the same way that aclr has higher
priority than aload in the previous examples. Remember that the register signals are
not inferred unless the design meets the conditions described previously. However, if
your HDL described the desired behavior, the software always implements logic with
the correct functionality.
In Verilog HDL, the following code for sload and sclr could replace the
if (ena) q <= data; statements in the Verilog HDL in Example 1439 (after adding
the control signals to the module declaration).
Example 1441. Verilog HDL sload and sclr Control Signals
if
(ena) begin
if (sclr)
q <= 1'b0;
else if (sload)
q <= sdata;
else
q <= data;
end
June 2012
Altera Corporation
1450
In VHDL, the following code for sload and sclr could replace the IF (ena ='1')
THEN q <= data; END IF; statements in the VHDL in Example 1440 on page 1448
(after adding the control signals to the entity declaration).
Example 1442. VHDL sload and sclr Control Signals
IF (ena ='1') THEN
IF (sclr = '1') THEN
q <= '0';
ELSIF (sload = '1') THEN
q <= sdata;
ELSE
q <= data;
END IF;
END IF;
Latches
A latch is a small combinational loop that holds the value of a signal until a new value
is assigned.
1
Altera recommends that you design without the use of latches whenever possible.
f For additional information about the issues involved in designing with latches and
combinational loops, refer to the Design Recommendations for Altera Devices and the
Quartus II Design Assistant chapter in volume 1 of the Quartus II Handbook.
Latches can be inferred from HDL code when you did not intend to use a latch, as
described in Unintentional Latch Generation. If you do intend to infer a latch, it is
important to infer it correctly to guarantee correct device operation as detailed in
Inferring Latches Correctly on page 1451.
Latches have limited support in formal verification tools. Therefore, ensure that you
do not infer latches unintentionally.
1451
The full_case attribute can be used in Verilog HDL designs to treat unspecified cases
as dont care values (X). However, using the full_case attribute can cause simulation
mismatches because this attribute is a synthesis-only attribute, so simulation tools still
treat the unspecified cases as latches.
f For more information about using attributes in your synthesis tool, refer to the
appropriate chapter in the Synthesis section in volume 1 of the Quartus II Handbook.
The Quartus II Integrated Synthesis chapter in volume 1 of the Quartus II Handbook
provides an example explaining possible simulation mismatches.
Omitting the final else or when others clause in an if or case statement can also
generate a latch. Dont care (X) assignments on the default conditions are useful in
preventing latch generation. For the best logic optimization, assign the default case or
final else value to dont care (X) instead of a logic value.
The VHDL code sample in Example 1443 prevents unintentional latches. Without the
final else clause, this code creates unintentional latches to cover the remaining
combinations of the sel inputs. When you are targeting a Stratix device with this
code, omitting the final else condition can cause the synthesis software to use up to
six LEs, instead of the three it uses with the else statement. Additionally, assigning
the final else clause to 1 instead of X can result in slightly more LEs, because the
synthesis software cannot perform as much optimization when you specify a constant
value compared to a dont care value.
Example 1443. VHDL Code Preventing Unintentional Latch Creation
LIBRARY ieee;
USE IEEE.std_logic_1164.all;
ENTITY nolatch IS
PORT (a,b,c: IN STD_LOGIC;
sel: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
oput: OUT STD_LOGIC);
END nolatch;
ARCHITECTURE rtl OF nolatch IS
BEGIN
PROCESS (a,b,c,sel) BEGIN
if sel = "00000" THEN
oput <= a;
ELSIF sel = "00001" THEN
oput <= b;
ELSIF sel = "00010" THEN
oput <= c;
ELSE
--- Prevents latch inference
oput <= ''X'; --/
END if;
END PROCESS;
END rtl;
June 2012
Altera Corporation
1452
Any use of latches generates warnings and is flagged if the design is migrated to a
HardCopy ASIC. In addition, timing analysis does not completely model latch timing
in some cases. Do not use latches unless required by your design, and you fully
understand the impact of using the latches.
When using Quartus II integrated synthesis, latches that are inferred by the software
are reported in the User-Specified and Inferred Latches section of the Compilation
Report. This report indicates whether the latch is considered safe and free of timing
hazards.
If a latch or combinational loop in your design is not listed in the User-Specified and
Inferred Latches section, it means that it was not inferred as a safe latch by the
software and is not considered glitch-free.
All combinational loops listed in the Analysis & Synthesis Logic Cells Representing
Combinational Loops table in the Compilation Report are at risk of timing hazards.
These entries indicate possible problems with your design that you should
investigate. However, it is possible to have a correct design that includes
combinational loops. For example, it is possible that the combinational loop cannot be
sensitized. This can occur in cases where there is an electrical path in the hardware,
but either the designer knows that the circuit never encounters data that causes that
path to be activated, or the surrounding logic is set up in a mutually exclusive manner
that prevents that path from ever being sensitized, independent of the data input.
For macrocell-based devices, such as MAX 7000 and MAX 3000, all data (D-type)
latches and set-reset (S-R) latches listed in the Analysis & Synthesis User-Specified
and Inferred Latches table have an implementation free of timing hazards, such as
glitches. The implementation includes both a cover term to ensure there is no
glitching and a single macrocell in the feedback loop.
For 4-input LUT-based devices, such as Stratix devices, the Cyclone series, and
MAX II devices, all latches in the User-Specified and Inferred Latches table with a
single LUT in the feedback loop are free of timing hazards when a single input
changes. Because of the hardware behavior of the LUT, the output does not glitch
when a single input toggles between two values that are supposed to produce the
same output value, such as a D-type input toggling when the enable input is inactive
or a set input toggling when a reset input with higher priority is active. This hardware
behavior of the LUT means that no cover term is required for a loop around a single
LUT. The Quartus II software uses a single LUT in the feedback loop whenever
possible. A latch that has data, enable, set, and reset inputs in addition to the output
fed back to the input cannot be implemented in a single 4-input LUT. If the Quartus II
software cannot implement the latch with a single-LUT loop because there are too
many inputs, the User-Specified and Inferred Latches table indicates that the latch is
not free of timing hazards.
For 6-input LUT-based devices, the software can implement all latch inputs with a
single adaptive look-up table (ALUT) in the combinational loop. Therefore, all latches
in the User-Specified and Inferred Latches table are free of timing hazards when a
single input changes.
If a latch is listed as a safe latch, other optimizations performed by the Quartus II
software, such as physical synthesis netlist optimizations in the Fitter, maintain the
hazard-free performance.
1453
To ensure hazard-free behavior, only one control input can change at a time. Changing
two inputs simultaneously, such as deasserting set and reset at the same time, or
changing data and enable at the same time, can produce incorrect behavior in any
latch.
Quartus II integrated synthesis infers latches from always blocks in Verilog HDL and
process statements in VHDL, but not from continuous assignments in Verilog HDL or
concurrent signal assignments in VHDL. These rules are the same as for register
inference. The software infers registers or flipflops only from always blocks and
process statements.
The Verilog HDL code sample in Example 1444 infers a S-R latch correctly in the
Quartus II software.
Example 1444. Verilog HDL Set-Reset Latch
module simple_latch (
input SetTerm,
input ResetTerm,
output reg LatchOut
);
always @ (SetTerm or ResetTerm) begin
if (SetTerm)
LatchOut = 1'b1
else if (ResetTerm)
LatchOut = 1'b0
end
endmodule
The VHDL code sample in Example 1445 infers a D-type latch correctly in the
Quartus II software.
Example 1445. VHDL Data Type Latch
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY simple_latch IS
PORT (
enable, data
: IN STD_LOGIC;
q
: OUT STD_LOGIC
);
END simple_latch;
ARCHITECTURE rtl OF simple_latch IS
BEGIN
latch : PROCESS (enable, data)
BEGIN
IF (enable = '1') THEN
q <= data;
END IF;
END PROCESS latch;
END rtl;
The following example shows a Verilog HDL continuous assignment that does not
infer a latch in the Quartus II software:
assign latch_out = (~en & latch_out) | (en & data);
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The behavior of the assignment is similar to a latch, but it may not function correctly
as a latch, and its timing is not analyzed as a latch.
Quartus II integrated synthesis also creates safe latches when possible for
instantiations of the LPM_LATCH megafunction. You can use this megafunction to
create a latch with any combination of data, enable, set, and reset inputs. The same
limitations apply for creating safe latches as for inferring latches from HDL code.
Inferring the Altera LPM_LATCH function in another synthesis tool ensures that the
implementation is also recognized as a latch in the Quartus II software. If a
third-party synthesis tool implements a latch using the LPM_LATCH megafunction,
the Quartus II integrated synthesis lists the latch in the User-Specified and Inferred
Latches table in the same way as it lists latches created in HDL source code. The
coding style necessary to produce an LPM_LATCH implementation may depend on
your synthesis tool. Some third-party synthesis tools list the number of LPM_LATCH
functions that are inferred.
For LUT-based families, the Fitter uses global routing for control signals, including
signals that Analysis and Synthesis identifies as latch enables. In some cases the
global insertion delay may decrease the timing performance. If necessary, you can
turn off the Quartus II Global Signal logic option to manually prevent the use of
global signals. Global latch enables are listed in the Global & Other Fast Signals table
in the Compilation Report.
Tri-State Signals. This section explains how to create tri-state signals for
bidirectional I/O pins.
Adder Trees on page 1459. This section explains the different coding styles that
lead to optimal results for devices with 4-input LUTs and 6-input ALUTs.
State Machines on page 1461. This section helps ensure the best results when
you use state machines.
1455
Tri-State Signals
When you target Altera devices, you should use tri-state signals only when they are
attached to top-level bidirectional or output pins. Avoid lower-level bidirectional
pins, and avoid using the Z logic value unless it is driving an output or bidirectional
pin.
Synthesis tools implement designs with internal tri-state signals correctly in Altera
devices using multiplexer logic, but Altera does not recommend this coding practice.
1
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1456
Clock Multiplexing
Clock multiplexing is sometimes used to operate the same logic function with
different clock sources. This type of logic can introduce glitches that create functional
problems, and the delay inherent in the combinational logic can lead to timing
problems. Clock multiplexers trigger warnings from a wide range of design rule
check and timing analysis tools.
Altera recommends using dedicated hardware to perform clock multiplexing when it
is available, instead of using multiplexing logic. For example, you can use the Clock
Switchover feature or the Clock Control Block available in certain Altera devices.
These dedicated hardware blocks avoid glitches, ensure that you use global low-skew
routing lines, and avoid any possible hold time problems on the device due to logic
delay on the clock line. Many Altera devices also support dynamic PLL
reconfiguration, which is the safest and most robust method of changing clock rates
during device operation.
f Refer to the appropriate device data sheet or handbook for device-specific
information about clocking structures. Also refer to the ALTCLKCTRL Megafunction
User Guide, the ALTPLL Megafunction User Guide, and the Phase-Locked Loops
Reconfiguration (ALTPLL_RECONFIG) Megafunction User Guide.
If you implement a clock multiplexer in logic cells because the design has too many
clocks to use the clock control block, or if dynamic reconfiguration is too complex for
your design, it is important to consider simultaneous toggling inputs and ensure
glitch-free transitions.
Figure 142 shows a simple representation of a clock multiplexer (mux) in a device
with 6-input LUTs.
Figure 142. Simple Clock Multiplexer in a 6-Input LUT
clk_select (static)
clk0
clk1
Sys_clk
clk2
clk3
The data sheet for your target device describes how LUT outputs may glitch during a
simultaneous toggle of input signals, independent of the LUT function. Although, in
practice, the 4:1 MUX function does not generate detectable glitches during
simultaneous data input toggles, it is possible to construct cell implementations that
do exhibit significant glitches, so this simple clock mux structure is not recommended.
An additional problem with this implementation is that the output behaves erratically
during a change in the clk_select signals. This behavior could create timing
violations on all registers fed by the system clock and result in possible metastability.
1457
A more sophisticated clock select structure can eliminate the simultaneous toggle and
switching problems, as in Figure 143.
Figure 143. Glitch-Free Clock Multiplexer Structure
sel0
DQ
DQ
DQ
clk0
clk_out
DQ
sel1
DQ
DQ
clk1
This structure can be generalized for any number of clock channels. Example 1448
contains a parameterized version in Verilog HDL. The design enforces that no clock
activates until all others have been inactive for at least a few cycles, and that activation
occurs while the clock is low. The design applies a synthesis_keep directive to the
AND gates on the right side of the figure, which ensures there are no simultaneous
toggles on the input of the clk_out OR gate.
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Switching from clock A to clock B requires that clock A continue to operate for at least a
few cycles. If the old clock stops immediately, the design sticks. The select signals are
implemented as a one-hot control in this example, but you can use other encoding if
you prefer. The input side logic is asynchronous and is not critical. This design can
tolerate extreme glitching during the switch process.
1459
Adder Trees
Structuring adder trees appropriately to match your targeted Altera device
architecture can result in significant performance and density improvements. A good
example of an application using a large adder tree is a finite impulse response (FIR)
correlator. Using a pipelined binary or ternary adder tree appropriately can greatly
improve the quality of your results.
This section explains why coding recommendations are different for Altera 4-input
LUT devices and 6-input LUT devices.
CLK)
sum1;
sum2;
sum3;
sum4;
// 2-bit additions
assign sum1 = A + B;
assign sum2 = C + D;
assign sum3 = sumreg1 + sumreg2;
assign sum4 = sumreg3 + E;
assign out = sumreg4;
endmodule
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You cannot pack a LAB full when using this type of coding style because of the
number of LAB inputs. However, in a typical design, the Quartus II Fitter can pack
other logic into each LAB to take advantage of the unused ALMs.
Example 1450. Verilog HDL Pipelined Ternary Tree
module ternary_adder_tree (a, b, c, d, e, clk, out);
parameter width = 16;
input [width-1:0] a, b, c, d, e;
input clk;
output [width-1:0] out;
wire [width-1:0] sum1, sum2;
reg [width-1:0] sumreg1, sumreg2;
// registers
always @ (posedge clk)
begin
sumreg1 <= sum1;
sumreg2 <= sum2;
end
// 3-bit additions
assign sum1 = a + b + c;
assign sum2 = sumreg1 + d + e;
assign out = sumreg2;
endmodule
These examples show pipelined adders, but partitioning your addition operations can
help you achieve better results in nonpipelined adders as well. If your design is not
pipelined, a ternary tree provides much better performance than a binary tree. For
example, depending on your synthesis tool, the HDL code
sum = (A + B + C) + (D + E) is more likely to create the optimal implementation of
a 3-input adder for A + B + C followed by a 3-input adder for sum1 + D + E than the
code without the parentheses. If you do not add the parentheses, the synthesis tool
may partition the addition in a way that is not optimal for the architecture.
1461
State Machines
Synthesis tools can recognize and encode Verilog HDL and VHDL state machines
during synthesis. This section presents guidelines to ensure the best results when you
use state machines. Ensuring that your synthesis tool recognizes a piece of code as a
state machine allows the tool to recode the state variables to improve the quality of
results, and allows the tool to use the known properties of state machines to optimize
other parts of the design. When synthesis recognizes a state machine, it is often able to
improve the design area and performance.
To achieve the best results on average, synthesis tools often use one-hot encoding for
FPGA devices and minimal-bit encoding for CPLD devices, although the choice of
implementation can vary for different state machines and different devices. Refer to
your synthesis tool documentation for specific ways to control the manner in which
state machines are encoded.
f For information about state machine encoding in Quartus II integrated synthesis,
refer to the State Machine Processing section in the Quartus II Integrated Synthesis
chapter in volume 1 of the Quartus II Handbook.
To ensure proper recognition and inference of state machines and to improve the
quality of results, Altera recommends that you observe the following guidelines,
which apply to both Verilog HDL and VHDL:
Assign default values to outputs derived from the state machine so that synthesis
does not generate unwanted latches.
Separate the state machine logic from all arithmetic functions and data paths,
including assigning output values.
If your design contains an operation that is used by more than one state, define the
operation outside the state machine and cause the output logic of the state
machine to use this value.
If a state machine enters an illegal state due to a problem with the device, the design
likely ceases to function correctly until the next reset of the state machine. Synthesis
tools do not provide for this situation by default. The same issue applies to any other
registers if there is some kind of fault in the system. A default or when others clause
does not affect this operation, assuming that your design never deliberately enters
this state. Synthesis tools remove any logic generated by a default state if it is not
reachable by normal state machine operation.
Many synthesis tools (including Quartus II integrated synthesis) have an option to
implement a safe state machine. The software inserts extra logic to detect an illegal
state and force the state machines transition to the reset state. It is commonly used
when the state machine can enter an illegal state. The most common cause of this
situation is a state machine that has control inputs that come from another clock
domain, such as the control logic for a dual-clock FIFO.
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This option protects only state machines by forcing them into the reset state. All other
registers in the design are not protected this way. If the design has asynchronous
inputs, Altera recommends using a synchronization register chain instead of relying
on the safe state machine option.
f For additional information about tool-specific options for implementing state
machines, refer to the tool vendors documentation or the appropriate chapter in the
Synthesis section in volume 1 of the Quartus II Handbook.
The following two sections, Verilog HDL State Machines and VHDL State
Machines on page 1466, describe additional language-specific guidelines and
coding examples.
If you are using the SystemVerilog standard, use enumerated types to describe
state machines. For more information, refer too SystemVerilog State Machine
Coding Example on page 1465.
Represent the states in a state machine with the parameter data types in
Verilog-1995 and Verilog-2001, and use the parameters to make state assignments.
For more information, refer tooVerilog-2001 State Machine Coding Example on
page 1463. This parameter implementation makes the state machine easier to
read and reduces the risk of errors during coding.
1
Altera recommends against the direct use of integer values for state
variables, such as next_state <= 0. However, using an integer does not
prevent inference in the Quartus II software.
No state machine is inferred in the Quartus II software if the state transition logic
uses arithmetic similar to that in the following example:
case (state)
0: begin
if (ena) next_state <= state + 2;
else next_state <= state + 1;
end
1: begin
...
endcase
1463
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1465
state_0
state_1
state_2
state_3
state_4
3'b000
3'b001
3'b010
3'b011
3'b100
In this case, the state and next_state assignments are assigned a state_x instead of
a state_x, for example:
next_state <= state_3;
Although the define construct is supported, Altera strongly recommends the use of
the parameter data type because doing so preserves the state names throughout
synthesis.
SystemVerilog State Machine Coding Example
The module enum_fsm in Example 1452 is an example of a SystemVerilog state
machine implementation that uses enumerated types. Altera recommends using this
coding style to describe state machines in SystemVerilog.
June 2012
In Quartus II integrated synthesis, the enumerated type that defines the states for the
state machine must be of an unsigned integer type as in Example 1452. If you do not
specify the enumerated type as int unsigned, a signed int type is used by default. In
this case, the Quartus II integrated synthesis synthesizes the design, but does not infer
or optimize the logic as a state machine.
Altera Corporation
1466
1467
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1468
Multiplexers
Multiplexers form a large portion of the logic utilization in many FPGA designs. By
optimizing your multiplexer logic, you ensure the most efficient implementation in
your Altera device. This section addresses common problems and provides design
guidelines to achieve optimal resource utilization for multiplexer designs. The section
also describes various types of multiplexers, and how they are implemented.
f For more information, refer to the Advanced Synthesis Cookbook.
Multiplexer Types
This section addresses how multiplexers are created from various types of HDL code.
CASE statements, IF statements, and state machines are all common sources of
multiplexer logic in designs. These HDL structures create different types of
multiplexers, including binary multiplexers, selector multiplexers, and priority
multiplexers. Understanding how multiplexers are created from HDL code, and how
they might be implemented during synthesis, is the first step toward optimizing
multiplexer structures for best results.
Binary Multiplexers
Binary multiplexers select inputs based on binary-encoded selection bits.
Example 1454 shows Verilog HDL code for two ways to describe a simple 4:1 binary
multiplexer.
Example 1454. Verilog HDL Binary-Encoded Multiplexers
case (sel)
2'b00: z
2'b01: z
2'b10: z
2'b11: z
endcase
=
=
=
=
a;
b;
c;
d;
1469
Stratix series devices starting with the Stratix II device family feature 6-input look up
tables (LUTs) which are perfectly suited for 4:1 multiplexer building blocks (4 data
and 2 select inputs). The extended input mode facilitates implementing 8:1 blocks,
and the fractured mode handles residual 2:1 multiplexer pairs. For device families
using 4-input LUTs, such as the Cyclone series and Stratix devices, the 4:1 binary
multiplexer is efficiently implemented by using two 4-input LUTs. Larger binary
multiplexers are decomposed by the synthesis tool into 4:1 multiplexer blocks,
possibly with a residual 2:1 multiplexer at the head.
Selector Multiplexers
Selector multiplexers have a separate select line for each data input. The select lines
for the multiplexer are one-hot encoded. Example 1455 shows a simple Verilog HDL
code example describing a one-hot selector multiplexer.
Example 1455. Verilog HDL One-Hot-Encoded Case Statement
case (sel)
4'b0001:
4'b0010:
4'b0100:
4'b1000:
default:
endcase
z
z
z
z
z
=
=
=
=
=
a;
b;
c;
d;
1'bx;
Selector multiplexers are commonly built as a tree of AND and OR gates. An N-input
selector multiplexer of this structure is slightly less efficient in implementation than a
binary multiplexer. However, in many cases the select signal is the output of a
decoder, in which case Quartus II Synthesis will try to combine the selector and
decoder into a binary multiplexer.
Priority Multiplexers
In priority multiplexers, the select logic implies a priority. The options to select the
correct item must be checked in a specific order based on signal priority. These
structures commonly are created from IF, ELSE, WHEN, SELECT, and ?: statements in
VHDL or Verilog HDL. The example VHDL code in Example 1456 probably results
in the schematic implementation illustrated in Figure 144.
Example 1456. VHDL IF Statement Implying Priority
IF cond1 THEN z <= a;
ELSIF cond2 THEN z <= b;
ELSIF cond3 THEN z <= c;
ELSE z <= d;
END IF;
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The multiplexers in Figure 144 form a chain, evaluating each condition or select bit
sequentially.
Figure 144. Priority Multiplexer Implementation of an IF Statement
cond3
b
cond2
a
cond1
Depending on the number of multiplexers in the chain, the timing delay through this
chain can become large, especially for device families with 4-input LUTs.
To improve the timing delay through the multiplexer, avoid priority multiplexers if
priority is not required. If the order of the choices is not important to the design, use a
CASE statement to implement a binary or selector multiplexer instead of a priority
multiplexer. If delay through the structure is important in a multiplexed design
requiring priority, consider recoding the design to reduce the number of logic levels to
minimize delay, especially along your critical paths.
1471
Some designs do not require that the outcome in the unused cases be considered,
often because designers assume these cases will not occur. For these types of designs,
you can specify any value for the default or OTHERS assignment. However, be aware
that the assignment value you choose can have a large effect on the logic utilization
required to implement the design due to the different ways synthesis tools treat
different values for the assignment, and how the synthesis tools use different speed
and area optimizations.
To obtain best results, explicitly define invalid CASE selections with a separate default
or OTHERS statement instead of combining the invalid cases with one of the defined
cases.
If the value in the invalid cases is not important, specify those cases explicitly by
assigning the X (dont care) logic value instead of choosing another value. This
assignment allows your synthesis tool to perform the best area optimizations.
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1472
determine the final result. Therefore, forcing the use of intermediate calculations
increases the area required to implement the function, as well as increasing the logic
depth because of the cascading. It is typically better to create full separate CRC blocks
for each data width that you require in the design, and then multiplex them together
to choose the appropriate mode at a given time
Synthesize each CRC block as a separate project in your third-party synthesis tool
and then write a separate Verilog Quartus Mapping (.vqm) or EDIF netlist file for
each.
1473
Comparators
Synthesis software, including Quartus II integrated synthesis, uses device and
context-specific implementation rules for comparators (<, >, or ==) and selects the best
one for your design. This section provides some information about the different types
of implementations available and provides suggestions on how you can code your
design to encourage a specific implementation.
The == comparator is implemented in general logic cells. The < comparison can be
implemented using the carry chain or general logic cells. In devices with 6-input
ALUTs, the carry chain is capable of comparing up to three bits per cell. In devices
with 4-input LUTs, the capacity is one bit of comparison per cell, which is similar to an
add/subtract chain. The carry chain implementation tends to be faster than the
general logic on standalone benchmark test cases, but can result in lower performance
when it is part of a larger design due to the increased restriction on the Fitter. The area
requirement is similar for most input patterns. The synthesis software selects an
appropriate implementation based on the input pattern.
If you are using Quartus II integrated synthesis, you can guide the synthesis by using
specific coding styles. To select a carry chain implementation explicitly, rephrase your
comparison in terms of addition. As a simple example, the following coding style
allows the synthesis tool to select the implementation, which is most likely using
general logic cells in modern device families:
wire [6:0] a,b;
wire alb = a<b;
In the following coding style, the synthesis tool uses a carry chain (except for a few
cases, such as when the chain is very short or the signals a and b minimize to the same
signal):
wire [6:0] a,b;
wire [7:0] tmp = a - b;
wire alb = tmp[7]
This second coding style uses the top bit of the tmp signal, which is 1 in twos
complement logic if a is less than b, because the subtraction a b results in a negative
number.
If you have any information about the range of the input, you have dont care
values that you can use to optimize the design. Because this information is not
available to the synthesis tool, you can often reduce the device area required to
implement the comparator with specific hand implementation of the logic.
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You can also check whether a bus value is within a constant range with a small
amount of logic area by using the logic structure in Figure 145. This type of logic
occurs frequently in address decoders.
Figure 145. Example Logic Structure for Using Comparators to Check a Bus Value Range
Address[ ]
< 2f00
Select[3]
< 200
< 1a0
< 100
Select[2]
Select[1]
Select[0]
Counters
Implementing counters in HDL code is easy; they are implemented with an adder
followed by registers. Remember that the register control signals, such as enable (ena),
synchronous clear (sclr), and synchronous load (sload), are available. For the best
area utilization, ensure that the up/down control or controls are expressed in terms of
one addition instead of two separate addition operators.
If you use the following coding style, your synthesis tool may implement two
separate carry chains for addition (if it doesnt detect the issue and optimize the logic):
out <= count_up ? out + 1 : out - 1;
The following coding style requires only one adder along with some other logic:
out <= out + (count_up ? 1 : -1);
In this case, the coding style better matches the device hardware because there is only
one carry chain adder, and the 1 constant logic is implemented in the LUT in front of
the adder without adding extra area utilization.
1475
Create carry and cascade chains using CARRY, CARRY_SUM, and CASCADE primitives
Use I/O buffers to specify I/O standards, current strengths, and other I/O
assignments
Use I/O buffers to specify differential pin names in your HDL code, instead of
using the automatically-generated negative pin name for each pair
f For details about and examples of using these types of assignments, refer to the
Designing with Low-Level Primitives User Guide.
Conclusion
Because coding style and megafunction implementation can have such a large effect
on your design performance, it is important to match the coding style to the device
architecture from the very beginning of the design process. To improve design
performance and area utilization, take advantage of advanced device features, such as
memory and DSP blocks, as well as the logic architecture of the targeted Altera device
by following the coding recommendations presented in this chapter.
f For additional optimization recommendations, refer to the Area and Timing
Optimization chapter in volume 2 of the Quartus II Handbook.
November 2011
December 2010
July 2010
12.0.0
11.1.0
10.1.0
10.0.0
November 2009
June 2012
Version
9.1.0
Altera Corporation
Changes
Updated support for Controlling Inference and Implementation in Device RAM Blocks
1476
Version
Changes
March 2009
9.0.0
November 2008
8.1.0
May 2008
8.0.0
Added information to Avoid Unsupported Reset and Control Conditions on page 614
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
Introduction
All registers in digital devices, such as FPGAs, have defined signal-timing
requirements that allow each register to correctly capture data at its input ports and
produce an output signal. To ensure reliable operation, the input to a register must be
stable for a minimum amount of time before the clock edge (register setup time or tSU)
and a minimum amount of time after the clock edge (register hold time or tH). The
register output is available after a specified clock-to-output delay (tCO).
If the data violates the setup or hold time requirements, the output of the register
might go into a metastable state. In a metastable state, the voltage at the register
output hovers at a value between the high and low states, which means the output
transition to a defined high or low state is delayed beyond the specified tCO. Different
destination registers might capture different values for the metastable signal, which
can cause the system to fail.
In synchronous systems, the input signals must always meet the register timing
requirements, so that metastability does not occur. Metastability problems commonly
occur when a signal is transferred between circuitry in unrelated or asynchronous
clock domains, because the signal can arrive at any time relative to the destination
clock.
The MTBF due to metastability is an estimate of the average time between instances
when metastability could cause a design failure. A high MTBF (such as hundreds or
thousands of years between metastability failures) indicates a more robust design.
You should determine an acceptable target MTBF in the context of your entire system
and taking in account that MTBF calculations are statistical estimates.
The metastability MTBF for a specific signal transfer, or all the transfers in a design,
can be calculated using information about the design and the device characteristics.
Improving the metastability MTBF for your design reduces the chance that signal
transfers could cause metastability problems in your device.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
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152
f For more information about metastability due to signal synchronization, its effects in
FPGAs, and how MTBF is calculated, refer to the Understanding Metastability in FPGAs
white paper on the Altera website. Your overall device MTBF is also affected by other
FPGA failure mechanisms that you cannot control with your design. For information
about Altera device reliability, refer to the Reliability Report on the Altera website.
The Quartus II software provides analysis, optimization, and reporting features to
help manage metastability in Altera designs. These metastability features are
supported only for designs constrained with the Quartus II Timing Analyzer. Both
typical and worst-case MBTF values are generated for select device families.
h For information about device and version support for the metastability features in the
Quartus II software, refer to the Quartus II Help.
This chapter contains the following topics:
For information about the reports generated by the timing analyzer, refer to
Metastability and MTBF Reporting on page 155. For more information about
optimizing the MTBF, refer to MTBF Optimization on page 158.
153
The registers in the chain are all clocked by the same clock or phase-related clocks.
The first register in the chain is driven asynchronously or from an unrelated clock
domain.
Each register fans out to only one register, except the last register in the chain.
The length of the synchronization register chain is the number of registers in the
synchronizing clock domain that meet the above requirements. Figure 151 shows a
sample two-register synchronization chain.
Figure 151. Sample Synchronization Register Chain
Synchronization Chain
Clock 1 Domain
Data
Clock 2 Domain
D
Clock 1
Output
Registers
Clock 2
The path between synchronization registers can contain combinational logic as long
as all registers of the synchronization register chain are in the same clock domain.
Figure 152 shows an example of a synchronization register chain that includes logic
between the registers.
Figure 152.
Data
Clock 1
Clock 2 Domain
Q
Clock 2
Data
Output
Registers
Clock 2
D
Clock 2
The Quartus II software uses the design timing constraints to determine which
connections are asynchronous signal transfers, as described in How Timing
Constraints Affect Synchronizer Identification and Metastability Analysis on
page 154.
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The timing slack available in the register-to-register paths of the synchronizer allows a
metastable signal to settle, and is referred to as the available settling time. The
available settling time in the MTBF calculation for a synchronizer is the sum of the
output timing slacks for each register in the chain. Adding available settling time with
additional synchronization registers improves the metastability MTBF.
155
Registers that are at the end of false paths are also considered synchronization
registers because false paths are not timing-analyzed. Because there are no timing
requirements for these paths, the signal may change at any point, which may violate
the tSU and tH of the register. Therefore, these registers are identified as
synchronization registers. If these registers are not used for synchronization, you can
turn off synchronizer identification and analysis. To do so, set Synchronizer
Identification to Off for the first synchronization register in these register chains.
Metastability Reports
Metastability reports provide summaries of the metastability analysis results. In
addition to the MTBF Summary and Synchronizer Summary reports, the Timing
Analyzer tool reports additional statistics in a report for each synchronizer chain.
h For more information about how to access metastability reports in the Quartus II
software, refer to Viewing Metastability Reports in Quartus II Help.
1
If the design uses only the Auto Synchronizer Identification setting, the reports list
likely synchronizers but do not report MTBF. To obtain an MTBF for each register
chain, force identification of synchronization registers as described in Identifying
Synchronizers for Metastability Analysis on page 154.
If the synchronizer chain does not meet its timing requirements, the reports list
identified synchronizers but do not report MTBF. To obtain MTBF calculations, ensure
that the design is properly constrained and that the synchronizer meets its timing
requirements, as described in How Timing Constraints Affect Synchronizer
Identification and Metastability Analysis on page 154.
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The MTBF Summary Report reports the Typical MTBF of Design and the Worst-Case
MTBF of Design for supported fully-characterized devices. The typical MTBF result
assumes typical conditions, defined as nominal silicon characteristics for the selected
device speed grade, as well as nominal operating conditions. The worst case MTBF
result uses the worst case silicon characteristics for the selected device speed grade.
When you analyze multiple timing corners in the timing analyzer, the MTBF
calculation may vary because of changes in the operating conditions, and the timing
slack or available metastability settling time. Altera recommends running
multi-corner timing analysis to ensure that you analyze the worst MTBF results,
because the worst timing corner for MTBF does not necessarily match the worst
corner for timing performance.
h For more information about turning on multicorner timing analysis in the Quartus II
software, refer to the Timing Analyzer page in Quartus II Help.
The MTBF Summary report also lists the Number of Synchronizer Chains Found
and the length of the Shortest Synchronizer Chain, which can help you identify
whether the report is based on accurate information. If the number of synchronizer
chains found is different from what you expect, or if the length of the shortest
synchronizer chain is less than you expect, you might have to add or change
Synchronizer Identification settings for the design. The report also provides the
Worst Case Available Settling Time, defined as the available settling time for the
synchronizer with the worst MTBF.
You can use the reported Fraction of Chains for which MTBFs Could Not be
Calculated to determine whether a high proportion of chains are missing in the
metastability analysis. A fraction of 1, for example, means that MTBF could not be
calculated for any chains in the design. MTBF is not calculated if you have not
identified the chain with the appropriate Synchronizer identification option, or if
paths are not timing-analyzed and therefore have no valid slack for metastability
analysis. You might have to correct your timing constraints to enable complete
analysis of the applicable register chains.
Finally, the MTBF Summary report specifies how an increase of 100ps in available
settling time increases the MTBF values. If your MTBF is not satisfactory, this metric
can help you determine how much extra slack would be required in your
synchronizer chain to allow you to reach the desired design MTBF.
157
For information about the toggle rate, see Synchronizer Data Toggle Rate in MTBF
Calculation on page 157.
The following information is also included to help you locate the chain is in your
design:
June 2012
There are two other assignments associated with toggle rates, which are not used for
metastability MTBF calculations. The I/O Maximum Toggle Rate is only used for
pins, and specifies the worst-case toggle rates used for signal integrity purposes. The
Power Toggle Rate assignment is used to specify the expected time-averaged toggle
rate, and is used by the PowerPlay Power Analyzer to estimate time-averaged power
consumption.
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MTBF Optimization
In addition to reporting synchronization register chains and MTBF values found in
the design, the Quartus II software can also protect these registers from optimizations
that might negatively impact MTBF and can optimize the register placement and
routing if the MTBF is too low. Synchronization register chains must first be explicitly
identified as synchronizers, as described in Identifying Synchronizers for
Metastability Analysis on page 154. Altera recommends that you set Synchronizer
Identification to Forced If Asynchronous for all registers that are part of a
synchronizer chain.
Optimization algorithms, such as register duplication and logic retiming in physical
synthesis, are not performed on identified synchronization registers. The Fitter
protects the number of synchronization registers specified by the Synchronizer
Register Chain Length option which is described in the next section.
In addition, the Fitter optimizes identified synchronizers for improved MTBF by
placing and routing the registers to increase their output setup slack values. Adding
slack in the synchronizer chain increases the available settling time for a potentially
metastable signal, which improves the chance that the signal resolves to a known
value, and exponentially increases the design MTBF. The Fitter optimizes the number
of synchronization registers specified by the Synchronizer Register Chain Length
option.
Metastability optimization is on by default. To view or change the option, on the
Assignments menu, click Settings. Under Fitter Settings, click More Settings. From
the More Settings dialog box, you can turn on or off the Optimize Design for
Metastability option. To turn the optimization on or off with Tcl, use the following
command:
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY <ON|OFF>
159
You can also set the Synchronization Register Chain Length on a node or an entity in
the Assignment Editor. You can set this value on the first register in a synchronization
chain to specify how many registers to protect and optimize in this chain. This
individual setting is useful if you want to protect and optimize extra registers that you
have created in a specific synchronization chain that has low MTBF, or optimize less
registers for MTBF in a specific chain where the maximum frequency or timing
performance is not being met. To make the global setting with Tcl, use the following
command:
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH
<number of registers>
To apply the assignment to a design instance or the first register in a specific chain
with Tcl, use the following command:
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH
<number of registers> -to <register or instance name>
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Scripting Support
You can run procedures and make settings described in this chapter in a Tcl script.
You can also run some procedures at a command prompt. For detailed information
about scripting command options, refer to the Quartus II Command-Line and Tcl API
Help browser. To run the Help browser, type the following command at the command
prompt:
quartus_sh --qhelp r
f For more information about Tcl scripting, refer to the Tcl Scripting chapter in volume 2
of the Quartus II Handbook. For more information about settings and constraints in the
Quartus II software, refer to the Quartus II Settings File Reference Manual. For more
information about command-line scripting, refer to the Command-Line Scripting
chapter in volume 2 of the Quartus II Handbook and About Quartus II Scripting in
Quartus II Help.
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Option
Description
-append
If output is sent to a file, this option appends the result to that file.
Otherwise, the file is overwritten.
-file <name>
-panel_name <name>
Sends the results to the panel and specifies the name of the new
panel.
-stdout
MTBF Optimization
To ensure that metastability optimization described on page MTBF Optimization on
page 158 is turned on (or to turn it off), use the following command:
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY <ON|OFF>
To apply the assignment to a design instance or the first register in a specific chain,
use the following command:
set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH
<number of registers> -to <register or instance name>
1513
Conclusion
Alteras Quartus II software provides industry-leading analysis and optimization
features to help you manage metastability in your FPGA designs. Set up your
Quartus II project with the appropriate constraints and settings to enable the software
to analyze, report, and optimize the design MTBF. Take advantage of these features in
the Quartus II software and follow the guidelines in this chapter to make your design
more robust with respect to metastability.
Version
Changes
June 2012
12.0.0
November 2011
10.0.2
Template update.
December 2010
10.0.1
July 2010
10.0.0
Technical edit.
November 2009
9.1.0
March 2009
9.0.0
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
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November 2012
QII51017-12.1.0
QII51017-12.1.0
This chapter provides guidelines to help you partition your design to take advantage
of Quartus II incremental compilation, and to help you create a design floorplan
using LogicLock regions when they are recommended to support the compilation
flow.
The Quartus II incremental compilation feature allows you to partition a design,
compile partitions separately, and reuse results for unchanged partitions. Incremental
compilation provides the following benefits:
f For more information about the incremental compilation feature and application
examples, refer to the Quartus II Incremental Compilation for Hierarchical and Team-Based
Design chapter in volume 1 of the Quartus II Handbook. For feature support, refer to
About Incremental Compilation in Quartus II Help.
This document contains the following sections:
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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9001:2008
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162
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Overview: Incremental Compilation
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Flows Using Incremental Compilation
163
Source FileUse this setting to resynthesize the source code (with any new
assignments, and replace any previous synthesis or Fitter results).
If you modify the design source, the software automatically resynthesizes the
partitions with the appropriate netlist type, which makes the Source File
setting optional in this case.
Post-Synthesis (default)Use this setting to re-fit the design (with any new Fitter
assignments), but preserve the synthesis results when the source files have not
changed. If it is difficult to meet the required timing performance, you can use this
setting to allow the Fitter the most flexibility in placement and routing. This
setting does not reduce compilation time as much as the Post-Fit setting or
preserve timing performance from the previous compilation.
Post-FitUse this setting to preserve Fitter and performance results when the
source files have not changed. This setting reduces compilation time the most, and
preserves timing performance from the previous compilation.
The Quartus II software Rapid Recompile feature instructs the Compiler to reuse the
compatible compilation results if most of the design has not changed since the last
compilation. This feature reduces compilation time and preserves performance when
there are small and isolated design changes within a partition, and works with all
netlist type settings. With this feature, you do not have control over which parts of the
design are recompiled; the Compiler determines which parts of the design must be
recompiled. You can turn on the Rapid Recompile option in the Quartus II software
on the Incremental Compilation page of the Settings dialog box.
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Flows Using Incremental Compilation
In the standard incremental compilation flow, the top-level design is divided into
partitions, which can be compiled and optimized together in one Quartus II project. If
another team member or IP provider is developing source code for the top-level
design, they can functionally verify their partition independently, and then simply
provide the partitions source code to the project lead for integration into the top-level
design. If the project lead wants to compile the top-level design when source code is
not yet complete for a partition, they can create an empty placeholder for the partition
until the code is ready and added to the top-level design.
Compiling all design partitions in a single Quartus II project ensures that all design
logic is compiled with a consistent set of assignments, and allows the software to
perform global placement and routing optimizations. Compiling all design logic
together is beneficial for FPGA design flows because all parts of the design must use
the same shared set of device resources. Therefore, it is often easier to ensure good
quality of results when partitions are developed within a single top-level Quartus II
project.
In the team-based incremental compilation flow, you can design and optimize
partitions by accessing the top-level project from a shared source control system or
creating copies of the top-level Quartus II project framework. As development
continues, designers export their partition so that the post-synthesis netlist or postfitting results can be integrated into the top-level design.
If required for third-party IP delivery, or in cases where designers cannot access a
shared or copied top-level project framework, you can create and compile a design
partition logic in isolation and export a partition that is included in the top-level
project. If this type of design flow is necessary, planning and rigorous design
guidelines might be required to ensure that designers have a consistent view of
project assignments and resource allocations. Therefore, developing partitions in
completely separate Quartus II projects can be more challenging than having all
source code within one project or developing design partitions within the same toplevel project framework.
You can also combine design flows and use exported partitions only when it is
necessary to support your design environment. For example, if the top-level design
includes one or more design blocks that will be optimized by remote designers or IP
providers, you can integrate those blocks into the reserved partitions in top-level
design when the code is complete, but also have other partitions that will be
developed within the top-level design.
If any partitions are developed independently, the project lead must ensure that
top-level constraints (such as timing constraints, any relevant floorplan or pin
assignments, and optimization settings) are consistent with those used by all
designers working independently.
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Flows Using Incremental Compilation
165
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Why Plan Partitions and Floorplan Assignments?
Hierarchy A
Hierarchy A
Hierarchy B
Hierarchy B
Hierarchy A
Compile
with
partition
boundaries
Hierarchy B
You can use the Merge command in the Design Partitions window to combine
hierarchical partitions into a single partition, as long as they share the same
immediate parent partition. Merging partitions allows additional optimizations for
partition I/O ports that connect between or feed more than one of the merged
hierarchical design blocks.
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Why Plan Partitions and Floorplan Assignments?
167
When partitions are placed together, the Fitter can perform placement optimizations
on the design as a whole to optimize the placement of cross-boundary paths.
However, the Fitter can never perform logic optimizations such as physical synthesis
across the partition boundary. If partitions are fit separately in different projects, or if
some partitions use previous post-fitting results, the Fitter does not place and route
the entire cross-boundary path at the same time and cannot fully optimize placement
across the partition boundaries. Good design partitions can be placed independently
because cross-partition paths are not the critical timing paths in the design.
There are possible timing performance utilization effects due to partitioning and
creating a floorplan. Not all designs encounter these issues, but you should consider
these effects if a flat version of your design is very close to meeting its timing
requirements, or is close to using all the device resources, before adding partition or
floorplan assignments:
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
General Partitioning Guidelines
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
General Partitioning Guidelines
169
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines
Try to isolate timing-critical logic from logic that you expect to easily meet timing
requirements. Doing so allows you to preserve the satisfactory results for non-critical
partitions and focus optimization iterations on only the timing-critical portions of the
design to minimize compilation time.
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines
1611
Partition B
Cross-boundary partition
routing delay is not the
critical timing path
If a design cannot include both input and output registers for each partition due to
latency or resource utilization concerns, choose to register one end of each connection.
If you register every partition output, for example, the combinational logic that occurs
in each cross-partition path is included in one partition so that it can be optimized
together.
It is a good synchronous design practice to include registers for every output of a
design block. Registered outputs ensure that the input timing performance for each
design block is controlled exclusively within the destination logic block. For more
information about I/O ports and registers for each partition, refer to Partition
Statistics Report on page 1634, and Incremental Compilation Advisor on
page 1649.
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines
When dividing your design into partitions, consider the types of functions at the
partition boundaries. Figure 163 shows an expansive function with more outputs
than inputs in the left diagram, which makes a poor partition boundary, and, on the
right side, a better place to assign the partition boundary that minimizes
cross-partition I/Os. Adding registers to one or both sides of the cross-partition path
in this example would further improve partition quality.
Figure 163. Minimizing I/O Between Partitions by Moving the Partition Boundary
Expansive function:
Not ideal partition boundary
Glue
Logic
C
A
B
Glue
Logic
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines
1613
For more information about the number of I/O ports, as well as the number of
inter-partition connections for each partition, refer to Partition Statistics Report on
page 1634. For more information about the number of intra-partition (within a
partition) and inter-partition (between partitions) timing edges, refer to Incremental
Compilation Advisor on page 1649.
Keep Logic in the Same Partition for Optimization and Merging on page 1613
Avoid Signals That Drive Multiple Partition I/O or Connect I/O Together on
page 1616
Connect I/O Pin Directly to I/O Register for Packing Across Partition
Boundaries on page 1617
Include All Tri-State and Enable Logic in the Same Partition on page 1622
Include Bidirectional I/O Registers in the Same Partition (For Older Device
Families) on page 1623
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines
If a combinational logic path is split across two partitions, the logic cannot be
optimized or merged into one logic cell in the device. This effect can result in an extra
logic cell in the path, increasing the logic delay. As a very simple example, consider
two inverters on the same signal in two different partitions, A and B, as shown in the
left diagram of Figure 165. To maintain correct incremental functionality, these two
inverters cannot be removed from the design during optimization because they occur
in different design partitions. The Quartus II software cannot use information about
other partitions when it compiles each partition, because each partition is allowed to
change independently from the other.
On the right side of the figure, partitions A and B are merged to group the logic in
blocks A and B into one partition. If the two blocks A and B are not under the same
immediate parent partition, you can create a wrapper file to define a new level of
hierarchy that contains both blocks, and set this new hierarchy block as the partition.
With the logic contained in one partition, the software can optimize the logic and
remove the two inverters (shown in gray), which reduces the delay for that logic path.
Removing two inverters is not a significant reduction in resource utilization because
inversion logic is readily available in Altera device architecture. However, this
example is a simple demonstration of the types of logic optimization that are
prevented by partition boundaries.
Figure 165. Keeping Logic in the Same Partition for Optimization
Merged Parition
In a flat design, the Fitter can also merge logical instantiations into the same physical
device resource. With incremental compilation, logic defined in different partitions
cannot be merged to use the same physical device resource.
For example, the Fitter can merge two single-port RAMs from a design into one
dedicated RAM block in the device. If the two RAMs are defined in different
partitions, the Fitter cannot merge them into one dedicated device RAM block.
This limitation is a only a concern if merging is required to fit the design in the target
device. Therefore, you are more likely to encounter this issue during troubleshooting
rather than during planning, if your design uses more logic than is available in the
device.
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines
1615
VCC
Merged Partition
VCC
GND
GND
For more information about how many input ports are fed by GND or VCC, refer to
Partition Statistics Report on page 1634. For more information about port
connections, refer to Incremental Compilation Advisor on page 1649.
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines
Avoid Signals That Drive Multiple Partition I/O or Connect I/O Together
Do not use the same signal to drive multiple ports of a single partition or directly
connect two ports of a partition. If the same signal drives multiple ports of a partition,
or if two ports of a partition are directly connected, those ports are logically
equivalent. However, the software has limited information about connections made in
another partition (including the top-level partition), the compilation cannot take
advantage of the equivalence. This restriction usually produces sub-optimal results.
If your design has these types of connections, redefine the partition boundaries to
remove the affected ports. If one signal from a higher-level partition feeds two input
ports of the same partition, feed the one signal into the partition, and then make the
two connections within the partition. If an output port drives an input port of the
same partition, the connection can be made internally without going through any I/O
ports. If an input port drives an output port directly, the connection can likely be
implemented without the ports in the lower-level partition by connecting the signals
in a higher-level partition.
Figure 167 shows an example of one signal driving more than one port. The left
diagram shows a design where a single clock signal is used to drive both the read and
write clocks of a RAM block. Because the RAM block is compiled as a separate
partition A, the RAM block is implemented as though there are two unique clocks. If
you know that the port connectivity will not change (that is, the ports will always be
driven by the same signal in the top-level partition), redefine the port interface so that
there is only a single port that can drive both connections inside the partition. You can
create a wrapper file to define a partition that has fewer ports, as shown in the
diagram on the right side. With the single clock fed into the partition, the RAM can be
optimized into a single-clock RAM instead of a dual-clock RAM. Single-clock RAM
can provide better performance in the device architecture. Additionally, partition A
might use two global routing lines for the two copies of the clock signal. Partition B
can use one global line that fans out to all destinations. Using just the single port
connection prevents overuse of global routing resources.
Figure 167. Preventing One Signal from Driving Multiple Partition Inputs
Top
Top
rd_clk
Clock
wr_clk
Dualclock
RAM
A
rd_clk
Clock
wr_clk
Singleclock
RAM
A
For more information about partition ports that have the same driving signal and
ports that are directly connected together, refer to Incremental Compilation Advisor
on page 1649.
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines
1617
Top
Clock
Clock
Notice that this diagram also shows another example of a single pin feeding two ports
of a partition boundary. In the left diagram, partition B does not have the information
that the clock and inverted clock come from the same source. In the right diagram,
partition B has more information to help optimize the design because the clock is
connected as one port of the partition.
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines
The path between the input pin and register includes only input ports of partitions
that have one fan-out each.
The path between the register and output pin includes only output ports of
partitions that have one fan-out each.
The following examples of I/O register packing illustrate this point using Block
Design File (.bdf) schematics to describe the design logic.
Example 1Output Register in Partition Feeding Multiple Output Pins
In this example, a subdesign contains a single register, as shown in Figure 169.
Figure 169. Subdesign with One Register, Designated as a Separate Partition
If the top-level design instantiates the subdesign with a single fan-out directly feeding
an output pin, and designates the subdesign as a separate design partition, the
Quartus II software can perform cross-partition register packing because the single
partition port feeds the output pin directly.
In Example 1, the top-level design instantiates the subdesign in Figure 169 as an
output register with more than one fan-out signal, as shown in Figure 1610.
Figure 1610. Top-Level Design Instantiating the Subdesign in Figure 169 with Two Output Pins
In this case, the Quartus II software does not perform output register packing. If there
is a Fast Output Register assignment on pin out, the software issues a warning that
the Fitter cannot pack the node to an I/O pin because the node and the I/O cell are
connected across a design partition boundary.
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Design Partition Guidelines
1619
Place the register in the same partition as the output pin. The simplest method
is to move the register from the subdesign partition into the partition
containing the output pin. Doing so guarantees that the Fitter can optimize the
two nodes without violating partition boundaries.
Duplicate the register in your subdesign HDL as shown in Figure 1611 so that
each register feeds only one pin, and then connect the extra output pin to the
new port in the top-level design as shown in Figure 1612. Doing so converts
the cross-partition register packing into the simplest case where each register
has a single fan-out.
Figure 1611. Modified Subdesign from Figure 169 with Two Output Registers and Two Output Ports
Figure 1612. Modified Top-Level Design from Figure 1610 Connecting Two Output Ports to Output Pins
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Design Partition Guidelines
Example 2Input Register in Partition Fed by an Inverted Input Pin or Output Register in
Partition Feeding an Inverted Output Pin
In this example, a subdesign designated as a separate partition contains a register, as
shown in Figure 169. The top-level design in Figure 1613 instantiates the subdesign
as an input register with the input pin inverted. The top-level design in Figure 1614
instantiates the subdesign as an output register with the signal inverted before
feeding an output pin.
Figure 1613. Top-Level Design Instantiating the Subdesign in Figure 169 as an Input Register with an Inverted Input
Pin
Figure 1614. Top-Level Design Instantiating the Subdesign in Figure 169 as an Output Register Feeding an Inverted
Output Pin
In these cases, the Quartus II software does not perform register packing. If there is a
Fast Input Register assignment on pin in, as shown in Figure 1613, or a Fast Output
Register assignment on pin out, as shown in Figure 1614, the Quartus II software
issues a warning that the Fitter cannot pack the node to an I/O pin because the node
and I/O cell are connected across a design partition boundary.
This type of register packing is not allowed because it requires moving logic across a
design partition boundary to place into a single I/O device atom. To perform register
packing, either the register must be moved out of the subdesign partition, or the
inverter must be moved into the subdesign partition to be implemented in the
register.
To allow the Quartus II software to pack the register in the subdesign from
Figure 169 with the input pin in, as shown in Figure 1613 or the output pin out, as
shown in Figure 1614, restructure your HDL code to place the register in the same
partition as the inverter by making one of the following changes:
Move the register from the subdesign partition into the top-level partition
containing the pin. Doing so ensures that the Fitter can optimize the I/O register
and inverter without violating partition boundaries.
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Design Partition Guidelines
1621
Move the inverter from the top-level block into the subdesign, and then connect
the subdesign directly to a pin in the top-level design. Doing so allows the Fitter to
optimize the inverter into the register implementation, so that the register is
directly connected to a pin, which enables register packing.
Figure 1616. Merged Partition Allows Synthesis to Convert Internal Tri-State Logic to Combinational Logic
Top
Merged Partition
Merged partition allows synthesis to
convert tri-state logic into
combinational logic.
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Design Partition Guidelines
A
A
Top
B
Top
B
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines
1623
Include Bidirectional I/O Registers in the Same Partition (For Older Device
Families)
For a bidirectional partition port that feeds a bidirectional I/O pin at the top level, all
logic that forms the bidirectional I/O cell must reside in the same partition in the
Stratix II, Stratix, Cyclone II, and Cyclone device families (this restriction does not
apply to newer devices). Additionally, as discussed in the previous two
recommendations, the I/O logic must feed the I/O pin without any intervening logic.
In Figure 1618, all the I/O logic must be defined inside the same partition for the
Quartus II software to implement all three registers in the I/O element along with the
tri-state logic in the affected devices. The logic connected to the registers can occur in
the same partition or any other partition; only the I/O registers must be grouped with
the tri-state logic definition. The bidirectional I/O port of the partition must be
directly connected to the bidirectional device pin at the top level. The signal can go
through several partition boundaries if necessary, as long as the connection path
contains no logic.
Figure 1618. Including All Bidirectional I/O Registers in the Same Partition (for Older Devices)
Top
Output Enable Register
D
Output
Register
Logic
to/from
any
partition
Tri-State
Logic
Bidir.
pin
Input
Register
Partition
Bidirectional logic is within one partition, and I/O logic directly feeds I/O pin
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Avoid signals that drive multiple partition I/O or connect I/O together
Connect I/O directly to I/O register for packing across partition boundaries
Include bidirectional I/O registers in the same partition (in older device families)
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines for Third-Party IP Delivery
1625
False Timing
Paths
Top
VCC
D
A_Reset
CLRN
CLRN
VCC
D
Q
VCC
CLRN
CLRN
B_Reset
Reset
CLRN
CLRN
This circuit design can help you achieve timing closure and partition independence
for your global reset signal. Evaluate the circuit and consider how it works for your
design.
f For more information and design recommendations for reset structures, refer to the
Recommended Design Practices chapter in volume 1 of the Quartus II Handbook.
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines for Third-Party IP Delivery
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines for Third-Party IP Delivery
1627
If the exported IP core is small, you can reduce the potential for problems by using
constraints to promote clock and high fan-out signals to regional routing signals that
cover only part of the device, instead of global routing signals. In this case, the
Quartus II software is likely to find a routing solution in the top-level design because
there are many regional routing signals available on most Altera devices, and designs
do not typically overuse regional resources.
To ensure that an IP block can utilize a regional clock signal, view the resource
coverage of regional clocks in the Chip Planner, and then align LogicLock regions that
constrain partition placement with available global clock routing resources. For
example, if the LogicLock region for a particular partition is limited to one device
quadrant, that partitions clock can use a regional clock routing type that covers only
one device quadrant. When all partition logic is available, the project lead can compile
the entire design at the top level with floorplan assignments to allow the use of
regional clocks that span only a part of the device.
If global resources are heavily used in the overall design, or the IP designer requires
global clocks for their partition, you can set up constraints to avoid signal overuse at
the top-level by assigning the appropriate type of global signals or setting a maximum
number of clock signals for the partition.
You can use the Global Signal assignment to force or prevent the use of a global
routing line, making the assignment to a clock source node or signal. You can also
assign certain types of global clock resources in some device families, such as regional
clocks. For example, if you have an IP core, such as a memory interface that specifies
the use of a dual regional clock, you can constrain the IP to part of the device covered
by a regional clock and change the Global Signal assignment to use a regional clock.
This type of assignment can reduce clocking congestion and conflicts.
Alternatively, partition designers can specify the number of clocks allowed in the
project using the maximum clocks allowed options in the More Fitter Settings dialog
box. Specify Maximum number of clocks of any type allowed, or use the Maximum
number of global clocks allowed, Maximum number of regional clocks allowed,
and Maximum number of periphery clocks allowed options to restrict the number of
clock resources of a particular type in your design.
If you require more control when planning a design with integrated partitions, you
can assign a specific signal to use a particular clock network in Stratix II and newer
device families by assigning the clock control block instance called CLKCTRL. You
can make a point-to-point assignment from a clock source node to a destination node,
or a single-point assignment to a clock source node with the Global Clock CLKCTRL
Location logic option. Set the assignment value to the name of the clock control block:
CLKCTRL_G<global network number> for a global routing network, or CLKCTRL_R<regional
network number> for a dedicated regional routing network in the device.
If you want to disable the automatic global promotion performed in the Fitter to
prevent other signals from being placed on global (or regional) routing networks, turn
off the Auto Global Clock and Auto Global Register Control Signals options in the
More Fitter Settings dialog box.
h For information about how to disable automatic global promotion, refer to More Fitter
Settings Dialog Box in Quartus II Help.
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines for Third-Party IP Delivery
If you are using design partition scripts for independent partitions, the Quartus II
software can automatically write the commands to pass global constraints and turn
off automatic options.
h For more information about how to generate design partition scripts, refer to
Generating Design Partition Scripts for Project Management in Quartus II Help.
f For more information about how clock networks affect partition design, refer to the
Analyzing and Optimizing the Design Floorplan with the Chip Planner chapter in volume 2
of the Quartus II Handbook.
Alternatively, to avoid problems when integrating partitions into the top-level design,
you can direct the Fitter to discard the placement and routing of the partition netlist
by using the post-synthesis netlist, which forces the Fitter to reassign all the global
signals for the partition when compiling the top-level design.
Tri-state outputs cannot be assigned as virtual pins because internal tri-state signals
are not supported in Altera devices. Connect the signal in the design with regular
logic, or allow the software to implement the signal as an external device I/O pin.
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Partition Guidelines for Third-Party IP Delivery
1629
delay between the logic can lead to problems in meeting timing requirements. You can
reduce this effect by ensuring that input and output ports of the partitions are
registered whenever possible. Additionally, using the same top-level project
framework helps to avoid this problem by providing the software with full
information about other design partitions in the top-level design.
To ensure that the software correctly optimizes the input and output logic in any
independent partitions, you might be required to perform some manual timing
budgeting. For each unregistered timing path that crosses between partitions, make
timing assignments on the corresponding I/O path in each partition to constrain both
ends of the path to the budgeted timing delay. Assigning a timing budget for each
part of the connection ensures that the software optimizes the paths appropriately.
When performing manual timing budgeting in a partition for I/O ports that become
internal partition connections in a top-level design, you can assign location and
timing constraints to the virtual pin that represents each connection to further
improve the quality of the timing budget. Refer to Assign Virtual Pins on
page 1628 for a description of virtual pins.
1
If you use design partition scripts, the Quartus II software can write I/O timing
budget constraints automatically for virtual pins.
h For more information about how to generate design partition scripts, refer to
Generating Design Partition Scripts for Project Management in Quartus II Help.
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Checking Partition Quality
If the project lead creates a copy of the top-level project framework that includes all
the settings and constraints needed for the design, this framework should include
PLLs and other interface logic if this information is important to optimize partitions.
If you use a separate Quartus II project for an independent design block (such as
when a designer or third-party IP provider does not have access to the entire design
framework), include a copy of the top-level PLL in the lower-level partition as shown
in Figure 1620.
In either case, the IP partition in the separate Quartus II project should contain just the
partition logic that will be exported to the top-level design, while the full project
includes more information about the top-level design. When the partition is complete,
you can export just the partition without exporting the auxiliary PLL components to
the top-level design. When you export a partition, the Quartus II software exports any
hierarchy under the specified partition into the Quartus II Exported Partition File
(.qxp), but does not include logic defined outside the partition (the PLL in this
example).
Figure 1620. Recreating a Top-Level PLL in a Lower-Level Partition
Top Partition
in Lower-Level
Project
Virtual
Input
Pins
PLL From
Top-Level
Design
Device Input
Clock
Lower-Level
Partition
to be
Exported
Virtual
Output
Pins
Outputs to
Device Pins
Other Inputs
from Device
Pins
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Checking Partition Quality
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Checking Partition Quality
Figure 1621 shows the Design Partition Planner after making a design partition
assignment to one instance and dragging another instance away from the top-level
block within the same partition (two design blocks in the pale blue shaded box). The
figure shows the connections between each partition and information about the size
of each design instance.
Figure 1621. Design Partition Planner
You can switch between connectivity display mode and hierarchical display mode, or
temporarily to a view-only hierarchy display. You can also remove the connection
lines between partitions and I/O banks by turning off Display connections to I/O
banks, or use the settings on the Connection Counting tab in the Bundle
Configuration dialog box to adjust how the connections are counted in the bundles.
To optimize design performance, confine failing paths within individual design
partitions so that there are no failing paths passing between partitions, as discussed in
earlier sections. In the top-level entity, child entities that contain failing paths are
marked by a small red dot in the upper right corner of the entity box.
To view the critical timing paths from a timing analyzer report, first perform a timing
analysis on your design, and then in the Design Partition Planner, click Show Timing
Data on the View menu.
h For more information about the Design Partition Planner, refer to About the Design
Partition Planner and Using the Design Partition Planner in Quartus II Help.
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Checking Partition Quality
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Checking Partition Quality
Figure 1622 shows a design displayed in the Design Partition Planner and the Chip
Planner with different colors for the top-level design and the three major design
instances.
Figure 1622. Design Partition Planner and Chip Planner
h For more information about the Design Partition Planner, refer to About the Design
Partition Planner and Using the Design Partition Planner in Quartus II Help.
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Checking Partition Quality
1635
You can also view statistics about the resource and port connections for a particular
partition on the Statistics tab of the Design Partition Properties dialog box. The
Show All Partitions button allows you to view all the partitions in the same report.
The Partition Merge Partition Statistics report also shows statistics for the Internal
Congestion: Total Connections and Registered Connections. This information
represents how many signals are connected within the partition. It then lists the
inter-partition connections for each partition, which helps you to see how partitions
are connected to each other.
h For more information about the Partition Merge Reports, refer to Partition Merge
Reports in Quartus II Help.
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Including SDC Constraints from Lower-Level Partitions for Third-Party IP Delivery
6. Even if the quality of results is acceptable, you can repeat step 3 through step 5 by
further dividing a large partition into several smaller partitions, which can
improve compilation time in subsequent incremental compilations. You can repeat
these steps until you achieve a good trade-off point (that is, all critical paths are
localized within partitions, the quality of results is not negatively affected, and the
size of each partition is reasonable).
You can also remove or disable partition assignments defined in the top-level design
at any time during the design flow to compile the design as one flat compilation and
get all possible design optimizations to assess the results. To disable the partitions
without deleting the assignments, use the Ignore partition assignments during
compilation option on the Incremental Compilation page of the Settings dialog box
in the Quartus II software. This option disables all design partition assignments in
your project and runs a full compilation, ignoring all partition boundaries and
netlists. This option can be useful if you are using partitions to reduce compilation
time as you develop various parts of the design, but can run a long compilation near
the end of the design cycle to ensure the design meets its timing requirements.
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Including SDC Constraints from Lower-Level Partitions for Third-Party IP Delivery
1637
This section uses the example design shown in Figure 1623 to illustrate these
recommendations. The top-level design instantiates a lower-level design block called
module_A that is set as a design partition and developed by an IP designer in a
separate Quartus II project.
Figure 1623. Example Design to Illustrate SDC Constraints
In this top-level design, there is a single clock setting called clk associated with the
FPGA input called top_level_clk. The top-level .sdc contains the following
constraint for the clock:
create_clock -name {clk} -period 3.000 -waveform { 0.000 1.500 }
[get_ports {TOP_LEVEL_CLK}]
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Including SDC Constraints from Lower-Level Partitions for Third-Party IP Delivery
Virtual clocks and generated clocks that are consistently used for source
synchronous interfaces
Clock uncertainties
Additionally, the .sdc with project-wide constraints should contain all project-wide
timing exception assignments, such as the following:
The designer of module_A includes this .sdc as part of the separate Quartus II project.
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Including SDC Constraints from Lower-Level Partitions for Third-Party IP Delivery
1639
The partition-specific .sdc is used in the separate Quartus II project and must be
exported back to the project lead for the top-level design. The project lead must use
the partition-specific constraints to properly constrain the placement, routing, or both,
if the partition logic is fit at the top level, and to ensure that final timing sign-off is
accurate. Use the following guidelines in the partition-specific .sdc to simplify these
export and integration steps:
Create a hierarchy variable for the partition (such as module_A_hierarchy) and set
it to an empty string because the partition is the top-level instance in the separate
Quartus II project. The project lead modifies this variable for the top-level
hierarchy, reducing the effort of translating constraints on lower-level design
hierarchies into constraints that apply in the top-level hierarchy. Use the following
Tcl command first to check if the variable is already defined in the project, so that
the top-level design does not use this empty hierarchy path: if {![info exists
module_A_hierarchy]}.
Use the hierarchy variable in the partition-specific .sdc as a prefix for assignments
in the project. For example, instead of naming a particular instance of a register
reg:inst, use ${module_A_hierarchy}reg:inst. Also, use the hierarchy variable
as a prefix to any wildcard characters (such as * ).
Pay attention to the location of the assignments to I/O ports of the partition. In
most cases, these assignments should be specified in the .sdc with project-wide
constraints, because the partition interface depends on the top-level design. If you
want to set I/O constraints within the partition, the team must ensure that the I/O
port names are identical in all projects so that the assignments can be integrated
successfully without changes.
If the design team follows these recommendations, the project lead should be able to
include the .sdc with the partition-specific constraints provided by the partition
designer directly in the top-level design.
Example Step 2: Partition Designer Creates .sdc with Partition-Specific Constraints
The partition designer compiles the design with the .sdc with project-wide constraints
and might want to add some additional constraints. In this example, the designer
realizes that he or she must specify a false path between the register called reg_in_1
and all destinations in this design block with the wildcard character (such as * ).
This constraint applies entirely within the partition and must be exported to the
top-level design, so it qualifies for inclusion in the .sdc with partition-specific
constraints. The designer first defines the module_A_hierarchy variable and uses it
when writing the constraint as follows:
if {![info exists module_A_hierarchy]} {
set module_A_hierarchy ""
}
set_false_path -from [get_registers ${module_A_hierarchy}reg_in_1] -to
[get_registers ${module_A_hierarchy}*]
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Introduction to Design Floorplans
When the project lead performs top-level timing analysis, the false path assignment
from the lower-level module_A project expands to the following:
set_false_path -from module_A:inst|reg_in_1 -to module_A:inst|*
Adding the hierarchy path as a prefix to the SDC command makes the constraint legal
in the top-level design, and ensures that the wildcard does not affect any nodes
outside the partition that it was intended to target.
By following the guidelines in this section, constraint propagation between the
separate Quartus II projects can be managed effectively.
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Introduction to Design Floorplans
1641
Location assignments for each partition ensure that there are no placement conflicts
between partitions. If there are no LogicLock region assignments, or if LogicLock
regions are set to auto-size or floating location, no device resources are specifically
allocated for the logic associated with the region. If you do not clearly define resource
allocation, logic placement can conflict when you integrate the partitions in the
top-level design if you reuse the placement information from the exported netlist.
Creating a floorplan is also recommended for timing-critical partitions that have little
timing margin to maintain good quality of results when the design changes.
Floorplan assignments are not required for non-critical partitions compiled in the
same Quartus II project. The logic for partitions that are not timing-critical can be
placed anywhere in the device on each recompilation if that is best for your design.
Design floorplan assignments prevent the situation in which the Fitter must place a
partition in an area of the device where most resources are used by other partitions. A
LogicLock region provides a reasonable region to re-place logic after a change, so the
Fitter does not have to scatter logic throughout the available space in the device.
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Introduction to Design Floorplans
Figure 1624 illustrates the problems that may be associated with refitting designs
that do not have floorplan location assignments. The left floorplan shows the initial
placement of a four-partition design (P1-P4) without any floorplan location
assignments. The right floorplan shows the device if a change occurs to P3. After
removing the logic for the changed partition, the Fitter must re-place and reroute the
new logic for P3 in the scattered white space shown in Figure 1624. The placement of
the post-fit netlists for other partitions forces the Fitter to implement P3 with the
device resources that have not been used.
Figure 1624. Representation of Device Floorplan without Location Assignments
P2
P1
P3
P2
P1
P3
P1
P4
Change in P3
P1
P2
P4
P2
P1
P1
P3
The Fitter has a more difficult task because of more difficult physical constraints, and
as a result, compilation time often increases. The Fitter might not be able to find any
legal placement for the logic in partition P3, even if it could in the initial compilation.
Additionally, if the Fitter can find a legal placement, the quality of results often
decreases in these cases, sometimes dramatically, because the new partition is now
scattered throughout the device.
Figure 1625 shows the initial placement of a four-partition design with floorplan
location assignments. Each partition is assigned to a LogicLock region. The second
part of the figure shows the device after partition P3 is removed. This placement
presents a much more reasonable task to the Fitter and yields better results.
Figure 1625. Representation of Device Floorplan with Location Assignments
P2
P3
P2
Change in P3
P1
P4
P1
P4
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Floorplan Placement Guidelines
1643
Early Floorplan
An early floorplan is created before the design stage. You can plan an early floorplan
at the top level of a design to allocate each partition a portion of the device resources.
Doing so allows the designer for each block to create the logic for their design
partition without conflicting with other logic. Each partition can be optimized in a
separate Quartus II project if required, and the design can still be easily integrated in
the top-level design. Even within one Quartus II project, each partition can be locked
down with a post-fit netlist, and you can be sure there is space in the device floorplan
for other partitions.
When you have compiled your complete design, or after you have integrated the first
versions of partitions developed in separate Quartus II projects, you can use the
design information and Quartus II features to tune and improve the floorplan, as
described in the following section.
Late Floorplan
A late floorplan is created or modified after the design is created, when the code is
close to complete and the design structure is likely to remain stable. Creating a late
floorplan is typically necessary only if you are starting to use incremental compilation
late in the design flow, or need to reserve space for a logic block that becomes
timing-critical but still has HDL changes to be integrated. When the design is
complete, you can take advantage of the Quartus II analysis features to check the
floorplan quality. To adjust the floorplan, you can perform iterative compilations as
required and assess the results of different assignments.
1
It may not be possible to create a good-quality late floorplan if you do not create
partitions in the early stages of the design.
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Floorplan Placement Guidelines
Floorplan assignments can help maintain good performance when designs change
incrementally, as described in Why Create a Floorplan? on page 1641. However,
poor placement assignments in an incremental compilation can often adversely affect
performance results, as compared to a flat compilation, because the assignments limit
the options for the Fitter. Investing time to find good region placement is required to
match the performance of a full flat compilation.
Use the following general procedure to create a floorplan:
1. Divide the design into partitions.
2. Assign the partitions to LogicLock regions.
3. Compile the design.
4. Analyze the results.
5. Modify the placement and size of regions, as required.
You might have to perform these steps several times to find the best combination of
design partitions and LogicLock regions that meet the resource and timing goals of
the design.
f For more information about performing these steps, refer to the Quartus II Incremental
Compilation for Hierarchical and Team-Based Design chapter in volume 1 of the Quartus II
Handbook.
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Floorplan Placement Guidelines
1645
It is important that you use the Fitter-chosen locations only as a starting point to give
the regions a good fixed size and location. Ensure that all LogicLock regions in the
design have a fixed size and have their origin locked to a specific location on the
device. On average, regions with fixed size and location yield better timing
performance than auto-sized regions.
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Floorplan Placement Guidelines
The easiest way to move and resize regions is to drag the region location and borders
in the Chip Planner. Make sure that you select the User-Defined region in the
floorplan (as opposed to the Fitter-Placed region from the last compilation) so that
you can change the region.
Generally, you can keep the Fitter-determined relative placement of the regions, but
make adjustments if required to meet timing performance. If you find that the early
timing estimate did not result in good relative placements, try performing a full
compilation so that the Fitter can optimize for a full placement and routing.
If two LogicLock regions have several connections between them, ensure they are
placed near each other to improve timing performance. By placing connected regions
near each other, the Fitter has more opportunity to optimize inter-region paths when
both partitions are recompiled. Reducing the criticality of inter-region paths also
allows the Fitter more flexibility when placing other logic in each region.
If resource utilization is low in the overall device, enlarge the regions. Doing so
usually improves the final results because it gives the Fitter more freedom to place
additional or modified logic added to the partition during subsequent incremental
compilations. It also allows room for optimizations such as pipelining and physical
synthesis logic duplication.
Try to have each region evenly full, with the same fullness that the complete design
would have without LogicLock regions; Altera recommends approximately 75% full.
Allow more area for regions that are densely populated, because overly congested
regions can lead to poor results. Allow more empty space for timing-critical partitions
to improve results. However, do not make regions too large for their logic. Regions
that are too large can result in wasted resources and also lead to suboptimal results.
Ideally, almost the entire device should be covered by LogicLock regions if all
partitions are assigned to regions.
Regions should not overlap in the device floorplan. If two partitions are allocated on
an overlapping portion of the chip, each may independently claim common resources
in this region. This leads to resource conflicts when integrating results into a top-level
design. In a single project, overlapping regions give more difficult constraints to the
Fitter and can lead to reduced quality of results.
You can create hierarchical LogicLock regions to ensure that the logic in a child
partition is physically placed inside the LogicLock region for its parent partition. This
can be useful when the parent partition does not contain registers at the boundary
with the lower-level child partition and has a lot of signal connectivity. To create a
hierarchical relationship between regions in the LogicLock Regions window, drag and
drop the child region to the parent region.
I/O Connections
Consider I/O timing when placing regions. Using I/O registers can minimize I/O
timing problems, and using boundary registers on partitions can minimize problems
connecting regions or partitions. However, I/O timing might still be a concern. It is
most important for flows where each partition is compiled independently, because the
Fitter can optimize the placement for paths between partitions if the partitions are
compiled at the same time.
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Floorplan Placement Guidelines
1647
Place regions close to the appropriate I/O, if necessary. For example, DDR memory
interfaces have very strict placement rules to meet timing requirements. Incorporate
any specific placement requirements into your floorplan as required. You should
create LogicLock regions for internal logic only, and provide pin location assignments
for external device I/O pins (instead of including the I/O cells in a LogicLock region
to control placement).
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MRAM
DSP
M4K RAM
M512 RAM
MRAM
DSP
M4K RAM
M512 RAM
Exclude DSP
blocks from
LogicLock region
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Design Floorplan Placement Guidelines
To view any resource exceptions, right-click in the LogicLock Regions window, and
then click LogicLock Regions Properties. In the LogicLock Regions Properties dialog
box, select the design element (module or entity) in the Members box, and then click
Edit. In the Edit Node dialog box, to set up a resource exception, click the Edit button
next to the Excluded element types box, and then turn on the design element types to
be excluded from the region. You can choose to exclude combinational logic or
registers from logic cells, or any of the sizes of TriMatrix memory blocks, or DSP
blocks.
If the excluded logic is in its own lower-level design entity (even if it is within the
same design partition), you can assign the entity to a separate LogicLock region to
constrain its placement in the device.
You can also use this feature with the LogicLock Reserved property to reserve specific
resources for logic that will be added to the design.
Creating Floorplan Location Assignments With Tcl CommandsExcluding or Filtering
Certain Device Elements (Such as RAM or DSP Blocks)
To assign a code block to a LogicLock region, with exclusions, use the following
command:
set_logiclock_contents -region <LogicLock region name> -to <block>
-exceptions \"<keyword>:<keyword>"
<LogicLock region name>The name of the LogicLock region to which the code
block is assigned.
blockA code block in a Quartus II project hierarchy, which can aslo be a design
partition.
Keyword variables:
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Checking Floorplan Quality
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Checking Floorplan Quality
h For information about the Statistics tab in the LogicLock Region Properties dialog
box, refer to LogicLock Region Properties Dialog Box in Quartus II Help.
Locate the Quartus II TimeQuest Timing Analyzer Path in the Chip Planner
In the TimeQuest analyzer user interface, you can locate a specific path in the Chip
Planner to view its placement and perform a report timing operation (for example,
report timing for all paths with less than 0 ns slack).
h For information about how to locate paths between the TimeQuest analyzer and the
Chip Planner, refer to Locate Dialog Box in Quartus II Help.
Routing Utilization
The Chip Planner includes a feature to display a color map of routing congestion. This
display helps identify areas of the chip that are too tightly packed.
In the Chip Planner, red LAB blocks indicate higher routing congestion. You can
position the mouse pointer over a LAB to display a tooltip that reports the logic and
routing utilization information.
h For information about how to how to view a color map of routing congestion in the
Chip Planner, refer to About the Chip Planner in Quartus II Help.
You should see only minor degradation in fMAX after the design is partitioned and
floorplan location assignments are created. There is some performance cost
associated with setting up a design for incremental compilation; approximately
3% is typical.
The area increase should be no more than 5% after the design is partitioned and
floorplan location assignments are created.
The time spent in the routing stage should not significantly increase.
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Recommended Design Flows and Application Examples
1651
The amount of compilation time spent in the routing stage is reported in the Messages
window with an Info message that indicates the elapsed time for Fitter routing
operations. If you notice a dramatic increase in routing time, the floorplan location
assignments may be creating substantial routing congestion. In this case, decrease the
number of LogicLock regions, which typically reduces the compilation time in
subsequent incremental compilations and may also improve design performance.
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Recommended Design Flows and Application Examples
Create a Floorplan Assignment for One Design Block with Difficult Timing
Use this flow when you have one timing-critical design block that requires more
optimization than the rest of your design. You can take advantage of incremental
compilation to reduce your compilation time without creating a full design floorplan.
In this scenario, you do not want to create floorplan assignments for the entire design.
Instead, you can create a region to constrain the location of your critical design block,
and allow the rest of the logic to be placed anywhere on the device. To create a region
for critical design block, follow these steps:
1. Divide up your design into partitions. Consider the guidelines in Design
Partition Guidelines on page 1610 to determine partition boundaries. Ensure
that you isolate the timing-critical logic in a separate partition.
2. Define a LogicLock region for the timing-critical partition. Ensure that you capture
the correct amount of device resources in the region. Turn on the Reserved
property to prevent any other logic from being placed in the region.
If the design block is not complete, reserve space in the design floorplan based
on your knowledge of the design specifications, connectivity between design
blocks, and estimates of the size of the partition based on any initial
implementation numbers.
If the critical design block has initial source code ready, compile the design to
place the LogicLock region. Save the Fitter-determined size and origin, and
then enlarge the region to provide more flexibility and allow for future design
changes.
As the rest of the design is completed, and the device fills up, the timing-critical
region reserves an area of the floorplan. When you make changes to the design block,
the logic will be re-placed in the same part of the device, which helps ensure good
quality of results.
Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Conclusion
1653
5. Create LogicLock regions for each partition to create a design floorplan. This
floorplan should consider the connectivity between partitions and estimates of the
size of each partition based on any initial implementation numbers and
knowledge of the design specifications. Use the guidelines described in this
chapter to choose a size and location for each LogicLock region.
6. Provide the constraints from the top-level design to partition designers using one
of the following procedures:
a. Create a copy of the top-level Quartus II project framework by checking out the
appropriate files from a source control system, using the Copy Project
command, or creating a project archive. Provide each partition designer with
the copy of the project.
b. Provide the constraints with documentation or scripts.
h To use design partition scripts to pass constraints and generate separate Quartus II
projects, refer to Generating Design Partition Scripts for Project Management in Quartus II
Help.
Conclusion
Incremental compilation can significantly improve your design productivity,
especially for large, complex designs. To take advantage of the feature, it is worth
spending time to create quality partition and floorplan assignments. Follow the
guidelines to set up your design hierarchy and source code for incremental
compilation.
Floorplan location assignments are required when design blocks are developed
independently and are recommended for timing-critical partitions that are expected
to change. Follow the guidelines to create and modify LogicLock regions to create
good placement assignments for your design partitions.
Remember that you do not have to follow all the guidelines exactly to implement an
incremental compilation design flow, but following the guidelines can maximize your
chances of success.
Version
Changes
November 2012
12.1.0
June 2012
12.0.0
November 2011
11.0.1
Template update.
May 2011
11.0.0
Updated links.
November 2012
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Chapter 16: Best Practices for Incremental Compilation Partitions and Floorplan Assignments
Document Revision History
Version
December 2010
July 2010
Changes
Removed the explanation of the bottom-up design flow where designers work
completely independently, and replaced with Alteras recommendations for team-based
environments where partitions are developed in the same top-level project framework,
plus an explanation of the bottom-up process for including independent partitions from
third-party IP designers.
Expanded the Merge command explanation to explain how it now accommodates crosspartition boundary optimizations.
Redefined the bottom-up design flow as team-based and reorganized previous design
flow examples to include steps on how to pass top-level design information to lower-level
projects.
Added I/O register packing examples from Incremental Compilation for Hierarchical and
Team-Based Designs chapter
10.1.0
10.0.0
October 2009
9.1.0
March 2009
9.0.0
November 2008
8.1.0
May 2007
8.0.0
Initial release.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
Section 4. Synthesis
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Section 4: Synthesis
This chapter describes the Integrated Synthesis design flow and provides scripting
techniques for applying all the options and settings described in this chapter.
As programmable logic designs become more complex and require increased
performance, advanced synthesis becomes an important part of a design flow. The
Altera Quartus II software includes advanced Integrated Synthesis that fully
supports VHDL, Verilog HDL, and Altera-specific design entry languages, and
provides options to control the synthesis process. With this synthesis support, the
Quartus II software provides a complete, easy-to-use solution.
This chapter contains the following sections:
f For examples of Verilog HDL and VHDL code synthesized for specific logic functions,
refer to the Recommended HDL Coding Styles chapter in volume 1 of the Quartus II
Handbook. For more information about coding with primitives that describe specific
low-level functions in Altera devices, refer to the Designing With Low-Level Primitives
User Guide.
Design Flow
The Quartus II Analysis & Synthesis stage of the compilation flow runs Integrated
Synthesis, which fully supports Verilog HDL, VHDL, and Altera-specific languages,
and major features of the SystemVerilog language. For more information, refer to
Language Support on page 174.
In the synthesis stage of the compilation flow, the Quartus II software performs logic
synthesis to optimize design logic and performs technology mapping to implement
the design logic in device resources such as logic elements (LEs) or adaptive logic
modules (ALMs), and other dedicated logic blocks. The synthesis stage generates a
single project database that integrates all your design files in a project (including any
netlists from third-party synthesis tools).
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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172
You can use Analysis & Synthesis to perform the following compilation processes:
Analyze Current Fileparses your current design source file to check for syntax
errors. This command does not report many semantic errors that require further
design synthesis. To perform this analysis, on the Processing menu, click Analyze
Current File.
Analysis & Elaborationchecks your design for syntax and semantic errors and
performs elaboration to identify your design hierarchy. To perform Analysis &
Elaboration, on the Processing menu, point to Start, and then click Start
Analysis & Elaboration.
For more information about the Hierarchy Elaboration flow, refer to Start
Hierarchy Elaboration Command (Processing Menu) in Quartus II Help.
The Quartus II Integrated Synthesis design and compilation flow consists of the
following steps:
1. Create a project in the Quartus II software and specify the general project
information, including the top-level design entity name.
2. Create design files in the Quartus II software or with a text editor.
3. On the Project menu, click Add/Remove Files in Project and add all design files to
your Quartus II project using the Files page of the Settings dialog box.
4. Specify Compiler settings that control the compilation and optimization of your
design during synthesis and fitting. For synthesis settings, refer to Quartus II
Synthesis Options on page 1723.
5. Add timing constraints to specify the timing requirements.
1
6. Compile your design. To synthesize your design, on the Processing menu, point to
Start, and then click Start Analysis & Synthesis. To run a complete compilation
flow including placement, routing, creation of a programming file, and timing
analysis, click Start Compilation on the Processing menu.
7. After obtaining synthesis and placement and routing results that meet your
requirements, program or configure your Altera device.
Integrated Synthesis generates netlists that enable you to perform functional
simulation or gate-level timing simulation, timing analysis, and formal verification.
173
Figure 171 shows the basic design flow using Quartus II Integrated Synthesis.
Figure 171. Quartus II Design Flow Using Quartus II Integrated Synthesis
AHDL (1)
BDF (2)
Functional/RTL
Simulation
Constraints
& Settings
Gate-Level
Functional
Simulation
Internal
Synthesis
Netlist
Constraints
& Settings
Fitter
Timing
Analyzer
Assembler
Gate-Level Timing
Simulation
Post
Placement and Routing
Simulation Files
(.vho/.vo and .sdo)
No
Post
Placement and Routing
Formal Verification File
(.vo)
Formal Verification
Using Source Code as
Golden Netlist, and VO
as Revised Netlist
Yes
Configuration/
Programming
Files (.sof/.pof)
Configure/Program Device
f For an overall summary of features in the Quartus II software, refer to the Introduction
to the Quartus II Software manual.
h For more information about Quartus II projects and the compilation flow, refer to
Managing Files in a Project and About Compilation Flows in Quartus II Help.
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Language Support
This section describes Quartus II Integrated Synthesis support for HDL, schematic
design entry, graphical state machine entry, and how to specify the Verilog HDL or
VHDL language version in your design. This section also describes language features
such as Verilog HDL macros, initial constructs and memory system tasks, and VHDL
libraries. Design Libraries on page 1712 describes how to compile and reference
design units in custom libraries, and Using Parameters/Generics on page 1716
describes how to use parameters or generics and pass them between languages.
To ensure that the Quartus II software reads all associated project files, add each file to
your Quartus II project by clicking Add/Remove Files in Project on the Project menu.
You can add design files to your project. You can mix all supported languages and
netlists generated by third-party synthesis tools in a single Quartus II project.
h You can also use the available templates in the Quartus II Text Editor for various
Verilog and VHDL features. For more information, refer to Insert Template Dialog Box
in Quartus II Help.
SystemVerilog-2005 (IEEE Standard 1800-2005) (the Compiler does not support all
constructs)
The Verilog HDL code samples provided in this document follow the Verilog-2001
standard unless otherwise specified. The Quartus II Compiler uses the Verilog-2001
standard by default for files that have the extension .v, and the SystemVerilog
standard for files that have the extension .sv.
If you use scripts to add design files, you can use the -HDL_VERSION command to
specify the HDL version for each design file. For more information, refer to Adding
an HDL File to a Project and Setting the HDL Version on page 1785.
The Quartus II software support for Verilog HDL is case sensitive in accordance with
the Verilog HDL standard. The Quartus II software supports the compiler directive
`define, in accordance with the Verilog HDL standard.
The Quartus II software supports the include compiler directive to include files with
absolute paths (with either / or \ as the separator), or relative paths. When
searching for a relative path, the Quartus II software initially searches relative to the
project directory. If the Quartus II software cannot find the file, the software then
searches relative to all user libraries and then relative to the directory location of the
current file.
For more information about specifying synthesis directives, refer to Synthesis
Directives on page 1727.
h For more information about Verilog HDL, refer to About Verilog HDL in Quartus II
Help.
175
h For more information about Quartus II Verilog HDL support, refer to Quartus II
Verilog HDL Support in Quartus II Help.
h For more information about specifying a default Verilog HDL version for all files,
refer to Specifying Verilog Input Settings in Quartus II Help.
h For more information about controlling the Verilog HDL version that compiles your
design in a design file with the VERILOG_INPUT_VERSION synthesis directive, refer to
verilog_input_version Synthesis Directive in Quartus II Help.
h For more information about Verilog HDL synthesis attributes and directives, refer to
Verilog HDL Synthesis Attributes and Directives in Quartus II Help.
Specify a library search order for resolving cell instances (as does a library
mapping file)
Specify overrides to the logical library search order for specified instances
Specify overrides to the logical library search order for all instances of specified
cells
Where:
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designthe keyword that starts a design statement for specifying the top of the
design.
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Table 171 lists the type of clauses for the config_rule_statement keyword:
Table 171. Type of Clauses for the config_rule_statement Keyword
Clause Type
Description
Specifies the logical libraries to search to resolve a default cell instance. A default cell instance is an
instance in the design that is not specified in a subsequent instance or cell clause in the configuration.
default
You specify these libraries with the liblist keyword. The following is an example of a default clause:
default liblist lib1 lib2;
Also specifies resolving default instances in the logical libraries (lib1 and lib2).
Because libraries are inherited, some simulators (for example, VCS) also search the default (or current)
library as well after the searching the logical libraries (lib1 and lib2).
Specifies a specific instance. The specified instance clause depends on the use of the following
keywords:
usespecifies that the instance is an instance of the specified cell in the specified logical library.
cell
A cell clause is similar to an instance clause, except that the cell clause specifies all instances of a
cell definition instead of specifying a particular instance. What it specifies depends on the use of the
liblist or use keywords:
liblistspecifies the logical libraries to search to resolve all instances of the cell.
Hierarchical Configurations
A design can have more than one configuration. For example, you can define a
configuration that specifies the source code you use in particular instances in a sub
hierarchy, then define a configuration for a higher level of the design.
Suppose, for example, a sub hierarchy of a design is an eight-bit adder and the RTL
Verilog code describes the adder in a logical library named rtllib and the gate-level
code describes the adder in a logical library named gatelib. If you want to use the
gate-level code for the 0 (zero) bit of the adder and the RTL level code for the other
seven bits, the configuration might appear as shown in Example 172:
Example 172.
config cfg1;
design aLib.eight_adder;
default liblist rtllib;
instance adder.fulladd0 liblist gatelib;
endconfig
177
If you are instantiating this eight-bit adder eight times to create a 64-bit adder, use
configuration cfg1 for the first instance of the eight-bit adder, but not in any other
instance. A configuration that would perform this function is shown in Example 173:
Example 173.
config cfg2;
design bLib.64_adder;
default liblist bLib;
instance top.64add0 use work.cfg1:config;
endconfig
The name of the unbound module may be different than the name of the cell that is
bounded to the instance.
Suffix :config
To distinguish between a module by the same name, use the optional extension
:config to refer to configuration names. For example, you can always refer to a cfg2
configuration as cfg2:config (even if the cfg2 module does not exist).
SystemVerilog Support
The Quartus II software supports the SystemVerilog constructs.
1
Designs written to support the Verilog-2001 standard might not compile with the
SystemVerilog setting because the SystemVerilog standard has several new reserved
keywords.
h For more information about the supported SystemVerilog constructs and the
supported Verilog-2001 features, refer to Quartus II Support for SystemVerilog and
Quartus II Support for Verilog 2001 in Quartus II Help.
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Initial blocks do not infer power-up conditions in some third-party EDA synthesis
tools. If you convert between synthesis tools, you must set your power-up conditions
correctly.
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Quartus II Integrated Synthesis supports the $readmemb and $readmemh system tasks
to initialize memories. Example 174 shows an initial construct that initializes an
inferred RAM with $readmemb.
Example 174. Verilog HDL Code: Initializing RAM with the readmemb Command
reg [7:0] ram[0:15];
initial
begin
$readmemb("ram.txt", ram);
end
When creating a text file to use for memory initialization, specify the address using
the format @<location> on a new line, and then specify the memory word such as
110101 or abcde on the next line. Example 175 shows a portion of a Memory
Initialization File (.mif) for the RAM in Example 174.
Example 175. Text File Format: Initializing RAM with the readmemb Command
@0
00000000
@1
00000001
@2
00000010
@e
00001110
@f
00001111
179
To specify multiple macros, you can repeat the option more than once, as in
Example 178.
Example 178. Specifying Verilog HDL Macros a = 2 and b = 3
quartus_map my_design --verilog_macro="a=2" --verilog_macro="b=3" r
VHDL Support
The Quartus II Compilers Analysis & Synthesis module supports the following
VHDL standards:
The Quartus II Compiler uses the VHDL 1993 standard by default for files that have
the extension .vhdl or .vhd.
1
The VHDL code samples provided in this chapter follow the VHDL 1993 standard.
To specify a default VHDL version for all files, follow these steps:
1. On the Assignments menu, click Settings.
2. In the Category list, expand Analysis & Synthesis Settings and select VHDL
Input.
3. On the VHDL Input page, under VHDL version, select the appropriate version,
and then click OK.
To override the default VHDL version for each VHDL design file, follow these steps:
1. On the Project menu, click Add/Remove Files in Project.
2. On the Files page, select the appropriate file in the list, and then click Properties.
3. In the HDL version list, select VHDL_2008, VHDL_1993, or VHDL_1987, and
then click OK.
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You can also specify the VHDL version that compiles your design for each design file
with the VHDL_INPUT_VERSION synthesis directive, as shown in Example 179. This
directive overrides the default HDL version and any HDL version specified in the File
Properties dialog box.
Example 179. Controlling the VHDL Input Version with a Synthesis Directive
--synthesis VHDL_INPUT_VERSION <language version>
Example 1710. VHDL 2008Controlling the VHDL Input Version with a Synthesis Directive
/* synthesis VHDL_INPUT_VERSION <language version> */
VHDL_1987
VHDL_1993
VHDL_2008
VHDL-2008 Support
The Quartus II software contains support for VHDL 2008 with constructs defined in
the IEEE Standard 1076-2008 version of the IEEE Standard VHDL Language Reference
Manual.
h For more information, refer to Quartus II Support for VHDL 2008 in Quartus II Help.
1711
Altera recommends that you import component declarations for Altera primitives
such as GLOBAL and DFFE from the altera_primitives_components package and not
the altera_mf_components package.
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AHDL Support
The Quartus II Compilers Analysis & Synthesis module fully supports the Altera
Hardware Description Language (AHDL).
AHDL designs use Text Design Files (.tdf). You can import AHDL Include Files (.inc)
into a .tdf with an AHDL include statement. Altera provides .inc files for all
megafunctions shipped with the Quartus II software.
1
The AHDL language does not support the synthesis directives or attributes in this
chapter.
h For more information about AHDL, refer to About AHDL in the Quartus II Help.
Schematic entry methods do not support the synthesis directives or attributes in this
chapter.
h For information about creating and editing schematic designs, refer to About Schematic
Design Entry in Quartus II Help.
Design Libraries
By default, the Quartus II software compiles all design files into the work library. If
you do not specify a design library, if a file refers to a library that does not exist, or if
the referenced library does not contain a referenced design unit, the Quartus II
software searches the work library. This behavior allows the Quartus II software to
compile most designs with minimal setup, but you have the option of creating
separate custom design libraries.
To compile your design files into specific libraries (for example, when you have two
or more functionally different design entities that share the same name), you can
specify a destination library for each design file in various ways, as described in the
following subsections:
Specifying a Destination Library Name in the Settings Dialog Box on page 1713
Specifying a Destination Library Name in the Quartus II Settings File or with Tcl
on page 1713
1713
When the Quartus II Compiler analyzes the file, it stores the analyzed design units in
the destination library of the file.
1
A design can contain two or more entities with the same name if the Quartus II
software compiles the entities into separate libraries.
When compiling a design instance, the Quartus II software initially searches for the
entity in the library associated with the instance (which is the work library if you do
not specify any library). If the Quartus II software could not locate the entity
definition, the software searches for a unique entity definition in all design libraries. If
the Quartus II software finds more than one entity with the same name, the software
generates an error. If your design uses multiple entities with the same name, you must
compile the entities into separate libraries.
In VHDL, you can associate an instance with an entity in several ways, as described in
Mapping a VHDL Instance to an Entity in a Specific Library on page 1714. In
Verilog HDL, BDF schematic entry, AHDL, VQM and EDIF netlists, you can use
different libraries for each of the entities that have the same name, and compile the
instantiation into the same library as the appropriate entity.
For more information about Tcl scripting, refer to Scripting Support on page 1784.
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You can specify a single destination library for all your design units in a given source
file by specifying the library name in the Settings dialog box, editing the .qsf, or using
the Tcl interface. To organize your design units in a single file into different libraries
rather than just a single library, you can use the library directive to change the
destination VHDL library in a source file.
The Quartus II software generates an error if you use the library directive in a design
unit.
1715
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Example 1717. VHDL Code: Default Binding to the Directly Visible Entity
use mylib.foo; -- make entity foo in library mylib directly visible
architecture rtl of top
component foo is
generic (...)
port (...);
end component;
begin
-- This instance will be bound to entity foo in library mylib
inst: foo
port map(...);
end architecture rtl;
Using Parameters/Generics
This section describes how the Quartus II software supports parameters (known as
generics in VHDL) and how you can pass these parameters between design
languages.
You can enter default parameter values for your design in the Default Parameters
page under the Analysis & Synthesis Settings page in the Settings dialog box.
Default parameters enable you to add, change, and delete global parameters for the
current assignment. In AHDL, the Quartus II software inherits parameters, so any
default parameters apply to all AHDL instances in your design. You can also specify
parameters for instantiated modules in a .bdf. To specify parameters in a .bdf
instance, double-click the parameter value box for the instance symbol, or right-click
the symbol and click Properties, and then click the Parameters tab. For more
information about the GUI-based entry methods, the interpretation of parameter
values, and format recommendations, refer to Setting Default Parameter Values and
BDF Instance Parameter Values on page 1717.
1717
You can specify parameters for instantiated modules in your design source files with
the provided syntax for your chosen language. Some designs instantiate entities in a
different language; for example, they might instantiate a VHDL entity from a Verilog
HDL design file. You can pass parameters or generics between VHDL, Verilog HDL,
AHDL, and BDF schematic entry, and from EDIF or VQM to any of these languages.
You do not require an additional procedure to pass parameters from one language to
another. However, sometimes you must specify the type of parameter you are
passing. In those cases, you must follow certain guidelines to ensure that the
Quartus II software correctly interprets the parameter value. For more information
about parameter type rules, refer to Passing Parameters Between Two Design
Languages on page 1719.
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Table 172 lists valid parameter strings and how the Quartus II software interprets the
parameter strings. Use the type-encoded format only when necessary to resolve
ambiguity.
Table 172. Valid Parameter Strings and Interpretations
Parameter String
S"abc", s"abc"
"abc123", "123abc"
F"12.3", f"12.3"
-5.4
D"123", d"123"
123, -123
X"ff", H"ff"
Hexadecimal value FF
Q"77", O"77"
Octal value 77
B"1010", b"1010"
SB"1010", sb"1010"
E"apple", e"apple"
P"1 unit"
A(...), a(...)
You can select the parameter type for global parameters or global constants with the
pull-down list in the Parameter tab of the Symbol Properties dialog box. If you do not
specify the parameter type, the Quartus II software interprets the parameter value
and defines the parameter type. You must specify parameter type with the pull-down
list to avoid ambiguity.
1
If you open a .bdf in the Quartus II software, the software automatically updates the
parameter types of old symbol blocks by interpreting the parameter value based on
the language-independent format. If the Quartus II software does not recognize the
parameter value type, the software sets the parameter type as untyped.
The Quartus II software supports the following parameter types:
Unsigned Integer
Signed Integer
Unsigned Binary
Signed Binary
Octal
Hexadecimal
Float
Enum
String
Boolean
Char
Untyped/Auto
1719
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Example 1719. Verilog HDL Top-Level Design Instantiating and Passing Parameters to VHDL
Entity from Example 1718
vhdl_sub inst (...);
defparam inst.name = "lower";
defparam inst.width = 3;
defparam inst.num_string = "321";
defparam inst.f = "grape"; // Must exactly match enum value
defparam inst.binary_vector = 4'b1010;
defparam inst.signed_vector = 4'sb1010;
Example 1721. VHDL Top-Level Design Instantiating and Passing Parameters to the Verilog HDL
Module from Example 1720
inst:veri_sub
generic map (
name => "lower",
width => 3,
number_string => "321"
binary_vector = "1010"
signed_vector = "1010")
To use an HDL subdesign such as the one shown in Example 1720 in a top-level .bdf
design, you must generate a symbol for the HDL file, as shown in Figure 172. Open
the HDL file in the Quartus II software, and then, on the File menu, point to
Create/Update, and then click Create Symbol Files for Current File.
To specify parameters on a .bdf instance, double-click the parameter value box for the
instance symbol, or right-click the symbol and click Properties, and then click the
Parameters tab. Right-click the symbol and click Update Design File from Selected
Block to pass the updated parameter to the HDL file.
Figure 172. BDF Top-Level Design Instantiating and Passing Parameters to the Verilog HDL
Module from Example 1720
1721
Incremental Compilation
Incremental compilation manages a design hierarchy for incremental design by
allowing you to divide your design into multiple partitions. Incremental compilation
ensures that the Quartus II software resynthesizes only the updated partitions of your
design during compilation, to reduce the compilation time and the runtime memory
usage. The feature maintains node names during synthesis for all registered and
combinational nodes in unchanged partitions. You can perform incremental synthesis
by setting the netlist type for all design partitions to Post-Synthesis.
You can also preserve the placement and routing information for unchanged
partitions. This feature allows you to preserve performance of unchanged blocks in
your design and reduces the time required for placement and routing, which
significantly reduces your design compilation time.
h For more information about incremental compilation, refer to About Incremental
Compilation in Quartus II Help.
f For more information about incremental compilation, refer to Quartus II Incremental
Compilation for Hierarchical and Team-Based Design and Best Practices for Incremental
Compilation Partitions and Floorplan Assignments chapters in volume 1 of the Quartus II
Handbook.
Parallel Synthesis
The Parallel Synthesis logic option reduces compilation time for synthesis. The
option enables the Quartus II software to use multiple processors to synthesize
multiple partitions in parallel.
This option is available when you perform the following tasks:
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By default, the Quartus II software enables the Parallel Synthesis option. To disable
parallel synthesis, follow these steps:
1. On the Assignments menu, click Settings.
2. In the Category list, click Analysis & Synthesis Settings, and then click More
Settings to select Parallel Synthesis.
You can also set the Parallel Synthesis option with the following Tcl command, as
shown in Example 1722:
Example 1722. Setting the Parallel Synthesis Option with Tcl Command
set_global_assignment -name parallel_synthesis off
If you use the command line, you can differentiate among the interleaved messages
by turning on the Show partition that generated the message option in the Messages
page. This option shows the partition ID in parenthesis for each message.
You can view all the interleaved messages from different partitions in the Messages
window. The Partition column in the Messages window displays the partition ID of
the partition referred to in the message. After compilation, you can sort the messages
by partition.
h For more information about displaying the Partition column, refer to About the
Messages Window in Quartus II Help.
1723
When you apply a Quartus II Synthesis option globally or to an entity, the option
affects all lower-level entities in the hierarchy path, including entities instantiated
with Altera and third-party IP.
The following subsections describe the following common synthesis options in the
Quartus II software, and provide HDL examples on how to use each option:
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Controlling Clock Enable Signals with Auto Clock Enable Replacement and
direct_enable on page 1748
1725
Other Settings:
Synthesis Attributes
The Quartus II software supports synthesis attributes for Verilog HDL and VHDL,
also commonly called pragmas. These attributes are not standard Verilog HDL or
VHDL commands. Synthesis tools use attributes to control the synthesis process. The
Quartus II software applies the attributes in the HDL source code, and attributes
always apply to a specific design element. Some synthesis attributes are also available
as Quartus II logic options via the Quartus II software or scripting. Each attribute
description in this chapter indicates a corresponding setting or a logic option that you
can set in the Quartus II software. You can specify only some attributes with HDL
synthesis attributes.
Attributes specified in your HDL code are not visible in the Assignment Editor or in
the .qsf. Assignments or settings made with the Quartus II software, the .qsf, or the
Tcl interface take precedence over assignments or settings made with synthesis
attributes in your HDL code. The Quartus II software generates warning messages if
the software finds invalid attributes, but does not generate an error or stop the
compilation. This behavior is necessary because attributes are specific to various
design tools, and attributes not recognized in the Quartus II software might be for a
different EDA tool. The Quartus II software lists the attributes specified in your HDL
code in the Source assignments table of the Analysis & Synthesis report.
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Verilog HDL is case sensitive; therefore, synthesis attributes in Verilog HDL files are
also case sensitive.
Example 1723. Specifying Synthesis Attributes in Verilog-1995
// synthesis <attribute> [ = <value> ]
or
/* synthesis <attribute> [ = <value> ] */
You cannot use the open one-line comment in Verilog HDL when a semicolon is
necessary after the line, because it is not clear to which HDL element that the attribute
applies. For example, you cannot make an attribute assignment such as
reg r; // synthesis <attribute> because the Quartus II software could read the
attribute as part of the next line.
To apply multiple attributes to the same instance in Verilog-1995, separate the
attributes with spaces, as shown in Example 1724:
Example 1724. Applying Multiple Attributes to the Same Instance in Verilog-1996
//synthesis <attribute1> [ = <value> ] <attribute2> [ = <value> ]
For example, to set the maxfan attribute to 16 (for details, refer to Maximum FanOut on page 1747) and set the preserve attribute (for details, refer to Preserve
Registers on page 1742) on a register called my_reg, use the following syntax as
shown in Example 1725:
Example 1725. Setting maxfan and preserve Attribute on a Register
Because formal verification tools do not recognize the exemplar, pragma, and altera
keywords, avoid using these attribute keywords when using formal verification.
1727
Formal verification does not support the Verilog-2001 attribute syntax because the
tools do not recognize the syntax.
To apply multiple attributes to the same instance in Verilog-2001 or SystemVerilog,
separate the attributes with commas, as shown in Example 1727:
Example 1727. Applying Multiple Attributes
(* <attribute1> [ = <value1>], <attribute2> [ = <value2> ] *)
VHDL attributes, as shown in Example 1729, declare and apply the attribute type to
the object you specify.
Example 1729. Synthesis Attributes in VHDL
attribute <attribute> : <attribute type> ;
attribute <attribute> of <object> : <object type> is <value>;
The Quartus II software defines and applies each attribute separately to a given node.
For VHDL designs, the software declares all supported synthesis attributes in the
altera_syn_attributes package in the Altera library. You can call this library from
your VHDL code to declare the synthesis attributes, as shown in Example 1730:
Example 1730.
LIBRARY altera;
USE altera.altera_syn_attributes.all;
Synthesis Directives
The Quartus II software supports synthesis directives, also commonly called compiler
directives or pragmas. You can include synthesis directives in Verilog HDL or VHDL
code as comments. These directives are not standard Verilog HDL or VHDL
commands. Synthesis tools use directives to control the synthesis process. Directives
do not apply to a specific design node, but change the behavior of the synthesis tool
from the point in which they occur in the HDL source code. Other tools, such as
simulators, ignore these directives and treat them as comments.
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You can enter synthesis directives in your code using the syntax in Example 1731,
Example 1732, and Example 1733, in which <directive> and <value> are variables,
and the entry in brackets are optional. For synthesis directives, no equal sign before
the value is necessary; this is different than the Verilog syntax for synthesis attributes.
The examples in this chapter demonstrate each syntax form.
1
Verilog HDL is case sensitive; therefore, all synthesis directives are also case sensitive.
Example 1731. Specifying Synthesis Directives with Verilog HDL
// synthesis <directive> [ <value> ]
or
/* synthesis <directive> [ <value> ] */
In addition to the synthesis keyword shown above, the software supports the
pragma, synopsys, and exemplar keywords in Verilog HDL and VHDL for
compatibility with other synthesis tools. The Quartus II software also supports the
keyword altera, which allows you to add synthesis directives that only Quartus II
Integrated Synthesis feature recognizes, and not by other tools that recognize the
same synthesis directives.
1
Because formal verification tools ignore the exemplar, pragma, and altera keywords,
Altera recommends that you avoid using these directive keywords when you use
formal verification to prevent mismatches with the Quartus II results.
Optimization Technique
The Optimization Technique logic option specifies the goal for logic optimization
during compilation; that is, whether to attempt to achieve maximum speed
performance or minimum area usage, or a balance between the two.
h For more information about the Optimization Technique logic option, refer to
Optimization Technique logic option in Quartus II Help.
1729
For one set of gating input values, the value output of the gated clock remains
constant and does not change as the base clock changes
For one value of the base clock, changes in the gating inputs do not change the
value output for the gated clock
ena
ena
ena1
ena1
ena
clk
clk
ena
ena
ena
ena1
ena
ena2
ena1
clk
ena2
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clk
1730
This option does not support registers in RAM, DSP blocks, or I/O related WYSIWYG
primitives. Because the gated-clock conversion cannot trace the base clock from the
gated clock, the gated clock conversion does not support multiple design partitions
from incremental compilation in which the gated clock and base clock are not in the
same hierarchical partition. A gated clock tree, instead of every gated clock, is the
basis of each conversion. Therefore, if you cannot convert a gated clock from a root
gated clock of a multiple cascaded gated clock, the conversion of the entire gated
clock tree fails.
The Info tab in the Messages window lists all the converted gated clocks. You can
view a list of converted and nonconverted gated clocks from the Compilation Report
under the Optimization Results of the Analysis & Synthesis Report. The Gated Clock
Conversion Details table lists the reasons for nonconverted gated clocks.
h For more information about Auto Gated Clock Conversion logic option and a list of
supported devices, refer to Auto Gated Clock Conversion logic option in Quartus II Help.
Timing-Driven Synthesis
The Timing-Driven Synthesis logic option specifies whether Analysis & Synthesis
should use the SDC timing constraints of your design to better optimize the circuit.
When you turn on this option, Analysis & Synthesis runs timing analysis to obtain
timing information about the netlist, and then considers the SDC timing constraints to
focus on critical portions of your design when optimizing for performance, while
optimizing noncritical portions for area. When you turn on this option, Analysis &
Synthesis also protects SDC constraints by not merging duplicate registers that have
incompatible timing constraints. For more information, refer to SDC Constraint
Protection on page 1731.
When you turn on the Timing-Driven Synthesis logic option, Analysis & Synthesis
increases performance by improving logic depth on critical portions of your design,
and improving area on noncritical portions of your design. The increased
performance affects the amount of area used, specifically adaptive look-up tables
(ALUTs) and registers in your design. Depending on how much of your design is
timing critical, overall area can increase or decrease when you turn on the
Timing-Driven Synthesis logic option. Runtime and peak memory use increases
slightly if you turn on the Timing-Driven Synthesis logic option.
When you turn on the Timing-Driven Synthesis logic option, the Optimization
Technique logic option has the following effect. With Optimization Technique
Speed, Timing-Driven Synthesis optimizes timing-critical portions of your design for
performance at the cost of increasing area (logic and register utilization). With an
Optimization Technique of Balanced, Timing-Driven Synthesis also optimizes the
timing-critical portions of your design for performance, but the option allows only
limited area increase. With Optimization Technique Area, Timing-Driven Synthesis
optimizes your design only for area. Timing-Driven Synthesis prevents registers
with incompatible timing constraints from merging for any Optimization Technique
setting. If your design contains multiple partitions, you can select Timing-Driven
Synthesis unique options for each partition. If you use a .qxp as a source file, or if
your design uses partitions developed in separate Quartus II projects, the software
cannot properly compute timing of paths that cross the partition boundaries.
1731
Even with the Optimization Technique logic option set to Speed, the Timing-Driven
Synthesis option still considers the resource usage in your design when increasing
area to improve timing. For example, the Timing-Driven Synthesis option checks if a
device has enough registers before deciding to implement the shift registers in logic
cells instead of RAM for better timing performance.
When using incremental compilation, Integrated Synthesis allows each partition to
use up all the registers in a device. You can use the Maximum Number of LABs
settings to specify the number of LABs that every partition can use. If your design has
only one partition, you can also use the Maximum Number of LABs settings to limit
the number of resources that your design can use. This limitation is useful when you
add more logic to your design.
To turn on or turn off the Timing-Driven Synthesis logic option, follow these steps:
1. On the Assignment menu, click Settings.
2. In the Category list, select Analysis & Synthesis Settings. In the Analysis &
Synthesis Settings page, turn on or turn off Timing-Driven Synthesis.
1
Altera recommends that you select a specific device for timing-driven synthesis to
have the most accurate timing information. When you select auto device,
timing-driven synthesis uses the smallest device for the selected family to obtain
timing information.
h For more information about Timing-Driven Synthesis logic option and a list of
supported devices, refer to Timing-Driven Synthesis logic option in Quartus II Help.
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f For more information about optimizing your design for power utilization, refer to the
Power Optimization chapter in volume 2 of the Quartus II Handbook. For information
about analyzing your power results, refer to the PowerPlay Power Analysis chapter in
volume 3 of the Quartus II Handbook.
The RAM balancing feature does not support Stratix V devices because Stratix V has
only M20K memory blocks.
By default, Quartus II Integrated Synthesis considers the information in the targeted
device to identify the number of available DSP or RAM blocks. However, in
incremental compilation, each partition considers the information in the device
independently and consequently assumes that the partition has all the DSP and RAM
blocks in the device available for use, resulting in over allocation of DSP or RAM
blocks in your design, which means that the total number of DSP or RAM blocks used
by all the partitions is greater than the number of DSP or RAM blocks available in the
device, leading to a no-fit error during the fitting process.
The following sections describe the methods to prevent a no-fit error during the fitting
process:
Using Assignments to Limit the Number of RAM and DSP Blocks on page 1733
1733
f For more information about using LogicLock regions to create a floorplan for
incremental compilation, refer to the Quartus II Incremental Compilation for Hierarchical
and Team-Based Design chapter in volume 1 of the Quartus II Handbook.
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Restructure Multiplexers
The Restructure Multiplexers logic option restructures multiplexers to create more
efficient use of area, allowing you to implement multiplexers with a reduced number
of LEs or ALMs.
When multiplexers from one part of your design feed multiplexers in another part of
your design, trees of multiplexers form. Multiplexers may arise in different parts of
your design through Verilog HDL or VHDL constructs such as the if, case, or
?: statements. Multiplexer buses occur most often as a result of multiplexing
together arrays in Verilog HDL, or STD_LOGIC_VECTOR signals in VHDL. The
Restructure Multiplexers logic option identifies buses of multiplexer trees that have a
similar structure. This logic option optimizes the structure of each multiplexer bus for
the target device to reduce the overall amount of logic in your design.
Results of the multiplexer optimizations are design dependent, but area reductions as
high as 20% are possible. The option can negatively affect your designs fMAX.
f For more information about optimizing for multiplexers, refer to the Multiplexers
section of the Recommended HDL Coding Styles chapter in volume 1 of the Quartus II
Handbook.
h For more information about the Multiplexer Restructuring Statistics report table for
each bus of multiplexers, refer to Analysis & Synthesis Optimization Results Reports in
Quartus II Help.
h For more information about the Restructure Multiplexers logic option, including the
settings and a list of supported device families, refer to Restructure Multiplexers logic
option in Quartus II Help.
Synthesis Effort
The Synthesis Effort logic option specifies the overall synthesis effort level in the
Quartus II software.
h For more information about Synthesis Effort logic option, including a list of
supported device families, refer to Synthesis Effort logic option in Quartus II Help.
Synthesis Seed
The Synthesis Seed option specifies the seed that Synthesis uses to randomly run
synthesis in a slightly different way. You can use this seed when your design is close
to meeting requirements, to get a slightly different result. The seeds that produce the
best result for a design might change if your design changes.
To set the Synthesis Seed option from the Quartus II software, on the Analysis &
Synthesis Settings page, click More Settings. The default value is 1. You can specify a
positive integer value.
1735
The default state machine encoding, Auto, uses one-hot encoding for FPGA devices
and minimal-bits encoding for CPLDs. These settings achieve the best results on
average, but another encoding style might be more appropriate for your design, so
this option allows you to control the state machine encoding.
f For guidelines on how to correctly infer and encode your state machine, refer to the
Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook.
For one-hot encoding, the Quartus II software does not guarantee that each state has
one bit set to one and all other bits set to zero. Quartus II Integrated Synthesis creates
one-hot register encoding with standard one-hot encoding and then inverts the first
bit. This results in an initial state with all zero values, and the remaining states have
two 1 values. Quartus II Integrated Synthesis encodes the initial state with all zeros
for the state machine power-up because all device registers power up to a low value.
This encoding has the same properties as true one-hot encoding: the software
recognizes each state by the value of one bit. For example, in a one-hot-encoded state
machine with five states, including an initial or reset state, the software uses the
register encoding shown in Example 1734:
Example 1734. Register Encoding
State
State
State
State
State
0
1
2
3
4
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
1
If you set the State Machine Processing logic option to User-Encoded in a Verilog
HDL design, the software starts with the original design values for the state constants.
For example, a Verilog HDL design can contain a declaration such as shown in
Example 1735:
Example 1735.
parameter S0 = 4'b1010, S1 = 4'b0101, ...
If the software infers the states S0, S1,... the software uses the encoding 4'b1010,
4'b0101,... . If necessary, the software inverts bits in a user-encoded state machine to
ensure that all bits of the reset state of the state machine are zero.
1
You can view the state machine encoding from the Compilation Report under the
State Machines of the Analysis & Synthesis Report. The State Machine Viewer
displays only a graphical representation of the state machines as interpreted from
your design.
f For more information about the State Machine Viewer, refer to the State Machine
Viewer section of the Analyzing Designs with Quartus II Netlist Viewers chapter in
volume 1 of the Quartus II Handbook.
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1736
To assign your own state encoding with the User-Encoded setting of the State
Machine Processing option in a VHDL design, you must apply specific binary
encoding to the elements of an enumerated type because enumeration literals have no
numeric values in VHDL. Use the syn_encoding synthesis attribute to apply your
encoding values. For more information, refer to Manually Specifying State
Assignments Using the syn_encoding Attribute.
h For information about the State Machine Processing logic option, including the
settings and supported devices, refer to State Machine Processing logic option in
Quartus II Help.
Enumeration Types
"default"
Use an encoding based on the number of enumeration literals in the Enumeration Type. If the number
of literals is less than five, use the "sequential" encoding. If the number of literals is more than five,
but fewer than 50, use a "one-hot" encoding. Otherwise, use a "gray" encoding.
"sequential"
Use a binary encoding in which the first enumeration literal in the Enumeration Type has encoding 0
and the second 1.
"gray"
Use an encoding in which the encodings for adjacent enumeration literals differ by exactly one bit. An
N-bit gray code can represent 2N values.
"johnson"
Use an encoding similar to a gray code. An N-bit Johnson code can represent at most 2N states, but
requires less logic than a gray encoding.
"one-hot"
The default encoding style requiring N bits, in which N is the number of enumeration literals in the
Enumeration Type.
"compact"
"user"
Encode each state using its value in the Verilog source. By changing the values of your state constants,
you can change the encoding of your state machine.
The syn_encoding attribute must follow the enumeration type definition, but precede
its use.
1737
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=
=
=
=
"11"
"01"
"10"
"00"
1738
Altera recommends that you specify an encoding style, rather than a manual user
encoding, especially when the enumeration type has a large number of enumeration
literals. The Quartus II software can implement Enumeration Types with the different
encoding styles, as shown in Table 174.
Table 174. enum_encoding Attribute Values
Attribute Value
Enumeration Types
"default"
Use an encoding based on the number of enumeration literals in the enumeration type. If the number
of literals are fewer than five, use the "sequential" encoding. If the number of literals are more than
five, but fewer than 50 literals, use a "one-hot" encoding. Otherwise, use a "gray" encoding.
"sequential"
Use a binary encoding in which the first enumeration literal in the enumeration type has encoding 0
and the second 1.
"gray"
Use an encoding in which the encodings for adjacent enumeration literals differ by exactly one bit. An
N-bit gray code can represent 2N values.
"johnson"
Use an encoding similar to a gray code. An N-bit Johnson code can represent at most 2N states, but
requires less logic than a gray encoding.
"one-hot"
The default encoding style requiring N bits, in which N is the number of enumeration literals in the
enumeration type.
1739
The safe state machine value does not use any user-defined default logic from your
HDL code that corresponds to unreachable states. Verilog HDL and VHDL enable you
to specify a behavior for all states in the state machine explicitly, including
unreachable states. However, synthesis tools detect if state machine logic is
unreachable and minimize or remove the logic. Synthesis tools also remove any flag
signals or logic that indicate such an illegal state. If the software implements the state
machine as safe, the recovery logic added by Quartus II Integrated Synthesis forces its
transition from an illegal state to the reset state.
You can set the Safe State Machine logic option globally, or on individual state
machines. To set this logic option, on the Analysis & Synthesis Settings page, select
More Settings. In the Existing option settings list, select Safe State Machine, and
turn on this option in the Setting list.
You can set the syn_encoding safe attribute on a state machine in HDL, as shown in
Example 1739 through Example 1741.
Example 1739. Verilog HDL Code: a Safe State Machine Attribute
reg [2:0] my_fsm /* synthesis syn_encoding = "safe" */;
Example 1740. Verilog-2001 and SystemVerilog Code: a Safe State Machine Attribute
(* syn_encoding = "safe" *) reg [2:0] my_fsm;
If you create the safe state machine assignment on an instance that the software fails
to recognize as a state machine, or an entity that contains a state machine, the software
takes no action. You must restructure the code, so that the software recognizes and
infers the instance as a state machine.
h For more information about the Safe State Machine logic option, refer to Safe State
Machine logic option in Quartus II Help.
f For guidelines to ensure that the software correctly infers your state machine, refer to
the Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook.
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Power-Up Level
This logic option causes a register (flipflop) to power up with the specified logic level,
either high (1) or low (0). The registers in the core hardware power up to 0 in all Altera
devices. For the register to power up with a logic level high, the Compiler performs an
optimization referred to as NOT-gate push back on the register. NOT-gate push back
adds an inverter to the input and the output of the register, so that the reset and
power-up conditions appear to be high and the device operates as expected. The
register itself still powers up to 0, but the register output inverts so the signal arriving
at all destinations is 1.
The Power-Up Level option supports wildcard characters, and you can apply this
option to any register, registered logic cell WYSIWYG primitive, or to a design entity
containing registers, if you want to set the power level for all registers in your design
entity. If you assign this option to a registered logic cell WYSIWYG primitive, such as
an atom primitive from a third-party synthesis tool, you must turn on the Perform
WYSIWYG Primitive Resynthesis logic option for the option to take effect. You can
also apply the option to a pin with the logic configurations described in the following
list:
If you turn on this option for an input pin, the option transfers to the register that
the pin drives, if all these conditions are present:
No logic, other than inversion, between the pin and the register.
If you turn on this option for an output or bidirectional pin, the option transfers to
the register that feeds the pin, if all these conditions are present:
No logic, other than inversion, between the register and the pin.
h For more information about the Power-Up Level logic option, including information
on the supported device families, refer to Power-Up Level logic option in Quartus II
Help.
1741
The following register declarations all set a power-up level of VCC or a logic value 1,
as shown in Example 1742:
Example 1742.
signal q : std_logic = '1';
reg q = 1'b1;
-- power-up to VCC
// power-up to VCC
reg q;
initial begin q = 1'b1; end
// power-up to VCC
f For more information about NOT-gate push back, the power-up states for Altera
devices, and how set and reset control signals affect the power-up level, refer to the
Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook.
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1742
Preserve Registers
This attribute and logic option directs the Compiler not to minimize or remove a
specified register during synthesis optimizations or register netlist optimizations.
Optimizations can eliminate redundant registers and registers with constant drivers;
this option prevents the software from reducing a register to a constant or merging
with a duplicate register. This option can preserve a register so you can observe the
register during simulation or with the SignalTap II Logic Analyzer. Additionally, this
option can preserve registers if you create a preliminary version of your design in
which you have not specified the secondary signals. You can also use the attribute to
preserve a duplicate of an I/O register so that you can place one copy of the I/O
register in an I/O cell and the second in the core.
1
This option cannot preserve registers that have no fan-out. To prevent the removal of
registers with no fan-out, refer to Noprune Synthesis Attribute/Preserve Fan-out
Free Register Node on page 1743.
The Preserve Registers logic option prevents the software from inferring a register as
a state machine.
You can set the Preserve Registers logic option in the Quartus II software, or you can
set the preserve attribute in your HDL code, as shown in Example 1743 through
Example 1745. In these examples, the Quartus II software preserves the my_reg
register.
The = 1 after the preserve in Example 1743 and Example 1744 is optional, because
the assignment uses a default value of 1 when you specify the assignment.
Example 1745. VHDL Code: preserve Attribute
signal my_reg : stdlogic;
attribute preserve : boolean;
attribute preserve of my_reg : signal is true;
h For more information about the Preserve Registers logic option and the supported
devices, refer to Preserve Registers logic option in Quartus II Help.
1743
h For more information about the Disable Register Merging logic option and the
supported devices, refer to Disable Register Merging logic option in Quartus II Help.
May 2013
You must use the noprune attribute instead of the logic option if the register has no
immediate fan-out in its module or entity. If you do not use the synthesis attribute, the
software removes (or prunes) registers with no fan-out during Analysis &
Elaboration before the logic synthesis stage applies any logic options. If the register
has no fan-out in the full design, but has fan-out in its module or entity, you can use
the logic option to retain the register through compilation.
Altera Corporation
1744
The software supports the attribute name syn_noprune for compatibility with other
synthesis tools.
Example 1749. Verilog HDL Code: syn_noprune Attribute
reg my_reg /* synthesis syn_noprune */;
h For more information about Preserve Fan-out Free Register Node logic option and a
list of supported devices, refer to Preserve Fan-out Free Register logic option in Quartus II
Help.
The option cannot keep nodes that have no fan-out. You cannot maintain node names
for wires with tri-state drivers, or if the signal feeds a top-level pin of the same name
(the software changes the node name to a name such as <net name>~buf0).
You can use the Ignore LCELL Buffers logic option to direct Analysis & Synthesis to
ignore logic cell buffers that the Implement as Output of Logic Cell logic option or
the LCELL primitive created. If you apply this logic option to an entity, it affects all
lower-level entities in the hierarchy path.
To avoid unintended design optimizations, ensure that any entity instantiated with
Altera or third-party IP that relies on logic cell buffers for correct behavior does not
inherit the Ignore LCELL Buffers logic option. For example, if an IP core uses logic
cell buffers to manage high fan-out signals and inherits the Ignore LCELL Buffers
logic option, the target device may no longer function properly.
You can turn off the Ignore LCELL Buffers logic option for a specific entity to
override any assignments inherited from higher-level entities in the hierarchy path if
logic cell buffers created by the Implement as Output of Logic Cell logic option or
the LCELL primitive are required for correct behavior.
1745
You can set the Implement as Output of Logic Cell logic option in the Quartus II
software, or you can set the keep attribute in your HDL code, as shown in
Example 1752 through Example 1754. In these examples, the Compiler maintains
the node name my_wire.
1
In addition to keep, the Quartus II software supports the syn_keep attribute name for
compatibility with other synthesis tools.
Example 1752. Verilog HDL Code: keep Attribute
wire my_wire /* synthesis keep = 1 */;
h For more information about the Implement as Output of Logic Cell logic option and
the supported devices, refer to Implement as Output of Logic Cell logic option in
Quartus II Help.
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1746
You can set the Netlist Optimizations logic option to Never Allow in the Quartus II
software to disable retiming along with other synthesis netlist optimizations, or you
can set the dont_retime attribute in your HDL code, as shown in Example 1755
through Example 1757. In these examples, the code prevents my_reg register from
being retimed.
Example 1755. Verilog HDL Code: dont_retime Attribute
reg my_reg /* synthesis dont_retime */;
*/;
1747
Maximum Fan-Out
This Maximum Fan-Out attribute and logic option direct the Compiler to control the
number of destinations that a node feeds. The Compiler duplicates a node and splits
its fan-out until the individual fan-out of each copy falls below the maximum fan-out
restriction. You can apply this option to a register or a logic cell buffer, or to a design
entity that contains these elements. You can use this option to reduce the load of
critical signals, which can improve performance. You can use the option to instruct the
Compiler to duplicate a register that feeds nodes in different locations on the target
device. Duplicating the register can enable the Fitter to place these new registers
closer to their destination logic to minimize routing delay.
To turn off the option for a given node if you set the option at a higher level of the
design hierarchy, in the Netlist Optimizations logic option, select Never Allow. If not
disabled by the Netlist Optimizations option, the Compiler acknowledges the
maximum fan-out constraint as long as the following conditions are met:
The node feeds other logic cells, DSP blocks, RAM blocks, and pins through data,
address, clock enable, and other ports, but not through any asynchronous control
ports (such as asynchronous clear).
The Compiler does not create duplicate nodes in these cases, because there is no clear
way to duplicate the node, or to avoid the small differences in timing which could
produce functional differences in the implementation (in the third condition above in
which asynchronous control signals are involved). If you cannot apply the constraint
because you do not meet one of these conditions, the Compiler issues a message to
indicate that the Compiler ignores the maximum fan-out assignment. To instruct the
Compiler not to check node destinations for possible problems such as the third
condition, you can set the Netlist Optimizations logic option to Always Allow for a
given node.
1
If you have enabled any of the Quartus II netlist optimizations that affect registers,
add the preserve attribute to any registers to which you have set a maxfan attribute.
The preserve attribute ensures that the netlist optimization algorithms, such as
register retiming, do not affect the registers.
f For details about netlist optimizations, refer to the Netlist Optimizations and Physical
Synthesis chapter in volume 2 of the Quartus II Handbook.
You can set the Maximum Fan-Out logic option in the Quartus II software. This
option supports wildcard characters. You can also set the maxfan attribute in your
HDL code, as shown in Example 1761 through Example 1763. In these examples,
the Compiler duplicates the clk_gen register, so its fan-out is not greater than 50.
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In addition to maxfan, the Quartus II software supports the syn_maxfan attribute for
compatibility with other synthesis tools.
Example 1761. Verilog HDL Code: syn_maxfan Attribute
reg clk_gen /* synthesis syn_maxfan = 50 */;
h For more information about the Maximum Fan-Out logic option and the supported
devices, refer to Maximum Fan-Out logic option in Quartus II Help.
Controlling Clock Enable Signals with Auto Clock Enable Replacement and
direct_enable
The Auto Clock Enable Replacement logic option allows the software to find logic
that feeds a register and move the logic to the registers clock enable input port. To
solve fitting or performance issues with designs that have many clock enables, you
can turn off this option for individual registers or design entities. Turning the option
off prevents the software from using the registers clock enable port. The software
implements the clock enable functionality using multiplexers in logic cells.
If the software does not move the specific logic to a clock enable input with the Auto
Clock Enable Replacement logic option, you can instruct the software to use a direct
clock enable signal. The attribute ensures that the signal drives the clock enable port,
and the software does not optimize or combine the signal with other logic.
Example 1764 through Example 1766 show how to set this attribute to ensure that
the attribute preserves the signal and uses the signal as a clock enable.
1749
h For more information about the Auto Clock Enable Replacement logic option and
the supported devices, refer to Auto Clock Enable Replacement logic option in Quartus II
Help.
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Shift Registers
Use the Auto Shift Register Replacement logic option to control shift register
inference. This option has three settings: Off, Auto and Always. Auto is the default
setting in which Quartus II Integrated Synthesis decides which shift registers to
replace or leave in registers. Placing shift registers in memory saves logic area, but can
have a negative effect on fmax. Quartus II Integrated Synthesis uses the optimization
technique setting, logic and RAM utilization of your design, and timing information
from Timing-Driven Synthesis to determine which shift registers are located in
memory and which are located in registers. To disable inference, turn off this option
for the entire project on the Analysis & Synthesis Settings page of the Settings dialog
box by clicking More Settings and setting the option to Off. You can also disable the
option for a specific block with the Assignment Editor. Even if you set the logic option
to On or Auto, the software might not infer small shift registers because small shift
registers do not benefit from implementation in dedicated memory. However, you can
use the Allow Any Shift Register Size for Recognition logic option to instruct
synthesis to infer a shift register even when its size is too small.
You can use the Allow Shift Register Merging across Hierarchies option to prevent
the Compiler from merging shift registers in different hierarchies into one larger shift
register. The option has three settings: On, Off, and Auto. The Auto setting is the
default setting, and the Compiler decides whether or not to merge shift registers
across hierarchies. When you turn on this option, the Compiler allows all shift
registers to merge across hierarchies, and when you turn off this option, the Compiler
does not allow any shift registers to merge across hierarchies. You can set this option
globally or on entities or individual nodes.
1
The registers that the software maps to the ALTSHIFT_TAPS megafunction and places
in RAM are not available in the Simulator because their node names do not exist after
synthesis.
The Compiler turns off the Auto Shift Register Replacement logic option when you
select a formal verification tool on the EDA Tool Settings page. If you do not select a
formal verification tool, the Compiler issues a warning and the compilation report
lists shift registers that the logic option might infer. To enable a megafunction for the
shift register in the formal verification flow, you can either instantiate a shift register
explicitly with the MegaWizard Plug-In Manager or make the shift register into a
black box in a separate entity or module.
h For more information about the Auto Shift Register Replacement logic option and
the supported devices, refer to Auto Shift Register Replacement logic option in Quartus II
Help.
1751
Although the software implements inferred shift registers in RAM blocks, you cannot
turn off the Auto RAM Replacement option to disable shift register replacement. Use
the Auto Shift Register Replacement option (refer to Shift Registers on
page 1750).
The software might not infer very small RAM or ROM blocks because you can
implement very small memory blocks with the registers in the logic. However, you
can use the Allow Any RAM Size for Recognition and Allow Any ROM Size for
Recognition logic options to instruct synthesis to infer a memory block even when its
size is too small.
The software turns off the Auto ROM Replacement logic option when you select a
formal verification tool in the EDA Tool Settings page. If you do not select a formal
verification tool, the software issues a warning and a report panel provides a list of
ROMs that the logic option might infer. To enable a megafunction for the shift register
in the formal verification flow, you can either instantiate a ROM explicitly using the
MegaWizard Plug-In Manager or create a black box for the ROM in a separate entity
or in a separate module.
Although formal verification tools do not support inferred RAM blocks, due to the
importance of inferring RAM in many designs, the software turns on the Auto RAM
Replacement logic option when you select a formal verification tool in the EDA Tool
Settings page. The software automatically performs black box instance for any
module or entity that contains an inferred RAM block. The software issues a warning
and lists the black box created in the compilation report. This black box allows formal
verification tools to proceed; however, the formal verification tool cannot verify the
entire module or entire entity that contains the RAM. Altera recommends that you
explicitly instantiate RAM blocks in separate modules or in separate entities so that
the formal verification tool can verify as much logic as possible.
h For more information about the Auto RAM Replacement and Auto ROM
Replacement logic options and their supported devices, refer to Auto RAM
Replacement logic option and Auto ROM Replacement logic option in Quartus II Help.
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Resource aware RAM, ROM and shift register inference is controlled by the Resource
Aware Inference for Block RAM option. You can disable this option for the entire
project in the More Analysis & Synthesis Settings dialog box, or per partition in the
Assignment Editor.
When you select the Auto setting, resource aware RAM, ROM, and shift register
inference use the resource counts from the largest device.
For designs with multiple partitions, Quartus II Integrated Synthesis considers one
partition at a time. Therefore, for each partition, it assumes that all RAM blocks are
available to that partition. If this causes a no-fit error, you can limit the number of
RAM blocks available per partition with the Maximum Number of M512 Memory
Blocks, Maximum Number of M4K/M9K/M20K/M10K Memory Blocks, Maximum
Number of M-RAM/M144K Memory Blocks and Maximum Number of LABs
settings in the Assignment Editor. The balancer also uses these options. For more
information, refer to Limiting Resource Usage in Partitions on page 1732.
If the number of words is less than 16, use a RAM block if the total number of bits
is greater than or equal to 64.
If the number of words is greater than or equal to 16, use a RAM block if the total
number of bits is greater than or equal to 32.
For the Cyclone family of devices, the software uses the following rules:
If the number of words is greater than or equal to 64, use a RAM block.
If the number of words is greater than or equal to 16 and less than 64, use a RAM
block if the total number of bits is greater than or equal to 128.
h For more information about the Auto RAM to Logic Cell Conversion logic options
and the supported devices, refer to Auto RAM to Logic Cell Conversion logic option in
Quartus II Help.
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If you specify a logic value, the memory appears as a RAM or ROM block in the RTL
Viewer, but Integrated Synthesis converts the memory to regular logic during
synthesis.
In addition to ramstyle and romstyle, the Quartus II software supports the
syn_ramstyle attribute name for compatibility with other synthesis tools.
Example 1767 through Example 1769 specify that you must implement all memory
in the module or the my_memory_blocks entity with a specific type of block.
Example 1767. Verilog-1995 Code: Applying a romstyle Attribute to a Module Declaration
module my_memory_blocks (...) /* synthesis romstyle = "M4K" */;
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Example 1770 through Example 1772 specify that you must implement the inferred
my_ram or my_rom memory with regular logic instead of a TriMatrix memory block.
Example 1770. Verilog-1995 Code: Applying a syn_ramstyle Attribute to a Variable Declaration
reg [0:7] my_ram[0:63] /* synthesis syn_ramstyle = "logic" */;
You can control the depth of an inferred memory block and optimize its usage with
the max_depth attribute. You can also optimize the usage of the memory block with
this attribute. Example 1773 through Example 1775 specify the depth of the inferred
memory mem using the max_depth synthesis attribute.
Example 1773. Verilog-1995 Code: Applying a max_depth Attribute to a Variable Declaration
reg [7:0] mem [127:0] /* synthesis max_depth = 2048 */
The syntax for setting these attributes in HDL is the same as the syntax for other
synthesis attributes, as shown in Synthesis Attributes on page 1725.
1755
Example 1777 shows the code to set the RAM style attribute for shift registers in
VHDL.
Example 1777. VHDL Code: Setting the RAM Style Attribute for Shift Registers
attribute ramstyle : string;attribute ramstyle of sr : signal is "M20K";
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You can also assign the RAM style attribute for shift registers globally, which will
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To set the Add Pass-Through Logic to Inferred RAMs logic option with the
Quartus II software, click More Settings on the Analysis & Synthesis Settings page
of the Settings dialog box. Example 1778 and Example 1779 use two addresses and
normally require extra logic after the RAM to ensure that the read-during-write
conditions in the device match the HDL code. If your design does not require a
defined read-during-write condition, the extra logic is not necessary. With the
no_rw_check attribute, Quartus II Integrated Synthesis does not generate the extra
logic.
Example 1778. Verilog HDL Inferred RAM Using no_rw_check Attribute
module ram_infer (q, wa, ra, d, we, clk);
output [7:0] q;
input [7:0] d;
input [6:0] wa;
input [6:0] ra;
input we, clk;
reg [6:0] read_add;
(* ramstyle = "no_rw_check" *) reg [7:0] mem [127:0];
always @ (posedge clk) begin
if (we)
mem[wa] <= d;
read_add <= ra;
end
assign q = mem[read_add];
endmodule
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You can use a ramstyle attribute with the MLAB value, so that the Quartus II software
can infer a small RAM block and place it in an MLAB.
1
You can use this attribute in cases in which some asynchronous RAM blocks might be
coded with read-during-write behavior that does not match the Stratix III, Stratix IV,
and Stratix V architectures. Thus, the device behavior would not exactly match the
behavior that the code describes. If the difference in behavior is acceptable in your
design, use the ramstyle attribute with the no_rw_check value to specify that the
software should not check the read-during-write behavior when inferring the RAM.
When you set this attribute, Quartus II Integrated Synthesis allows the behavior of the
output to differ when the asynchronous read occurs on an address that had a write on
the most recent clock edge. That is, the functional HDL simulation results do not
match the hardware behavior if you write to an address that is being read. To include
these attributes, set the value of the ramstyle attribute to MLAB, no_rw_check.
Example 1780 and Example 1781 show the method of setting two values to the
ramstyle attribute with a small asynchronous RAM block, with the ramstyle
synthesis attribute set, so that the software can implement the memory in the MLAB
memory block and so that the read-during-write behavior is not important. Without
the attribute, this design requires 512 registers and 240 ALUTs. With the attribute, the
design requires eight memory ALUTs and only 15 registers.
Example 1780. Verilog HDL Inferred RAM Using no_rw_check and MLAB Attributes
module async_ram (
input
[5:0] addr,
input
[7:0] data_in,
input
clk,
input
write,
output [7:0] data_out );
(* ramstyle = "MLAB, no_rw_check" *) reg [7:0] mem[0:63];
assign
data_out = mem[addr];
1759
Example 1781. VHDL Inferred RAM Using no_rw_check and MLAB Attributes
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ram IS
PORT (
clock: IN STD_LOGIC;
data: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
write_address: IN INTEGER RANGE 0 to 31;
read_address: IN INTEGER RANGE 0 to 31;
we: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR (2 DOWNTO 0));
END ram;
ARCHITECTURE rtl OF ram IS
TYPE MEM IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL ram_block: MEM;
ATTRIBUTE ramstyle : string;
ATTRIBUTE ramstyle of ram_block : signal is "MLAB , no_rw_check";
SIGNAL read_address_reg: INTEGER RANGE 0 to 31;
BEGIN
PROCESS (clock)
BEGIN
IF (clock'event AND clock = '1') THEN
IF (we = '1') THEN
ram_block(write_address) <= data;
END IF;
read_address_reg <= read_address;
END IF;
END PROCESS;
q <= ram_block(read_address_reg);
END rtl;
h For more information about the Add Pass-Through Logic to Inferred RAMs logic
option and the supported devices, refer to Add Pass-Through Logic to Inferred RAMs
logic option in Quartus II Help.
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In VHDL, you can also initialize the contents of an inferred memory by specifying a
default value for the corresponding signal. In Verilog HDL, you can use an initial
block to specify the memory contents. Quartus II Integrated Synthesis automatically
converts the default value into a .mif for the inferred RAM.
Specifying a multstyle of "dsp" does not guarantee that the Quartus II software can
implement a multiplication in dedicated DSP hardware. The final implementation
depends on several conditions, including the availability of dedicated hardware in the
target device, the size of the operands, and whether or not one or both operands are
constant.
In addition to multstyle, the Quartus II software supports the syn_multstyle
attribute name for compatibility with other synthesis tools.
When applied to a Verilog HDL module declaration, the attribute specifies the default
implementation style for all instances of the * operator in the module. For example, in
the following code examples, the multstyle attribute directs the Quartus II software
to implement all multiplications inside module my_module in the dedicated
multiplication hardware.
Example 1785. Verilog-1995 Code: Applying a multstyle Attribute to a Module Declaration
module my_module (...) /* synthesis multstyle = "dsp" */;
1761
When applied to a Verilog HDL variable declaration, the attribute specifies the
implementation style for a multiplication operator, which has a result directly
assigned to the variable. The attribute overrides the multstyle attribute with the
enclosing module, if present. In Example 1787 and Example 1788, the multstyle
attribute applied to variable result directs the Quartus II software to implement a *
b in logic rather than the dedicated hardware.
Example 1787. Verilog-2001 Code: Applying a multstyle Attribute to a Variable Declaration
wire [8:0] a, b;
(* multstyle = "logic" *) wire [17:0] result;
assign result = a * b; //Multiplication must be
//directly assigned to result
When applied directly to a binary expression that contains the * operator, the attribute
specifies the implementation style for that specific operator alone and overrides any
multstyle attribute with the target variable or enclosing module. In Example 1789,
the multstyle attribute indicates that you must implement a * b in the dedicated
hardware.
Example 1789. Verilog-2001 Code: Applying a multstyle Attribute to a Binary Expression
wire [8:0] a, b;
wire [17:0] result;
assign result = a * (* multstyle = "dsp" *) b;
You cannot use Verilog-1995 attribute syntax to apply the multstyle attribute to a
binary expression.
When applied to a VHDL entity or architecture, the attribute specifies the default
implementation style for all instances of the * operator in the entity or architecture. In
Example 1790, the multstyle attribute directs the Quartus II software to use
dedicated hardware, if possible, for all multiplications inside architecture rtl of entity
my_entity.
Example 1790. VHDL Code: Applying a multstyle Attribute to an Architecture
architecture rtl of my_entity is
attribute multstyle : string;
attribute multstyle of rtl : architecture is "dsp";
begin
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Latches have limited support in formal verification tools. Do not infer latches
unintentionally, for example, through an incomplete case statement when using
formal verification. Formal verification tools support the full_case synthesis
attribute (with limited support for attribute syntax, as described in Synthesis
Attributes on page 1725).
Using the full_case attribute might cause a simulation mismatch between the
Verilog HDL functional and the post-Quartus II simulation because unknown case
statement cases can still function as latches during functional simulation. For
example, a simulation mismatch can occur with the code in Example 1792 when sel
is 2'b11 because a functional HDL simulation output behaves as a latch and the
Quartus II simulation output behaves as a dont care value.
Altera recommends making the case statement full in your regular HDL code,
instead of using the full_case attribute.
1763
The case statement in Example 1792 is not full because you do not specify some sel
binary values. Because you use the full_case attribute, synthesis treats the output as
dont care when the sel input is 2'b11.
Example 1792. Verilog HDL Code: a full_case Attribute
module full_case (a, sel, y);
input [3:0] a;
input [1:0] sel;
output y;
reg y;
always @ (a or sel)
case (sel) // synthesis full_case
2'b00: y=a[0];
2'b01: y=a[1];
2'b10: y=a[2];
endcase
endmodule
Verilog-2001 syntax also accepts the statements in Example 1793 in the case header
instead of the comment form as shown in Example 1792.
Example 1793. Verilog-2001 Syntax for the full_case Attribute
(* full_case *) case (sel)
Parallel Case
The parallel_case attribute indicates that you must consider a Verilog HDL case
statement as parallel; that is, you can match only one case item at a time. Case items in
Verilog HDL case statements might overlap. To resolve multiple matching case items,
the Verilog HDL language defines a priority among case items in which the case
statement always executes the first case item that matches the case expression value.
By default, the Quartus II software implements the extra logic necessary to satisfy this
priority relationship.
Attaching a parallel_case attribute to a case statement header allows the Quartus II
software to consider its case items as inherently parallel; that is, at most one case item
matches the case expression value. Parallel case items simplify the generated logic.
In VHDL, the individual choices in a case statement might not overlap, so they are
always parallel and this attribute does not apply.
Altera recommends that you use this attribute only when the case statement is truly
parallel. If you use the attribute in any other situation, the generated logic does not
match the functional simulation behavior of the Verilog HDL.
1
Altera recommends that you avoid using the parallel_case attribute, because you
may mismatch the Verilog HDL functional and the post-Quartus II simulation.
If you specify SystemVerilog-2005 as the supported Verilog HDL version for your
design, you can use the SystemVerilog keyword unique to achieve the same result as
the parallel_case directive without causing simulation mismatches.
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Example 1794 shows a casez statement with overlapping case items. In functional
HDL simulation, the software prioritizes the three case items by the bits in sel. For
example, sel[2] takes priority over sel[1], which takes priority over sel[0].
However, the synthesized design can simulate differently because the parallel_case
attribute eliminates this priority. If more than one bit of sel is high, more than one
output (a, b, or c) is high as well, a situation that cannot occur in functional HDL
simulation.
Example 1794. Verilog HDL Code: a parallel_case Attribute
module parallel_case (sel, a, b, c);
input [2:0] sel;
output a, b, c;
reg a, b, c;
always @ (sel)
begin
{a, b, c} = 3'b0;
casez (sel) // synthesis parallel_case
3'b1??: a = 1'b1;
3'b?1?: b = 1'b1;
3'b??1: c = 1'b1;
endcase
end
endmodule
Verilog-2001 syntax also accepts the statements as shown in Example 1795 in the
case (or casez) header instead of the comment form, as shown in Example 1794.
Example 1795. Verilog-2001 Syntax
(* parallel_case *) casez (sel)
1765
You can use these directives to indicate a portion of code for simulation only. The
synthesis tool reads synthesis-specific directives and processes them during synthesis;
however, third-party simulation tools read the directives as comments and ignore
them. Example 1796, Example 1797, and Example 1798 show these directives.
Example 1796. Verilog HDL Code: Translate Off and On
// synthesis translate_off
parameter tpd = 2;
// Delay for simulation
#tpd;
// synthesis translate_on
If you want to ignore only a portion of code in Quartus II Integrated Synthesis, you
can use the Altera-specific attribute keyword altera. For example, use the // altera
translate_off and // altera translate_on directives to direct Quartus II
Integrated Synthesis to ignore a portion of code that you intend only for other
synthesis tools.
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You can use this directive with translate_off and translate_on to create one HDL
source file that includes a megafunction instantiation for synthesis and a behavioral
description for simulation.
Formal verification tools do not support the read_comments_as_HDL directive because
the tools do not recognize the directive.
In Example 1799, Example 17100, and Example 17101, the Compiler synthesizes
the commented code enclosed by read_comments_as_HDL because the directive is
visible to the Quartus II Compiler. VHDL 2008 allows block comments, which
comments are also supported for synthesis directives.
Because synthesis directives are case sensitive in Verilog HDL, you must match the
case of the directive, as shown in the following examples.
Example 1799. Verilog HDL Code: Read Comments as HDL
// synthesis read_comments_as_HDL on
// my_rom lpm_rom (.address (address),
//
.data
(data));
// synthesis read_comments_as_HDL off
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Example 17103 and Example 17104 show that the Verilog-2001 syntax also accepts
the type of statements instead of the comment form in Example 17102.
Example 17103. Verilog-2001 Code: the useioff Attribute
(* useioff = 1 *)
(* useioff = 1 *)
input [1:0] a, b;
output [2:0] o;
1769
Example 17105 through Example 17107 show different ways of assigning my_pin1
to Pin C1 and my_pin2 to Pin 4 on a different target device.
Example 17105. Verilog-1995 Code: Applying Chip Pin to a Single Pin
input my_pin1 /* synthesis chip_pin = "C1" */;
input my_pin2 /* synthesis altera_chip_pin_lc = "@4" */;
For bus I/O ports, the value of the chip pin attribute is a comma-delimited list of pin
assignments. The order in which you declare the range of the port determines the
mapping of assignments to individual bits in the port. To leave a bit unassigned, leave
its corresponding pin assignment blank.
Example 17108 assigns my_pin[2] to Pin_4, my_pin[1] to Pin_5, and my_pin[0] to
Pin_6.
Example 17108. Verilog-1995 Code: Applying Chip Pin to a Bus of Pins
input [2:0]
Example 17109 reverses the order of the signals in the bus, assigning my_pin[0] to
Pin_4 and my_pin[2] to Pin_6 but leaves my_pin[1] unassigned.
Example 17109. Verilog-1995 Code: Applying Chip Pin to Part of a Bus
input [0:2]
Example 17110 assigns my_pin[2] to Pin 4 and my_pin[0] to Pin 6, but leaves
my_pin[1] unassigned.
Example 17110. VHDL Code: Applying Chip Pin to Part of a Bus of Pins
entity my_entity is
port(my_pin: in std_logic_vector(2 downto 0););
end my_entity;
attribute chip_pin of my_pin: signal is "4, , 6";
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Example 17111 shows a VHDL example on how to assign pin location and I/O
standard.
Example 17111. VHDL Code: Assigning Pin Location and I/O Standard
attribute altera_chip_pin_lc: string;
attribute altera_attribute: string;
attribute altera_chip_pin_lc of clk: signal is "B13";
attribute altera_attribute of clk:signal is "-name IO_STANDARD ""3.3-V
LVCMOS""";
Example 17112 shows a Verilog-2001 example on how to assign pin location and I/O
standard.
Example 17112. Verilog-2001 Code: Assigning Pin Location and I/O Standard
(* altera_attribute = "-name IO_STANDARD \"3.3-V LVCMOS\"" *)(* chip_pin
= "L5" *)input clk;
(* altera_attribute = "-name IO_STANDARD LVDS" *)(* chip_pin = "L4"
*)input sel;
output [3:0] data_o, input [3:0] data_i);
If the Quartus II option or assignment includes a target, source, and section tag, you
must use the syntax in Example 17114 for each .qsf variable assignment:
Example 17114. Syntax for Each .qsf Variable Assignment
-name <variable> <value>
-from <source> -to <target> -section_id <section>
1771
Example 17115 shows the syntax for the full attribute value, including the optional
target, source, and section tags for two different .qsf assignments.
Example 17115. Syntax for Full Attribute Value
" -name <variable_1> <value_1> [-from <source_1>] [-to <target_1>] [-section_id \
<section_1>]; -name <variable_2> <value_2> [-from <source_2>] [-to <target_2>] \
[-section_id <section_2>] "
If the assigned value of a variable is a string of text, you must use escaped quotes
around the value in Verilog HDL (as shown in Example 17116), or double-quotes in
VHDL (as shown in Example 17117):
Example 17116. Assigned Value of a Variable in Verilog HDL (With Nonexistent Variable and
Value Terms)
"VARIABLE_NAME \"STRING_VALUE\""
Example 17117. Assigned Value of a Variable in VHDL (With Nonexistent Variable and Value
Terms)
"VARIABLE_NAME ""STRING_VALUE"""
To find the .qsf variable name or value corresponding to a specific Quartus II option
or assignment, you can set the option setting or assignment in the Quartus II software,
and then make the changes in the .qsf. You can also refer to the Quartus II Settings File
Manual, which documents all variable names.
Example 17118 through Example 17120 use altera_attribute to set the power-up
level of an inferred register.
1
For inferred instances, you cannot apply the attribute to the instance directly.
Therefore, you must apply the attribute to one of the output nets of the instance. The
Quartus II software automatically moves the attribute to the inferred instance.
Example 17118. Verilog-1995 Code: Applying altera_attribute to an Instance
reg my_reg /* synthesis altera_attribute = "-name POWER_UP_LEVEL HIGH"
*/;
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Example 17121 through Example 17123 use the altera_attribute to disable the
Auto Shift Register Replacement synthesis option for an entity. To apply the Altera
Attribute to a VHDL entity, you must set the attribute on its architecture rather than
on the entity itself.
Example 17121. Verilog-1995 Code: Applying altera_attribute to an Entity
module my_entity() /* synthesis altera_attribute = "-name
AUTO_SHIFT_REGISTER_RECOGNITION OFF" */;
You can also use altera_attribute for more complex assignments that have more
than one instance. In Example 17125 through Example 17127, the altera_attribute
cuts all timing paths from reg1 to reg2, equivalent to this Tcl or .qsf command, as
shown in Example 17124:
Example 17124.
set_instance_assignment -name CUT ON -from reg1 -to reg2 r
Example 17125. Verilog-1995 Code: Applying altera_attribute with the -to Option
reg reg2;
reg reg1 /* synthesis altera_attribute = "-name CUT ON -to reg2" */;
Example 17126. Verilog-2001 and SystemVerilog Code: Applying altera_attribute with the -to
Option
reg reg2;
(* altera_attribute = "-name CUT ON -to reg2" *) reg reg1;
Example 17127. VHDL Code: Applying altera_attribute with the -to Option
signal reg1, reg2 : std_logic;
attribute altera_attribute: string;
attribute altera_attribute of reg1 : signal is "-name CUT ON -to reg2";
1773
You can specify either the -to option or the -from option in a single
altera_attribute; Integrated Synthesis automatically sets the remaining option to
the target of the altera_attribute. You can also specify wildcards for either option.
For example, if you specify * for the -to option instead of reg2 in these examples,
the Quartus II software cuts all timing paths from reg1 to every other register in this
design entity.
You can use the altera_attribute only for entity-level settings, and the assignments
(including wildcards) apply only to the current entity.
Project Navigator
The Hierarchy tab of the Project Navigator provides a view of the project hierarchy
and a summary of resource and device information about the current project. After
Analysis & Synthesis, before the Fitter begins, the Project Navigator provides a
summary of utilization based on synthesis data, before Fitter optimizations have
occurred.
If an entity in the Hierarchy tab contains parameter settings, a tooltip displays the
settings when you hold the pointer over the entity.
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Quartus II Messages
The messages that appear during Analysis & Synthesis describe many of the
optimizations during the synthesis stage, and provide information about how the
software interprets your design. Altera recommends checking the messages to
analyze Critical Warnings and Warnings, because these messages can relate to
important design problems. Read the Info messages to get more information about
how the software processes your design.
The software groups the messages by following types: Info, Warning, Critical
Warning, and Error.
h For more information about the Messages window and message suppression, refer to
About the Messages Window and About Message Suppression in Quartus II Help.
f For more information about the Messages, refer to Managing Quartus II Projects
chapter in volume 2 of the Quartus II Handbook.
You can specify the type of Analysis & Synthesis messages that you want to view by
selecting the Analysis & Synthesis Message Level option. You can specify the
display level by performing the following steps:
1. On the Assignments menu, click Settings.
2. In the Category list, click Analysis & Synthesis Settings.
3. Click More Settings. Select the level for the Analysis & Synthesis Message Level
option.
Error messageindicates an actual problem with your design. Your HDL code
can be invalid due to a syntax or semantic error, or it might not be synthesizable as
written.
1775
In Example 17128, the sensitivity list contains multiple copies of the variable i. While
the Verilog HDL language does not prohibit duplicate entries in a sensitivity list, it is
clear that this design has a typing error: Variable j should be listed on the sensitivity
list to avoid a possible simulation or synthesis mismatch.
Example 17128. Generating an HDL Warning Message
//dup.v
module dup(input i, input j, output reg o);
always @ (i or i)
o = i & j;
endmodule
When processing the HDL code, the Quartus II software generates the warning
message shown in Example 17129:
Example 17129.
Warning: (10276) Verilog HDL sensitivity list warning at dup.v(2):
sensitivity list contains multiple entries for "i".
In Verilog HDL, variable names are case sensitive, so the variables my_reg and MY_REG
in Example 17130 are two different variables. However, declaring variables that have
names in different cases is confusing, especially if you use VHDL, in which variables
are not case sensitive.
Example 17130. Generating HDL Info Messages
// namecase.v
module namecase (input i, output o);
reg my_reg;
reg MY_REG;
assign o = i;
endmodule
When processing the HDL code, the Quartus II software generates the following
informational message, as shown in Example 17131:
Example 17131.
Info: (10281) Verilog HDL information at namecase.v(3): variable name
"MY_REG" and variable name "my_reg" should not differ only in case.
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not
HDL
not
1776
The Quartus II software allows you to control how many HDL messages you can
view during the Analysis & Elaboration of your design files. You can set the HDL
Message Level to enable or disable groups of HDL messages, or you can enable or
disable specific messages, as described in the following sections.
For more information about synthesis directives and their syntax, refer to Synthesis
Directives on page 1727.
Purpose
Description
Level1
Level2
High-severity and
medium-severity messages
Level3
You must address all issues reported at the Level1 setting. The default HDL message
level is Level2.
To set the HDL Message Level in the Quartus II software, follow these steps:
1. On the Assignments menu, click Settings.
2. In the Category list, click Analysis & Synthesis Settings.
3. Set the necessary message level from the pull-down menu in the HDL Message
Level list, and then click OK.
You can override this default setting in a source file with the message_level
synthesis directive, which takes the values level1, level2, and level3, as shown in
Example 17133 and Example 17134.
Example 17133. Verilog HDL Examples of message_level Directive
// altera message_level level1
or
/* altera message_level level3 */
1777
A message_level synthesis directive remains effective until the end of a file or until
the next message_level directive. In VHDL, you can use the message_level synthesis
directive to set the HDL Message Level for entities and architectures, but not for other
design units. An HDL Message Level for an entity applies to its architectures, unless
overridden by another message_level directive. In Verilog HDL, you can use the
message_level directive to set the HDL Message Level for a module.
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For example, if entity A contains a register (DFF atom) called my_dff, its full hierarchy
name would be A:my_A_inst|my_dff.
To instruct the Compiler to generate node names that do not contain entity names, on
the Compilation Process Settings page of the Settings dialog box, click More
Settings, and then turn off Display entity name for node name. With this option
turned off, the node names use the convention in shown in Example 17138:
Example 17138.
<instance_name 0>|<instance_name 1>|...|<instance_name n> |<node_name>
1779
AHDL designs explicitly declare DFF registers rather than infer, so the software uses
the user-declared name for the register.
For schematic designs using a .bdf, your design names all elements when you
instantiate the elements in your design, so the software uses the name you defined for
the register or DFF.
In the special case that a wire or signal (such as my_dff_out in the preceding
examples) is also an output pin of your top-level design, the Quartus II software
cannot use that name for the register (for example, cannot use my_dff_out) because
the software requires that all logic and I/O cells have unique names. Here, Quartus II
Integrated Synthesis appends ~reg0 to the register name.
For example, the Verilog HDL code in Example 17141 generates a register called
q~reg0:
Example 17141. Verilog HDL Register Feeding Output Pin
module my_dff (input clk, input d, output q);
always @ (posedge clk)
q <= d;
endmodule
This situation occurs only for registers driving top-level pins. If a register drives a port
of a lower level of the hierarchy, the software removes the port during hierarchy
flattening and the register retains its original name, in this case, q.
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State Machines
Packed Input and Output Registers of RAM and DSP Blocks on page 1782
1781
Quartus II Integrated Synthesis creates synonyms for registers duplicated with the
Maximum Fan-Out option (or maxfan attribute). Therefore, timing assignments
applied to nodes that are duplicated with this option are applied to the new nodes as
well.
The Quartus II Fitter can also change node names after synthesis (for example, when
the Fitter uses register packing to pack a register into an I/O element, or when
physical synthesis modifies logic). The Fitter creates synonyms for duplicated
registers so timing analysis can use the existing node name when applying
assignments.
You can instruct the Quartus II software to preserve certain nodes throughout
compilation so you can use them for verification or making assignments. For more
information, refer to Preserving Register Names on page 1782.
State Machines
If your HDL code infers a state machine, the software maps the registers that
represent the states into a new set of registers that implement the state machine. Most
commonly, the software converts the state machine into a one-hot form in which one
register represents each state. In this case, for Verilog HDL or VHDL designs, the
registers take the name of the state register and the states.
For example, consider a Verilog HDL state machine in which the states are parameter
state0 = 1, state1 = 2, state2 = 3, and in which the software declares the state
machine register as reg [1:0] my_fsm. In this example, the three one-hot state
registers are my_fsm.state0, my_fsm.state1, and my_fsm.state2.
An AHDL design explicitly specifies state machines with a state machine name. Your
design names state machine registers with synthesized names based on the state
machine name, but not the state names. For example, if a my_fsm state machine has
four state bits, The software might synthesize these state bits with names such as
my_fsm~12, my_fsm~13, my_fsm~14, and my_fsm~15.
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For schematic designs using a .bdf, your design names all elements when you
instantiate the elements in your design and the software uses the name you defined
when possible.
1783
If logic cells, such as those created in Example 17142, are packed with registers in
device architectures such as the Stratix and Cyclone device families, those names
might not appear in the netlist after fitting. In other devices, such as newer families in
the Stratix and Cyclone series device families, the register and combinational nodes
are kept separate throughout the compilation, so these names are more often
maintained through fitting.
When logic optimizations occur during synthesis, it is not always possible to retain
the initial names as described. Sometimes, synthesized names are used, which are the
wire names with a tilde (~) and a number appended. For example, if a complex
expression is assigned to wire w and that expression generates several logic cells, those
cells can have names such as w, w~1, and w~2. Sometimes the original wire name w is
removed, and an arbitrary name such as rtl~123 is created. Quartus II Integrated
Synthesis attempts to retain user names whenever possible. Any node name ending
with ~<number> is a name created during synthesis, which can change if the design is
changed and re-synthesized. Knowing these naming conventions helps you
understand your post-synthesis results, helping you to debug your design or create
assignments.
During synthesis, the software maintains combinational clock logic by not changing
nodes that might be clocks. The software also maintains or protects multiplexers in
clock trees, so that the TimeQuest analyzer has information about which paths are
unate, to allow complete and correct analysis of combinational clocks. Multiplexers
often occur in clock trees when the software selects between different clocks. To help
with the analysis of clock trees, the software ensures that each multiplexer
encountered in a clock tree is broken into 2:1 multiplexers, and each of those 2:1
multiplexers is mapped into one lookup table (independent of the device family). This
optimization might result in a slight increase in area, and for some designs a decrease
in timing performance. You can turn off this multiplexer protection with the option
Clock MUX Protection under More Settings on the Analysis & Synthesis Settings
page of the Settings dialog box.
h For more information about Clock MUX Protection logic option and a list of
supported devices, refer to Clock MUX Protection logic option in Quartus II Help.
May 2013
Setting the keep attribute for combinational logic can increase the area utilization and
increase the delay of the final mapped logic because the attribute requires the
insertion of extra combinational logic. Use the attribute only when necessary.
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Scripting Support
You can run procedures and make settings in a Tcl script. You can also run some
procedures at a command prompt. For detailed information about scripting command
options, refer to the Quartus II Command-Line and Tcl API Help browser.
To run the Help browser, type the command at the command prompt shown in
Example 17143:
Example 17143.
quartus_sh --qhelp r
f For more information about Tcl scripting, refer to the Tcl Scripting chapter in volume 2
of the Quartus II Handbook. For more information about all settings and constraints in
the Quartus II software, refer to the Quartus II Settings File Manual. For more
information about command-line scripting, refer to the Command-Line Scripting
chapter in volume 2 of the Quartus II Handbook.
h For more information about Tcl scripting, refer to API Functions for Tcl in Quartus II
Help.
You can specify many of the options described in this section either on an instance, at
the global level, or both.
To make a global assignment, use the Tcl command shown in Example 17144:
Example 17144.
set_global_assignment -name <QSF Variable Name> <Value> r
To make an instance assignment, use the Tcl command shown in Example 17145:
Example 17145.
set_instance_assignment -name <QSF Variable Name> <Value>\ -to
<Instance Name> r
To set the Synthesis Effort option at the command line, use the --effort option with
the quartus_map executable, as shown in Example 17146.
Example 17146. Command Syntax for Specifying Synthesis Effort Option
quartus_map <Design name> --effort= "auto | fast" r
The early timing estimate feature gives you preliminary timing estimates before
running a full compilation, which results in a quicker iteration time; therefore, you
can save significant compilation time to get a good estimation of the final timing of
your design.
1785
If you want to run fast synthesis with the Fitter Early Timing Estimate option, use the
command shown in Example 17147. This command runs the full flow with timing
analysis:
Example 17147. Command Syntax for Running Fast Synthesis with Early Timing Estimate Option
quartus_sh --flow early_timing_estimate_with_synthesis <Design name> r
name
name
name
-name
-name
You can use any file extension for design files, as long as you specify the correct
language when adding the design file. For example, you can use .h for Verilog HDL
header files.
To specify the Verilog HDL or VHDL version, use the option shown in
Example 17149, at the end of the VERILOG_FILE or VHDL_FILE command:
Example 17149.
-
VERILOG_1995
VERILOG_2001
SYSTEMVERILOG_2005
VHDL_1987
VHDL_1993
VHDL_2008
For example, to add a Verilog HDL file called my_file.v written in Verilog-1995, use
the command shown in Example 17150:
Example 17150.
set_global_assignment name VERILOG_FILE my_file.v HDL_VERSION \
VERILOG_1995
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In Example 17151, the syn_encoding attribute associates a binary encoding with the
states in the enumerated type count_state. In this example, the states are encoded
with the following values: zero = "11", one = "01", two = "10", three = "00".
Example 17151. Specifying User-Encoded States with the syn_encoding Attribute in VHDL
ARCHITECTURE rtl OF my_fsm IS
TYPE count_state is (zero, one, two, three);
ATTRIBUTE syn_encoding : STRING;
ATTRIBUTE syn_encoding OF count_state : TYPE IS "11 01 10 00";
SIGNAL present_state, next_state : count_state;
BEGIN
You can also use the syn_encoding attribute in Verilog HDL to direct the synthesis tool
to use the encoding from your HDL code, instead of using the State Machine
Processing option.
The syn_encoding value "user" instructs the Quartus II software to encode each state
with its corresponding value from the Verilog HDL source code. By changing the
values of your state constants, you can change the encoding of your state machine.
In Example 17152, the states are encoded as follows:
init = "00"
last = "11"
next = "01"
later = "10"
Example 17152. Verilog-2001 and SystemVerilog Code: Specifying User-Encoded States with
the syn_encoding Attribute
(* syn_encoding = "user" *) reg [1:0] state;
parameter init = 0, last = 3, next = 1, later = 2;
always @ (state) begin
case (state)
init:
out = 2'b01;
next:
out = 2'b10;
later:
out = 2'b11;
last:
out = 2'b00;
endcase
end
Without the syn_encoding attribute, the Quartus II software encodes the state
machine based on the current value of the State Machine Processing logic option.
If you also specify a safe state machine (as described in Safe State Machine on
page 1738), separate the encoding style value in the quotation marks from the safe
value with a comma, as follows: safe, one-hot or safe, gray.
For more information, refer to Manually Specifying State Assignments Using the
syn_encoding Attribute on page 1736.
1787
Assigning a Pin
To assign a signal to a pin or device location, use the Tcl command shown in
Example 17153:
Example 17153.
The <file name> variable is the name used for internally generated netlist files during
incremental compilation. If you create the partition in the Quartus II software, netlist
files are named automatically by the Quartus II software based on the instance name.
If you use Tcl to create your partitions, you must assign a custom file name that is
unique across all partitions. For the top-level partition, the specified file name is
ignored, and you can use any dummy value. To ensure the names are safe and
platform independent, file names should be unique, regardless of case. For example, if
a partition uses the file name my_file, no other partition can use the file name
MY_FILE. To make file naming simple, Altera recommends that you base each file
name on the corresponding instance name for the partition.
The <destination> is the short hierarchy path of the entity. A short hierarchy path is the
full hierarchy path without the top-level name, for example:
"ram:ram_unit|altsyncram:altsyncram_component" (with quotation marks). For the
top-level partition, you can use the pipe (|) symbol to represent the top-level entity.
For more information about hierarchical naming conventions, refer to Node-Naming
Conventions in Quartus II Integrated Synthesis on page 1778.
The <partition name> is the partition name you designate, which should be unique and
less than 1024 characters long. The name may only consist of alphanumeric
characters, as well as pipe ( | ), colon ( : ), and underscore ( _ ) characters. Altera
recommends enclosing the name in double quotation marks (" ").
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Conclusion
The Quartus II Integrated Synthesis supports Verilog HDL, SystemVerilog, VHDL,
and Altera-specific languages, making the synthesis feature an easy-to-use,
standalone solution for Altera designs. You can use the synthesis options in the
software or in your HDL code to better control the way your design is synthesized,
helping you improve your synthesis results. Use Quartus II reports and messages to
analyze your compilation results.
May 2011
December 2010
Version
13.0.0
12.0.0
11.1.0
11.0.0
10.1.0
Changes
Updated Specifying Pin Locations with chip_pin on page 1465, and Shift Registers
on page 1448.
Updated VHDL-2008 Support on page 139 to include the condition operator (explicit
and implicit) support.
Added Creating LogicLock Regions on page 1332 and Using Assignments to Limit
the Number of RAM and DSP Blocks on page 1333.
Updated Turning Off the Add Pass-Through Logic to Inferred RAMs no_rw_check
Attribute on page 1355.
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July 2010
December 2009
May 2013
Version
Changes
10.0.0
Turning Off the Add Pass-Through Logic to Inferred RAMs no_rw_check Attribute on
page 955
Adding an HDL File to a Project and Setting the HDL Version on page 983
Inferring Multiplier, DSP, and Memory Functions from HDL Code on page 950
9.1.1
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Version
Changes
November 2009
March 2009
9.1.0
Adding an HDL File to a Project and Setting the HDL Version on page 981
9.0.0
Analysis & Synthesis Settings Page of the Settings Dialog Box on page 924
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
This chapter documents support for the Synopsys Synplify software in the
Quartus II software, as well as key design flows, methodologies, and techniques for
achieving optimal results in Altera devices.
This chapter includes the following topics:
The content in this chapter applies to the Synplify, Synplify Pro, and Synplify Premier
software unless otherwise specified. This chapter includes the following sections:
This chapter assumes that you have set up, licensed, and are familiar with the
Synplify software.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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182
The Synplify software also supports the FLEX 8000 and MAX 9000 legacy devices that
are supported only in the Altera MAX+PLUS II software, as well as ACEX 1K,
APEX II, APEX 20K, APEX 20KC, APEX 20KE, FLEX 10K, and FLEX 6000 legacy
devices that are supported by the Quartus II software version 9.0 and earlier.
Design Flow
The following steps describe a basic Quartus II software design flow using the
Synplify software:
1. Create Verilog HDL or VHDL design files.
2. Set up a project in the Synplify software and add the HDL design files for
synthesis.
3. Select a target device and add timing constraints and compiler directives in the
Synplify software to help optimize the design during synthesis.
4. Synthesize the project in the Synplify software.
5. Create a Quartus II project and import the following files generated by the
Synplify software into the Quartus II software. Use the following files for
placement and routing, and for performance evaluation:
The Synopsys Constraints Format (.scf) file for TimeQuest Timing Analyzer
constraints
If your design uses the Classic Timing Analyzer for timing analysis in the
Quartus II software versions 10.0 and earlier, the Synplify software
generates timing constraints in the Tcl Constraints File (.tcl). If you are
using the Quartus II software versions 10.1 and later, you must use the
TimeQuest Timing Analyzer for timing analysis.
183
Figure 181 shows the recommended design flow using the Synplify and the
Quartus II software.
Figure 181. Recommended Design Flow
System
Verilog
(.v)
VHDL
(.vhd)
Verilog
HDL
(.v)
Functional/RTL
Simulation
Synplify Software
TechnologySpecific Netlist
(.vqm/edf)
Forward-Annotated
Project Constraints
(.tcl/.acf)
Synopsys Constraints
format (.scf) File
Quartus II Software
Gate-Level
Functional
Simulation
Post-Synthesis
Simulation Files
(.vho/.vo)
Gate-Level Timing
Simulation
No
Post-Place-and-Route
Simulation File
(.vho/.vo)
Yes
Configuation/Programming
Files (.sof/.pof)
Program/Configure Device
The Synplify software supports VHDL, Verilog HDL, and SystemVerilog source files.
However, only the Synplify Pro and Premier software support mixed synthesis,
allowing a combination of VHDL and Verilog HDL or SystemVerilog format source
files.
Specify timing constraints and attributes for a design in a SCOPE Design Constraints
File (.sdc) with the SCOPE window in the Synplify software using the standard
Synopsys Design Constraint (SDC) format, or directly in the HDL source file. You can
also define compiler directives in the HDL source file. Many of these constraints are
forward-annotated for use by the Quartus II software. See Table 181 on page 184 for
a list of the files generated by Synplify.
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The HDL Analyst that is included in the Synplify software is a graphical tool for
generating schematic views of the technology-independent RTL view netlist (.srs) and
technology-view netlist (.srm) files. You can use the Synplify HDL Analyst to analyze
and debug your design visually. The HDL Analyst supports cross-probing between
the RTL and Technology views, the HDL source code, the Finite State Machine (FSM)
viewer, and between the technology view and the timing report file in the Quartus II
software.
1
A separate license file is required to enable the HDL Analyst in the Synplify software.
The Synplify Pro and Premier software include the HDL Analyst.
After synthesis is complete, import the .vqm or .edf netlist to the Quartus II software
for place-and-route. Use the .tcl file generated by the Synplify software to
forward-annotate your project constraints including device selection, called the
generated .scf file to forward-annotate TimeQuest Timing Analyzer timing
constraints, and optionally to set up your project in the Quartus II software.
If area and timing requirements are satisfied, use the files generated by the Quartus II
software to program or configure the Altera device. As shown in Figure 181, if your
area or timing requirements are not met, you can change the constraints in the
Synplify software or the Quartus II software and rerun synthesis. Altera recommends
that you provide timing constraints in the Synplify software and any placement
constraints in the Quartus II software. Repeat the process until area and timing
requirements are met.
You can perform simulation and formal verification at various stages in the design
process. You can perform final timing analysis after placement and routing is
complete.
f For more information about how the Synplify software supports formal verification,
refer to Section V. Formal Verification in volume 3 of the Quartus II Handbook.
You can also use other options and techniques in the Quartus II software to meet area
and timing requirements, such as WYSIWYG Primitive Resynthesis, which can
perform optimizations on your .vqm netlist within the Quartus II software.
f For information about netlist optimizations, refer to the Netlist Optimizations and
Physical Synthesis chapter in volume 3 of the Quartus II Handbook.
1
In some cases, you might be required to modify the source code if the area and timing
requirements cannot be met using options in the Synplify and Quartus II software.
During synthesis, the Synplify software produces several intermediate and output
files, which are listed and described in Table 181.
Technology-independent RTL netlist file that can be read only by the Synplify software.
.srm
.srr
File Description
(1)
185
File Description
Technology-specific netlist in .vqm or .edf file format.
.vqm/.edf
A .vqm file is created for all Altera device families supported by the Quartus II software. An .edf file is
created for devices supported by the MAX+PLUS II software.
Forward-annotated constraints file containing constraints and assignments.
.tcl
A .tcl file for the Quartus II software is created for all devices. The .tcl file contains the appropriate Tcl
commands to create and set up a Quartus II project and pass placement constraints.
.acf
Assignment and Configurations file for backward compatibility with the MAX+PLUS II software. For
devices supported by the MAX+PLUS II software, the MAX+PLUS II assignments are imported from the
MAX+PLUS II .acf file.
.scf
Synopsys Constraint Format file containing timing constraints for the TimeQuest Timing Analyzer.
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The Quartus Version list is available only after selecting an Altera device.
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To specify the Quartus II software version used in the Synplify software, perform the
following steps:
1. In the Synplify software, on the Project menu, click Implementation Options.
2. Click the Implementation Results tab.
3. Specify your version of the Quartus II software in the Quartus Version list.
Alternatively, type the following command at the command line:
set_option -quartus_version <version number> r
187
The Synplify Synthesis Report File (.srr) contains timing reports of estimated
place-and-route delays. The Quartus II software can perform further optimizations on
a post-synthesis netlist from third-party synthesis tools. In addition, designs might
contain black boxes or intellectual property (IP) functions that have not been
optimized by the third-party synthesis software. Actual timing results are obtained
only after the design has been fully placed and routed in the Quartus II software. For
these reasons, the Quartus II post place-and-route timing reports provide a more
accurate representation of the design. Use the statistics in these reports to evaluate
design performance.
Clock Frequencies
For single-clock designs, you can specify a global frequency when using the
push-button flow. While this flow is simple and provides good results, it often does
not meet the performance requirements for more advanced designs. You can use
timing constraints, compiler directives, and other attributes to help optimize the
performance of a design. You can enter these attributes and directives directly in the
HDL code. Alternatively, you can enter attributes (not directives) into an .sdc file with
the SCOPE window in the Synplify software.
Use the SCOPE window to set global frequency requirements for the entire design
and individual clock settings. Use the Clocks tab in the SCOPE window to specify
frequency (or period), rise times, fall times, duty cycle, and other settings. Assigning
individual clock settings, rather than over-constraining the global frequency, helps the
Quartus II software and the Synplify software achieve the fastest clock frequency for
the overall design. The define_clock attribute assigns clock constraints.
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Equation 182 illustrates the relationship between tSU and the input delay:
Equation 182.
t SU = clock period external input delay
Multicycle Paths
A multicycle path is a path that requires more than one clock cycle to propagate.
Specify any multicycle paths in the design in the Multi-Cycle Paths tab of the SCOPE
window, or with the define_multicycle_path attribute. You should specify which
paths are multicycle to prevent the Quartus II and the Synplify compilers from
working excessively on a non-critical path. Not specifying these paths can also result
in an inaccurate critical path reported during timing analysis.
False Paths
False paths are paths that should be ignored during timing analysis, or be assigned
low (or no) priority during optimization. Some examples of false paths include slow
asynchronous resets, and test logic that has been added to the design. Set these paths
in the False Paths tab of the SCOPE window, or use the define_false_path attribute.
189
FSM Compiler
If the FSM Compiler is turned on, the compiler automatically detects state machines
in a design, which are then extracted and optimized. The FSM Compiler analyzes
state machines and implements sequential, gray, or one-hot encoding, based on the
number of states. The compiler also performs unused-state analysis, optimization of
unreachable states, and minimization of transition logic. Implementation is based on
the number of states, regardless of the coding style in the HDL code
If the FSM Compiler is turned off, the compiler does not optimize logic as state
machines. The state machines are implemented as coded in the HDL code. Thus, if the
coding style for a state machine is sequential, the implementation is also sequential.
Use the syn_state_machine complier directive to specify or prevent a state machine
from being extracted and optimized. To override the default encoding of the FSM
Compiler, use the syn_encoding directive.
The values for the syn_encoding directive are described in Table 182.
Table 182. syn_encoding Directive Values
Value
Description
Sequential
Generates state machines with the fewest possible flipflops. Sequential, also called binary, state machines
are useful for area-critical designs when timing is not the primary concern.
Gray
Generates state machines where only one flipflop changes during each transition. Gray-encoded state
machines tend to be free of glitches.
One-hot
Generates state machines containing one flipflop for each state. One-hot state machines typically provide
the best performance and shortest clock-to-output delays. However, one-hot implementations are usually
larger than sequential implementations.
Safe
Generates extra control logic to force the state machine to the reset state if an invalid state is reached. You
can use the safe value in conjunction with any of the other three values, which results in the state machine
being implemented with the requested encoding scheme and the generation of the reset logic.
Example 181 shows sample VHDL code for applying the syn_encoding directive.
Example 181. Sample VHDL Code for syn_encoding
SIGNAL current_state : STD_LOGIC_VECTOR(7 DOWNTO 0);
ATTRIBUTE syn_encoding : STRING;
ATTRIBUTE syn_encoding OF current_state : SIGNAL IS "sequential";
By default, the state machine logic is optimized for speed and area, which may be
potentially undesirable for critical systems. The safe value generates extra control
logic to force the state machine to the reset state if an invalid state is reached.
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Maximum Fan-Out
When your design has critical path nets with high fan-out, use the syn_maxfan
attribute to control the fan-out of the net. Setting this attribute for a specific net results
in the replication of the driver of the net to reduce overall fan-out. The syn_maxfan
attribute takes an integer value and applies it to inputs or registers. The syn_maxfan
attribute cannot be used to duplicate control signals. The minimum allowed value of
the attribute is 4. Using this attribute might result in increased logic resource
utilization, thus straining routing resources, which can lead to long compilation times
and difficult fitting.
If you must duplicate an output register or an output enable register, you can create a
register for each output pin by using the syn_useioff attribute. Refer to Register
Packing on page 1810.
Preserving Nets
During synthesis, the compiler maintains ports, registers, and instantiated
components. However, some nets cannot be maintained to create an optimized circuit.
Applying the syn_keep directive overrides the optimization of the compiler and
preserves the net during synthesis. The syn_keep directive is a Boolean data type
value and can be applied to wires (Verilog HDL) and signals (VHDL). Setting the
value to true preserves the net through synthesis.
Register Packing
Altera devices allow register packing into I/O cells. Altera recommends allowing the
Quartus II software to make the I/O register assignments. However, you can control
register packing with the syn_useioff attribute. The syn_useioff attribute is a
Boolean data type value that can be applied to ports or entire modules. Setting the
value to 1 instructs the compiler to pack the register into an I/O cell. Setting the value
to 0 prevents register packing in both the Synplify and Quartus II software.
Resource Sharing
The Synplify software uses resource sharing techniques during synthesis, by default,
to reduce area. Turning off the Resource Sharing option on the Options tab of the
Implementation Options dialog box improves performance results for some designs.
You can also turn off the option for a specific module with the syn_sharing attribute.
If you turn off this option, be sure to check the results to verify improvement in timing
performance. If there is no improvement, turn on Resource Sharing.
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Preserving Hierarchy
The Synplify software performs cross-boundary optimization by default, which
causes the design to flatten to allow optimization. You can use the syn_hier attribute
to override the default compiler settings. The syn_hier attribute applies a string value
to modules, architectures, or both. Setting the value to hard maintains the boundaries
of a module, architecture, or both, but allows constant propagation. Setting the value
to locked prevents all cross-boundary optimizations. Use the locked setting with the
partition setting to create separate design blocks and multiple output netlists for
incremental compilation, as described in Using MultiPoint Synthesis with
Incremental Compilation on page 1831.
By default, the Synplify software generates a hierarchical .vqm file. To flatten the file,
set the syn_netlist_hierarchy attribute to 0.
RouteShrinks the effective period for the constrained registers by the specified
value without affecting the clock period that is forward-annotated to the
Quartus II software.
Use the following Tcl command syntax to specify an input or output register delay in
nanoseconds.
Example 182. Specifying an Input or Output Register Delay Using Tcl Command Syntax
define_reg_input_delay {<register>} -route <delay in ns>
define_reg_output_delay {<register>} -route <delay in ns>
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syn_direct_enable
This attribute controls the assignment of a clock-enable net to the dedicated enable
pin of a register. With this attribute, you can direct the Synplify mapper to use a
particular net as the only clock enable when the design has multiple clock enable
candidates.
To use this attribute as a compiler directive to infer registers with clock enables, enter
the syn_direct_enable directive in your source code, instead of the SCOPE
spreadsheet.
The syn_direct_enable data type is Boolean. A value of 1 or true enables net
assignment to the clock-enable pin. The following is the syntax for Verilog HDL:
object /* synthesis syn_direct_enable = 1 */ ;
I/O Standard
For certain Altera devices, specify the I/O standard type for an I/O pad in the design
with the I/O Standard panel in the Synplify SCOPE window.
Example 183 shows the Synplify SDC syntax for the define_io_standard constraint,
in which the delay_type must be either input_delay or output_delay.
Example 183. Synplify SDC Syntax for the define_io_standard Constraint
define_io_standard [-disable|-enable] {<objectName>} -delay_type \
[input_delay|output_delay] <columnTclName>{<value>} [<columnTclName>{<value>}...]
f For details about supported I/O standards, refer to the Altera I/O Standards section in
the Synopsys FPGA Synthesis Reference Manual.
Altera-Specific Attributes
You can use the attributes described in this section with specific Altera device
features, which are forward-annotated to the Quartus II project, and are used during
place-and-route.
altera_chip_pin_lc
Use the altera_chip_pin_lc attribute to make pin assignments. This attribute applies a
string value to inputs and outputs. Use the attribute only on the ports of the top-level
entity in the design. Do not use this attribute to assign pin locations from entities at
lower levels of the design hierarchy.
1
The altera_chip_pin_lc attribute is not supported for any MAX series device.
In the SCOPE window, set the value of the altera_chip_pin_lc attribute to a pin
number or a list of pin numbers.
1813
Example 184 shows VHDL code for making location assignments for supported
Altera devices. Pin location assignments for these devices are written to the output .tcl
file.
Example 184. Making Location Assignments in VHDL
ENTITY sample (data_in : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
data_out: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
ATTRIBUTE altera_chip_pin_lc : STRING;
ATTRIBUTE altera_chip_pin_lc OF data_out : SIGNAL IS "14, 5, 16, 15";
altera_io_powerup
Use the altera_io_powerup attribute to define the power-up value of an I/O register
that has no set or reset. This attribute applies a string value (high|low) to ports with
I/O registers. By default, the power-up value of the I/O register is set to low.
altera_io_opendrain
Use the altera_io_opendrain attribute to specify open-drain mode I/O ports. This
attribute applies a boolean data type value to outputs or bidirectional ports for
devices that support open-drain mode.
When you are using NativeLink integration, the path to your project must not contain
empty spaces. The Synplify software uses Tcl scripts to communicate with the
Quartus II software, and the Tcl language does not accept arguments with empty
spaces in the path.
Use NativeLink integration to integrate the Synplify software and Quartus II software
with a single GUI for both synthesis and place-and-route operations. NativeLink
integration allows you to run the Quartus II software from within the Synplify
software GUI, or to run the Synplify software from within the Quartus II software
GUI.
This section explains the different NativeLink flows and provides details about how
constraints are passed to the Quartus II software, and describes the following topics:
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Using the Quartus II Software to Run the Synplify Software on page 1815
The <project_name>_cons.tcl file is used to set up the Quartus II project and directs the
<project_name>.tcl file to pass constraints from the Synplify software to the Quartus II
software. By default, the <project_name>.tcl file contains device, timing, and location
assignments. The <project_name>.tcl file contains the command to use the
Synplify-generated .scf constraints file with the TimeQuest Timing Analyzer.
1815
For best results, Synopsys recommends that you set constraints in the Synplify
software and use a Tcl script to pass these constraints to the Quartus II software,
instead of opening the Synplify software from within the Quartus II software.
To set up the Synplify software in the Quartus II software, on the Tools menu, click
Options. In the Options dialog box, click EDA Tool Options and specify the path of
the Synplify or Synplify Pro software under Location of Executable.
h For more information about using NativeLink integration with the Synplify software
in the Quartus II software, refer to About Using the Synplify Software with the Quartus II
Software in Quartus II Help.
Running the Synplify software with NativeLink integration is supported on both
floating network and node-locked fixed PC licenses. Both types of licenses support
batch mode compilation.
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Synopsys recommends that you modify constraints using the SCOPE constraint editor
window, rather than using the generated .sdc, .scf, or .tcl file.
The following list of Synplify constraints are converted to the equivalent Quartus II
SDC commands and are forward-annotated to the Quartus II software in the .scf file:
define_clock
define_input_delay
define_output_delay
define_multicycle_path
define_false_path
All Synplify constraints described in the following sections are mapped to SDC
commands for the TimeQuest Timing Analyzer.
h For syntax and arguments for these commands, refer to the applicable subsection or
refer to Synplify Help. For a list of corresponding commands in the Quartus II
software, refer to the Quartus II Help.
Multicycle Path
Specify a multicycle path constraint in the Synplify software with the
define_multicycle_path command. This command is passed to the Quartus II
software with the set_multicycle_path command.
False Path
Specify a false path constraint in the Synplify software with the define_false_path
command. This command is passed to the Quartus II software with the
set_false_path command.
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You can instantiate a megafunction in your HDL code with the MegaWizard Plug-In
Manager to parameterize the function, or instantiate the function using the port and
parameter definition. The MegaWizard Plug-In Manager provides a graphical
interface within the Quartus II software for customizing and parameterizing any
available megafunction for the design. For more information about the MegaWizard
Plug-In Manager flow with the Synplify software, refer to Instantiating Altera
Megafunctions With the MegaWizard Plug-In Manager on page 1817 and
Instantiating Intellectual Property With the MegaWizard Plug-In Manager and IP
Toolbench on page 1819.
f For more information about specific Altera megafunctions, refer to the Quartus II
Help. For more information about IP functions, refer to the appropriate IP
documentation.
The Synplify software also automatically recognizes certain types of HDL code, and
infers the appropriate megafunction when a megafunction provides optimal results.
The Synplify software provides options to control inference of certain types of
megafunctions, as described in Inferring Altera Megafunctions from HDL Code on
page 1822.
f For more information about instantiating versus inferring megafunctions, refer to the
Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook. This
chapter also provides details about using the MegaWizard Plug-In Manager in the
Quartus II software and explains the files generated by the wizard, as well as coding
style recommendations and HDL examples for inferring megafunctions in Altera
devices.
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Verify that the correct Quartus II version is specified in the Synplify software before
compiling the MegaWizard-generated file to ensure that the software uses the correct
library definitions for the megafunction. The Quartus Version setting must match the
version of the Quartus II software used to generate the customized megafunction in
the MegaWizard Plug-In Manager.
For details about how to set the Quartus II version in the Synplify software, refer to
Specifying the Quartus II Software Version on page 185.
In addition, ensure that the QUARTUS_ROOTDIR environment variable specifies the
installation directory location of the correct Quartus II version. The Synplify software
uses this information to launch the Quartus II software in the background. The
environment variable setting must match the version of the Quartus II software used
to generate the customized megafunction in the MegaWizard Plug-In Manager. Refer
to Using the Quartus II Software to Run the Synplify Software on page 1815 for
more details.
1819
The Synplify software directs the Quartus II software to generate information in two
ways:
For these functions, the Synplify software uses the logic information for resource and
timing estimation and optimization, and then instantiates the megafunction in the
output .vqm netlist file so the Quartus II software can implement the appropriate
device primitives. By default, the Synplify software uses the clear box model when
available, and otherwise uses the grey box model. To change this behavior, perform
the following steps:
1. In the Synplify software, click Implementation Options.
2. On the Device tab, specify one of the following values for the Altera Models
option:
Onuses the clearbox model when available and the grey box model when the
clearbox model is unavailable
clearbox_onlyenables the clear box model, but not the grey box model
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For information about including Quartus II-specific files in your Synplify project so
they are automatically passed to the Quartus II software along with the output .vqm
file, refer to Including Files for Quartus II Placement and Routing Only on
page 1822.
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Example 186 shows a sample top-level file that instantiates my_vhdlIP.vhd, which is
a simplified customized variation generated by the MegaWizard Plug-In Manager
and the IP Toolbench.
Example 186. Sample Top-Level VHDL Code with Black Box Instantiation of IP
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY top IS
PORT (
clk: IN STD_LOGIC ;
count: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END top;
ARCHITECTURE rtl OF top IS
COMPONENT my_vhdlIP
PORT (
clock: IN STD_LOGIC ;
q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end COMPONENT;
attribute syn_black_box : boolean;
attribute syn_black_box of my_vhdlIP: component is true;
BEGIN
vhdlIP_inst : my_vhdlIP PORT MAP (
clock => clk,
q => count
);
END rtl;
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f For more information about applying these attributes, refer to the Altera Constraints,
Attributes, and Options chapter of the Synopsys FPGA Synthesis Reference Manual.
-verilog
-verilog
-verilog
-verilog
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Inferring Multipliers
Figure 182 shows the HDL Analyst view of an unsigned 8 8 multiplier with two
pipeline stages after synthesis in the Synplify software. This multiplier is converted
into an ALTMULT_ADD or ALTMULT_ACCUM megafunction. For devices with DSP
blocks, the software might implement the function in a DSP block instead of regular
logic, depending on device utilization. For some devices, the software maps directly
to DSP block device primitives instead of instantiating a megafunction in the .vqm
file.
Figure 182. HDL Analyst View of LPM_MULT Megafunction (Unsigned 8 8 Multiplier with
Pipeline=2)
Resource Balancing
While mapping multipliers to DSP blocks, the Synplify software performs resource
balancing for optimum performance.
Altera devices have a fixed number of DSP blocks, which includes a fixed number of
embedded multipliers. If the design uses more multipliers than are available, the
Synplify software automatically maps the extra multipliers to logic elements (LEs), or
adaptive logic modules (ALMs).
If a design uses more multipliers than are available in the DSP blocks, the Synplify
software maps the multipliers in the critical paths to DSP blocks. Next, any wide
multipliers, which might or might not be in the critical paths, are mapped to DSP
blocks. Smaller multipliers and multipliers that are not in the critical paths might then
be implemented in the logic (LEs or ALMs). This ensures that the design fits
successfully in the device.
Controlling the DSP Block Inference
You can implement multipliers in DSP blocks or in logic in Altera devices that contain
DSP blocks. You can control this implementation through attribute settings in the
Synplify software.
Signal Level Attribute
You can control the implementation of individual multipliers by using the
syn_multstyle attribute as shown in the following Verilog HDL code:
<signal_name> /* synthesis syn_multstyle = "logic" */;
where <signal_name> is the name of the signal.
1
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Table 183 describes the signal level attribute values that control the implementation
of the multipliers in the DSP blocks or LEs in the Synplify software.
Table 183. DSP Block Attribute Settings in the Synplify Software
Attribute Name
syn_multstyle
Value
Description
lpm_mult
logic
LPM function not inferred and multipliers implemented LEs by the Synplify
software
block_mult
Example 189 and Example 1810 show simple Verilog HDL and VHDL code using
the syn_multstyle attribute.
Example 189. Signal Attributes for Controlling DSP Block Inference in Verilog HDL Code
module mult(a,b,c,r,en);
input [7:0] a,b;
output [15:0] r;
input [15:0] c;
input en;
wire [15:0] temp /* synthesis syn_multstyle="logic" */;
assign temp = a*b;
assign r = en ? temp : c;
endmodule
Example 1810. Signal Attributes for Controlling DSP Block Inference in VHDL Code
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity onereg is port (
r : out std_logic_vector(15 downto 0);
en : in std_logic;
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
c : in std_logic_vector(15 downto 0)
);
end onereg;
architecture beh of onereg is
signal temp : std_logic_vector(15 downto 0);
attribute syn_multstyle : string;
attribute syn_multstyle of temp : signal is "logic";
begin
temp <= a * b;
r <= temp when en='1' else c;
end beh;
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Inferring RAM
When a RAM block is inferred from an HDL design, the Synplify software uses an
Altera megafunction to target the device memory architecture. For some devices, the
Synplify software maps directly to memory block device primitives instead of
instantiating a megafunction in the .vqm file.
Follow these guidelines for the Synplify software to successfully infer RAM in a
design:
Resets on the memory are not supported. Refer to the device family
documentation for information about whether read and write ports must be
synchronous.
Some Verilog HDL statements with blocking assignments might not be mapped to
RAM blocks, so avoid blocking statements when modeling RAMs in Verilog HDL.
For some device families, the syn_ramstyle attribute specifies the implementation to
use for an inferred RAM. You can apply the syn_ramstyle attribute globally, to a
module, or to a RAM instance, to specify registers or block_ram values. To turn off
RAM inference, set the attribute value to registers.
When inferring RAM for some Altera device families, the Synplify software generates
additional bypass logic. This logic is generated to resolve a half-cycle read/write
behavior difference between the RTL and post-synthesis simulations. The RTL
simulation shows the memory being updated on the positive edge of the clock; the
post-synthesis simulation shows the memory being updated on the negative edge of
the clock. To eliminate bypass logic, the output of the RAM must be registered. By
adding this register, the output of the RAM is seen after a full clock cycle, by which
time the update has occurred, thus eliminating the need for bypass logic.
For devices with TriMatrix memory blocks, disable the creation of glue logic by
setting the syn_ramstyle value to no_rw_check. Set syn_ramstyle to no_rw_check to
disable the creation of glue logic in dual-port mode.
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Example 1811 shows sample VHDL code for inferring dual-port RAM.
Example 1811. VHDL Code for Inferred Dual-Port RAM
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
ENTITY dualport_ram IS
PORT ( data_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data_in: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wr_addr, rd_addr: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
we: IN STD_LOGIC;
clk: IN STD_LOGIC);
END dualport_ram;
ARCHITECTURE ram_infer OF dualport_ram IS
TYPE Mem_Type IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL mem: Mem_Type;
SIGNAL addr_reg: STD_LOGIC_VECTOR (6 DOWNTO 0);
BEGIN
data_out <= mem (CONV_INTEGER(rd_addr));
PROCESS (clk, we, data_in) BEGIN
IF (clk='1' AND clk'EVENT) THEN
IF (we='1') THEN
mem(CONV_INTEGER(wr_addr)) <= data_in;
END IF;
END IF;
END PROCESS;
END ram_infer;
1827
Example 1812 shows an example of the VHDL code preventing bypass logic for
inferring dual-port RAM. The extra latency behavior stems from the inferring
methodology and is not required when instantiating a megafunction.
Example 1812. VHDL Code for Inferred Dual-Port RAM Preventing Bypass Logic
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
ENTITY dualport_ram IS
PORT ( data_out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data_in : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wr_addr, rd_addr : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
we : IN STD_LOGIC;
clk : IN STD_LOGIC);
END dualport_ram;
ARCHITECTURE ram_infer OF dualport_ram IS
TYPE Mem_Type IS ARRAY (127 DOWNTO 0) OF STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL mem : Mem_Type;
SIGNAL addr_reg : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL tmp_out : STD_LOGIC_VECTOR(7 DOWNTO 0); --output register
BEGIN
tmp_out <= mem (CONV_INTEGER(rd_addr));
PROCESS (clk, we, data_in) BEGIN
IF (clk='1' AND clk'EVENT) THEN
IF (we='1') THEN
mem(CONV_INTEGER(wr_addr)) <= data_in;
END IF;
data_out <= tmp_out; --registers output preventing
-- bypass logic generation.
END IF;
END PROCESS;
END ram_infer;
RAM Initialization
Use the Verilog HDL $readmemb or $readmemh system tasks in your HDL code to
initialize RAM memories. The Synplify compiler forward-annotates the initialization
values in the .srs (technology-independent RTL netlist) file and the mapper generates
a corresponding hexadecimal memory initialization (.hex) file. One .hex file is created
for each of the altsyncram megafunctions that are inferred in the design. The .hex file
is associated with the altsyncram instance in the .vqm file using the init_file
attribute.
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Example 1813 and Example 1814 illustrate how RAM memories can be initialized
through HDL code, and how the corresponding .hex file is generated using Verilog
HDL.
Example 1813. Using $readmemb System Task to Initialize an Inferred RAM in Verilog HDL Code
initial
begin
$readmemb("mem.ini", mem);
end
always @(posedge clk)
begin
raddr_reg <= raddr;
if(we)
mem[waddr] <= data;
end
Inferring ROM
When a ROM block is inferred from an HDL design, the Synplify software uses an
Altera megafunction to target the device memory architecture. For some devices, the
Synplify software maps directly to memory block device atoms instead of
instantiating a megafunction in the .vqm file. Follow these guidelines for the Synplify
software to successfully infer ROM in a design:
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7. Compile your design in the Quartus II software and preserve the compilation
results with the post-fit netlist in incremental compilation.
8. When you make design or synthesis optimization changes to part of your design,
resynthesize only the partition you modified to generate a new netlist and .tcl file.
Do not regenerate netlist files for the unmodified partitions.
9. Import the new netlist and .tcl file into the Quartus II software and recompile the
design in the Quartus II software with incremental compilation.
f For more information about creating partitions and using the incremental compilation
in the Quartus II software, refer to the Quartus II Incremental Compilation for
Hierarchical and Team-Based Design chapter in volume 1 of the Quartus II Handbook.
1831
After you have created multiple .vqm files using one of these two methods, you must
create the appropriate Quartus II projects to place-and-route the design.
D
Partition B
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F
Partition F
1832
In this case, modules A, B, and F are Compile Points. The top-level Compile Point
consists of the top-level block in the design (that is, block A in this example),
including the logic that is not defined under another Compile Point. In this example,
the design for top-level Compile Point A also includes the logic in one of its
subblocks, C. Because block F is defined as its own Compile Point, it is not treated as
part of the top-level Compile Point A. Another separate Compile Point B contains the
logic in blocks B, D, and E. One netlist is created for the top-level module A and
submodule C, another netlist is created for B and its submodules D and E, while a
third netlist is created for F.
Apply Compile Points to the module, or to the architecture in the Synplify Pro SCOPE
spreadsheet, or to the .sdc file. You cannot set a Compile Point in the Verilog HDL or
VHDL source code. You can set the constraints manually using Tcl or by editing the
.sdc file, or you can use one of two methods in the GUI, as described in the following
subsections.
Defining Compile Points With .tcl or .sdc Files
To set Compile Points with a .tcl or .sdc file, use the define_compile_point command,
as shown in Example 1815.
Example 1815. The define_compile_point Command
define_compile_point [-disable] {<objname>} -type {locked, partition}
In Example 1815, <objname> represents any module in the design. The Compile Point
type {locked, partition} indicates that the Compile Point represents a partition for
the Quartus II incremental compilation flow.
Each Compile Point has a set of constraint files that begin with the
define_current_design command to set up the SCOPE environment, as follows:
define_current_design {<my_module>}
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3. Select the module you want to designate as a Compile Point and click OK. The
software automatically sets the Compile Points in the top-level constraint file and
creates a lower-level constraint file for each Compile Point.
To use Compile Points effectively, you must provide timing constraints (timing
budgeting) for each Compile Point; the more accurate the constraints, the better
your results are. Constraints are not automatically budgeted, so manual time
budgeting is essential. Altera recommends that you register all inputs and outputs
of each partition. This avoids any logic delay penalty on signals that
cross-partition boundaries.
When using the Synplify attribute syn_useioff to pack registers in the I/O
Elements (IOEs) of Altera devices, these registers must be in the top-level module.
Otherwise, you must direct the Quartus II software to perform I/O register
packing instead of the syn_useioff attribute. You can use the Fast Input Register
or Fast Output Register options, or set I/O timing constraints and turn on
Optimize I/O cell register placement for timing on the Fitter Settings page of the
Settings dialog box in the Quartus II software.
There is no incremental synthesis support for top-level logic; any logic in the
top-level is resynthesized during every compilation in the Synplify software.
f For more information about using Compile Points and setting Synplify attributes and
constraints for both top-level and lower-level Compile Points, refer to the Synopsys
FPGA Synthesis User Guide and the Synopsys FPGA Synthesis Reference Manual in the
Synplify software.
Creating a Quartus II Project for Compile Points and Multiple .vqm Files
During compilation, the Synplify Pro and Premier software creates a <top-level
project>.tcl file that provides the Quartus II software with the appropriate constraints
and design partition assignments, creating a partition for each .vqm file along with
the information to set up a Quartus II project. For details about using this Tcl script to
set up your Quartus II project and pass your constraints, refer to Running the
Quartus II Software Manually With the Synplify-Generated Tcl Script on page 1815.
Depending on your design methodology, you can create one Quartus II project for all
netlists or a separate Quartus II project for each netlist. In the standard incremental
compilation design flow, you create design partition assignments and optional
LogicLock floorplan location assignments for each partition in the design within a
single Quartus II project. This methodology allows for the best quality of results and
performance preservation during incremental changes to your design.
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You might require a bottom-up design flow if each partition must be optimized
separately, such as for third-party IP delivery. If you use this flow, Altera recommends
you create a design floorplan to avoid placement conflicts between each partition. To
follow this design flow in the Quartus II software, create separate Quartus II projects,
export each design partition and incorporate it into a top-level design using the
incremental compilation features to maintain placement results.
The following sections describe how to create the Quartus II projects for these two
design flows.
Creating a Single Quartus II Project for a Standard Incremental Compilation Flow
Use the <top-level project>.tcl file that contains the Synplify assignments for all
partitions within the project. This method allows you to import all the partitions into
one Quartus II project and optimize all modules within the project at once, while
taking advantage of the performance preservation and compilation-time reduction
that incremental compilation offers. Figure 184 shows a visual representation of the
design flow for the example design in Figure 183 on page 1831.
Figure 184. Design Flow Using Multiple .vqm Files with One Quartus II Project
Quartus II Project
a.vqm
Use the top-level Tcl file a.tcl
to import Synplify Pro assignments.
b.vqm
f.vqm
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a.vqm
Quartus II Project
Quartus II Project
b.vqm
f.vqm
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1837
Example 1816 shows an example of the A.v top-level file. Follow the same procedure
for lower-level files that also contain a black box for any module beneath the current
level hierarchy.
Example 1816. Verilog HDL Black Box for Top-Level File A.v
module A (data_in, clk, e, ld, data_out);
input data_in, clk, e, ld;
output [15:0] data_out;
wire [15:0] cnt_out;
B U1 (.data_in (data_in),.clk(clk), .ld (ld),.data_out(cnt_out));
F U2 (.d(cnt_out), .clk(clk), .e(e), .q(data_out));
// Any other code in A.v goes here.
endmodule
// Empty Module Declarations of Sub-Blocks B and F follow here.
// These module declarations (including ports) are required for black
// boxes.
module B (data_in, clk, ld, data_out) /* synthesis syn_black_box */ ;
input data_in, clk, ld;
output [15:0] data_out;
endmodule
module F (d, clk, e, q) /* synthesis syn_black_box */ ;
input [15:0] d;
input clk, e;
output [15:0] q;
endmodule
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Example 1817 shows an example of the A.vhd top-level file. Follow this same
procedure for any lower-level files that contain a black box for any block beneath the
current level of hierarchy.
Example 1817. VHDL Black Box for Top-Level File A.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY synplify;
USE synplify.attributes.all;
ENTITY A IS
PORT ( data_in : IN INTEGER RANGE 0 TO 15;
clk, e, ld : IN STD_LOGIC;
data_out : OUT INTEGER RANGE 0 TO 15 );
END A;
ARCHITECTURE a_arch OF A IS
COMPONENT B PORT(
data_in : IN INTEGER RANGE 0 TO 15;
clk, ld : IN STD_LOGIC;
d_out : OUT INTEGER RANGE 0 TO 15 );
END COMPONENT;
COMPONENT F PORT(
d : IN INTEGER RANGE 0 TO 15;
clk, e: IN STD_LOGIC;
q : OUT INTEGER RANGE 0 TO 15 );
END COMPONENT;
attribute syn_black_box of B: component is true;
attribute syn_black_box of F: component is true;
-- Other component declarations in A.vhd go here
signal cnt_out : INTEGER RANGE 0 TO 15;
BEGIN
U1 : B
PORT MAP (
data_in => data_in,
clk => clk,
ld => ld,
d_out => cnt_out );
U2 : F
PORT MAP (
d => cnt_out,
clk => clk,
e => e,
q => data_out );
-- Any other code in A.vhd goes here
END a_arch;
After you complete the steps described in this section, you have a netlist file for each
partition of the design. These files are ready for use with the incremental compilation
flow in the Quartus II software.
1839
a.vqm
Use a.tcl to import top-level
Synplify Pro assignments.
Enter any lower-level
assignments manually.
b.vqm
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f.vqm
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a.vqm
Quartus II Project
Quartus II Project
b.vqm
Use the lower-level
Tcl file b.tcl to Import
Synplify Assignments
f.vqm
Use the lower-level
Tcl file f.tcl to Import
Synplify Assignments
If you use the NativeLink integration feature described in Using the Quartus II
Software to Run the Synplify Software on page 1815, the Synplify software does not
use any information about design partition assignments that you have set in the
Quartus II software.
If you create netlist files with multiple Synplify projects, or if you do not use the
Synplify Pro or Premier-generated .tcl files to update constraints in your Quartus II
project, you must ensure that your Synplify .vqm netlists align with your Quartus II
partition settings.
1841
After you have set up your Quartus II project with .vqm netlist files as separate
design partitions, set the appropriate Quartus II options to preserve your compilation
results. On the Assignments menu, click Design Partitions Window. Change the
Netlist Type to Post-Fit to preserve the previous compilations post-fit placement
results. If you do not make these settings, the Quartus II software does not reuse the
placement or routing results from the previous compilation.
You can take advantage of incremental compilation with your Synplify design to
reduce compilation time in the Quartus II software and preserve the results for
unchanged design blocks.
f For more information about using Quartus II incremental compilation, refer to the
Quartus II Incremental Compilation for Hierarchical and Team-Based Design chapter in
volume 1 of the Quartus II Handbook.
Conclusion
Taking advantage of the Synopsys Synplify and Altera Quartus II design flows allow
you to control how your design files are prepared for the Quartus II place-and-route
process, as well as improve performance and optimize a design for use with Altera
devices.
Version
June 2012
12.0.0
November 2011
10.1.1
Template update.
December 2010
10.1.0
Changes
Edited the Creating a Quartus II Project for Compile Points and Multiple .vqm
Files on page 1433 section for changes with the incremental compilation flow.
Edited the Creating a Quartus II Project for Multiple .vqm Files on page 1439
section for changes with the incremental compilation flow.
Editorial changes.
July 2010
10.0.0
November 2009
9.1.0
Added new section Exporting Designs to the Quartus II Software Using NativeLink
Integration on page 1414.
March 2009
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Version
November 2008
May 2008
8.1.0
8.0.0
Changes
Changed the chapter title from Synplicity Synplify & Synplify Pro Support to
Synopsys Synplify Support
Revised Table 91
Added new section Changing Synplifys Default Behavior for Instantiated Altera
Megafunctions
Added new section Including Files for Quartus II Placement and Routing Only
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
This chapter documents support for the Mentor Graphics Precision RTL Synthesis
and Precision RTL Plus Synthesis software in the Quartus II software design flow, as
well as key design methodologies and techniques for improving your results for
Altera devices.
The topics discussed in this chapter include:
This chapter assumes that you have set up, licensed, and installed the Precision
Synthesis software and the Quartus II software. You must set up, license, and install
the Precision RTL Plus Synthesis software if you want to use the incremental synthesis
feature for incremental compilation and block-based design.
f To obtain and license the Precision Synthesis software, refer to the Mentor Graphics
website at www.mentor.com. To install and run the Precision Synthesis software and
to set up your work environment, refer to the Precision Synthesis Installation Guide in
the Precision Manuals Bookcase. To access the Manuals Bookcase in the Precision
Synthesis software, click Help and select Open Manuals Bookcase.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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192
The Precision Synthesis software also supports the FLEX 8000 and MAX 9000 legacy
devices that are supported only in the Altera MAX+PLUS II software, as well as
ACEX 1K, APEX II, APEX 20K, APEX 20KC, APEX 20KE, FLEX 10K, and FLEX
6000 legacy devices that are supported by the Quartus II software version 9.0 and
earlier.
Design Flow
The following steps describe a basic Quartus II design flow using the Precision
Synthesis software:
1. Create Verilog HDL or VHDL design files.
2. Create a project in the Precision Synthesis software that contains the HDL files for
your design, select your target device, and set global constraints. Refer to
Creating and Compiling a Project in the Precision Synthesis Software on
page 195 for details.
3. Compile the project in the Precision Synthesis software.
4. Add specific timing constraints, optimization attributes, and compiler directives to
optimize the design during synthesis.
1
5. Synthesize the project in the Precision Synthesis software. With the design analysis
and cross-probing capabilities of the Precision Synthesis software, you can identify
and improve circuit area and performance issues using prelayout timing
estimates.
6. Create a Quartus II project and import the following files generated by the
Precision Synthesis software into the Quartus II project:
193
If your design uses the Classic Timing Analyzer for timing analysis in the
Quartus II software versions 10.0 and earlier, the Precision Synthesis
software generates timing constraints in the Tcl Constraints File (.tcl). If you
are using the Quartus II software versions 10.1 and later, you must use the
TimeQuest Timing Analyzer for timing analysis.
Tcl Script Files (.tcl) to set up your Quartus II project and pass constraints
You can run the Quartus II software from within the Precision Synthesis software,
or run the Precision Synthesis software using the Quartus II software. Refer to
Running the Quartus II Software from within the Precision Synthesis Software
on page 1910 and Using the Quartus II Software to Run the Precision Synthesis
Software on page 1912 for more information.
7. After obtaining place-and-route results that meet your requirements, configure or
program the Altera device.
Figure 191 shows the Quartus II design flow using the Precision Synthesis software
as described in these steps, which are further described in detail in this chapter.
Figure 191. Design Flow Using the Precision Synthesis Software and Quartus II Software
Design Specifications
System
Verilog
VHDL
Constraints and
Settings
Verilog HDL
Precision Synthesis
TechnologySpecific Netlist
(.edf)
Forward-Annotated Projec
Configuration
(.tcl/.acf)
Quartus II Timing Constraints
in SDC format (.sdc)
Constraints and
Settings
Quartus II Software
No
Requirements
Satisfied?
Post-Synthesis
Simulation Files
(.vho/.vo)
Post Place-and-Route
Simulation File
(.vho/.vo)
Yes
Configuration/Programming Files
(.sof/.pof)
Program/Configure Device
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If your area or timing requirements are not met, you can change the constraints and
resynthesize the design in the Precision Synthesis software, or you can change the
constraints to optimize the design during place-and-route in the Quartus II software.
Repeat the process until the area and timing requirements are met.
You can use other options and techniques in the Quartus II software to meet area and
timing requirements. For example, the WYSIWYG Primitive Resynthesis option can
perform optimizations on your EDIF netlist in the Quartus II software.
f For more information about netlist optimizations, refer to the Netlist Optimizations and
Physical Synthesis chapter in volume 2 of the Quartus II Handbook. For more
recommendations about how to optimize your design, refer to the Area and Timing
Optimization chapter in volume 2 of the Quartus II Handbook.
While simulation and analysis can be performed at various points in the design
process, final timing analysis should be performed after placement and routing is
complete.
During synthesis, the Precision Synthesis software produces several intermediate and
output files, which are described in Table 191.
Table 191. Precision Synthesis Software Intermediate and Output Files
File Extension
.psp
.xdb
.rep
File Description
Mentor Graphics Design Database File.
(1)
.vqm/.edf
(2)
By default, the Precision Synthesis software creates .vqm files for Arria series, Cyclone series, and Stratix
series devices, and creates .edf files for ACEX, APEX, FLEX, and MAX series devices. The Precision
Synthesis software can create .edf files for all Altera devices supported by the Quartus II software, but
defaults to creating .vqm files when the device is supported.
.tcl
Forward-annotated Tcl assignments and constraints file. The <project name>.tcl file is generated for all
devices. The .tcl file acts as the Quartus II Project Configuration file and is used to make basic project and
placement assignments, and to create and compile a Quartus II project.
.acf
Assignment and Configurations file for backward compatibility with the MAX+PLUS II software. For
devices supported by the MAX+PLUS II software, the MAX+PLUS II assignments are imported from the
MAX+PLUS II .acf file.
Quartus II timing constraints file in Synopsys Design Constraints format.
.sdc
This file is generated automatically if the device uses the TimeQuest Timing Analyzer by default in the
Quartus II software, and has the naming convention <project name>_pnr_constraints.sdc. For more
information about generating a TimeQuest constraint file, refer to Exporting Designs to the Quartus II
Software Using NativeLink Integration on page 1910.
195
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default, the Precision Synthesis software saves all timing constraints and attributes in
two files: precision_rtl.sdc and precision_tech.sdc. The precision_rtl.sdc file contains
constraints set on the RTL-level database (post-compilation) and the
precision_tech.sdc file contains constraints set on the gate-level database
(post- synthesis) located in the current implementation directory.
You can also enter constraints at the command line. After adding constraints at the
command line, update the .sdc file with the update constraint file command. You can
add constraints that change infrequently directly to the HDL source files with HDL
attributes or pragmas.
1
The Precision .sdc file contains all the constraints for the Precision Synthesis project.
For the Quartus II software, placement constraints are written in a .tcl file and timing
constraints for the TimeQuest Timing Analyzer are written in the Quartus II .sdc file.
f For details about the syntax of Synopsys Design Constraint commands, refer to the
Precision RTL Synthesis Users Manual and the Precision Synthesis Reference Manual. For
more details and examples of attributes, refer to the Attributes chapter in the Precision
Synthesis Reference Manual. To access these manuals in the Precision Synthesis
software, click Help and select Open Manuals Bookcase.
Because the .sdc file format requires that timing constraints be set relative to defined
clocks, you must specify your clock constraints before applying any other timing
constraints.
You also can use multicycle path and false path assignments to relax requirements or
exclude nodes from timing requirements, which can improve area utilization and
allow the software optimizations to focus on the most critical parts of the design.
f For details about the syntax of Synopsys Design Constraint commands, refer to the
Precision RTL Synthesis Users Manual and the Precision Synthesis Reference Manual. To
access these manuals in the Precision Synthesis software, click Help and select Open
Manuals Bookcase.
197
Pin number
I/O standard
Drive strength
set_attribute -name DRIVE -value "<drive strength in mA>" -port <port name>
Slew rate
You can also specify these options in the GUI. To specify a pin number or other I/O
setting in the Precision Synthesis GUI, follow these steps:
1. After compiling the design, expand Ports in the Design Hierarchy Browser.
2. Under Ports, expand Inputs or Outputs.
1
You also can assign I/O settings by right-clicking the pin in the Schematic
Viewer.
3. Right-click the desired pin name and select Set Input Constraints under Inputs or
Set Output Constraints under Outputs.
4. Type the desired pin number on the Altera device in the Pin Number box in the
Port Constraints dialog box.
5. Select the I/O standard from the IO_STANDARD list.
6. For output pins, you can also select a drive strength setting and slew rate setting
using the DRIVE and SLOW SLEW lists.
You also can use synthesis attributes or pragmas in your HDL code to make these
assignments. Example 191 and Example 192 show code samples that make a pin
assignment in your HDL code.
Example 191. Verilog HDL Pin Assignment
//pragma attribute clk pin_number P10;
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You can use the same syntax to assign the I/O standard using the IOSTANDARD
attribute, drive strength using the attribute DRIVE, and slew rate using the
SLEW attribute.
1
For more details about attributes and how to set these attributes in your HDL code,
refer to the Precision Synthesis Reference Manual. To access this manual, in the Precision
Synthesis software, click Help and select Open Manuals Bookcase.
You also can make the assignment by right-clicking on the pin in the Schematic
Viewer.
For the Stratix series, Cyclone series, and the MAX II device families, the Precision
Synthesis software can move an internal register to an I/O register without any
restrictions on design hierarchy.
For more mature devices, the Precision Synthesis software can move an internal
register to an I/O register only when the register exists in the top-level of the
hierarchy. If the register is buried in the hierarchy, you must flatten the hierarchy so
that the buried registers are moved to the top-level of the design.
199
You also can make this assignment by right-clicking the pin in the Schematic Viewer
or by attaching the nopad attribute to the port in the HDL source code.
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There are several schematic viewers available in the Precision Synthesis software: RTL
schematic, Technology-mapped schematic, and Critical Path schematic. These
analysis tools allow you to quickly and easily isolate the source of timing or area
issues, and to make additional constraint or code changes to optimize the design.
1911
After you specify an Altera device as the target, set the options for the Quartus II
software. On the Tools menu, click Set Options. On the Integrated Place and Route
page, under Quartus II Modular, specify the path to the Quartus II executables in the
Path to Quartus II installation tree box.
To automate the place-and-route process, click Run Quartus II in the Quartus II
Modular window of the Precision Synthesis toolbar. The Quartus II software uses the
current implementation directory as the Quartus II project directory and runs a full
compilation in the background (that is, the user interface does not appear).
Two primary Precision Synthesis software commands control the place-and-route
process. Use the setup_place_and_route command to set the place-and-route
options. Start the process with the place_and_route command.
Precision Synthesis software uses individual Quartus II executables, such as analysis
and synthesis (quartus_map), Fitter (quartus_fit), and the TimeQuest Timing
Analyzer (quartus_sta) for improved runtime and memory utilization during place
and route. This flow is referred to as the Quartus II Modular flow option in the
Precision Synthesis software. By default, the Precision Synthesis software generates a
Quartus II Project Configuration File (.tcl file) for current device families. Timing
constraints that you set during synthesis are exported to the Quartus II
place-and-route constraints file <project name>_pnr_constraints.sdc.
After you compile the design in the Quartus II software from within the Precision
Synthesis software, you can invoke the Quartus II GUI manually and then open the
project using the generated Quartus II project file. You can view reports, run analysis
tools, specify options, and run the various processing flows available in the Quartus II
software.
f For more information about running the Quartus II software from within the
Precision Synthesis software, refer to the Altera Quartus II Integration chapter in the
Precision Synthesis Reference Manual. To access this manual in the Precision Synthesis
software, click Help and select Open Manuals Bookcase.
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create_clock
set_input_delay
set_output_delay
set_max_delay
set_min_delay
set_false_path
set_multicycle_path
create_clock
You can specify a clock in the Precision Synthesis software, as shown in Example 193.
Example 193. Specifying a Clock using create_clock
create_clock -name <clock_name> -period <period in ns> -waveform {<edge_list>} -domain \
<ClockDomain> <pin>
1913
set_input_delay
This port-specific input delay constraint is specified in the Precision Synthesis
software, as shown in Example 194.
Example 194. Specifying set_input_delay
set_input_delay {<delay_value> <port_pin_list>} -clock <clock_name> -rise -fall -add_delay
Although the Precision Synthesis software allows you to set input delays on pins
inside the design, these constraints are not sent to the Quartus II software, and a
message is displayed.
set_output_delay
This port-specific output delay constraint is specified in the Precision Synthesis
software, as shown in Example 195.
Example 195. Using the set_output_delay Constraint
set_output_delay {<delay_value> <port_pin_list>} -clock <clock_name> -rise -fall -add_delay
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Although the Precision Synthesis software allows you to set output delays on pins
inside the design, these constraints are not sent to the Quartus II software.
The set_max_delay and set_min_delay commands specify that the maximum and
minimum respectively, required delay for any start point in <from_node_list> to any
endpoint in <to_node_list> must be less than or greater than <delay_value>. Typically,
you use these commands to override the default setup constraint for any path with a
specific maximum or minimum time value for the path.
The node lists can contain a collection of clocks, registers, ports, pins, or cells. The
-from and -to parameters specify the source (start point) and the destination
(endpoint) of the timing path, respectively. The source list (<from_node_list>) cannot
include output ports, and the destination list (<to_node_list>) cannot include input
ports. If you include more than one node on a list, you must enclose the nodes in
quotes or in braces ({ }).
If you specify a clock in the source list, you must specify a clock in the destination list.
Applying set_max_delay or set_min_delay setting between clocks applies the
exception from all registers or ports driven by the source clock to all registers or ports
driven by the destination clock. Applying exceptions between clocks is more efficient
than applying them for specific node-to-node, or node-to-clock paths. If you want to
specify pin names in the list, the source must be a clock pin and the destination must
be any non-clock input pin to a register. Assignments from clock pins, or to and from
cells, apply to all registers in the cell or for those driven by the clock pin.
set_false_path
The false path constraint is specified in the Precision Synthesis software, as shown in
Example 198.
Example 198. Using the set_false_path Constraint
set_false_path -to <to_node_list> -from <from_node_list> -reset_path
The node lists can be a list of clocks, ports, instances, and pins. Multiple elements in
the list can be represented using wildcards such as * and ?.
In a place-and-route Tcl constraints file, this false path setting in the Precision
Synthesis software is mapped to a set_false_path setting. The Quartus II software
supports setup, hold, rise, or fall options for this assignment.
1915
The node lists for this assignment represents top-level ports and/or nets connected to
instances (end points of timing assignments).
Any false path setting in the Precision Synthesis software can be mapped to a setting
in the Quartus II software with a through path specification.
set_multicycle_path
This multicycle path constraint is specified in the Precision Synthesis software, as
shown in Example 199.
Example 199. Using the set_multicycle_path Constraint
set_multicycle_path <multiplier_value> [-start] [-end] -to <to_node_list> -from <from_node_list> \
-reset_path
The node list can contain clocks, ports, instances, and pins. Multiple elements in the
list can be represented using wildcards such as * and ?. Paths without multicycle path
definitions are identical to paths with multipliers of 1. To add one additional cycle to
the datapath, use a multiplier value of 2. The option start indicates that source clock
cycles should be considered for the multiplier. The option end indicates that
destination clock cycles should be considered for the multiplier. The default is to
reference the end clock.
In the place-and-route Tcl constraints file, the multicycle path setting in the Precision
Synthesis software is mapped to a set_multicycle_path setting. The Quartus II
software supports the rise or fall options on this assignment.
The node lists represent top-level ports and/or nets connected to instances (end
points of timing assignments). The node lists can contain wildcards (such as *); the
Quartus II software automatically expands all wildcards.
Any multicycle path setting in Precision Synthesis software can be mapped to a
setting in the Quartus II software with a -through specification.
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f For more information about specific Altera megafunctions and IP functions, refer to
the IP and Megafunctions page of the Altera website.
The Precision Synthesis software automatically recognizes certain types of HDL code
and infers the appropriate function. The Precision Synthesis software provides
options to control inference of certain types of megafunctions, as described in
Inferring Altera Megafunctions from HDL Code on page 1919.
f For a detailed discussion about instantiating functions versus inferring functions to
target Altera architecture-specific features, refer to the Recommended HDL Coding
Styles chapter in volume 1 of the Quartus II Handbook. This chapter also provides
details on using the MegaWizard Plug-In Manager in the Quartus II software and
explains the files generated by the wizard, as well as coding style recommendations
and HDL examples for inferring functions in Altera devices.
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The generated grey box netlist file, <output file>_syn.v, is always in Verilog HDL
format, even if you select VHDL as the output file format.
There is currently no grey box support for SOPC Builder systems in the MegaWizard
Plug-In Manager. For information about creating a grey box netlist file from the
command line, search Altera's Knowledge Database. Alternatively, you can use a
black box approach as described in Instantiating Black Box IP Functions With
Generated Verilog HDL Files.
Altera Corporation
1918
The syn_black_box and black_box directives are supported only on module or entity
definitions.
Example 1910 shows a sample top-level file that instantiates my_verilogIP.v, which
is a simplified customized variation generated by the MegaWizard Plug-In Manager
and IP Toolbench.
Example 1910. Top-Level Verilog HDL Code with Black Box Instantiation of IP
module top (clk, count);
input clk;
output[7:0] count;
my_verilogIP verilogIP_inst (.clock (clk), .q (count));
endmodule
// Module declaration
// The following attribute is added to create a
// black box for this module.
module my_verilogIP (clock, q) /* synthesis syn_black_box */;
input clock;
output[7:0] q;
endmodule
The syn_black_box and black_box directives are supported only on module or entity
definitions.
1919
Example 1911 shows a sample top-level file that instantiates my_vhdlIP.vhd, which
is a simplified customized variation generated by the MegaWizard Plug-In Manager
and IP Toolbench.
Example 1911. Top-Level VHDL Code with Black Box Instantiation of IP
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY top IS
PORT (
clk: IN STD_LOGIC ;
count: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END top;
ARCHITECTURE rtl OF top IS
COMPONENT my_vhdlIP
PORT (
clock: IN STD_LOGIC ;
q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end COMPONENT;
attribute syn_black_box : boolean;
attribute syn_black_box of my_vhdlIP: component is true;
BEGIN
vhdlIP_inst : my_vhdlIP PORT MAP (
clock => clk,
q => count
);
END rtl;
Multipliers
The Precision Synthesis software detects multipliers in HDL code and maps them
directly to device atoms to implement the multiplier in the appropriate type of logic.
The Precision Synthesis software also allows you to control the device resources that
are used to implement individual multipliers, as described in the following section.
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1920
Description
ON
Use only DSP blocks to implement multipliers, regardless of the size of the multiplier.
OFF
Use only logic (LUTs) to implement multipliers, regardless of the size of the multiplier.
AUTO
Use logic (LUTs) or DSP blocks to implement multipliers, depending on the size of the
multipliers.
The dedicated_mult attribute can be applied to signals and wires; it does not work
when applied to a register. This attribute can be applied only to simple multiplier
code, such as a = b * c.
Some signals for which the dedicated_mult attribute is set can be removed during
synthesis by the Precision Synthesis software for design optimization. In such cases, if
you want to force the implementation, you should preserve the signal by setting the
preserve_signal attribute to TRUE, as shown in Example 1914 and Example 1915.
Example 1914. Setting the preserve_signal Attribute in Verilog HDL
//synthesis attribute <signal name> preserve_signal TRUE
1921
Example 1916 and Example 1917 are examples, in Verilog HDL and VHDL, of using
the dedicated_mult attribute to implement the given multiplier in regular logic in the
Quartus II software.
Example 1916. Verilog HDL Multiplier Implemented in Logic
module unsigned_mult (result, a, b);
output [15:0] result;
input [7:0] a;
input [7:0] b;
assign result = a * b;
//synthesis attribute result dedicated_mult OFF
endmodule
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1922
The Precision Synthesis software supports inference for these functions only if the
target device family has dedicated DSP blocks. Refer to Controlling DSP Block
Inference for more information.
f For more information about DSP blocks in Altera devices, refer to the appropriate
Altera device family handbook and device-specific documentation. For details about
which functions a given DSP block can implement, refer to the DSP Solutions Center
on the Altera website at www.altera.com.
f For more information about inferring multiply-accumulator and multiply-adder
megafunctions in HDL code, refer to the Recommended HDL Coding Styles chapter in
volume 1 of the Quartus II Handbook, and the Precision Synthesis Style Guide in the
Precision Synthesis Manuals Bookcase.
Description
TRUE
FALSE
To control inference, use the extract_mac attribute with the appropriate value from
Table 194 in your HDL code, as shown in Example 1918 and Example 1919.
Example 1918. Setting the extract_mac Attribute in Verilog HDL
//synthesis attribute <module name> extract_mac <value>
1923
[31:0] dataout;
[15:0] multa;
[31:0] adder_out;
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1925
The following steps show a general flow for partition-based incremental synthesis
with Quartus II incremental compilation.
1. Create Verilog HDL or VHDL design files.
2. Determine which hierarchical blocks you want to treat as separate partitions in
your design, and designate the partitions with the incr_partition attribute. For
the syntax to create partitions, refer to Creating Partitions with the incr_partition
Attribute on page 1925.
3. Create a project in the Precision RTL Plus Synthesis software and add the HDL
design files to the project.
4. Enable incremental synthesis in the Precision RTL Plus Synthesis software using
one of these methods:
On the Tools menu, click Set Options. On the Optimization page, turn on
Enable Incremental Synthesis.
5. Run the basic Precision Synthesis flow of compilation, synthesis, and place-androute on your design. In subsequent runs, the Precision RTL Plus Synthesis
software processes only the parts of the design that have changed, resulting in a
shorter iteration than the initial run. The performance of the unchanged partitions
is preserved.
The Precision RTL Plus Synthesis software sets the netlist types of the unchanged
partitions to Post-Fit and the changed partitions to Post-Synthesis. You can
change the netlist type during timing closure in the Quartus II software to obtain
the best QoR.
6. Import the EDIF or VQM netlist for each partition and the top-level .tcl file into the
Quartus II software, and set up the Quartus II project to use incremental
compilation.
7. Compile your Quartus II project.
8. If you want, you can change the Quartus II incremental compilation netlist type
for a partition with the Design Partitions Window. You can change the Netlist
Type to one of the following options:
To preserve the previous post-fit placement results, change the Netlist Type of
the partition to Post-Fit.
To preserve the previous routing results, set the Fitter Preservation Level of
the partition to Placement and Routing.
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Instance partition:
my_block my_block_inst(.clk(clk), .data_out(data_out));
// synthesis attribute my_block_inst incr_partition true
Instance partition:
component my_block is
port(
clk : in std_logic;
data_out : out std_logic_vector(31 downto 0)
);
end component;
attribute incr_partition : boolean;
attribute incr_partition of my_block_inst : label is true;
my_block_inst my_block
port map(clk, data_out);
1927
You must turn off the Add IO Pads option while synthesizing the
lower-level modules individually. Enable the Add IO Pads option only
while synthesizing the top-level module.
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Partition B
F
Partition F
In Figure 192, the top-level partition contains the top-level block in the design
(block A) and the logic that is not defined as part of another partition. In this example,
the partition for top-level block A also includes the logic in the sub-block C. Because
block F is contained in its own partition, it is not treated as part of the top-level
partition A. Another separate partition, B, contains the logic in blocks B, D, and E. In a
team-based design, different engineers may work on the logic in different partitions.
One netlist is created for the top-level module A and its submodule C, another netlist
is created for module B and its submodules D and E, while a third netlist is created for
module F. To create multiple EDIF netlist files for this design, follow these steps:
1. Generate an .edf file for module B. Use B.v/.vhd, D.v/.vhd, and E.v/.vhd as the
source files.
2. Generate an .edf file for module F. Use F.v/.vhd as the source file.
3. Generate a top-level .edf file for module A. Use A.v/.vhd and C.v/.vhd as the
source files. Ensure that you create black boxes for modules B and F, which were
optimized separately in the previous steps.
The goal is to individually synthesize and generate an .edf netlist file for each
lower-level module and then instantiate these modules as black boxes in the top-level
file. You can then synthesize the top-level file to generate the .edf netlist file for the
top-level design. Finally, both the lower-level and top-level .edf netlist files are
provided to your Quartus II project.
1
When you make design or synthesis optimization changes to part of your design,
resynthesize only the changed partition to generate the new .edf netlist file. Do not
resynthesize the implementations or projects for the unchanged partitions.
1929
A black box for the top-level file A.v is shown in the following example. Provide an
empty module declaration for any lower-level files, which also contain a black box for
any module beneath the current level of hierarchy.
Example 1924. Verilog HDL Black Box for Top-Level File A.v
module A (data_in, clk, e, ld, data_out);
input data_in, clk, e, ld;
output [15:0] data_out;
wire [15:0] cnt_out;
B U1 (.data_in (data_in),.clk(clk), .ld (ld),.data_out(cnt_out));
F U2 (.d(cnt_out), .clk(clk), .e(e), .q(data_out));
// Any other code in A.v goes here.
endmodule
// Empty Module Declarations of Sub-Blocks B and F follow here.
// These module declarations (including ports) are required for black
// boxes.
module B (data_in, clk, ld, data_out);
input data_in, clk, ld;
output [15:0] data_out;
endmodule
module F (d, clk, e, q);
input [15:0] d;
input clk, e;
output [15:0] q;
endmodule
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After you complete the steps outlined in this section, you have different EDIF netlist
files for each partition of the design. These files are ready for use with incremental
compilation in the Quartus II software.
1931
Depending on your design methodology, you can create one Quartus II project for all
EDIF netlists, or a separate Quartus II project for each EDIF netlist. In the standard
incremental compilation design flow, you create design partition assignments for each
partition in the design within a single Quartus II project. This methodology provides
the best QoR and performance preservation during incremental changes to your
design. You might require a bottom-up design flow if each partition must be
optimized separately, such as for third-party IP delivery.
To follow this design flow in the Quartus II software, create separate Quartus II
projects and export each design partition and incorporate it into a top-level design
using the incremental compilation features to maintain placement results.
The following sections describe how to create the Quartus II projects for these two
design flows.
a.edf
Use a.tcl to import
top-level Precsion
Synthesis software
assignments.
Enter any lower level
assignments manually.
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b.edf
f.edf
1932
a.edf
Quartus II Project
Quartus II Project
b.edf
Use b.tcl to import
Precision Synthesis
software assignments.
f.edf
Use f.tcl to import
Precision Synthesis
software assignments.
1933
Conclusion
The Mentor Graphics Precision Synthesis software and Quartus II design flow allow
you to control how to prepare your design files for the Quartus II place-and-route
process, which allows you to improve performance and optimizes your design for use
with Altera devices. Several of the methodologies outlined in this chapter can help
you optimize your design to achieve performance goals and decrease design time.
Version
June 2012
12.0.0
November 2011
10.1.1
December 2010
10.1.0
Changes
Template update.
Edited the Creating Quartus II Projects for Multiple EDIF Files on page 1530 section for
changes with the incremental compilation flow.
Editorial changes.
July 2010
10.0.0
November 2009
9.1.0
Updated list of supported devices for the Quartus II software version 9.0 release
Added information about the Precision RTL Plus incremental synthesis flow
Added section Creating Partitions with the incr_partition Attribute on page 1029
Renamed Creating a Project and Compiling the Design section to Creating and
Compiling a Project in the Precision RTL Synthesis Software
March 2009
November 2008
May 2008
June 2012
9.0.0
8.1.0
8.0.0
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f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
This chapter documents key design methodologies and techniques for Altera
devices using the LeonardoSpectrum and Quartus II design flow.
This chapter includes the following sections:
f Altera recommends using the advanced Mentor Graphics Precision RTL Synthesis
software for new designs in new device families. For more information about
Precision RTL Synthesis, refer to the Mentor Graphics Precision Synthesis Support
chapter in volume 1 of the Quartus II Handbook.
1
This chapter assumes that you have set up, licensed, and are familiar with the
LeonardoSpectrum software.
f To obtain and license the LeonardoSpectrum software, refer to the Mentor Graphics
website at www.mentor.com. For information about installing the LeonardoSpectrum
software and setting up your working environment, refer to the LeonardoSpectrum
Installation Guide and the LeonardoSpectrum Users Manual.
Contact Mentor Graphics for more information about support for newly-released
devices.
The LeonardoSpectrum software also supports the FLEX 8000 and MAX 9000 legacy
devices that are supported only in the Altera MAX+PLUS II software, as well as
ACEX 1K, APEX II, APEX 20K, APEX 20KC, APEX 20KE, FLEX 10K, and
FLEX 6000 legacy devices that are supported by the Quartus II software version 9.0
and earlier.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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9001:2008
Registered
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202
Design Flow
The following steps describe a basic Quartus II software design flow using the
LeonardoSpectrum software:
1. Create Verilog HDL or VHDL design files.
2. Import the Verilog HDL or VHDL design files into the LeonardoSpectrum
software for synthesis.
3. Select a target device and add timing constraints and compiler directives to help
optimize the design during synthesis.
4. Synthesize the project in the LeonardoSpectrum software.
5. Create a Quartus II project and import the technology-specific EDIF Input File
(.edf) netlist and the Tcl Script File (.tcl) generated by the LeonardoSpectrum
software into the Quartus II software for placement and routing and performance
evaluation.
6. After obtaining place-and-route results that meet your requirements, configure or
program the Altera device.
Figure 201 on page 203 shows the recommended design flow using the
LeonardoSpectrum and Quartus II software.
If your area and timing requirements are met, use the programming files generated by
the Quartus II software to program or configure the Altera device. If the area or
timing requirements are not met, change the constraints in the LeonardoSpectrum
software and rerun synthesis. Repeat the process until the area and timing
requirements are met. You can also use other Quartus II software options and
techniques to meet the area and timing requirements.
203
Figure 201. Recommended Design Flow Using LeonardoSpectrum and Quartus II Software
VHDL
(.vhd)
Verilog
HDL
(.v)
Functional/RTL
Simulation
Constraints
and Settings
LeonardoSpectrum Software
TechnologySpecific Netlist
(.edf)
Forward Annotated
Timing Constraints
(.tcl/.acf)
Gate-Level
Functional
Simulation
Constraints
and Settings
Post-Synthesis
Simulation Files
(.vho/.vo)
Quartus II Software
Gate-Level Timing
Simulation
No
Requirements
Satisfied?
Post Place-and-Route
Simulation File
(.vho/.vo)
Yes
Configuration/
Programming
Files (.sof/.pof)
Program/Configure Device
The LeonardoSpectrum software supports both VHDL and Verilog HDL source files.
With the appropriate license, the software also supports mixed synthesis, allowing a
combination of VHDL and Verilog HDL source files. During synthesis, the
LeonardoSpectrum software produces several intermediate and output files, which
are listed and described in Table 201.
Table 201. LeonardoSpectrum Intermediate and Output Files
File Extension(s)
File Description
.xdb
Technology-independent register transfer level (RTL) netlist file that can only be read by the
LeonardoSpectrum software.
.edf
.tcl
.acf
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A .tcl file for the Quartus II software is created for all devices. The .tcl file contains the appropriate
Tcl commands to create and set up a Quartus II project and pass placement constraints.
Assignment and Configurations file for backward compatibility with the MAX+PLUS II software.
For devices supported by the MAX+PLUS II software, the MAX+PLUS II assignments are imported
from the MAX+PLUS II .acf file.
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Altera recommends that you do not use project directory names that include spaces.
Some file operations in the LeonardoSpectrum software do not work correctly if the
path name contains spaces.
Specify timing constraints and compiler directives for the design in the
LeonardoSpectrum software, or in a constraint file (.ctr). These constraints are
forward-annotated in the .tcl file for use with the Classic Timing Analyzer in the
Quartus II software version 10.0 and earlier.
1
Timing-Driven Synthesis
The LeonardoSpectrum software supports timing-driven synthesis through
user-assigned timing constraints that optimize the performance of the design.
Constraints, such as clock frequency, can be specified globally or for individual clock
signals. The following sections describe how to set the various types of timing
constraints in the LeonardoSpectrum software.
The timing constraints described in Global PowerTab are set in the Constraints
FlowTab. In this FlowTab, there are PowerTabs at the bottom, such as Global and
Clock, for setting various constraints.
Global PowerTab
The Global PowerTab is the default PowerTab in the Constraints FlowTab where you
can specify the global clock frequency. The Clock Frequency setting on the Quick
Setup tab is equivalent to the Registers to Registers delay setting. You can also
specify the Input Ports to Registers, Registers to Output Ports, and Inputs to
Outputs delays that correspond to global tSU, tCO, and tPD requirements, respectively,
in the Quartus II software. The timing diagram on the Global PowerTab reflects the
settings you have made.
205
Clock PowerTab
You can set various constraints for each clock in your design. First, select the clock
name in the Clock(s) window. The clock names appear after the design is read from
the Input FlowTab. Configure settings for that particular clock and click Apply. You
can also specify the Duty Cycle, which is set to 5-% by default. The timing diagram
shows these settings.
If a clock has an Offset from the main clock, which is considered to be time 0, this
constraint corresponds to the OFFSET_FROM_BASE_CLOCK setting in the Quartus II
software.
You can specify the pin number for the clock input pin in the Pin Location box. This
pin number is passed to the Quartus II software for place-and-route, but does not
affect synthesis in the LeonardoSpectrum software.
Other Constraints
The following sections describe other constraints that can be set with the
LeonardoSpectrum user interface:
Encoding Style
Encoding Style
The LeonardoSpectrum software encodes state machines during the synthesis
process. To improve performance when coding state machines, separate state machine
logic from all arithmetic functions and data paths. When encoded, a design cannot be
re-encoded later in the optimization process. You must follow a particular VHDL or
Verilog HDL coding style for the LeonardoSpectrum software to identify the state
machine.
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Table 202 describes the state machine encoding styles supported by the
LeonardoSpectrum software.
Table 202. State Machine Encoding Styles in the LeonardoSpectrum Software
Style
Description
Binary
Generates state machines with the fewest possible flipflops. Binary state machines are useful for
area-critical designs when timing is not the primary concern.
Gray
Generates state machines where only one flipflop changes during each transition. Gray-encoded state
machines tend to be free of glitches.
One-hot
Generates state machines containing one flipflop for each state. One-hot state machines provide the best
performance and shortest clock-to-output delays. However, one-hot implementations are usually larger
than binary implementations.
Random
Generates state machines using random state machine encoding. Use random state machine encoding
only when no other implementation achieves the desired results.
Auto (Default)
Implements binary or one-hot encoding, depending on the size of enumerated types in the state machine.
The Encoding Style is created in the Input FlowTab. The setting instructs the software
to use a particular state machine encoding style for all state machines. The default
Auto encoding style implements binary or one-hot encoding, depending on the size of
enumerated types in the state machine.
f To ensure proper recognition and improve performance when coding state machines,
refer to the Recommended HDL Coding Styles chapter in volume 1 of the Quartus II
Handbook for design guidelines.
Resource Sharing
You should turn on Resource Sharing in the Input FlowTab to allow optimization,
which reduces device resources.
207
The LeonardoSpectrum software estimates the timing results based on timing models.
The software does not have the designs place-and-route information in the Quartus II
software, so it cannot report accurate routing delays. Additionally, if the design
includes any black boxed Altera-specific functions, the LeonardoSpectrum software
does not report timing information for these functions.
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Some IP cores require synthesis in the LeonardoSpectrum software. Refer to the user
guide for the specific IP.
209
Altera recommends using the MegaWizard Plug-In Manager to ensure that the ports
and parameters are set correctly.
The Stratix series and Cyclone series devices support the RAM primitive altsyncram
with a minimum RAM size of two bits, and a minimum RAM address width of
one bit.
To disable RAM inference, set the extract_ram and infer_ram variables to false.
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To enter the value false when performing synthesis in the user interface with the
Advanced FlowTabs, on the Tools menu, click Variable Editor, or add the set
extract_ram false and set infer_ram false commands to your synthesis script.
Inferring ROM
You can implement ROM behavior in HDL source code with CASE statements or
specify the ROM as a table. The LeonardoSpectrum software infers both synchronous
and asynchronous ROM, depending on the target Altera device. For example,
memory for Stratix series devices must be synchronous to be inferred.
To disable ROM inference, set the extract_rom variable to false. To enter the value
false when performing synthesis in the user interface with the Advanced FlowTabs,
on the Tools menu, click Variable Editor, or add the set extract_rom false
commands to your synthesis script.
LPM_MULT
ALTMULT_ACCUM
ALTMULT_ADD
You can instantiate these megafunctions in the design or direct the LeonardoSpectrum
software to infer the appropriate megafunction by recognizing a multiplier,
multiplier-accumulator (MAC), or multiplier-adder in the design. The Quartus II
software maps the functions to the DSP blocks in the device during place-and-route.
f For more information about inferring multipliers and DSP functions, including
examples of VHDL and Verilog HDL code, refer to the Recommended HDL Coding
Styles chapter in volume 1 of the Quartus II Handbook.
Simple Multipliers
The LPM_MULT megafunction implements the DSP block in the simple multiplier
mode. The following functionality is supported in this mode:
The DSP block includes registers for the input and output stages, and an
intermediate pipeline stage.
Multiplier Accumulators
The ALTMULT_ACCUM megafunction implements the DSP block in the
multiply-accumulator mode. The following functionality is supported in this mode:
The DSP block includes registers for the input and output stages, and an
intermediate pipeline stage.
2011
If the design requires input registers to be used as shift registers, use the black box
method to instantiate the ALTMULT_ACCUM megafunction.
Multiplier Adders
The LeonardoSpectrum software can infer multiplier adders and map them to either
the two-multiplier adder mode or the four-multiplier adder mode of the DSP blocks.
The LeonardoSpectrum software maps the HDL code to the correct ALTMULT_ADD
function.
The following functionality is supported in these modes:
The DSP block includes registers for the input and output stages, and an
intermediate pipeline stage.
Signed and unsigned arithmetic is supported, but support for the Verilog HDL
signed construct is limited.
Attribute Name
Global
extract_mac
Module
Signal
extract_mac
(2)
(3)
(1)
Value
Description
TRUE
FALSE
TRUE
FALSE
ON
OFF
dedicated_mult
LCELL
AUTO
LPM is inferred, but the Quartus II software automatically maps the multipliers
to either logic or DSP blocks based on the Quartus II software place-and-route.
Global Attribute
You can set the extract_mac global attribute to control the implementation of
multipliers in DSP blocks for the entire project. You can set this attribute with the
following script command:
set extract_mac <value>
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2013
Description
ON
OFF
LCELL
June 2012
LPM is inferred and multipliers are synthesized, implemented in logic, and optimized by the Quartus II software.
(1)
LPM is not inferred and multipliers are synthesized, implemented in logic, and optimized by the
LeonardoSpectrum software. (1)
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2014
Description
AUTO
LPM is inferred, but the Quartus II software maps the multipliers automatically to either the DSP block or logic
based on resource availability.
Some signals for which the dedicated_mult attribute is set may be removed during
synthesis by the LeonardoSpectrum software due to design optimization. In such
cases, if you want to force the implementation, you can preserve the signal from being
removed during synthesis by setting the preserve_signal attribute to true.
The extract_mac attribute must be set to false for the module or project level when
using the dedicated_mult attribute.
Example 203 and Example 204 are samples of Verilog HDL and VHDL codes,
respectively, using the dedicated_mult attribute.
Example 203. Signal Attributes for Controlling DSP Block Inference in Verilog HDL Code
module mult (AX, AY, BX, BY, m, n, o, p);
input [7:0] AX, AY, BX, BY;
output [15:0] m, n, o, p;
wire [15:0] m_i = AX * AY; // synthesis attribute m_i dedicated_mult ON
// synthesis attribute m_i preserve_signal TRUE
//Note that the preserve_signal attribute prevents
// signal m_i from being removed during synthesis
wire [15:0] n_i = BX * BY; // synthesis attribute n_i dedicated_mult OFF
wire [15:0] o_i = AX * BY; // synthesis attribute o_i dedicated_mult AUTO
wire [15:0] p_i = BX * AY; // synthesis attribute p_i dedicated_mult
LCELL
// since n_i , o_i , p_i signals are not preserved,
// they may be removed during synthesis based on the design
assign m = m_i;
assign n = n_i;
assign o = o_i;
assign p = p_i;
endmodule
2015
Example 204. Signal Attributes for Controlling DSP Block Inference in VHDL Code
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_signed.all;
ENTITY mult is
PORT( AX,AY,BX,BY: IN
std_logic_vector (17 DOWNTO 0);
m,n,o,p: OUT
std_logic_vector (35 DOWNTO 0));
attribute dedicated_mult: string;
attribute preserve_signal : boolean
END mult;
ARCHITECTURE struct of mult is
signal m_i, n_i, o_i, p_i :
attribute dedicated_mult of
attribute dedicated_mult of
attribute dedicated_mult of
attribute dedicated_mult of
begin
m_i
n_i
o_i
p_i
<=
<=
<=
<=
unsigned
unsigned
unsigned
unsigned
(AX)
(BX)
(AX)
(BX)
*
*
*
*
unsigned
unsigned
unsigned
unsigned
(AY);
(BY);
(BY);
(AY);
m <= std_logic_vector(m_i);
n <= std_logic_vector(n_i);
o <= std_logic_vector(o_i);
p <= std_logic_vector(p_i);
end struct;
June 2012
To access all the control signals for the DSP block, such as sign A, sign B, and
dynamic addnsub, use the black box technique.
While performing signed operations, ensure that the specified data width of the
output port matches the data width of the expected result. Otherwise, the sign bit
might be lost or data might be incorrect because the sign is not extended. For
example, if the data widths of input A and B are width_a and width_b, respectively,
the maximum data width of the result can be (width_a + width_b +2) for the
four-multipliers adder mode. Thus, the data width of the output port should be
less than or equal to (width_a + width_b +2).
While using the accumulator, the data width of the output port should be equal to
or greater than (width_a + width_b). The maximum width of the accumulator can
be (width_a + width_b + 16). Accumulators wider than this are implemented in
logic.
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2016
If the design uses more multipliers than are available in a particular device, the
Quartus II software may issue a no fit error. In such cases, use the attribute settings
in the LeonardoSpectrum software to control the mapping of multipliers in your
design to DSP blocks or logic.
2017
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2018
To set the correct constraints and compile the design, perform the following steps in
the LeonardoSpectrum software:
1. On the Tools menu, switch to the Advanced FlowTab instead of the Quick Setup
tab.
2. Set the target technology and speed grade for the device on the Technology
FlowTab.
3. Open the input source files on the Input FlowTab.
4. Click Read on the Input FlowTab to read the source files, but not begin
optimization.
5. Click the Module PowerTab located at the bottom of the Constraints FlowTab.
6. Select a module to be placed in a LogicLock region in the Modules section.
7. Turn on LogicLock.
8. Type the desired LogicLock region name under LogicLock.
9. Click Apply.
10. Repeat steps 6-9 for any other modules that you want to place in LogicLock
regions.
1
In some cases, you are prompted to save your LogicLock and other
non-global constraints in a Constraints File (.ctr) when you click anywhere
off the Constraints FlowTab. The default name is <project name>.ctr. This
file is added to your Input file list, and must be manually included later if
you recreate the project.
The command written into the LeonardoSpectrum Information or
Transcript Window is the Tcl command that is written into the .ctr file. The
format of the path for the module specified in the command should be
work.<module>.INTERFACE. To ensure that you do not see an optimized
version of the module, do not perform a Run Flow on the Quick Setup tab
prior to setting LogicLock constraints. Always use the Read command, as
described in step 4.
You might occasionally see multiple .edf files and LogicLock commands for the same
module. An unfolded version of a module is created when you instantiate a module
more than once and the boundary conditions of the instances are different. For
example, if you apply a constant to one instance of the block, it might be optimized to
eliminate unneeded logic. In this case, the LeonardoSpectrum software must create a
2019
separate module for each instantiation (unfolding). If this unfolding occurs, you see
more than one .edf file, and each .edf file has a LogicLock assignment to the same
LogicLock region. When you import the .edf files to the Quartus II software, the .edf
files created from the module are placed in different LogicLock regions. Any
optimizations performed in the Quartus II software using the LogicLock
methodology must be performed separately for each .edf file.
Use the .tcl file that is created for each .edf file by the LeonardoSpectrum software.
This method allows you to generate multiple Quartus II projects, one for each
block in the design. Each designer in the project can optimize their block
separately in the Quartus II software and preserve their results. Altera
recommends this method for bottom-up incremental and hierarchical design
methodologies because it allows each block in the design to be treated separately.
Each block can be brought into one top-level project with the import function.
or
June 2012
Altera Corporation
Use the <top-level project>.tcl file that contains the assignments for all blocks in the
project. This method allows the top-level designer to import all the blocks into one
Quartus II project. You can optimize all modules in the project at once in a
top-down design flow. If additional optimization is required for individual blocks,
each designer can use their .edf file to create a separate project at that time. You
must then add new assignments to the top-level project using the import function.
2020
In both methods, use the following steps to create the Quartus II project, import the
appropriate LogicLock assignments, and compile the design:
1. Place the .edf and .tcl files in the same directory.
2. On the View menu, point to Utility Windows and click Tcl Console to open the
Quartus II Tcl Console.
3. At the Tcl prompt, type source <path>/<project name>.tcl r.
4. To open the newly completed project, on the File menu, click Open Project.
Browse to and select the project name, and click Open.
f For more information about importing a design using incremental compilation, refer
to the Quartus II Incremental Compilation for Hierarchical and Team-Based Design chapter
in volume 1 of the Quartus II Handbook. For more information about importing
LogicLock assignments, see the Analyzing and Optimizing the Design Floorplan chapter
in volume 2 of the Quartus II Handbook.
Turn off Map IO Registers for the target technology on the Technology FlowTab.
Read the HDL files for the modules. Modules may include black box instantiations
of lower-level modules that are also maintained as separate .edf files.
Add constraints.
The following sections describe examples of black box modules in a block-based and
team-based design flow.
2021
In Figure 203, the top-level module A is assigned to one engineer (designer 1), while
two engineers work on the lower levels of the design. Designer 2 works on module B
and its submodules D and E, while designer 3 works on module C and its submodule
F.
Figure 203. Block-Based and Team-Based Design Example
Designer 1
Designer 2
Designer 3
One netlist is created for the top-level module A, another netlist is created for
module B and its submodules D and E, and another netlist is created for module C
and its submodule F. To create multiple .edf files, perform the following steps:
1. Generate an .edf file for module C. Use C.v and F.v as the source files.
2. Generate an .edf file for module B. Use B.v, D.v, and E.v as the source files.
3. Generate a top-level .edf file A.v for module A. Ensure that your black box
modules B and C were optimized separately in steps 1 and 2.
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Example 206 shows an example of the A.v top-level file. If any of your lower-level
files also contain a black-boxed lower-level file in the next level of hierarchy, follow
the same procedure.
Example 206. Verilog HDL Top-Level File Black Boxing Example
module A (data_in,clk,e,ld,data_out);
input data_in, clk, e, ld;
output [15:0] data_out;
reg [15:0] cnt_out;
reg [15:0] reg_a_out;
B U1 ( .data_in (data_in),.clk (clk), .e(e), .ld (ld),
.data_out(cnt_out) );
C U2 ( .d(cnt_out), .clk (clk), .e(e), .q (reg_out));
// Any other code in A.v goes here.
endmodule
// Empty Module Declarations of Sub-Blocks B and C follow here.
// These module declarations (including ports) are required for
blackboxing.
module B (data_in,e,ld,data_out );
input data_in, clk, e, ld;
output [15:0] data_out;
endmodule
module C (d,clk,e,q );
input d, clk, e;
output [15:0] q;
endmodule
2023
Example 207 shows an example of the A.vhd top-level file. If any of your lower-level
files also contain a black-boxed lower-level file in the next level of hierarchy, follow
the same procedure.
Example 207. VHDL Top-Level File Black Boxing Example
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY A IS
PORT ( data_in : IN INTEGER RANGE 0 TO 15;
clk : IN STD_LOGIC;
e : IN STD_LOGIC;
ld : IN STD_LOGIC;
data_out : OUT INTEGER RANGE 0 TO 15
);
END A;
ARCHITECTURE a_arch OF A IS
COMPONENT B PORT(
data_in : IN INTEGER RANGE 0 TO 15;
clk : IN STD_LOGIC;
e : IN STD_LOGIC;
ld : IN STD_LOGIC;
data_out : OUT INTEGER RANGE 0 TO 15
);
END COMPONENT;
COMPONENT C PORT(
d : IN INTEGER RANGE 0 TO 15;
clk : IN STD_LOGIC;
e : IN STD_LOGIC;
q : OUT INTEGER RANGE 0 TO 15
);
END COMPONENT;
-- Other component declarations in A.vhd go here
signal cnt_out : INTEGER RANGE 0 TO 15;
signal reg_a_out : INTEGER RANGE 0 TO 15;
BEGIN
CNT : C
PORT MAP (
data_in => data_in,
clk => clk,
e => e,
ld => ld,
data_out => cnt_out
);
REG_A : D
PORT MAP (
d => cnt_out,
clk => clk,
e => e,
q => reg_a_out
);
-- Any other code in A.vhd goes here
END a_arch;
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2024
Use the .tcl file that is created for each .edf file by the LeonardoSpectrum software.
This method generates multiple Quartus II projects, one for each block in the
design. Each designer in the project can optimize their block separately in the
Quartus II software and preserve their results. Designers should create a
LogicLock region for each block; the top-level designer should then import all the
blocks and assignments into the top-level project. Altera recommends this method
for bottom-up incremental and hierarchical design methodology because it allows
each block in the design to be treated separately; each block can be imported into
one top-level project.
or
Use the <top-level project>.tcl file that contains the information to set up the
top-level project. This method allows the top-level designer to create LogicLock
regions for each block and bring all the blocks into one Quartus II project.
Designers can optimize all modules in the project at once in a top-down design
flow. If additional optimization is required for individual blocks, each designer
creates a separate Quartus II project with each .edf file. New assignments must
then be added to the top-level project manually or through the import function.
f For more information about importing designs using incremental compilation, refer
to the Quartus II Incremental Compilation for Hierarchical and Team-Based Design chapter
in volume 1 of the Quartus II Handbook. For more information about importing
LogicLock regions, refer to the Analyzing and Optimizing the Design Floorplan chapter
in volume 2 of the Quartus II Handbook.
With both methods, use the following steps to create the Quartus II project and
compile the design:
1. Place the .edf and .tcl files in the same directory.
2. On the View menu, point to Utility Windows and click Tcl Console. The
Quartus II Tcl Console appears.
3. At a Tcl prompt, type source <path>/<project name>.tcl r.
4. On the File menu, click Open Project. In the New Project window, browse to and
select the project name. Click Open.
2025
3. Enter the target device family using the appropriate device keyword. The device
keyword is displayed on the Transcript or Information window when you select a
target Technology and click Load Library or Apply on the Technology FlowTab.
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Example 208 shows the LogicLock_Incremental.tcl file for the incremental synthesis
flow. You must modify the .tcl file before you can use it for your project.
Example 208. LogicLock_Interface.tcl Script File for Incremental Synthesis
##############################################
#### LogicLock Incremental Synthesis Flow ####
##############################################
## You must indicate which modules have changed (based on the source files
## that have changed) and provide the complete path to each module
## You must also specify the list of design files and the target Altera
## technology being used
# Read the design source files.
read <list of design files separated by spaces (such as block1.v block2.v)>
#
#
#
#
Get the list of modified modules in bottom-up "depth first search" order
where the lower-level blocks are listed first (these should be modules
that had LogicLock assignments and separate EDIF netlist files in the
first pass and had their source code modified)
}
foreach module $list_of_modified_modules {
set err_rc [regexp {\.(.*)\.(.*)\.(.*)} $module unused lib module_name arch]
present_design $module
undont_touch $module
auto_write $module_name.edf
# Ensure that the lower-level module is not written out in the EDIF file
# of the higher-level module.
noopt $module
}
2027
The LogicLock incremental design flow uses module-based design to help you
preserve performance of modules and have control over placement. By tagging the
modules that require separate .edf files, you can make multiple .edf files for use with
the Quartus II software from a single LeonardoSpectrum software project.
Conclusion
Taking advantage of the Mentor Graphics LeonardoSpectrum software and the
Quartus II design flow allows you to control how your design files are prepared for
the Quartus II place-and-route process, as well as to improve performance and
optimize a design for use with Altera devices. The methodologies outlined in this
chapter can help optimize a design to achieve performance goals and save design
time with the LeonardoSpectrum software. For the best results with new designs in
new device families, Altera recommends migrating to the advanced Mentor Graphics
Precision RTL Synthesis software.
Version
Changes
June 2012
12.0.0
November 2011
10.1.1
Template update.
December 2010
July 2010
10.1.0
10.0.0
November 2009
9.1.0
March 2009
9.0.0
November 2008
8.1.0
May 2008
8.0.0
Editorial changes.
No change to content.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
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Altera Corporation
2028
This chapter describes how you can use the Quartus II Netlist Viewers to analyze
and debug your designs.
As FPGA designs grow in size and complexity, the ability to analyze, debug, optimize,
and constrain your design is critical. With todays advanced designs, several design
engineers are involved in coding and synthesizing different design blocks, making it
difficult to analyze and debug the design. The Quartus II RTL Viewer, State Machine
Viewer, and Technology Map Viewer provide powerful ways to view your initial and
fully mapped synthesis results during the debugging, optimization, and constraint
entry processes.
This chapter contains the following sections:
Probing to a Source Design File and Other Quartus II Windows on page 2136
Probing to the Netlist Viewers from Other Quartus II Windows on page 2137
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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212
Using the RTL Viewer is a good way to view your initial synthesis results to
determine whether you have created the necessary logic, and that the logic and
connections have been interpreted correctly by the software. You can use the
RTL Viewer and State Machine Viewer to check your design visually before
simulation or other verification processes. Catching design errors at this early stage of
the design process can save you valuable time.
If you see unexpected behavior during verification, use the RTL Viewer to trace
through the netlist and ensure that the connections and logic in your design are as
expected. You can also view state machine transitions and transition equations with
the State Machine Viewer. Viewing your design helps you find and analyze the source
of design problems. If your design looks correct in the RTL Viewer, you know to focus
your analysis on later stages of the design process and investigate potential timing
violations or issues in the verification flow itself.
You can use the Technology Map Viewer to look at the results at the end of Analysis
and Synthesis. If you have compiled your design through the Fitter stage, you can
view your post-mapping netlist in the Technology Map Viewer (Post-Mapping) and
your post-fitting netlist in the Technology Map Viewer. If you perform only Analysis
and Synthesis, both the netlist viewers display the same post-mapping netlist.
In addition, you can use the RTL Viewer or Technology Map Viewer to locate the
source of a particular signal, which can help you debug your design. Use the
navigation techniques described in this chapter to search easily through your design.
You can trace back from a point of interest to find the source of the signal and ensure
the connections are as expected.
The Technology Map Viewer can help you locate post-synthesis nodes in your netlist
and make assignments when optimizing your design. This functionality is useful
when making a multicycle clock timing assignment between two registers in your
design. Start at an I/O port and trace forward or backward through the design and
through levels of hierarchy to find nodes of interest, or locate a specific register by
visually inspecting the schematic.
You can use the RTL Viewer, State Machine Viewer, and Technology Map Viewer in
many other ways throughout the design, debug, and optimization stages. This
chapter shows you how to use the various features of the netlist viewers to increase
your productivity when analyzing a design.
213
Before the netlist viewer can run the preprocessor stage, you must compile your
design:
To open the RTL Viewer or State Machine Viewer, first perform Analysis and
Elaboration.
To open the Technology Map Viewer (Post-Fitting) or the Technology Map Viewer
(Post-Mapping), first perform Analysis and Synthesis.
The netlist viewers display the results of the last successful compilation. Therefore, if
you make a design change that causes an error during Analysis and Elaboration, you
cannot view the netlist for the new design files, but you can still see the results from
the last successfully compiled version of the design files. If you receive an error
during compilation and you have not yet successfully run the appropriate
compilation stage for your project, the netlist viewer cannot be displayed; in this case,
the Quartus II software issues an error message when you try to open the netlist
viewer.
1
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If the netlist viewer is open when you start a new compilation, the netlist viewer
closes automatically. You must open the netlist viewer again to view the new design
netlist after compilation completes successfully.
Altera Corporation
214
Logic with no fan-out (its outputs are unconnected) and logic with no fan-in (its
inputs are unconnected) are removed from the display.
Pins, nets, wires, module ports, and certain logic are grouped into buses where
appropriate.
Chains of equivalent combinational gates are merged into a single gate. For
example, a 2-input AND gate feeding a 2-input AND gate is converted to a single
3-input AND gate.
State machine logic is converted into a state diagram, state transition table, and
state encoding table, which are displayed in the State Machine Viewer.
To run the RTL Viewer for a Quartus II project, first analyze the design to generate an
RTL netlist. To analyze the design and generate an RTL netlist, on the Processing
menu, point to Start and click Start Analysis & Elaboration. You can also perform a
full compilation on any process that includes the initial Analysis and Elaboration
stage of the Quartus II compilation flow.
To run the RTL Viewer, on the Tools menu, point to Netlist Viewers and click RTL
Viewer.
215
You can set the RTL Viewer preprocessing to run during a full compilation, which
allows you to open the RTL Viewer after Analysis and Synthesis has completed, but
while the Fitter is still running. In this case, you do not have to wait for the Fitter to
finish before viewing the schematic. This technique is useful for a large design that
requires a substantial amount of time in the place-and-route stage.
To set the RTL Viewer preprocessing to run during compilation, on the Assignments
menu, click Settings. In the Category list, select Compilation Process Settings and
turn on Run RTL Viewer preprocessing during compilation. By default, this option
is turned off.
Where possible, the port names of each hierarchy are maintained throughout
synthesis; however, port names might change or be removed from the design. For
example, if a port is unconnected or driven by GND or VCC, it is removed during
synthesis. When a port name changes, the port is assigned a related user logic name in
the design or a generic port name such as IN1 or OUT1.
You can view your Quartus II technology-mapped results after synthesis, fitting, or
timing analysis. To run the Technology Map Viewer for a Quartus II project, on the
Processing menu, point to Start and click Start Analysis & Synthesis to synthesize
and map the design to the target technology. At this stage, the Technology Map
Viewer shows the same post-mapping netlist as the Technology Map Viewer
(Post-Mapping). You can also perform a full compilation, or any process that includes
the synthesis stage in the compilation flow.
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If you have completed the Fitter stage, the Technology Map Viewer shows the
changes made to your netlist by the Fitter, such as physical synthesis optimizations,
while the Technology Map Viewer (Post-Mapping) shows the post-mapping netlist. If
you have completed the Timing Analysis stage, you can locate timing paths from the
Timing Analyzer report in the Technology Map Viewer (for more information, refer to
Viewing a Timing Path on page 2138). For a flow diagram, refer to Figure 211 on
page 213.
To run the Technology Map Viewer, on the Tools menu, point to Netlist Viewers and
click Technology Map Viewer, or select Technology Map Viewer from the
Applications toolbar.
To run the Technology Map Viewer (Post-Mapping), on the Tools menu, point to
Netlist Viewers and click Technology Map Viewer (Post-Mapping).
The Find paneallows you to find and locate specific design elements in the
schematic view.
Figure 212 shows the RTL Viewer and indicates these three parts, along with other
elements of the user interface. The netlist viewers also contain a toolbar that provides
tools to use in the schematic view.
You can have only one RTL Viewer, one Technology Map Viewer, one Technology
Map Viewer (Post-Mapping), and one State Machine Viewer window open at the
same time, although each window can show multiple pages. For example, you cannot
have two RTL Viewer windows open at the same time.
217
Figure 212 shows the schematic view and the Netlist Navigator pane of the RTL
Viewer.
Figure 212. RTL Viewer
Page
Toolbar
Edit
Toolbar
View
Toolbar
Tool
Toolbar
RTL Viewer
Toolbar
Find
Pane
Properties
Pane
Netlist
Navigator
Pane
Schematic View
Schematic View
The schematic view is shown on the right side of the RTL Viewer and Technology
Map Viewer. The schematic view contains a schematic representing the design logic in
the netlist. This view is the main screen for viewing your gate-level netlist in the RTL
Viewer and your technology-mapped netlist in the Technology Map Viewer.
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Schematic Symbols
The symbols for nodes in the schematic represent elements of your design netlist.
These elements include input and output ports, registers, logic gates, Altera
primitives, high-level operators, and hierarchical instances.
Figure 213 shows an example of an RTL Viewer schematic for a 3-bit synchronous
loadable counter. Example 211 shows the Verilog HDL code that produced this
schematic. This example includes multiplexers and a group of registers (Table 211) in
a bus along with an ADDER operator (Table 213 on page 2113) inferred by the
counting function in the HDL code.
The schematic in Figure 213 displays wire connections between nodes with a thin
black line and bus connections with a thick black line.
Figure 213. Example Schematic Diagram in the RTL Viewer
219
Example 211. Code Sample for Counter Schematic Shown in Figure 213
module counter (input [2:0] data, input clk, input load, output [2:0]
result);
reg [2:0] result_reg;
always @ (posedge clk)
if (load)
result_reg <= data;
else
result_reg <= result_reg + 1;
assign result = result_reg;
endmodule
Figure 214 shows a portion of the corresponding Technology Map Viewer schematic
with a compiled design that targets a Stratix device. In this schematic, you can see
the LCELL (logic cell) device-specific primitives that represent the counter function,
labeled with their post-synthesis node names. The REGOUT port represents the output
of the register in the LCELL; the COMBOUT port represents the output of the
combinational logic in the LUT of the LCELL. The hexadecimal number in
parentheses below each LCELL primitive represents the LUT mask, which is a
hexadecimal representation of the logic function of the LCELL.
Figure 214. Example Schematic Diagram in the Technology Map Viewer
Table 211 lists and describes the primitives and basic symbols that you can display in
the schematic view of the RTL Viewer and Technology Map Viewer. Table 213 on
page 2113 lists and describes the additional higher-level operator symbols in the RTL
Viewer schematic view.
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Altera Corporation
2110
The logic gates and operator primitives appear only in the RTL Viewer. Logic in the
Technology Map Viewer is represented by atom primitives, such as registers and
LCELLs.
Description
An input, output, or bidirectional port in the current level of hierarchy. A device input, output, or
bidirectional pin when viewing the top-level hierarchy. The symbol can also represent a bus.
Only one wire is shown connected to the bidirectional symbol, representing the input and output
paths.
Input symbols appear on the left-most side of the schematic. Output and bidirectional symbols
appear on the right-most side of the schematic.
I/O Connectors
An input or output connector, representing a net that comes from another page of the same
hierarchy (refer to Partitioning the Schematic into Pages on page 2128). To go to the page
that contains the source or the destination, right-click on the net and choose the page from the
menu (refer to Following Nets Across Schematic Pages on page 2129).
An OR, AND, or XOR gate primitive (the number of ports can vary). A small circle (bubble
symbol) on an input or output port indicates the port is inverted.
MULTIPLEXER
A multiplexer primitive with a selector port that selects between port 0 and port 1. A multiplexer
with more than two inputs is displayed as an operator (refer to Operator Symbols in the RTL
Viewer Schematic View on page 2113).
BUFFER
CARRY_SUM
A buffer primitive. The figure shows the tri-state buffer, with an inverted output enable port.
Other buffers without an enable port include LCELL, SOFT, CARRY, and GLOBAL. The NOT gate
and EXP expander buffers use this symbol without an enable port and with an inverted output
port.
A CARRY_SUM buffer primitive with the following ports:
SI SUM IN
SO SUM OUT
CI CARRY IN
CO CARRY OUT
2111
Description
A latch primitive with the following ports:
LATCH
DFFE/DFFEA/DFFEAS
Atom Primitive
Other Primitive
D data input
Q data output
PRE preset
CLR clear
A DFFE (data flipflop with clock enable) primitive, with the same ports as a latch and a clock
trigger. The other flipflop primitives are similar:
DFFEA (data flipflop with enable and asynchronous load) primitive with additional ALOAD
asynchronous load and ADATA data signals
DFFEAS (data flipflop with enable and synchronous and asynchronous load), which has
ASDATA as the secondary data port
An atom primitive. The symbol displays the atom name, the port names, and the atom type. The
blue shading indicates an atom primitive for which you can view the internal details. For more
information, refer to Viewing Contents of Atom Primitives on page 2123.
Any primitive that does not fall into the previous categories. Primitives are low-level nodes that
cannot be expanded to any lower hierarchy. The symbol displays the port names, the primitive
or operator type, and its name.
The figure shows an LCELL WYSIWYG primitive, with DATAA to DATAD and COMBOUT port
connections. This type of LCELL primitive is found in the Technology Map Viewer for
technology-specific atom primitives when the contents of the atom primitive cannot be viewed.
The RTL Viewer contains similar primitives if the source design is a VQM or EDIF netlist.
Instance
An instance in the design that does not correspond to a primitive or operator (a user-defined
hierarchy block). The symbol displays the port name and the instance name.
For more information about opening the schematic for the lower-level hierarchy, refer to
Traversing and Viewing the Design Hierarchy on page 2123.
Encrypted Instance
A user-defined encrypted instance in the design. The symbol displays the instance name. You
cannot open the schematic for the lower-level hierarchy, because the source design is
encrypted.
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2112
Description
RAM
A synchronous memory instance with registered inputs and optionally registered outputs. The
symbol shows the device family and the type of memory block. This figure shows a true
dual-port memory block in a Stratix M-RAM block.
Logic Cloud
A combinational logic cloud in the design. For more information, refer to Grouping
Combinational Logic into Logic Clouds on page 2125.
Constant
A constant signal value that is highlighted in gray and displayed in hexadecimal format by
default throughout the schematic. To change the format, refer to Changing the Constant Signal
Value Formatting on page 2126.
Table 212 lists and describes the symbol open only in the State Machine Viewer.
Table 212. Symbol Available Only in the State Machine Viewer
Symbol
Description
State Node
The node representing a state in a finite state machine. State transitions are
indicated with arcs between state nodes. The double circle border indicates the
state connects to logic outside the state machine, and a single circle border
indicates the state node does not feed outside logic.
2113
Table 213 lists and describes the additional higher level operator symbols in the RTL
Viewer schematic view.
Table 213. Operator Symbols in the RTL Viewer Schematic View
Symbol
(Part 1 of 2)
Description
An adder operator:
OUT = A + B
A multiplier operator:
OUT = A B
A divider operator:
OUT = A / B
Equals
A modulo operator:
OUT = (A % B)
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2114
(Part 2 of 2)
Description
A multiplexer:
OUT = DATA [SEL]
The data range size is 2sel range size
A selector:
A multiplexer with one-hot select input and more than two input signals
2115
In some cases, when you select a net that connects to nets in other levels of the
hierarchy, these connected nets are also highlighted in the current hierarchy. If you
prefer that these nets not be highlighted, use the Viewer Options dialog box option to
highlight a net only if the net is in the current hierarchy. Right-click in the schematic
and click Viewer Options. In the Net Selection section, turn on the Limit selections
to current hierarchy option.
Nodes inside atom primitives are not listed in the Netlist Navigator pane.
For each module in the design hierarchy, the Netlist Navigator pane displays the
applicable elements listed in Table 214. Click the + icon to expand an element.
Description
Modules or instances in the design that can be expanded to lower hierarchy levels.
State Machines State machine instances in the design that can be viewed in the State Machine Viewer.
Low-level nodes that cannot be expanded to any lower hierarchy level. These primitives include:
Primitives
Registers and gates that you can view in the RTL Viewer when using Quartus II integrated synthesis
Logic cell atoms in the Technology Map Viewer or in the RTL Viewer when using a VQM or EDIF from
third-party synthesis software
In the Technology Map Viewer, you can view the internal implementation of certain atom primitives, but
you cannot traverse into a lower-level of hierarchy.
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Description
The I/O ports in the current level of hierarchy.
Pins are device I/O pins when viewing the top hierarchy level and are I/O ports of the design when
viewing the lower-levels.
When a pin represents a bus or an array of pins, expand the pin entry in the list view to see individual
pin names.
Pins
Nets
Nets or wires connecting the nodes. When a net represents a bus or array of nets, expand the net entry in
the tree to see individual net names.
Logic Clouds
A group of related combinational logics of a particular source. You can automatically or manually group
combinational logics or ungroup logic clouds in your design.
Properties
The Properties pane is a dockable pane that displays only node type components such
as pins, primitives, and instances. This pane consists of two viewers; the connectivity
view and table view. The table view lists the fan-in, fan-out, parameters, and ports
tables. The connectivity view displays the selected block connectivity information
listed in the table view, such as fan-in or fan-out connection, schematic, truth table,
and Karnaugh map.
To open the Properties Pane, follow these steps:
1. In the Quartus II software, on the Tools menu, point to Netlist Viewers and click
RTL Viewer.
2. In the RTL Viewer window, on the View Toolbar, click the Property icon.
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Tool
Toolbar
Edit
Toolbar
Page
Toolbar
Properties Pane
Schematic View
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On the Tools menu, point to Netlist Viewers and click State Machine Viewer.
Right-click a state machine instance in the RTL Viewer and click Hierarchy Down.
Select a state machine instance in the RTL Viewer, and on the Project menu, point
to Hierarchy and click Down.
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Figure 216 shows an example of the State Machine Viewer for a simple state
machine.
Figure 216. The State Machine Viewer
Back/Forward Display
Toolbar
Highlight
Fan-in/Fan-out
Toolbar
View
Toolbar
Tool
Toolbar
State Machine
Viewer Toolbar
An encrypted block with a state machine displays encoding information in the state
encoding table, but does not display a state transition diagram or table.
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Conditionthe condition equation that causes the transition from source state to
destination state
To see all of the transitions to and from each state name, click the appropriate column
heading to sort on that column.
The text in each column is left-aligned by default; to change the alignment and to
make it easier to see the relevant part of the text, right-click the column and click
Align Right. To revert to left alignment, click Align Left.
Click in any cell in the table to select it. To select all cells, right-click in the cell and
click Select All; or, on the Edit menu, click Select All. To copy selected cells to the
clipboard, right-click the cells and click Copy Table; or, on the Edit menu, point to
Copy and click Copy Table. You can paste the table into any text editor as
tab-separated columns.
Options
The Options dialog box allows you to customize your settings, such as display
settings, colors, fonts, tracing, customize view, and shortcut commands. To open the
Options dialog box, in the RTL Viewer window, on the Tools menu, click Options.
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Netlist Viewers
If you want to customize the display settings for your preferred viewing, you can
direct the RTL Viewer and Technology Map Viewer to adjust the settings in the
schematic view. To adjust the display settings, on the Tools menu, click Options. In
the Netlist Viewers category, under Display Settings, you can select the options to
customize your display.
Display Settings
You can divide the schematic representation of a large design into multiple pages.
Dividing the display of the schematic into multiple pages does not affect your design,
and only controls the number of elements per page. Under Display Settings, the
Nodes per page option allows you to specify the number of nodes displayed per
page. The default value is 500 nodes; however, you can view from one to 1,000 nodes
per page. The Ports per page option allows you to specify the number of ports (or
pins) displayed per page. The default value is 1,000 ports (or pins); the range is 1 to
2,000 ports (or pins). The netlist viewers partition your design into a new page if
either the number of nodes or the number of ports exceeds the limit you specified.
Occasionally, the number of ports displayed on the page might exceed the limit you
specified, depending on the configuration of nodes on the page. If you turned on the
Display boundary around hierarchy levels option and the total number of nodes or
ports in the hierarchy exceeds the value you specified for the Nodes per page or Ports
per page options, the netlist viewers display the boundary as a hierarchy port
connector (refer to Table 211 on page 2110).
To display net names in your schematic, turn on the Show Net Name option. If you
turn on this option, the schematic view refreshes automatically to display the net
names. To show node names in the schematic view, turn on the Show node name
option. To change the value formatting, select the necessary format in the Constant
signal format list.
To view highlighting around the design element in range of the mouse pointer, turn
on the Enable rollover option. To more easily navigate through your design hierarchy,
you can direct the netlist viewers to automatically expand the hierarchy list in Netlist
Navigator pane and highlight the design element you selected in the schematic view.
This automatic expansion and selection of corresponding design elements is useful
when you have a complex schematic that spans multiple display pages in the netlist
viewers. To use the automatic expansion and selection feature, turn on the Enable
auto hierarchy expansion option.
To trace signal path in the schematic using the Global Net Routing feature, turn on the
Enable global net routing option.
Radial Menu Settings
To enable the radial menu, turn on the Enable radial menu option. The radial menu is
an octagonal menu with eight commands from which you can choose. This menu
provides a quick way to perform any of the commands with a single click whenever
you are in the schematic view.
To open the radial menu, right-click and hold anywhere in the schematic view and
wait for the menu to appear. By default, the menu appears after 0.2 seconds. The
radial menu appears with the mouse pointer always at the center point. The center
point of the menu is a non-trigger boundary in which no command is started.
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To run the necessary command, hold down the right mouse button, drag the mouse
onto the command, and then press the left mouse button. If you decide not to trigger
any command after the radial menu appears, press the Esc key or drag the pointer
back into the center point and release the mouse button.
To change the delay time before the radial menu appears, select the necessary interval
time in the drop-down list for Delay showing radial menu for. The default delay is
0.2 seconds.
Automatic Texts Hiding
This option allows you to automatically hide texts such as node names, port names,
and net names, depending on your preferred zoom level. By default, when your
schematic is zoomed 40% smaller, the text is hidden.
Colors
This option allow you to determine your preferred colors to represent the elements in
the schematics.
Fonts
This option allows you to determine the type of text, font size, color and style for the
node and net names in the schematics.
Tracing
If you want to filter information from the schematic view of your design to isolate
specific design elements for further inspection, or if you want to expand specific
design elements, you can direct the RTL Viewer and the Technology Map Viewer to
adjust the elements the viewers show in the schematic view. To adjust the filtering and
expansion settings in the RTL Viewer and Technology Map Viewer, on the Tools
menu, click Options. Under Tracing, you can select the options to control filtering and
expansion settings.
For all filtering commands, the netlist viewers stop tracing through the netlist when
they reach one of the following objects:
A pin
A specified number of filtering levels, counting from the selected node or port
A register
To specify the number of filtering levels, set the Number of filtering levels option to
specify the number of levels to expand. You can specify a value from one to 100.
To enable the Stop filtering at register option, turn on the Stop filtering at register
option. You can filter across hierarchies when you turn on the Filter across hierarchy
option.
By default, the filtered schematic shows all possible connections between the nodes
shown in the schematic. To remove the connections that are not directly part of the
path that was traced to generate a filtered netlist, turn off the Show all connections
between nodes option.
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To set the amount of logic you want to expand, set the Number of expansion levels
option to specify the number of levels to expand. You can specify a range from one to
100 levels. You can also set the Stop expanding at register option to specify whether
netlist expansion should stop when a register is reached.
Customize View
If you want to customize the schematic display for better viewing and to speed up
your debugging process, you can direct the RTL Viewer and the Technology Map
Viewer to remove fan-out free nodes, show simplify logic, group or ungroup related
nodes, and group combinational logic into a logic cloud. To adjust the options that
control the schematic display in the RTL Viewer and the Technology Map Viewer, on
the Tools menu, click Options. Under Customize View, you can select the options to
customize your view. These options are also available in the Customize View tab of
the RTL/Technology Map Viewer Options dialog box. To open the dialog box,
right-click in the schematic and click Viewer Options.
1
When you change settings, the list of previously viewed pages is cleared. The settings
are revision-specific, so different revisions can have different settings.
To remove fan-out free registers from your schematic display, turn on the Remove
registers without fan-out option. To remove all single-input nodes and merge a chain
of equivalent combinational gates that have direct connections (without inversion in
between) into a single multiple-input gate, turn on the Show simplified logic option.
To group all related nodes into a single node, turn on the Group all related nodes
option. You can manually group or ungroup any nodes by right-clicking the selected
nodes in the schematic and selecting Group Related Nodes or Ungroup Selected
Nodes. To group combinational logic into logic clouds, turn on the Group
combinational logic into logic cloud option.
Customize Logic and Customize Group options are available for the RTL Viewer,
whereas only the Customize Group option is available for the Technology Map
Viewer.
Shortcut Commands
You can choose eight commands to appear on the radial menu from a list of 18
available commands. To customize the command list on the menu, first open the RTL
Viewer or the Technology Map Viewer. On the Tools menu, select Options. On the
Shortcut Commands category list, drag and drop the icon under Shortcut buttons
into any region under Shortcut commands popup. You can click the icon under
Shortcut buttons to see its description.
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In addition, you can view the implementation of RAM and DSP blocks in certain
devices in the RTL Viewer or Technology Map Viewer. You can view the
implementation of RAM blocks in the Arria GX, Cyclone series, and Stratix series of
devices. You can view the implementation of DSP blocks only in Arria GX and Stratix
series of devices.
If you can view the contents of an atom instance, the internal contents are shown in
blue in the schematic view (Figure 218).
Figure 218. Instance That Can Be Expanded to View Internal Contents
To view the contents of one or more atom primitive instances, select the necessary
atom instances. Right-click a selected instance and click Display Content. You can
also double-click the necessary atom instance to view the contents. Figure 219 shows
an expanded version of the instance in Figure 218.
Figure 219. Internal Contents of the Atom Instance in Figure 218.
Instance Name
Hierarchical Boundary
Port Relationship
Between Boundaries
To hide the contents (and revert to the compact format), select and right-click the atom
instance or instances, and click Hide Content.
1
In the schematic view, the internal details in an atom instance cannot be selected as
individual nodes. Any mouse action on any of the internal details is treated as a
mouse action on the atom instance.
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The Properties dialog box contains the following information about the selected node:
The active level of the port (for example, active high or active low). An active low
port is denoted with an exclamation mark !.
The ports constant value (for example, VCC or GND). Table 215 describes the
possible value of a port.
Description
VCC
The port is not connected and has VCC value (tied to VCC)
GND
The port is not connected and has GND value (tied to GND)
--
The port is connected and has value (other than VCC or GND)
Unconnected
In the LUT of a logic cell (LCELL), the Properties dialog box contains the following
additional information:
The Karnaugh Map tabthe Karnaugh map representations of the LUT. The
Karnaugh map supports up to 6 input LUTs.
For more information about the Ports tab, refer to Viewing the Properties of
Instances and Primitives on page 2124.
For the definition of a logic cloud, refer to Table 211 on page 2110.
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When you change the number of nodes or ports per page, the change applies only to
new pages that are shown or opened in the netlist viewer. To refresh the current page
so that it displays the changed number of nodes or ports, click the Refresh button on
the toolbar.
You can go forward only if you have not made any changes to the view since going
back. Use the Back and Forward commands to switch between page views. These
commands do not undo an action, such as selecting a node.
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After you right-click to follow a connector port, the netlist viewer opens a new page,
which centers the view on the particular source or destination net using the same
zoom factor as the previous page. To trace a specific net to the new page of the
hierarchy, Altera recommends that you first select the necessary net, which highlights
it in red, before you right-click to traverse pages.
Input Connectors
Figure 2112 shows an example of the menu that appears when you right-click an
input connector. The From command opens the page containing the source of the
signal. The Related commands, if applicable, open the specified page containing
another connection fed by the same source.
Figure 2112. Input Connector Shortcut Menu
Signal source is on page 2
Output Connectors
Figure 2113 shows an example of the menu that appears when you right-click an
output connector. The To command opens the specified page that contains a
destination of the signal.
Figure 2113. Output Connector Shortcut Menu
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Go to Net Driver
To locate the source of a particular net in the schematic view, right-click the net, point
to Go to Net Driver and click Current page, Current hierarchy, or Across hierarchies.
Table 216 lists the Go to Net Driver commands.
Table 216. Go to Net Driver Commands
Command
Action
Current page
Locates the source or driver on the current page of the schematic only.
Current hierarchy
Locates the source in the current level of hierarchy, even if the source is located on another page of
the netlist schematic.
Across hierarchies
Locates the source across hierarchies until the software reaches the source at the top hierarchy level.
The schematic view opens the correct page of the schematic, if required, and adjusts
the centering of the page so that you can see the net source. The schematic shows the
default page for the net driver. The view is unfiltered, so no filtering results are kept.
Selected Nodes and Netsdisplays only the selected nodes and nets with the
connections between them
To filter your netlist, select a hierarchy box, node, port, net, or state node, right-click in
the window, point to Filter and click the appropriate filter command. The netlist
viewer generates a new page showing the netlist that remains after filtering.
When filtering in a state diagram in the State Machine Viewer, sources and
destinations refer to the previous and next transition states or paths between
transition states in the state diagram. The transition table and encoding table also
reflect the filtering.
You can go back to the netlist page before it was filtered using the Back command, as
described in Moving Back and Forward Through Schematic Pages on page 2128.
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When viewing a filtered netlist, clicking an item in the Netlist Navigator pane causes
the schematic view to display an unfiltered view of the appropriate hierarchy level.
You cannot use the Netlist Navigator pane to select items or navigate in a filtered
netlist.
Shows all the sources of the nodes input ports. For an example, refer to Figure 2114.
Net
Shows only the input source nodes that feed this port.
Shows the states that feed the selected state (previous transition states).
Shows all the destinations of the nodes output ports. For an example, refer to
Figure 2114.
Net
Shows the states that are fed by the selected states (next transition states).
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Sources
Selected Node
pin_name3
inst2
pin_name3
inst2OUT1
inst4
pin_name4
inst4OUT1
instOUT1
pin_name4
Destinations
pin_name5
pin_name
inst3
inst3OUT1
pin_name6
inst
pin_name
pin_name2
pin_name2
pin_name5
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Figure 2116 shows the schematic after filtering. If you select a net, the filtered page
shows the immediate sources and destinations of the selected net.
Figure 2116. Selected Nodes and Nets Filtering on Figure 2115 Schematic
New Schematic Created After Applying Selected Nodes and Nets Filtering
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Netlists of the same hierarchy displayed over more than one page are not grouped
with a box. Filtering and expanding on a blue atom primitive does not trace the
underlying netlist, even when Filter across hierarchy is enabled.
Figure 2117 and Figure 2118 show examples of filtering across hierarchical
boundaries. Figure 2117 shows a smaller example of an input port of the taps
instance after the Sources filter is applied, in which the input port of the lower-level
hierarchical block connects directly to an input pin of the design. The name of the
instance appears in the green border and as a tooltip when you move your mouse
pointer over the instance.
Figure 2117. Filtering Across Hierarchical Boundaries
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Figure 2118 shows a larger example of an input port of an instance after the Sources
filter is applied, in which the source comes from input pins that are fed through
another level of hierarchy.
Figure 2118. Filtering Across Hierarchical Boundaries
Sources command applied to an input port of an instance in which the source comes from input pins
that are fed through another level of hierarchy
SourcesDisplays the states that feed the selected states (previous transition
states)
DestinationsDisplays the states that are fed by the selected states (next
transition states)
The state transition table and state encoding table also reflect the changes to the filter.
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The expansion feature works across hierarchical boundaries if the filtered page
containing the port you want to expand was generated with the Filter across
hierarchy option turned on (for details about this option, refer to Filtering in the
Schematic View on page 2130). When viewing timing paths in the Technology Map
Viewer, the Expand command always works across hierarchical boundaries because
filtering across hierarchy is always turned on for these schematics (for details about
these schematics, refer to Viewing a Timing Path on page 2138).
The options available for locating an item depend on the type of node and whether it
exists after placement and routing. If a command is enabled in the menu, it is
available for the selected node. You can use the Locate in Assignment Editor
command for all nodes, but assignments might be ignored during placement and
routing if they are applied to nodes that do not exist after synthesis.
The netlist viewer automatically opens another window for the appropriate editor or
floorplan and highlights the selected node or net in the newly opened window. You
can switch back to the netlist viewer by selecting it in the Window menu or by closing,
minimizing, or moving the new window.
1
When probing to a logic cloud in the RTL Viewer, a message box appears, prompting
you to ungroup the logic cloud or allow it to remain grouped.
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Project Navigator
Chip Planner
Node Finder
Assignment Editor
Messages Window
Compilation Report
To locate elements in the netlist viewer from another Quartus II window, select the
node or nodes in the appropriate window; for example, select an entity in the Entity
list on the Hierarchy tab in the Project Navigator, or select nodes in the Timing
Closure Floorplan, or select node names in the From or To column in the Assignment
Editor. Next, right-click the selected object, point to Locate, and click Locate in RTL
Viewer or Locate in Technology Map Viewer. After you click this command, the
netlist viewer opens, or is brought to the foreground if the netlist viewer is open.
1
The first time the window opens after a compilation, the preprocessor stage runs
before the netlist viewer opens.
The netlist viewer shows the selected nodes and, if applicable, the connections
between the nodes. The display is similar to what you see if you right-click the object,
point to Filter, and click Selected Nodes & Nets using Filter Across Hierarchy. If the
nodes cannot be found in the netlist viewer, a message box displays the message:
Cant find requested location.
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In the RTL Viewer, the schematic page displays the nodes in the paths between the
source and destination registers with a summary of the total delay.
The RTL Viewer netlist is based on an initial stage of synthesis, so the post-fitting
nodes might not exist in the RTL Viewer netlist. Therefore, the internal delay numbers
are not displayed in the RTL Viewer as they are in the Technology Map Viewer, and
the timing path might not be displayed exactly as it appears in the timing analysis
report. If multiple paths exist between the source and destination registers, the RTL
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Viewer might display more than just the timing path. There are also some cases in
which the path cannot be displayed, such as paths through state machines, encrypted
intellectual property (IP), or registers that are created during the fitting process. In
cases where the timing path displayed in the RTL Viewer might not be the correct
path, the compiler issues messages.
Tooltips
A tooltip is displayed whenever the mouse pointer is held over an element in the
schematic. The tooltip contains useful information about a node, net, logic cloud,
input port, or output port. Table 219 lists the information contained in the tooltip for
each type of node.
The tooltip information for an instance (the first row in Table 219) includes a list of
the primitives found in that level of hierarchy and the number of each primitive
contained in the current instance. The number includes all hierarchical blocks below
the current instance in the hierarchy. This information lets you estimate the size and
complexity of a hierarchical block without navigating into the block.
The tooltip information for atom primitives in the Technology Map Viewer (the
second row in Table 219) shows the equation for the design atom. The equations are
an expanded version of the equations you can view in the Equations window in the
Timing Closure Floorplan. Advanced users can use these equations to analyze the
design implementation in detail.
h For more information about understanding equations, refer to the Quartus II Help.
To copy tooltips into the clipboard for use in other applications, right-click the
necessary node or netlist and click Copy Tooltip.
To turn off tooltips or change the duration of time that a tooltip appears in the view, in
the main Quartus II window, select Options. In the Tooltip Settings pane, turn on the
Enable tooltips option.
The Show names in tooltip for option specifies the number of seconds to display the
names of assigned nodes and pins in a tooltip when the pointer is over the assigned
nodes and pins. Selecting Unlimited displays the tooltip as long as the pointer
remains over the node or pin. Selecting 0 turns off tooltips. The default value is 5
seconds.
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The Delay showing tooltip for option specifies the number of seconds you must hold
the mouse pointer over assigned nodes and pins before the tooltip displays the names
of the assigned nodes and pins. Selecting 0 displays the tooltip immediately when the
pointer is over an assigned node or pin. Selecting Unlimited prevents the display of
tooltips. The default value is 1 second.
Table 219. Tooltip Information
Tooltip Format
(Part 1 of 2)
Description
Example Tooltips
Atom Primitive
Primitive
Pin
Connector
Net
Output Port
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(Part 2 of 2)
Tooltip Format
Description
Example Tooltips
(1)
(2)
(3)
(4)
(5)
(6)
State Machine
Transition Arc
Click Browse in the Find pane to specify the hierarchy level of the search. In the
Select Hierarchy Level dialog box, select the particular instance you want to
search.
Turn on the Include subentities option to include child hierarchies of the parent
instance during the search.
Click Options to open the Find Options dialog box. Turn on Instances, Nodes,
Pins, or any combination of the three to further refine the parameters of the search.
When you click the List button, a progress bar appears below the Find box.
All results that match the criteria you set are listed in a table. When you double-click
an item in the table, the related node is highlighted in red in the schematic view.
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Nodes grouped as logic clouds are not shown in the exported or copied schematic
image; the logic clouds are shown instead.
You can copy the entire image or a portion of the image. To copy the entire image,
right-click on the schematic, point to Copy, and then click Full Image. To copy a
portion of the image, right-click on the schematic, point to Copy, and then click Partial
Image. The cursor changes to a + sign to indicate that you can draw a box shape.
Drag the mouse pointer around the portion of the schematic you want to copy. When
you release the mouse button, the partial image is copied to the clipboard.
Occasionally, due to the design size and objects selected, an image is too large to copy
to the clipboard. In this case, the Quartus II software displays an error message.
To export or copy a schematic that is too large to copy in one piece, split the design
into multiple pages to export or to copy smaller portions of the design. For more
information about controlling how much of your design is shown on each schematic
page, refer to Partitioning the Schematic into Pages on page 2128. As an
alternative, use the Partial Image feature to copy a portion of the image.
Printing
To print your schematic page, on the File menu, click Print. You can print each
schematic page onto one page, or you can print selected parts of your schematic onto
one page with the Selection option. To control how much of your design is shown on
each schematic page, refer to Partitioning the Schematic into Pages on page 2128.
You cannot print the Netlist Navigator pane in the RTL Viewer and Technology Map
Viewer and the table view of the State Machine Viewer. You can use the State Machine
Viewer Copy command to copy the table to a text editor and print from the text editor.
Conclusion
The Quartus II RTL Viewer, State Machine Viewer, and Technology Map Viewer allow
you to explore and analyze your initial synthesis netlist, post-synthesis netlist, or
post-fitting and physical synthesis netlist. The netlist viewers provide a number of
features in the Netlist Navigator pane and schematic view to help you quickly trace
through your netlist and find specific hierarchies or nodes of interest. These
capabilities can help you debug, optimize, and constrain your design more efficiently
to increase your productivity.
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Date
Changes
Added the following sections:
November 2012
12.1.0
June 2012
12.0.0
November 2011
10.0.2
Template update.
December 2010
10.0.1
July 2010
10.0.0
November 2009
9.1.0
March 2009
9.0.0
November 2008
May 2008
November 2012
8.1.0
8.0.0
Altera Corporation
Updated screenshots
Updated chapter for the Quartus II software version 10.0, including major user interface
changes
Updated devices
Updated Figure 132, Figure 133, Figure 134, Figure 1314, and Figure 1330
Added .png and .gif to the list of supported image file formats
Added new sections Enabling and Disabling the Radial Menu, Changing the Time
Interval, Changing the Constant Signal Value Formatting, Logic Clouds in the RTL
Viewer, Logic Clouds in the Technology Map Viewer, Manually Group and Ungroup
Logic Clouds, Customizing the Shortcut Commands
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f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
Additional Information
This chapter provides additional information about the document and Altera.
Contact Method
Address
Website
www.altera.com/support
Website
www.altera.com/training
Email
Website
custrain@altera.com
www.altera.com/literature
nacomp@altera.com
(software licensing)
authorization@altera.com
Note to Table:
(1) You can also contact your local Altera sales office or sales representative.
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Info2
Additional Information
Typographic Conventions
Typographic Conventions
The following table shows the typographic conventions this document uses.
Visual Cue
Meaning
Indicate command names, dialog box titles, dialog box options, and other GUI
labels. For example, Save As dialog box. For GUI elements, capitalization matches
the GUI.
bold type
Indicates directory names, project names, disk drive names, file names, file name
extensions, software utility names, and GUI labels. For example, \qdesigns
directory, D: drive, and chiptrip.gdf file.
italic type
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Indicate keyboard keys and menu names. For example, the Delete key and the
Options menu.
Subheading Title
Courier type
Indicates command line commands and anything that must be typed exactly as it
appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.
Also indicates sections of an actual file, such as a Report File, references to parts of
files (for example, the AHDL keyword SUBDESIGN), and logic function names (for
example, TRI).
Numbered steps indicate a list of items when the sequence of the items is important,
such as the steps listed in a procedure.
Bullets indicate a list of items when the sequence of the items is not important.
The question mark directs you to a software help system with related information.
The feet direct you to another document or website with related information.
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2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
ISO
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and 9001:2008
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service Registered
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
May 2013
Altera Corporation
Constraining Designs
Revised:
November 2012
Part Number: QII52001-12.1.0
Chapter 2.
Command-Line Scripting
Revised:
June 2012
Part Number: QII52002-12.0.0
Chapter 3.
Tcl Scripting
Revised:
June 2012
Part Number: QII52003-12.0.0
Chapter 4.
I/O Management
Revised:
May 2013
Part Number: QII52013-13.0.0
Chapter 5.
Chapter 6.
Chapter 7.
Chapter 8.
Chapter 9.
May 2013
Altera Corporation
xviii
As a result of the increasing complexity of todays FPGA designs and the demand for
higher performance, designers must make a large number of complex timing and
logic constraints to meet their performance requirements. After you create a project
and design, you can use the Quartus II software Assignment Editor and other GUI
features to specify your initial design constraints, such as pin assignments, device
options, logic options, and timing constraints.
This section describes how to constrain designs, how to take advantage of Quartus II
modular executables, how to develop and run Tcl scripts to perform a wide range of
functions, and how to manage the Quartus II projects.
This section includes the following chapters:
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
1. Constraining Designs
November 2012
QII52001-12.1.0
QII52001-12.1.0
This chapter discusses the various tools and methods for constraining and
re-constraining Quartus II designs in different design flows, both with the Quartus II
GUI and with Tcl to facilitate a scripted flow.
Constraints, sometimes known as assignments or logic options, control the way the
Quartus II software implements a design for an FPGA. Constraints are also central in
the way that the TimeQuest Timing Analyzer and the PowerPlay Power Analyzer
inform synthesis, placement, and routing. There are several types of constraints:
Global design constraints and software settings, such as device family selection,
package type, and pin count.
Instance-level constraints.
User-created constraints are contained in one of two files: the Quartus II Settings File
(.qsf) or, in the case of timing constraints, the Synopsys Design Constraints file (.sdc).
Constraints and assignments made with the Device dialog box, Settings dialog box,
Assignment Editor, Chip Planner, and Pin Planner are contained in the Quartus II
Settings File. The .qsf file contains project-wide and instance-level assignments for the
current revision of the project in Tcl syntax. You can create separate revisions of your
project with different settings, and there is a separate .qsf file for each revision.
The TimeQuest Timing Analyzer uses industry-standard Synopsys Design
Constraints, also using Tcl syntax, that are contained in Synopsys Design Constraints
(.sdc) files. The TimeQuest Timing Analyzer GUI is a tool for making timing
constraints and viewing the results of subsequent analysis.
There are several ways to constrain a design, each potentially more appropriate than
the others, depending on your tool chain and design flow. You can constrain designs
for compilation and analysis in the Quartus II software using the GUI, as well as using
Tcl syntax and scripting. By combining the Tcl syntax of the .qsf files and the .sdc files
with procedural Tcl, you can automate iteration over several different settings,
changing constraints and recompiling.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Feedback Subscribe
12
Global Constraints
Global constraints affect the entire Quartus II project and all of the applicable logic in
the design. Many of these constraints are simply project settings, such as the targeted
device selected for the design. Synthesis optimizations and global timing and power
analysis settings can also be applied with globally. Global constraints are often made
when running the New Project Wizard, or in the Device dialog box or the Settings
dialog box, early project development.
The following are the most common types of global constraints:
Top-level entity of your design, and the names of the design files included in the
project
.sdc files for the TimeQuest timing analyzer to use during analysis as part of a full
compilation flow
Settings that direct compilation and analysis flows in the Quartus II software are also
stored in the Quartus II Settings File for your project, including the following global
software settings:
Settings for EDA tool integration such as third-party synthesis tools, simulation
tools, timing analysis tools, and formal verification tools.
13
Settings and settings file specifications for the Quartus II Assembler, SignalTap II
Logic Analyzer, PowerPlay power analyzer, and SSN Analyzer.
Global constraints and software settings stored in the Quartus II settings file are
specific to each revision of your design, allowing you to control the operation of the
software differently for different revisions. For example, different revisions can
specify different operating temperatures and different devices, so that you can
compare results.
Only the valid assignments made in the Assignment Editor are saved in the
Quartus II Settings File, which is located in the project directory. When you make a
design constraint, the new assignment is placed on a new line at the end of the file.
When you create or update a constraint in the GUI, the Quartus II software displays
the equivalent Tcl command in the System tab of the Messages window. You can use
the displayed messages as references when making assignments using Tcl commands.
h For more information about specifying initial global constraints and software settings,
refer to Setting up and Running a Compilation in Quartus II Help.
f For more information about how the Quartus II software uses Quartus II Settings
Files, refer to the Managing Quartus II Projects chapter in volume 2 of the Quartus II
Handbook.
November 2012
Altera Corporation
14
The Chip Planner allows you to view the device from a variety of different
perspectives, and you can make precise assignments to specific floorplan locations.
With the Chip Planner, you can adjust existing assignments to device resources, such
as pins, logic cells, and LABs using drag and drop features and a graphical interface.
You can also view equations and routing information, and demote assignments by
dragging and dropping assignments to various regions in the Regions window.
h For more information about the Assignment Editor, refer to About the Assignment
Editor in Quartus II Help. For more information about the Chip Planner, refer to About
the Chip Planner in Quartus II Help. For more information about the Pin Planner, refer
to Assigning Device I/O Pins in Pin Planner in Quartus II Help.
15
November 2012
Altera Corporation
16
Example 11 shows the way that the set_global_assignment Quartus II Tcl command
makes all global constraints and software settings, with set_location_assignment
constraining each I/O node in the design to a physical pin on the device.
However, after you initially create the Quartus II Settings File for your design, you
can export the contents to a procedural, executable Tcl (.tcl) file. You can then use that
generated script to restore certain settings after experimenting with other constraints.
You can also use the generated Tcl script to archive your assignments instead of
archiving the Quartus II Settings file itself.
17
To export your constraints as an executable Tcl script, on the Project menu, click
Generate Tcl File for Project. Example 12 shows the constraints in Example 11
converted to an executable Tcl script.
Example 12. Generated Tcl Script for a Quartus II Project (Part 1 of 2)
# Quartus II: Generate Tcl File for Project
# File: chiptrip.tcl
# Generated on: Tue Jun 08 13:08:48 2010
# Load Quartus II Tcl Project package
package require ::quartus::project
set need_to_close_project 0
set make_assignments 1
# Check that the right project is open
if {[is_project_open]} {
if {[string compare $quartus(project) "chiptrip"]} {
puts "Project chiptrip is not open"
set make_assignments 0
}
} else {
# Only open if not already open
if {[project_exists chiptrip]} {
project_open -revision chiptrip chiptrip
} else {
project_new -revision chiptrip chiptrip
}
set need_to_close_project 1
}
# Make assignments
if {$make_assignments} {
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F672C6
set_global_assignment -name TOP_LEVEL_ENTITY chiptrip
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:45:02 JUNE 08, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION 10.0
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING \
-section_id Top
November 2012
Altera Corporation
18
After setting initial values for variables to control constraint creation and whether or
not the project needs to be closed at the end of the script, the generated script checks
to see if a project is open. If a project is open but it is not the correct project, in this
case, chiptrip, the script prints Project chiptrip is not open to the console and
does nothing else.
If no project is open, the script determines if chiptrip exists in the current directory. If
the project exists, the script opens the project. If the project does not exist, the script
creates a new project and opens the project.
The script then creates the constraints. After creating the constraints, the script writes
the constraints to the Quartus II Settings File and then closes the project.
19
Similar to the constraints in the Quartus II Settings File, you can make the SDC
constraints in Example 13 part of an executable timing analysis script, as shown in
example Example 14.
Example 14. Tcl Script Making Basic Timing Constraints and Performing Mult-Corner Timing Analysis
project_open chiptrip
create_timing_netlist
#
# Create Constraints
#
create_clock -period 10.0 -waveform { 0 5.0 } clk2 -name clk2
create_clock -period 4.0 -waveform { 0 2.0 } clk1 -name clk1
# clk1 -> dir* : INPUT_MAX_DELAY = 1 ns
set_input_delay -max 1ns -clock clk1 [get_ports dir*]
# clk2 -> time* : OUTPUT_MAX_DELAY = -2 ns
set_output_delay -max -2ns -clock clk2 [get_ports time*]
#
# Perform timing analysis for several different sets of operating conditions
#
foreach_in_collection oc [get_available_operating_conditions] {
set_operating_conditions $oc
update_timing_netlist
report_timing -setup -npaths 1
report_timing -hold -npaths 1
report_timing -recovery -npaths 1
report_timing -removal -npaths 1
report_min_pulse_width -nworst 1
}
delete_timing_netlist
project_close
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The script in Example 14 opens the project, creates a timing netlist, then constrains
the two clocks in the design and applies input and output delay constraints. The clock
settings and delay constraints are identical to those in the .sdc file shown in
Example 13. The next section of the script updates the timing netlist for the
constraints and performs multi-corner timing analysis on the design.
Version
Changes
November 2012
12.1.0
June 2012
12.0.0
November 2011
10.0.2
Template update.
December 2010
10.0.1
Template update.
July 2010
10.0.0
Rewrote chapter to more broadly cover all design constraint methods. Removed procedural
steps and user interface details, and replaced with links to Quartus II Help.
November 2009
9.1.0
March 2009
Added section Probing to Source Design Files and Other Quartus II Windows on
page 12.
9.0.0
111
Version
Changes
November 2008
8.1.0
May 2008
8.0.0
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
November 2012
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112
2. Command-Line Scripting
June 2012
QII52002-12.0.0
QII52002-12.0.0
FPGA design software that easily integrates into your design flow saves time and
improves productivity. The Altera Quartus II software provides you with a
command-line executable for each step of the FPGA design flow to make the design
process customizable and flexible.
The benefits provided by command-line executables include:
Improved performance
The command-line executables are also completely interchangable with the Quartus II
GUI, allowing you to use the exact combination of tools that you prefer.
This chapter describes how to take advantage of Quartus II command-line
executables, and provides several examples of scripts that automate different
segments of the FPGA design flow. This chapter includes the following topics:
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Feedback Subscribe
22
Introductory Example
The following introduction to command-line executables demonstrates how to create
a project, fit the design, and generate programming files.
The tutorial design included with the Quartus II software is used to demonstrate this
functionality. If installed, the tutorial design is found in the
<Quartus II directory>/qdesigns/fir_filter directory.
Before making changes, copy the tutorial directory and type the four commands
shown in Example 21 at a command prompt in the new project directory.
1
filtref
filtref
filtref
filtref
23
This command starts the Quartus II Command-Line and Tcl API Help browser, a
viewer for information about the Quartus II Command-Line executables and Tcl API
(Figure 21).
June 2012
Altera Corporation
24
Use the -h option with any of the Quartus II Command-Line executables to get a
description and list of supported options. Use the --help=<option name> option for
detailed information about each option.
Figure 21. Quartus II Command-Line and Tcl API Help Browser
25
Option Precedence
If you use command-line executables, you must be aware of the precedence of various
project assignments and how to control the precedence. Assignments for a particular
project exist in the Quartus II Settings File (.qsf) for the project. Before the .qsf is
updated after assignment changes, the updated assignments are reflected in compiler
database files that hold intermediate compilation results..
All command-line options override any conflicting assignments found in the .qsf or
the compiler database files. There are two command-line options to specify whether
the .qsf or compiler database files take precedence for any assignments not specified
as command-line options.
1
The result of the last compilation, in the /db directory, which reflects the
assignments that existed when the project was compiled
Command-line options
Table 21 lists the precedence for reading assignments depending on the value of the
--read_settings_files option.
Table 21. Precedence for Reading Assignments
Option Specified
--read_settings_files = on
(Default)
--read_settings_files = off
June 2012
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26
Table 22 lists the locations to which assignments are written, depending on the value
of the --write_settings_files command-line option.
Table 22. Location for Writing Assignments
Option Specified
--write_settings_files = on (Default)
--write_settings_files = off
Compiler database
Example 23 assumes that a project named fir_filter exists, and that the analysis and
synthesis step has been performed (using the quartus_map executable).
Example 23. Write Settings Files
quartus_fit fir_filter --pack_register=off r
quartus_sta fir_filter r
mv fir_filter_sta.rpt fir_filter_1_sta.rpt r
quartus_fit fir_filter --pack_register=minimize_area
--write_settings_files=off r
quartus_sta fir_filter r
mv fir_filter_sta.rpt fir_filter_2_sta.rpt r
27
Analysis &
Synthesis
quartus_map
Design Assistant
quartus_drc
TimeQuest
Timing Analyzer
quartus_sta
Fitter
quartus_fit
Compiler Database
quartus_cdb
PowerPlay Power
Analyzer
quartus_pow
Assembler
quartus_asm
Programmer
quartus_pgm
Programming File
Converter
quartus_cpf
SignalTap II Logic
Analyzer
quartus_stp
Use the quartus_sh executable with the --flow option to perform a complete
compilation flow with a single command. The --flow option supports the smart
recompile feature and efficiently sets command-line arguments for each executable in
the flow.
The following example runs compilation, timing analysis, and programming file
generation with a single command:
quartus_sh --flow compile filtref r
June 2012
Altera Corporation
28
29
For example, a UNIX shell script could run other synthesis software, then
place-and-route the design in the Quartus II software, then generate output netlists
for other simulation software. Example 25 shows a script that synthesizes a design
with the Synopsys Synplify software, simulates the design using the Mentor Graphics
ModelSim software, and then compiles the design targeting a Cyclone III device.
Example 25. Script for End-to-End Flow
#!/bin/sh
# Run synthesis first.
# This example assumes you use Synplify software
synplify -batch synthesize.tcl
# If your Quartus II project exists already, you can just
# recompile the design.
# You can also use the script described in a later example to
# create a new project from scratch
quartus_sh --flow compile myproject
# Use the quartus_sta executable to do fast and slow-model
# timing analysis
quartus_sta myproject --model=slow
quartus_sta myproject --model=fast
# Use the quartus_eda executable to write out a gate-level
# Verilog simulation netlist for ModelSim
quartus_eda my_project --simulation --tool=modelsim --format=verilog
# Perform the simulation with the ModelSim software
vlib cycloneiii_ver
vlog -work cycloneiii_ver /opt/quartusii/eda/sim_lib/cycloneiii_atoms.v
vlib work
vlog -work work my_project.vo
vsim -L cycloneiii_ver -t 1ps work.my_project
Makefile Implementation
You can use the Quartus II command-line executables in conjunction with the make
utility to automatically update files when other files they depend on change. The file
dependencies and commands used to update files are specified in a text file called a
makefile.
To facilitate easier development of efficient makefiles, the following smart action
scripting command is provided with the Quartus II software:
quartus_sh --determine_smart_action r
Because assignments for a Quartus II project are stored in the .qsf, including it in
every rule results in unnecessary processing steps. For example, updating a setting
related to programming file generation, which requires re-running only quartus_asm,
modifies the .qsf, requiring a complete recompilation if the .qsf is included in every
rule.
The smart action command determines the earliest command-line executable in the
compilation flow that must be run based on the current .qsf, and generates a change
file corresponding to that executable. For example, if quartus_map must be re-run, the
smart action command creates or updates a file named map.chg. Thus, rather than
including the .qsf in each makefile rule, include only the appropriate change file.
June 2012
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210
Example 26 uses change files and the smart action command. You can copy and
modify it for your own use. A copy of this example is included in the help for the
makefile option, which is available by typing:
quartus_sh --help=makefiles r
= --family=Stratix
= --part=EP1S20F484C6
=
=
###################################################################
# Target implementations
###################################################################
STAMP = echo done >
$(PROJECT).map.rpt: map.chg $(SOURCE_FILES)
quartus_map $(MAP_ARGS) $(PROJECT)
$(STAMP) fit.chg
211
map.chg
fit.chg
sta.chg
asm.chg
A Tcl script is provided with the Quartus II software to create or modify files that are
specified as dependencies in the make rules, assisting you in makefile development.
Complete information about this Tcl script and how to integrate it with makefiles is
available by running the following command:
quartus_sh --help=determine_smart_action r
Creating output files (such as variation files, symbol files, and simulation netlist
files)
Each MegaWizard Plug-In provides a user interface for configuring the variation, and
performs validation and error checking of your selected ports and parameters. When
you create or update a variation with the GUI, the parameters and values are entered
through the GUI provided by the Plug-In. When you create a Plug-In variation with
the command line, you provide the parameters and values as command-line options.
Example 27 shows how to create a new variation file at a system command prompt.
Example 27. MegaWizard Plug-In Manager Command-Line Executable
qmegawiz [options] [module=<module name>|wizard=<wizard name>] [<param>=<value> ...
<port>=<used|unused> ...] [OPTIONAL_FILES=<optional files>] <variation file name>
When you use qmegawiz to update an existing variation file, the module or wizard
name is not required.
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Description
-silent
Run the MegaWizard Plug-In Manager in command-line mode, without displaying the
GUI.
-f:<param file>
A file that contains all options for the qmegawiz command. Refer to Parameter File on
page 216.
-p:<working directory>
Sets the default working directory. Refer toWorking Directory on page 217.
For information about specifying the module name or wizard name, refer to Module
and Wizard Names on page 213.
For information about specifying ports and parameters, refer to Ports and
Parameters on page 214.
For information about generating optional files, refer to Optional Files on
page 215.
For information about specifying the variation file name, refer to Variation File
Name on page 217.
Command-Line Support
Only the MegaWizard Plug-Ins listed in Table 24 support creation and update in
command-line mode. For Plug-Ins not listed in the table, you must use the
MegaWizard Plug-In Manager GUI for creation and updates.
Table 24. MegaWizard Plug-Ins with Command Line Support (Part 1 of 2)
MegaWizard Plug-In
Wizard Name
Module Name
alt2gxb
ALT2GXB
alt2gxb
alt4gxb
ALTGX
alt4gxb
ALTASMI_PARALLEL
altasmi_parallel
ALTCLKCTRL
altclkctrl
ALTDDIO_BIDIR
altddio_bidir
altddio_in
ALTDDIO_IN
altddio_in
altddio_out
ALTDDIO_OUT
altasmi_parallel
altclkctrl
altddio_bidir
altecc_decoder
altecc_encoder
altfp_abs
ALTECC
ALTFP_ABS
altddio_out
altecc_decoder
altecc_encoder
altfp_abs
213
Wizard Name
Module Name
ALTFP_ADD_SUB
altfp_add_sub
ALTFP_ATAN
altfp_atan
altfp_compare
ALTFP_COMPARE
altfp_compare
altfp_convert
ALTFP_CONVERT
altfp_convert
altfp_div
ALTFP_DIV
altfp_div
altfp_exp
ALTFP_EXP
altfp_exp
ALTFP_INV_SQRT
altfp_inv_sqrt
altfp_inv
ALTFP_INV
altfp_inv
altfp_log
ALTFP_LOG
altfp_log
ALTFP_MATRIX_INV
altfp_matrix_inv
ALTFP_MATRIX_MULT
altfp_matrix_mult
ALTFP_MULT
altfp_mult
ALTFP_SINCOS
altfp_sincos
ALTFP_SQRT
altfp_sqrt
altfp_add_sub
altfp_atan
altfp_inv_sqrt
altfp_matrix_inv
altfp_matrix_mult
altfp_mult
altfp_sincos
altfp_sqrt
altiobuf_bidir
altiobuf_in
altiobuf_bidir
ALTIOBUF
altiobuf_in
altiobuf_out
altlvds_rx
altlvds_tx
altmult_accum
altmult_complex
altotp
altpll_reconfig
altpll
altremote_update
altshift_taps
altiobuf_out
altlvds_rx
ALTLVDS
altlvds_tx
ALTMULT_ACCUM (MAC)
altmult_accum
ALTMULT_COMPLEX
altmult_complex
ALTOTP
altotp
ALTPLL_RECONFIG
altpll_reconfig
ALTPLL
altpll
ALTREMOTE_UPDATE
altremote_update
ALTSHIFT_TAPS
altshift_taps
RAM: 2-PORT
altsyncram
RAM: 1-PORT
altsyncram
ROM: 1-PORT
alttemp_sense
alt_c3gxb
dcfifo
scfifo
ALTTEMP_SENSE
alttemp_sense
ALT_C3GXB
alt_c3gxb
FIFO
dcfifo
scfifo
June 2012
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wizard="RAM: 2-PORT"
When there is a one-to-one mapping between the MegaWizard Plug-In, the wizard
name, and the module name, you can use either the wizard option or the module
option.
When there are multiple wizard names that correspond to one module name, use the
wizard option to specify one wizard. For example, use the wizard option if you create
a RAM, because one module is common to three wizards.
When there are multiple module names that correspond to one wizard name, use the
module option to specify one module. For example, use the module option if you
create a FIFO because one wizard is common to both modules.
If you edit or update an existing variation file, the wizard or module option is not
necessary, because information about the wizard or module is already in the variation
file.
You can specify port names in any order. Grouping does not matter. Separate port
configuration options from each other with spaces.
Specify a value for a parameter with the equal sign, for example:
<parameter>=<value>
You can specify parameters in any order. Grouping does not matter. Separate
parameter configuration options from each other with spaces. You can specify port
names and parameter names in upper or lower case; case does not matter.
All MegaWizard Plug-Ins allow you to specify the target device family with the
INTENDED_DEVICE_FAMILY parameter, as shown in the following example:
qmegawiz wizard=<wizard> INTENDED_DEVICE_FAMILY="Cyclone III" <file>
You must specify enough ports and parameters to create a legal configuration of the
Plug-In. When you use the GUI flow, each MegaWizard Plug-In performs validation
and error checking for the particular ports and parameters you choose. When you use
command-line options to specify ports and parameters, you must ensure that the
ports and parameters you use are complete for your particular configuration.
For example, when you use a RAM Plug-In to configure a RAM to be 32 words deep,
the Plug-In automatically configures an address port that is five bits wide. If you use
the command-line flow to configure a RAM that is 32 words deep, you must use one
option to specify the depth of the RAM, then calculate the width of the address port
and specify that width with another option.
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Invalid Configurations
If the combination of default and specified ports and parameters is not complete to
create a legal configuration of the Plug-In, qmegawiz generates an error message that
indicates what is missing and what values are supported. If the combination of
default and specified ports and parameters results in an illegal configuration of the
Plug-In, qmegawiz generates an error message that indicates what is illegal, and
displays the legal values.
Optional Files
In addition to the variation file, the MegaWizard Plug-In Manager can generate other
files, such as instantiation templates, simulation netlists, and symbols for graphic
design entry. Use the OPTIONAL_FILES parameter to control whether the MegaWizard
Plug-In Manager generates optional files. Table 25 lists valid arguments for the
OPTIONAL_FILES parameter.
Table 25. Arguments for the OPTIONAL_FILES Parameter
Argument
Description
INST
INC
CMP
BSF
BB
SIM_NETLIST
Controls the generation of the simulation netlist file, wherever there is wizard support.
SYNTH_NETLIST
Controls the generation of the synthesis netlist file, wherever there is wizard support.
ALL
NONE
Specify multiple optional files separated by a vertical bar character, for example:
OPTIONAL_FILES=<argument 1>|...|<argument n>
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If you prefix an argument with a dash (for example, -BB), it is excluded from the
generated optional files. If any of the optional files exist when you run qmegawiz and
they are excluded in the OPTIONAL_FILES parameter (with the NONE argument, or
prefixed with a dash), they are deleted.
You can combine the ALL argument with other excluded arguments to generate all
files except <excluded files>. You can combine the NONE argument with other included
arguments to generate no files except <files>.
When you combine multiple arguments, they are processed from left to right, and
arguments evaluated later have precedence over arguments evaluated earlier.
Therefore, use the ALL or NONE arguments first in a series of multiple arguments. When
ALL is the first argument, all optional files are generated before exclusions are
processed (deleted). When NONE is the first argument, none of the optional files are
generated (in other words, any that exist are deleted), then any files you subsequently
specify are generated.
Table 26 shows examples for the OPTIONAL_FILES parameter and describes the result
of each example.
Table 26. Examples of Different Optional File Arguments
Example Values for
OPTIONAL_FILES
Description
BB
The optional file <variation>_bb.v is generated, and no optional files are deleted
BB|INST
The optional file <variation>_bb.v is generated, then the optional file <variation>_inst.v is
generated, and no optional files are deleted.
NONE
No optional files are generated, and any existing optional files are deleted.
NONE|INC|BSF
Any existing optional files are deleted, then the optional file <variation>.inc is generated, then
the optional file <variation>.bsf is generated.
ALL|-INST
-BB
-BB|INST
The optional file <variation>_bb.v is deleted if it exists, then the optional file <variation>_inst.v
is generated.
The qmegawiz command accepts the ALL argument combined with other included file
arguments, for example, ALL|BB, but that combination is equivalent to ALL because
first all optional files are generated, and then the file <variation>_bb.v is generated a
second time. Additionally, the software accepts the NONE argument combined with
other excluded file arguments, for example, NONE|-BB, but that combination is
equivalent to NONE because no optional files are generated, any that exist are deleted,
and then the file <variation>_bb.v is deleted if it exists.
Parameter File
You can put all parameter values and port values in a file, and pass the file name as an
argument to qmegawiz with the -f:<parameter file> option. For example, the following
command specifies a parameter file named rom_params.txt:
qmegawiz -silent module=altsyncram -f:rom_params.txt myrom.v r
The rom_params.txt parameter file can include options similar to the following:
217
Working Directory
You can change the working directory that qmegawiz uses when it generates files. By
default, the working directory is the current directory when you execute the qmegawiz
command. Use the -p option to specify a different working directory, for example:
-p:<working directory>
You can specify the working directory with an absolute or relative path. Specify an
alternative working directory any time you do not want files generated in the current
directory. The alternative working directory can be useful if you generate multiple
variations in a batch script, and keep generated files for the different Plug-In
variations in separate directories.
1
If you use the -f option and the -p option together, the MegaWizard Plug-In Manager
sources the parameter file in a directory specified with the -p option, or in a directory
relative to that directory. For example, if you specify C:\project\work with the -p
option and work\params.txt with the -f option, the MegaWizard Plug-In Manager
attempts to source the file params.txt in C:\project\work\work.
Verilog HDL
.v
VHDL
.vhd
AHDL
.tdf
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Example 28 creates a project with a Tcl script and applies project constraints using
the tutorial design files in the <Quartus II installation directory>/qdesigns/fir_filter/
directory.
Example 28. Tcl Script to Create Project and Apply Constraints
project_new filtref -overwrite
# Assign family, device, and top-level file
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C12F256C6
set_global_assignment -name BDF_FILE filtref.bdf
# Assign pins
set_location_assignment -to clk Pin_28
set_location_assignment -to clkx2 Pin_29
set_location_assignment -to d[0] Pin_139
set_location_assignment -to d[1] Pin_140
# Other assignments could follow
project_close
Save the script in a file called setup_proj.tcl and type the commands illustrated in
Example 29 at a command prompt to create the design, apply constraints, compile
the design, and perform fast-corner and slow-corner timing analysis. Timing analysis
results are saved in two files, filtref_sta_1.rpt and filtref_sta_2.rpt.
Example 29. Script to Create and Compile a Project
quartus_sh -t setup_proj.tcl r
quartus_map filtref r
quartus_fit filtref r
quartus_asm filtref r
quartus_sta filtref --model=fast --export_settings=off r
mv filtref_sta.rpt filtref_sta_1.rpt r
quartus_sta filtref --export_settings=off r
mv filtref_sta.rpt filtref_sta_2.rpt r
Type the following commands to create the design, apply constraints, and compile the
design, without performing timing analysis:
quartus_sh -t setup_proj.tcl r
quartus_sh --flow compile filtref r
219
When options are not specified, the executable uses the project database values. If not
specified in the project database, the executable uses the Quartus II software default
values. For example, the fir_filter project is set to target the Cyclone device family, so
it is not necessary to specify the --family option.
Example 210. Shell Script to Check Design File Syntax
#!/bin/sh
FILES_WITH_ERRORS=""
# Iterate over each file with a .bdf or .v extension
for filename in `ls *.bdf *.v`
do
# Perform a syntax check on the specified file
quartus_map fir_filter --analyze_file=$filename
# If the exit code is non-zero, the file has a syntax error
if [ $? -ne 0 ]
then
FILES_WITH_ERRORS="$FILES_WITH_ERRORS $filename"
fi
done
if [ -z "$FILES_WITH_ERRORS" ]
then
echo "All files passed the syntax check"
exit 0
else
echo "There were syntax errors in the following file(s)"
echo $FILES_WITH_ERRORS
exit 1
fi
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The archive file is automatically named <project name>.qar. If you want to use a
different name, type the command with the -output option as shown in example
Example 213.
Example 213. Archiving a Project
quartus_sh --archive <project name> -output <filename> r
To restore a project archive, type the command shown in Example 214 at a command
prompt.
Example 214. Restoring a Project Archive
quartus_sh --restore <archive name> r
The command restores the project archive to the current directory and overwrites
existing files.
f For more information about archiving and restoring projects, refer to the Managing
Quartus II Projects chapter in volume 2 of the Quartus II Handbook.
221
Example 217 shows the commands for a DOS batch file for this example. With a DOS
batch file, you can specify the project name and the revision name once for both
commands. To create the DOS batch file, paste the following lines into a file called
update_memory.bat.
Example 217. Batch file to Update Memory Contents Without Recompiling
quartus_cdb --update_mif %1 --rev=%2
quartus_asm %1 --rev=%2
To run the batch file, type the following command at a command prompt:
update_memory.bat <project name> <revision name> r
This interactive command guides you through some questions, then creates an option
file based on your answers. Use --option to cause quartus_cpf to use the option file.
For example, the following command creates a compressed .pof that targets an
EPCS64 device:
quartus_cpf --convert --option=<filename>.opt --device=EPCS64 <file>.sof <file>.pof r
Alternatively, you can use the Convert Programming Files utility in the Quartus II
software GUI to create a Conversion Setup File (.cof). Configure any options you
want, including compression, then save the conversion setup. Use the following
command to run the conversion setup you specified.
quartus_cpf --convert <file>.cof r
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To attempt to fit the project called top as quickly as possible, type the command
shown in Example 218 at a command prompt.
Example 218. Fitting a Project Quickly
quartus_fit top --effort=fast --one_fit_attempt=on r
223
Use the Design Space Explorer (DSE) included with the Quartus II software script (by
typing quartus_sh --dse r at a command prompt) to improve design performance
by performing automated seed sweeping.
h For more information about the DSE, type quartus_sh --help=dse r at a command
prompt, or refer to Design Space Explorer in Quartus II Help.
If your design flow incorporates parameter files, those can be included in the
qmegawiz call in the same way you would include them from a command prompt:
qexec qmegawiz -silent -f:<parameter file>.txt <variation file name>
h For more information about the ::quartus::report Tcl package, refer to ::quartus::report
in Quartus II Help.
f For more information about the Quartus II Tcl scripting API, refer to the Tcl Scripting
chapter in volume 2 of the Quartus II Handbook.
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quartus_asm (Assembler)
Version
Changes
June 2012
12.0.0
November 2011
11.0.1
Template update.
May 2011
11.0.0
December 2010
10.1.0
July 2010
10.0.0
Updated script examples to use quartus_sta instead of quartus_tan, and other minor
updates throughout document.
November 2009
9.1.0
Updated Table 21 to add quartus_jli and quartus_jbcc executables and descriptions, and
other minor updates throughout document.
March 2009
9.0.0
No change to content.
225
Version
Changes
Added the following sections:
November 2008
May 2008
8.1.0
8.0.0
Changed Example 21, Example 22, Example 24, and Example 27 to use the
EP1C12F256C6 device
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
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3. Tcl Scripting
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QII52003-12.0.0
Introduction
Developing and running Tcl scripts to control the Altera Quartus II software allows
you to perform a wide range of functions, such as compiling a design or writing
procedures to automate common tasks.
You can use Tcl scripts to manage a Quartus II project, make assignments, define
design constraints, make device assignments, compile your design, perform timing
analysis, and access reports. Tcl scripts also facilitate project or assignment migration.
For example, when designing in different projects with the same prototype or
development board, you can automate reassignment of pin locations in each new
project. The Quartus II software can also generate a Tcl script based on all the current
assignments in the project, which aids in switching assignments to another project.
The Quartus II software Tcl commands follow the EDA industry Tcl application
programming interface (API) standards for command-line options. This simplifies
learning and using Tcl commands. If you encounter an error with a command
argument, the Tcl interpreter includes help information showing correct usage.
This chapter includes sample Tcl scripts for automating the Quartus II software. You
can modify these example scripts for use with your own designs. You can find more
Tcl scripts in the Design Examples section of the Support area on the Altera website.
This chapter includes the following topics:
Reporting on page 39
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
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32
Package Description
backannotate
chip_planner
Identify and modify resource usage and routing with the Chip Editor
database_manager
device
flow
incremental compilation
Manipulate design partitions and LogicLock regions, and settings related to incremental
compilation
insystem_memory_edit
insystem_source_probe
interact with the In-System Sources and Probes tool in an Altera device
jtag
logic_analyzer_interface
Query and modify the logic analyzer interface output pin state
misc
Perform miscellaneous tasks such as enabling natural bus naming, package loading, and
message posting
project
Create and manage projects and revisions, make any project assignments including timing
assignments
rapid_recompile
report
33
Package Description
rtl
sdc
sdc_ext
simulator
sta
Contains the set of Tcl functions for obtaining advanced information from the Quartus II
TimeQuest Timing Analyzer
stp
By default, only the minimum number of packages is loaded automatically with each
Quartus II executable. This keeps the memory requirement for each executable as low
as possible. Because the minimum number of packages is automatically loaded, you
must load other packages before you can run commands in those packages.
Because different packages are available in different executables, you must run your
scripts with executables that include the packages you use in the scripts. For example,
if you use commands in the sdc_ext package, you must use the quartus_sta
executable to run the script because the quartus_sta executable is the only one with
support for the sdc_ext package.
The following command prints lists of the packages loaded or available to load for an
executable, to the console:
<executable name> --tcl_eval help r
For example, type the following command to list the packages loaded or available to
load by the quartus_fit executable:
quartus_fit --tcl_eval help r
Loading Packages
To load a Quartus II Tcl package, use the load_package command as follows:
load_package [-version <version number>] <package name>
This command is similar to the package require Tcl command (described in Table 32
on page 34), but you can easily alternate between different versions of a Quartus II
Tcl package with the load_package command because of the -version option.
f For additional information about these and other Quartus II command-line
executables, refer to the Command-Line Scripting chapter in volume 2 of the Quartus II
Handbook.
This command runs the Quartus II Command-Line and Tcl API help browser, which
documents all commands and options in the Quartus II Tcl API.
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Quartus II Tcl help allows easy access to information about the Quartus II Tcl
commands. To access the help information, type help at a Tcl prompt, as shown in
Example 31.
Example 31. Help Output
tcl> help
--------------------------------------------------------------------------------------------------------Available Quartus II Tcl Packages:
---------------------------------Loaded
---------------------------::quartus::misc
::quartus::old_api
::quartus::project
::quartus::timing_assignment
::quartus::timing_report
Not Loaded
----------------------::quartus::device
::quartus::backannotate
::quartus::flow
::quartus::logiclock
::quartus::report
Description
help
To view a list of available Quartus II Tcl packages, loaded and not loaded.
help -tcl
To view a list of commands used to load Tcl packages and access command-line
help.
To view help for a specified Quartus II package that includes the list of available
Tcl commands. For convenience, you can omit the ::quartus:: package prefix,
and type help -pkg <package name> r.
If you do not specify the -version option, help for the currently loaded package
is displayed by default. If the package for which you want help is not loaded, help
for the latest version of the package is displayed by default.
Examples:
help -pkg ::quartus::project r
help -pkg project r
help -pkg project -version 1.0 r
<command_name> -h
or
<command_name> -help
To view short help for a Quartus II Tcl command for which the package is loaded.
Examples:
project_open -h r
project_open -help r
35
Table 32. Help Options Available in the Quartus II Tcl Environment (Part 2 of 2)
Help Command
Description
To load a Quartus II Tcl package with the specified version. If <version> is not
specified, the latest version of the package is loaded by default.
Example:
package require ::quartus::project 1.0 r
This command is similar to the load_package command.
package require
::quartus::<package name>
[<version>]
The advantage of the load_package command is that you can alternate freely
between different versions of the same package.
Type load_package <package name> [-version <version number>]r to
load a Quartus II Tcl package with the specified version. If the -version option is
not specified, the latest version of the package is loaded by default.
Example:
load_package ::quartus::project -version 1.0 r
To view complete help text for a Quartus II Tcl command.
If you do not specify the -version option, help for the command in the currently
loaded package version is displayed by default.
If the package version for which you want help is not loaded, help for the latest
version of the package is displayed by default.
Examples:
<command_name> -long_help
project_open -long_help r
help -cmd project_open r
help -cmd project_open -version 1.0 r
help -examples
help -quartus
To view help on the predefined global Tcl array that contains project information
and information about the Quartus II executable that is currently running.
quartus_sh --qhelp
To launch the Tk viewer for Quartus II command-line help and display help for the
command-line executables and Tcl API packages.
For more information about this utility, refer to the Command-Line Scripting
chapter in volume 2 of the Quartus II Handbook.
h The Tcl API help is also available in Quartus II online help. Search for the command or
package name to find details about that command or package.
Description
Run the specified Tcl script with optional arguments. The -t option is
the short form of the --script option.
--shell
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Description
-s
Open the executable in the interactive Tcl shell mode. The -s option is
the short form of the --shell option.
Evaluate as Tcl
Running an executable with the --tcl_eval option causes the executable to
immediately evaluate the remaining command-line arguments as Tcl commands. This
can be useful if you want to run simple Tcl commands from other scripting languages.
For example, the following command runs the Tcl command that prints out the
commands available in the project package.
quartus_sh --tcl_eval help -pkg project r
37
Some shell commands such as cd, ls, and others can be run in the Tcl Console
window, with the Tcl exec command. However, for best results, run shell commands
and Quartus II executables from a system command prompt outside of the Quartus II
software GUI.
Tcl messages appear in the System tab (Messages window). Errors and messages
written to stdout and stderr also are shown in the Quartus II Tcl Console window.
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f Refer to Interactive Shell Mode on page 36 for information about sourcing a script.
Scripting information for all Quartus II project settings and assignments is located in
the QSF Reference Manual. Refer to the Constraining Designs chapter in volume 2 of the
Quartus II Handbook for more information on making assignments.
Example 32 shows how to create a project, make assignments, and compile the
project. It uses the fir_filter tutorial design files in the qdesigns installation directory.
Run this script in the fir_filter directory, with the quartus_sh executable.
Example 32. Create and Compile a Project
load_package flow
# Create the project and overwrite any settings
# files that exist
project_new fir_filter -revision filtref -overwrite
# Set the device, the name of the top-level BDF,
# and the name of the top level entity
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C6F256C6
set_global_assignment -name BDF_FILE filtref.bdf
set_global_assignment -name TOP_LEVEL_ENTITY filtref
# Add other pin assignments here
set_location_assignment -to clk Pin_G1
# compile the project
execute_flow -compile
project_close
The assignments created or modified while a project is open are not committed to the
Quartus II Settings File (.qsf) unless you explicitly call export_assignments or
project_close (unless -dont_export_assignments is specified). In some cases, such
as when running execute_flow, the Quartus II software automatically commits the
changes.
f For information about scripted design flows for HardCopy II designs, refer to the
Script-Based Design for HardCopy II Devices chapter of the HardCopy Handbook. A
separate chapter in the HardCopy Handbook called Timing Constraints for HardCopy II
Devices also contains information about script-based design for HardCopy II devices,
with an emphasis on timing constraints.
Compiling Designs
You can run the Quartus II command-line executables from Tcl scripts. Use the
included flow package to run various Quartus II compilation flows, or run each
executable directly.
39
Reporting
It is sometimes necessary to extract information from the Compilation Report to
evaluate results. The Quartus II Tcl API provides easy access to report data so you do
not have to write scripts to parse the text report files.
If you know the exact cell or cells you want to access, use the get_report_panel_data
command and specify the row and column names (or x and y coordinates) and the
name of the appropriate report panel. You can often search for data in a report panel.
To do this, use a loop that reads the report one row at a time with the
get_report_panel_row command.
Column headings in report panels are in row 0. If you use a loop that reads the report
one row at a time, you can start with row 1 to skip the row with column headings. The
get_number_of_rows command returns the number of rows in the report panel,
including the column heading row. Because the number of rows includes the column
heading row, continue your loop as long as the loop index is less than the number of
rows.
Report panels are hierarchically arranged and each level of hierarchy is denoted by
the string || in the panel name. For example, the name of the Fitter Settings report
panel is Fitter||Fitter Settings because it is in the Fitter folder. Panels at the
highest hierarchy level do not use the || string. For example, the Flow Settings
report panel is named Flow Settings.
The code in Example 34 prints a list of all report panel names in your project. You can
run this code with any executable that includes support for the report package.
Example 34. Print All Report Panel Names
load_package report
project_open myproject
load_report
set panel_names [get_report_panel_names]
foreach panel_name $panel_names {
post_message "$panel_name"
}
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Timing Analysis
The Quartus II TimeQuest Timing Analyzer includes support for industry-standard
SDC commands in the sdc package. The Quartus II software also includes
comprehensive Tcl APIs and SDC extensions for the TimeQuest Timing Analyzer in
the sta, and sdc_ext packages.
f Refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II
Handbook for detailed information about how to perform timing analysis with the
Quartus II TimeQuest Timing Analyzer.
311
A module is another term for a Quartus II executable that performs one step in a flow.
For example, two modules are Analysis and Synthesis (quartus_map), and timing
analysis (quartus_sta).
A flow is a series of modules that the Quartus II software runs with predefined
options. For example, compiling a design is a flow that typically consists of the
following steps (performed by the indicated module):
1. Analysis and synthesis (quartus_map)
2. Fitter (quartus_fit)
3. Assembler (quartus_asm)
4. Timing Analyzer (quartus_sta)
Other flows are described in the help for the execute_flow Tcl command. In addition,
many commands in the Processing menu of the Quartus II GUI correspond to this
design flow.
To make an assignment automatically run a script, add an assignment with the
following form to the .qsf for your project:
set_global_assignment -name <assignment name> <executable>:<script
name>
The first argument passed in the argv variable (or quartus(args) variable) is the
name of the flow or module being executed, depending on the assignment you use.
The second argument is the name of the project and the third argument is the name of
the revision.
When you use the POST_MODULE_SCRIPT_FILE assignment, the specified script is
automatically run after every executable in a flow. You can use a string comparison
with the module name (the first argument passed in to the script) to isolate script
processing to certain modules.
Execution Example
Example 37 illustrates how automatic script execution works in a complete flow,
assuming you have a project called top with a current revision called rev_1, and you
have the following assignments in the .qsf for your project.
Example 37.
set_global_assignment -name PRE_FLOW_SCRIPT_FILE quartus_sh:first.tcl
set_global_assignment -name POST_MODULE_SCRIPT_FILE quartus_sh:next.tcl
set_global_assignment -name POST_FLOW_SCRIPT_FILE quartus_sh:last.tcl
When you compile your project, the PRE_FLOW_SCRIPT_FILE assignment causes the
following command to be run before compilation begins:
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Controlling Processing
The POST_MODULE_SCRIPT_FILE assignment causes a script to run after every module.
Because the same script is run after every module, you might have to include some
conditional statements that restrict processing in your script to certain modules.
For example, if you want a script to run only after timing analysis, use a conditional
test like the one shown in Example 38. It checks the flow or module name passed as
the first argument to the script and executes code when the module is quartus_sta.
Example 38. Restrict Processing to a Single Module
set module [lindex $quartus(args) 0]
if [string match "quartus_sta" $module] {
# Include commands here that are run
# after timing analysis
# Use the post-message command to display
# messages
post_message "Running after timing analysis"
}
Displaying Messages
Because of the way the Quartus II software runs the scripts automatically, you must
use the post_message command to display messages, instead of the puts command.
This requirement applies only to scripts that are run by the three assignments listed in
Automating Script Execution on page 310.
1
Refer to The post_message Command on page 314 for more information about this
command.
313
The Quartus II software defaults to natural bus naming. You can turn off natural bus
naming with the disable_natural_bus_naming command. For more information
about natural bus naming, type the following at a Quartus II Tcl prompt:
enable_natural_bus_naming -h r
Collection Commands
Some Quartus II Tcl functions return very large sets of data that would be inefficient
as Tcl lists. These data structures are referred to as collections. The Quartus II Tcl API
uses a collection ID to access the collection. There are two Quartus II Tcl commands
for working with collections, foreach_in_collection and get_collection_size. Use
the set command to assign a collection ID to a variable.
h For information about which Quartus II Tcl commands return collection IDs, refer to
foreach_in_collection in Quartus II Help.
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info (default)
extra_info
warning
critical_warning
error
315
If you copy the script in the previous example to a file named print_args.tcl, it
displays the following output when you type the command shown in Example 314
at a command prompt.
Example 314. Passing Command-Line Arguments to Scripts
quartus_sh -t print_args.tcl my_project 100MHz r
The value at index 0 is my_project
The value at index 1 is 100MHz
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If you save those commands in a Tcl script called print_cmd_args.tcl you see the
following output when you type the command shown in Example 316 at a command
prompt.
Example 316. Passing Command-Line Arguments for Scripts
quartus_sh -t print_cmd_args.tcl -project my_project -frequency 100MHz r
The project name is my_project
The frequency is 100MHz
Virtually all Quartus II Tcl scripts must open a project. Example 317 opens a project,
and you can optionally specify a revision name. The example checks whether the
specified project exists. If it does, the example opens the current revision, or the
revision you specify.
Example 317. Full-Featured Method to Open Projects
package require cmdline
variable ::argv0 $::quartus(args)
set options { \
{ "project.arg" "" "Project Name" } \
{ "revision.arg" "" "Revision Name" } \
}
array set optshash [::cmdline::getoptions ::argv0 $options]
# Ensure the project exists before trying to open it
if {[project_exists $optshash(project)]} {
if {[string equal "" $optshash(revision)]} {
# There is no revision name specified, so default
# to the current revision
project_open $optshash(project) -current_revision
} else {
# There is a revision name specified, so open the
# project with that revision
project_open $optshash(project) -revision \
$optshash(revision)
}
} else {
puts "Project $optshash(project) does not exist"
exit 1
}
# The rest of your script goes here
If you do not require this flexibility or error checking, you can use just the
project_open command, as shown in Example 318.
Example 318. Simple Method to Open Projects
set proj_name [lindex $argv 0]
project_open $proj_name
317
Create a new project called fir_filter, with a revision called filtref by typing the
following command at a Tcl prompt:
project_new -revision filtref fir_filter r
If the project file and project name are the same, the Quartus II software gives the
revision the same name as the project.
Because the revision named filtref matches the top-level file, all design files are
automatically picked up from the hierarchy tree.
Next, set a global assignment for the device with the following command:
set_global_assignment -name family Cyclone r
h To learn more about assignment names that you can use with the -name option, refer
to Quartus II Help.
1
For assignment values that contain spaces, enclose the value in quotation marks.
To quickly compile a design, use the ::quartus::flow package, which properly
exports the new project assignments and compiles the design with the proper
sequence of the command-line executables. First, load the package:
load_package flow r
To perform a full compilation of the FIR filter design, use the execute_flow command
with the -compile option:
exectue_flow -compile r
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This command compiles the FIR filter tutorial project, exporting the project
assignments and running quartus_map, quartus_fit, quartus_asm, and quartus_sta.
This sequence of events is the same as selecting Start Compilation from the
Processing menu in the Quartus II GUI.
When you are finished with a project, close it with the project_close command as
shown in Example 319.
Example 319.
project_close r
Use double quotation marks to group the words hello and world as one argument.
Double quotation marks allow substitutions to occur in the group. Substitutions can
be simple variable substitutions, or the result of running a nested command,
described in Substitutions on page 319. Use curly braces {} for grouping when you
want to prevent substitutions.
319
Variables
Assign a value to a variable with the set command. You do not have to declare a
variable before using it. Tcl variable names are case-sensitive. Example 320 assigns
the value 1 to the variable named a.
Example 320. Assigning Variables
set a 1
To access the contents of a variable, use a dollar sign ($) before the variable name.
Example 321 prints "Hello world" in a different way.
Example 321. Accessing Variables
set a Hello
set b world
puts "$a $b"
Substitutions
Tcl performs three types of substitution:
Backslash substitution
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Backlash Substitution
Backslash substitution allows you to quote reserved characters in Tcl, such as dollar
signs ($) and braces ([ ]). You can also specify other special ASCII characters like
tabs and new lines with backslash substitutions. The backslash character is the Tcl line
continuation character, used when a Tcl command wraps to more than one line.
Example 323 shows how to use the backslash character for line continuation.
Example 323. Backslash Substitution
set this_is_a_long_variable_name [string length "Hello \
world."]
Arithmetic
Use the expr command to perform arithmetic calculations. Use curly braces ({ }) to
group the arguments of this command for greater efficiency and numeric precision.
Example 324 sets b to the sum of the value in the variable a and the square root of 2.
Example 324. Arithmetic with the expr Command
set a 5
set b [expr { $a + sqrt(2) }]
Tcl also supports boolean operators such as && (AND), || (OR), ! (NOT), and
comparison operators such as < (less than), > (greater than), and == (equal to).
Lists
A Tcl list is a series of values. Supported list operations include creating lists,
appending lists, extracting list elements, computing the length of a list, sorting a list,
and more. Example 325 sets a to a list with three numbers in it.
Example 325. Creating Simple Lists
set a { 1 2 3 }
You can use the lindex command to extract information at a specific index in a list.
Indexes are zero-based. You can use the index end to specify the last element in the
list, or the index end-<n> to count from the end of the list. Example 326 prints the
second element (at index 1) in the list stored in a.
Example 326. Accessing List Elements
puts [lindex $a 1]
The llength command returns the length of a list. Example 327 prints the length of
the list stored in a.
Example 327. List Length
puts [llength $a]
321
The lappend command appends elements to a list. If a list does not already exist, the
list you specify is created. The list variable name is not specified with a dollar sign
($). Example 328 appends some elements to the list stored in a.
Example 328. Appending to a List
lappend a 4 5 6
Arrays
Arrays are similar to lists except that they use a string-based index. Tcl arrays are
implemented as hash tables. You can create arrays by setting each element
individually or with the array set command. To set an element with an index of Mon
to a value of Monday in an array called days, use the following command:
set days(Mon) Monday
The array set command requires a list of index/value pairs. This example sets the
array called days:
array set days { Sun Sunday Mon Monday Tue Tuesday \
Wed Wednesday Thu Thursday Fri Friday Sat Saturday }
Example 329 shows how to access the value for a particular index.
Example 329. Accessing Array Elements
set day_abbreviation Mon
puts $days($day_abbreviation)
Use the array names command to get a list of all the indexes in a particular array. The
index values are not returned in any specified order. Example 330 shows one way to
iterate over all the values in an array.
Example 330. Iterating Over Arrays
foreach day [array names days] {
puts "The abbreviation $day corresponds to the day \
name $days($day)"
}
Arrays are a very flexible way of storing information in a Tcl script and are a good
way to build complex data structures.
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Control Structures
Tcl supports common control structures, including if-then-else conditions and for,
foreach, and while loops. The position of the curly braces as shown in the following
examples ensures the control structure commands are executed efficiently and
correctly. Example 331 prints whether the value of variable a positive, negative, or
zero.
Example 331. If-Then-Else Structure
if { $a > 0 } {
puts "The value is positive"
} elseif { $a < 0 } {
puts "The value is negative"
} else {
puts "The value is zero"
}
1 2 3 }
$i < [llength $a] } {
"The list element at index $i is [lindex $a $i]"
i
You do not have to use the expr command in boolean expressions in control structure
commands because they invoke the expr command automatically.
323
Procedures
Use the proc command to define a Tcl procedure (known as a subroutine or function
in other scripting and programming languages). The scope of variables in a procedure
is local to the procedure. If the procedure returns a value, use the return command to
return the value from the procedure. Example 335 defines a procedure that
multiplies two numbers and returns the result.
Example 335. Simple Procedure
proc multiply { x y } {
set product [expr { $x * $y }]
return $product
}
Example 336 shows how to use the multiply procedure in your code. You must
define a procedure before your script calls it.
Example 336. Using a Procedure
proc multiply { x y } {
set product [expr { $x * $y }]
return $product
}
set a 1
set b 2
puts [multiply $a $b]
Define procedures near the beginning of a script. If you want to access global
variables in a procedure, use the global command in each procedure that uses a
global variable. Example 337 defines a procedure that prints an element in a global
list of numbers, then calls the procedure.
Example 337. Accessing Global Variables
proc print_global_list_element { i } {
global my_data
puts "The list element at index $i is [lindex $my_data $i]"
}
set my_data { 1 2 3}
print_global_list_element 0
File I/O
Tcl includes commands to read from and write to files. You must open a file before
you can read from or write to it, and close it when the read and write operations are
done. To open a file, use the open command; to close a file, use the close command.
When you open a file, specify its name and the mode in which to open it. If you do not
specify a mode, Tcl defaults to read mode. To write to a file, specify w for write mode
as shown in Example 338.
Example 338. Open a File for Writing
set output [open myfile.txt w]
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Tcl supports other modes, including appending to existing files and reading from and
writing to the same file.
The open command returns a file handle to use for read or write access. You can use
the puts command to write to a file by specifying a filehandle, as shown in
Example 339.
Example 339. Write to a File
set output [open myfile.txt w]
puts $output "This text is written to the file."
close $output
You can read a file one line at a time with the gets command. Example 340 uses the
gets command to read each line of the file and then prints it out with its line number.
Example 340. Read from a File
set input [open myfile.txt]
set line_num 1
while { [gets $input line] >= 0 } {
# Process the line of text here
puts "$line_num: $line"
incr line_num
}
close $input
Without the semicolon, it would be an invalid command because the set command
would not terminate until the new line after the comment.
The Tcl interpreter counts curly braces inside comments, which can lead to errors that
are difficult to track down. Example 342 causes an error because of unbalanced curly
braces.
Example 342. Unbalanced Braces in Comments
# if { $x > 0 } {
if { $y > 0 } {
# code here
}
325
External References
f For more information about Tcl, refer to the following sources:
Version
June 2012
12.0.0
November 2011
11.0.1
May 2011
11.0.0
December 2010
10.1.0
July 2010
10.0.0
November 2009
March 2009
9.1.0
9.0.0
Changes
Template update
Updated supported version of Tcl in the section Tool Command Language on page 32
Added the incremental_compilation, insystem_source_probe, and rtl packages to Table 31 and Table 3-2.
November 2008
8.1.0
May 2008
8.0.0
Updated references.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
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This section provides an overview of the I/O planning process, Altera FPGA pin
terminology, as well as the various methods for importing, exporting, creating, and
validating pin-related assignments using the Quartus II software. This section also
describes ways to use the Quartus II software to analyze signal integrity, including
simultaneous switching noise, as well as interfaces with third-party PCB design tools.
This section includes the following chapters:
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
4. I/O Management
May 2013
QII52013-13.0.0
QII52013-13.0.0
This chapter describes efficient management of the I/O pins in your target device.
You must consider I/O standards, pin placement guidelines, and hardware
capabilities in making pin-related assignments. You must begin I/O planning and
PCB development early in the development cycle.
The Quartus II Pin Planner, Pin Advisor, and I/O assignment analysis features
support early I/O planning and assignments. You can use the Pin Planner shown in
Figure 41 to plan I/O assignments early, to create and validate pin assignments, and
to generate a Pin-Out File (.pin) for use with third-party PCB tools. The Pin Advisor
suggests pin planning steps. Use I/O assignment analysis to validate your I/O pin
assignments.
Figure 41. Pin Planner
Device Package
View
All Pins
List
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Feedback Subscribe
42
Silicon Die
Bond Pad
Package
Solder Ball Layer
Package Pins
BGA package pins are small solder balls arranged in a grid pattern on the bottom of
the package. The Quartus II software identifies each pin with alphanumeric pin
numbers using a coordinate system of letters and numbers corresponding with the
pin row and column location.
43
Figure 43 shows the coordinate system to identify pin locations. The top row of pins
is labeled A and continues alphabetically as you move down. The left-most column of
pins is labeled 1 and increments by one as you move right. For example, pin number
B4 represents the pin located in row B and column 4. The letters I, O, Q, S, X, and Z are
never used in pin numbers. If the device contains more rows than letters of the
alphabet, the alphabet is repeated, prefixed with the letter A.
Figure 43. Row and Column Labeling
Column
1 2 3 4 5 6 7 ...
Row
A
B
C
D
E
F
G
Altera
Device Package
(Top View)
...
f For more information about the pin numbers for your Altera device, refer to the
Pin-Out Files for Altera Devices page of the Altera website.
Pads
Package pins are connected to pads located on the perimeter of the top metal layer of
the silicon die (refer to Figure 42). Figure 44 shows the numbering scheme for pads
on the device. Each pad is identified by a pad ID, which is numbered starting at 0, and
increments by one in a counterclockwise direction around the device.
Figure 44. Pad Number Ordering
29 28 27 ...
0
1
2
Altera
Silicon Die
...
To prevent signal integrity issues, the Quartus II software uses pin placement rules to
validate your pin placements and pin-related assignments. You must understand the
pad locations to which your pins were assigned, because some pin placement rules
describe pad placement restrictions. For example, to ensure signal integrity, in certain
devices there is a restriction on the number of I/O pins supported by a voltage
reference (VREF) pad. There are also restrictions on the number of pads between
single-ended input or output pins and a differential pin. The Quartus II software
performs pin placement analysis. Design compilation fails and the Quartus II
software reports an error if your design violates pin placement rules.
f For more information about pin placement guidelines, refer to the appropriate device
handbook available on the Literature and Technical Documentation page of the Altera
website.
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44
I/O Banks
I/O pins are organized into I/O banks designed to facilitate various supported I/O
standards. Each I/O bank is numbered and has its own voltage source pins, called
VCCIO pins, to offer the highest I/O performance. Depending on the device and I/O
standards for the pins in the I/O bank, the specified voltage of the VCCIO pin is
between 1.5 V and 3.3 V. Each I/O bank can support multiple pins with different I/O
standards, however the pins must use the same VCCIO signal.
Figure 45 shows the I/O banks of a Stratix II device. The pins in the I/O banks on
the left and right side support high-speed I/O standards such as LVDS, whereas the
pins on the top and bottom I/O banks support all single-ended I/O standards,
including data strobe signaling (DQS). Pins belonging to the same I/O bank must use
the same VCCIO signal.
f For more information about the capabilities of each I/O bank, refer to the appropriate
device handbook available on the Literature and Technical Documentation page of the
Altera website.
(1), (2), (3), (4)
DQS7T
VREF1B3
PLL7
DQS6T
VREF2B3
DQS5T
VREF3B3
VREF4B3
Bank 11
Bank 9
DQS4T
DQS3T
DQS2T
DQS1T
DQS0T
VREF0B4
VREF1B4
VREF2B4
VREF3B4
VREF4B4
PLL10
Bank 4
VR EF1B 5
VREF 4B5
VREF 0B2
VR EF3B5
PLL1
PLL4
Bank 12
Bank 8
PLL8
VREF4B8
VREF3B8
DQS8B
VREF2B8
DQS7B
VREF1B8
DQS6B
VREF0B8
DQS5B
PLL12
PLL6
Bank 7
VREF 3B6
VREF 2B6
VR EF1B6
Bank 10
VREF 4B6
Bank 6
VREF 0B1
VREF 1B1
Bank 1
VR EF3B1
VR EF0B6
PLL3
VR EF4B1
PLL2
VREF 2B1
VR EF2B5
Bank 5
Bank 2
VR EF1B2
VR EF2B2
VR EF3B 2
VREF 0B5
PLL5
VREF 4B2
Bank 3
PLL11
PLL9
VREF4B7
VREF3B7
VREF2B7
VREF1B7
VREF0B7
DQS4B
DQS3B
DQS2B
DQS1B
DQS0B
45
VREF Groups
A VREF group is a group of pins that includes one dedicated VREF pin as required by
voltage-referenced I/O standards. A VREF group is made up of a small number of
pins, as compared to the I/O bank, to maintain the signal integrity of the VREF pin.
One or more VREF groups exist in an I/O bank. The pins in a VREF group share the
same VCCIO and VREF voltages.
f For more information about I/O banks, VREF groups, and supported I/O standards,
refer to the appropriate device handbook available on the Literature and Technical
Documentation page of the Altera website.
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46
PCB Tool
No
Early I/O
Planning
Flow?
Yes
Configure
IP Core Nodes
or User Nodes
Yes
Analyze, Synthesize,
and Merge Partitions
No
Tcl
Assignment
Editor
Floorplan
Editor
No
Validate
Assignments?
Yes
Run Full
Compilation?
No (2)
Yes
Timing
Passed?
Yes
No
Change Pin
Assignments?
No
Perform Timing
Optimization (4)
Yes
Pin-Out File
.pin
Pin Assignments
Fully Validated
.fx
Import Pin
Assignment
47
Selecting a Device
Before you begin I/O planning you must select a device family that supports the I/O
resources, standards, clocking schemes required for your design.
f For more information, refer to the various device handbooks available on the
Literature and Technical Documentation page of the Altera website.
Currently, only the Mentor Graphics I/O Designer PCB tool and the Cadence
Allegro PCB tool are supported in this reverse I/O planning flow.
Figure 47. I/O Planning Flow Using an FPGA Xchange File from a PCB Tool
Altera
Quartus II Software
PCB Tool
Create and
Modify Pin
Assignments
.fx
FPGA Xchange
File
Design Files
(if available)
No
Validate?
Yes
Pins have been Validated
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48
Click Early Pin Planning in the Task window to define or import interface IP core
nodes or other user nodes not yet defined in the design. You can then generate a new
top-level design that preserves the I/O pin assignments.
Example 41. Top-Level Design File
module top (
clk_in,
rst,
a,
z,
b,
c_in,
d,
e);
input clk_in;
input rst_;
input a;
input z;
input [7:0] b;
input [7:0] c_in;
input [7:0] d;
output reg [7:0] e;
Early pin planning helps save time by accurately setting up critical I/O before
implementing the rest of the design.
The following sections describe the typical steps of the early I/O planning flow:
h For more information, refer to Assigning Device I/O Pins in Pin Planner in Quartus II
Help.
49
You can create complex interfaces with early pin planning. Figure 48 shows a
schematic representation of the DDIO_IN and DDIO_OUT megafunctions defined in
the Pin Planner. The ports in gray are internal ports, which are connected later in the
design.
Figure 48. Connections Between Input and Output Megafunctions and User Nodes
ddio_in
input_data[7:0]
INPUT
datain[7..0]
clk
INPUT
inclock
reset
INPUT
aclr
ddio
input
dataout_h[7..0]
OUTPUT
dataout_i[7..0]
OUTPUT
dataout[7..0]
OUTPUT
ddio_in_data_h[7..0]
ddio_in_data_I[7..0]
power up
low
inst8
ddio_out
ddio_out_data_h[7..0]
INPUT
datain_h[7..0]
ddio_out_data_I[7..0]
INPUT
datain_i[7..0]
ddio
output
output_dataout[7:0]
outclock
aclr
power up
low
inst7
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410
You must update the top-level design file whenever you change the top-level ports of
the design, including any node changes made in the Set Up Top-Level File tab.
411
Example 42 shows a sample of a top-level HDL wrapper file representing the design
in Figure 48.
Example 42. HDL Wrapper File Generated with the Early I/O Planning Flow
module top
(
reset,
input_data,
clk,
output_data,
ddio_in_dataout_h,
ddio_in_dataout_l,
ddio_out_datain_h,
ddio_out_datain_l
);
//
//
//
//
Internal
Internal
Internal
Internal
input reset;
input[7:0]input_data;
input clk;
output[7:0]output_data;
output[7:0]ddio_in_dataout_h /* synthesis altera_attribute="-name VIRTUAL_PIN ON" */;
output[7:0]ddio_in_dataout_l /* synthesis altera_attribute="-name VIRTUAL_PIN ON" */;
input[7:0]ddio_out_datain_h /* synthesis altera_attribute="-name VIRTUAL_PIN ON" */;
input[7:0]ddio_out_datain_l /* synthesis altera_attribute="-name VIRTUAL_PIN ON" */;
ddio_in ddio_in_inst
(
.aclr(reset),
.datain(input_data),
.inclock(clk),
.dataout_h(ddio_in_dataout_h),
.dataout_l(ddio_in_dataout_l)
);
ddio_out ddio_out_inst
(
.aclr(reset),
.datain_h(ddio_out_datain_h),
.datain_l(ddio_out_datain_l),
.outclock(clk),
.dataout(output_data)
);
endmodule
After you generate the top-level design file and compile the design, use I/O
assignment analysis as described in Validating Pin Assignments with I/O
Assignment Analysis on page 425 and continue with your design flow by
modifying or creating pin assignments with the Pin Planner.
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412
Description
Pin Name/Usage
The name of the design pin, or whether the pin is GND or VCC pin
Location
Dir
I/O Standard
Voltage
I/O Bank
User Assignment
Y or N indicating if the location assignment for the design pin was user
assigned (Y) or assigned by the Fitter (N)
f For more information, refer to the Pin-Out Files for Altera Devices page of the Altera
website.
413
To transfer device and pin-related information between the Quartus II software and
the Mentor Graphics I/O Designer software you must generate an .fx. Importing
assignments into the I/O Designer software requires both the .fx and a .pin generated
by the Quartus II software. However, the Quartus II software requires only the .fx to
import pin assignments back from the I/O Designer software.
f For more information about the I/O Designer software and the DxDesigner interface,
refer to the Mentor Graphics PCB Tools Support chapter in volume 2 of the Quartus II
Handbook.
Pin Planner
Tcl Scripts
May 2013
Overview
Create pin location assignments to one or more node names by dragging and dropping unassigned
pins into the package view
Edit pin location assignments for one or more node names by dragging and dropping groups of pins
in the package view
View the function of package pins with the Pin Legend window
Make correct pin location decisions by referring to the Pad View window
Generate a top-level wrapper file without design files based on early I/O assignments
Configure board trace model assignments, instead of capacitive loading assignments, to generate
Advanced I/O Timing results
Altera Corporation
414
Table 42. Overview of Quartus II Tools and Features to Create Pin-Related Assignments (Part 2 of 2)
Feature
Chip Planner
Synthesis
Attributes
Overview
Create and change pin locations by dragging and dropping pins into the floorplan
Make correct pin location decisions by referring to the pad ID number and spacing
Display I/O banks, VREF groups, and differential pin pairing information
Embed pin-related assignments with attributes in the design files to pass assignments to the
Quartus II software
415
When you select migration devices early in the design process, the Pin Planner
displays only the pins that are available in the current device and in all migration
devices. If you select migration devices later in your design cycle, there may be
assignments for I/O nodes in your original design that do not have corresponding
pins in a migration device. If no corresponding pin exists, the Compiler cannot honor
the assignment and an error occurs when you try to recompile the design.
The Pin Migration View window helps you identify the difference in pins that can
exist between migration devices. For example, Figure 410 shows the highlighted pin
AC24 existed in the target EP2S30 device, but does not exist in one of the migration
devices, resulting in a No Connect (NC).
Figure 410. Pin Migration View
The migration result for the pin function of highlighted PIN_AC23 is not an NC but a
voltage reference VREFB1N2 even though the pin is an NC in one of the migration
devices. VREF standards have a higher priority than an NC, thus the migration result
display the voltage reference. Even if you do not use that pin for a port connection in
your design, you must use the VREF standard for I/O standards that require it on the
actual board for the migration device.
If one of the migration devices has pins intended for connection to VCC or GND and
these same pins are I/O pins on a different device in the migration path, the
Quartus II software ensures these pins are not used for I/O. Ensure that these pins are
connected to the correct PCB plane.
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When migrating between two devices in the same package, pins that are not
connected to the smaller die may be intended to connect to VCC or GND on the larger
die. To facilitate migration, you can connect these pins to VCC or GND in your original
design because the pins are not physically connected to the smaller die.
f For more information about migration, refer to AN90: SameFrame Pin-Out Design for
FineLine BGA Packages. For more information about designing for HardCopy series
devices, refer to the Designing HardCopy Series Devices chapter in volume 1 of the
Quartus II Handbook.
Pin number
I/O bank
VREF group
Edge
h For more information about device support for I/O bank, VREF group, and edge
location assignments, refer to I/O bank, VREF group, and edge in Quartus II Help.
You can assign your pins to a location with the Pin Planner. It is common to place a
group of pins (or bus) with compatible I/O standards in the same I/O bank or VREF
group. For example, two buses with two compatible I/O standards, such as 2.5-V and
SSTL-II Class I, can be placed in the same I/O bank.
417
If your design contains a large bus that exceeds the pins available in a particular I/O
bank, you can use edge location assignments to place the bus. Edge location
assignments improve the circuit board routing ability of large buses, because they are
close together near an edge. Figure 411 shows Altera device package edges.
Figure 411. Die View and Package View of the Four Edges on an Altera Device
Silicon Die View
Top Edge
Top Edge
Left Edge
Right Edge
Left Edge
Bottom Edge
Right Edge
Bottom Edge
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If you have a single-ended clock that feeds a PLL, assign the pin only to the positive
clock pin of a differential pair in the target device. Single-ended pins that feed a PLL
and are assigned to the negative clock pin device cause the design to not fit.
For more information about assigning locations for differential pins in HDL code with
low-level I/O primitives, refer toCreating Pin Assignments with Low-Level I/O
Primitives on page 422.
Figure 412. Creating a Differential Pin Pair in the Pin Planner
419
override I/O placement rules on pins, such as for system reset pins that do not switch
during normal design activity. Setting a value of 0 MHz for this assignment causes the
Fitter to recognize the pin at a DC state throughout device operation. The Fitter
excludes the assigned pin from placement rule analysis. Do not assign an
IO_MAXIMUM_TOGGLE RATE of 0 MHz to any actively switching pin or your
design may not function as intended.
h For more information about creating and running Tcl scripts with the Quartus II
software, refer to Creating and Running Tcl Scripts in Quartus II Help.
f For more information about using Tcl scripts to create pin-related assignments, refer
to the Tcl Scripting chapter in volume 2 of the Quartus II Handbook and API Functions
for Tcl in Quartus II Help.
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Using synthesis attributes for signal names that are top-level pins
Synthesis Attributes
Synthesis attributes allow you to embed pin-related assignments in your HDL code.
During Analysis and Synthesis, the Quartus II software reads these synthesis
attributes and translates them into assignments. The assignments are then populated
in the Pin Planner. If you modify or delete these pin assignments in the Pin Planner
and then recompile your design, any changes made in the Pin Planner take
precedence over the assignments you made with synthesis attributes in your HDL
code. Quartus II integrated synthesis supports the chip_pin, useioff, and
altera_attribute synthesis attributes.
f For more information about integrated synthesis, synthesis attributes, and syntax,
refer to the Quartus II Integrated Synthesis chapter in volume 1 of the Quartus II
Handbook. For more information about synthesis attributes supported by third-party
synthesis tools, contact your vendor.
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Example 44 and Example 45 use the chip_pin and useioff attributes to embed
location and Fast Input Register logic option assignments in both a Verilog HDL and
VHDL design file using the synthesis attributes.
Example 44. Verilog HDL Example
input my_pin1 /* synthesis chip_pin = "C1" useioff = 1 */;
altera_attribute
Use the altera_attribute synthesis attribute to create other pin-related assignments
in your HDL code. The altera_attribute attribute is understood only by Quartus II
integrated synthesis and supports all types of instance assignments.
h For more information, refer to altera_attribute VHDL Synthesis Attribute, and
altera_attribute Verilog HDL Synthesis Attribute in Quartus II Help.
Example 46 and Example 47 use the altera_attribute attribute to embed Fast
Input Register logic option assignments and I/O standard assignments in both a
Verilog HDL and a VHDL design file.
Example 46. Verilog HDL Example
input my_pin1 /* synthesis altera_attribute = "-name FAST_INPUT_REGISTER ON; -name
IO_STANDARD \"2.5 V\" " */ ;
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HDL
Required?
Checks the number of pins assigned to an I/O bank against the number of pins
allowed in the I/O bank.
No
Checks that no more than one VCCIO is required for the pins assigned to the I/O
bank.
No
Rule
423
HDL
Required?
Checks that no more than one VREF is required for the pins assigned to the I/O
bank.
No
Checks whether the pin location supports the assigned I/O standard.
No
Checks whether the pin location supports the assigned I/O standard and
direction. For example, certain I/O standards on a particular pin location can
only support output pins.
No
Checks that open drain is turned off for all pins with a differential I/O standard.
No
Checks whether the drive strength assignments are within the specifications of
the I/O standard.
No
Checks whether the pin location supports the assigned drive strength.
No
Checks whether the pin location supports BUSHOLD. For example, dedicated
clock pins do not support BUSHOLD.
No
No
Electromigration check
No
Checks whether the pin location along with the I/O standard assigned supports
PCI_IO clamp diode.
No
Checks that all pins connected to a SERDES in your design are assigned to
dedicated SERDES pin locations.
Yes
Checks whether pins connected to a PLL are assigned to the dedicated PLL pin
locations.
Yes
Rule
HDL
Required?
Checks that no single-ended I/O pin exists in the same I/O bank
as a DPA.
No
No
No
No
No
Rule
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Description
HDL
Required?
No
No
When the live I/O check feature is turned on, the Quartus II software prevents you
from assigning pins to unavailable locations. The following are examples of
unassignable locations:
The negative pin of a differential pair if the positive pin of the differential pair is
assigned with a node name with a differential I/O standard
Pin locations that do not support the I/O standard assigned to the selected node
name
For HSTL- and SSTL-type I/O standards, VREF groups of a different VREF voltage
than the selected node name
You can turn on or turn off the live I/O check feature at any time. By default, the live
I/O check feature is turned off. When the live I/O check feature is turned on, the
Quartus II software immediately checks whether your new pin-related assignments
pass the basic I/O buffer rules. The Live I/O Check Status window displays the total
numbers of errors and warnings while you create and edit pin-related assignments.
The Messages window shows detailed messages about any errors or warnings.
Although the live I/O check feature checks all the basic I/O buffer rules, you must
run I/O assignment analysis to validate your pin-related assignments against the
complete set of I/O system rules.
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h For more information about using the live I/O check feature to validate pin
assignments, refer to Assigning Device I/O Pins in Pin Planner in Quartus II Help.
If you have partial or complete design files, you must perform Analysis and Synthesis
to generate a synthesized (mapped) netlist before you can perform I/O assignment
analysis.
Performing I/O assignment analysis directs the Fitter to read assignments from your
mapped netlist and the .qsf to determine the legality of your pin-related assignments.
These pin-related assignments include pin settings such as I/O standards, drive
strength, and location assignments.
Incomplete I/O assignments trigger warnings during I/O assignment analysis. You
can view the I/O Assignment Warnings report to find and resolve warnings
generated during I/O assignment analysis. For example, you may receive a warning
that some of the pins in the design are missing a drive strength or slew rate.
Single-ended output and bidirectional pins default to the non-calibrated OCT setting
if you do not assign drive strength and slew rate options to the pins, or if other OCT
options are assigned to the pins. To resolve this issue, you can either assign drive
strength or slew rate settings to the pins with the Current Strength or Slew Rate or
Slow Slew Rate logic options, or assign the Termination logic option to the pins with
a series setting. You cannot use drive strength and slew rate settings when a pin is
assigned an OCT setting.
During I/O assignment analysis the Fitter automatically assigns suggested pin
locations to unassigned pins in your design, based on your design constraints, so it
can perform pin legality checks. For example, if you assign an edge location to a
group of LVDS pins, the Fitter assigns pin locations for each LVDS pin in the specified
edge location and then performs legality checks. To display the Fitter-placed pins use
the Show Fitter Placements feature in the Pin Planner. To accept these suggested pin
locations, you must back-annotate your pin assignments.
h For more information about the Show Fitter Placements feature, refer to the Show
Commands in Quartus II Help. For more information about back-annotating
assignments, refer to Back-Annotating Assignments for A Project in Quartus II Help.
The following design flows show two different circumstances in which you can use
I/O assignment analysis:
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Use the flow shown in Figure 413 if the you must complete board layout before
starting the design. This flow does not require design files and checks the legality
of your pin assignments.
Use the flow shown in Figure 414 if your design is complete. This flow
thoroughly checks the legality of your pin assignments against any design files
provided.
Each flow involves creating pin assignments, running analysis, and reviewing the
report file.
If you create pin-related assignments in Mentor Graphics I/O Designer software, you
can import a .fx into the Quartus II software.
Running I/O assignment analysis performs limited checks on pin assignments made
in a design in which you specified a device, but does not yet include any HDL design
files. For example, you can create a Quartus II project with only a target device
specified and create pin-related assignments based on circuit board layout
considerations that are already determined. Even though the Quartus II project does
not yet contain any design files, you can reserve input and output pins and create
pin-related assignments for each pin with the Pin Planner. After you assign an I/O
standard to each reserved pin, run I/O assignment analysis to ensure that there are no
I/O standard conflicts in each I/O bank. Figure 413 shows the work flow for
assigning and analyzing pin-outs without design files.
Figure 413. Assigning and Analyzing Pin-Outs without Design Files
Create a Quartus II Project
Assignments
Correct?
No
Yes
427
When you make and analyze pin-related assignments without design files, make sure
you reserve the pins you intend to use as I/O pins, so the Fitter can determine each
pin type. After performing I/O assignment analysis, correct any errors reported by
the Fitter and rerun I/O assignment analysis until all errors are corrected.
1
Without a complete design, running I/O assignment analysis performs limited checks
and cannot guarantee that your assignments do not violate design rules.
.edf
.vqm
.v
.vhd
.bdf
.tdf
Assignments
Correct?
No
Yes
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If you run I/O assignment analysis on incomplete design files, you may still
encounter errors during full compilation. For example, you may assign a clock to a
user I/O pin instead of assigning it to a dedicated clock pin, or design the clock to
drive a PLL that you have not yet instantiated in the design. The checks run during
I/O assignment analysis do not account for the logic that the pin drives, and do not
check that only a dedicated clock input pin can drive the clock port of a PLL. To obtain
better coverage, analyze as much of the design as possible, especially logic that
connects to pins. For example, if your design includes PLLs or LVDS blocks, include
these MegaWizard Plug-In Manager-generated files. To assign and analyze
pin-related assignments successfully, after performing I/O assignment analysis,
correct any errors reported by the Fitter and rerun I/O assignment analysis until all
errors are corrected.
Figure 415 shows the compilation time benefit of performing I/O assignment
analysis before running a full compilation.
Figure 415. Saving Compilation Time with the I/O Assignment Analysis
Errors Reported and Fixed
Without
Start I/O Assignment Analysis
Command
With
Start I/O Assignment Analysis
Command
I/O
Assignment
Analysis
Errors
Reported
and Fixed
Compilation Time
Optimizing I/O Assignment Analysis with Output Enable Group Logic Option
Assignments
Each device has a certain number of VREF pins, and each VREF pin supports a certain
number of I/O pins. A VREF pin and its supported I/O pins are called a VREF bank.
The VREF pins are used only for inputs with VREF I/O standards, such as HSTL- and
SSTL-type I/O standards. VREF outputs do not require the VREF pin. When a
voltage-referenced input is present in a VREF bank, only a certain number of outputs
can be present in that VREF bank. For example, for devices in the Stratix II flip chip
package, only 20 outputs can be present in a VREF bank when a VREF I/O standard
input is present in that bank.
f For more information about device VREF pins and their associated I/O pins, refer to
the Pin-Out Files for Altera Devices page of the Altera website.
For interfaces that use bidirectional VREF I/O pins, your design must meet the output
restriction for each I/O bank when the pins are driving in either direction. If a set of
bidirectional signals are controlled by different output enables, they are treated as
independent output enables during I/O assignment analysis, thus creating a situation
in which the Fitter may determine that your design violates VREF restrictions. To treat
429
the set of bidirectional signals as a single output enable group so that the Fitter does
not determine that the design violates the requirements for the maximum number of
pins driving out of a VREF group, assign the Output Enable Group logic option
assignment to the bidirectional signals. Assign an integer value for the Output Enable
Group logic option assignment and assign the same integer value to all sets of signals
that are driving in the same direction. Assigning this logic option to groups of signals
is important in the case of external memory interfaces.
For example, in the case of a DDR2 interface in a Stratix II device, the device can have
30 pins in a VREF group. Each byte lane for a 8 DDR2 interface has one DQS pin and
eight DQ pins, for a total of nine pins per byte lane. The DDR2 interface uses SSTL-18
Class I as its I/O standard, which is a VREF I/O standard. In typical interfaces, each
byte lane has its own output enable. In this example, the DDR2 interface has four byte
lanes. Using 30 I/O pins in a VREF group, there are three byte lanes and an extra byte
lane that supports the three remaining pins. If you do not use the Output Enable
Group logic option assignment, the Fitter analyzes each byte lane as an independent
group driven by a unique output enable during I/O assignment analysis. With this
arrangement, the worst-case scenario is when the three pins are inputs, and the other
27 pins are outputs. In this case, the 27 output pins violate the 20 output pin limit.
In a DDR2 interface, all DQS and DQ pins are always driven in the same direction.
Therefore, the Fitter reports an error that is not applicable to your design. Assigning
the Output Enable Group logic option assignment to the DQS and DQ pins forces the
Fitter to check these pins as a group driven by a common output enable during I/O
assignment analysis. When you use the Output Enable Group logic option
assignment, the DQS and DQ pins are checked as all input pins or all output pins and
are not in violation of the I/O rules.
You can also use the Output Enable Group logic option assignment with pins that are
driven only at certain times. For example, the data mask signal in DDR2 interfaces is
an output signal, but it is driven only when the DDR2 is writing (bidirectional signals
are outputs). To avoid errors during I/O assignment analysis, use the Output Enable
Group logic option assignment to assign the data mask to the same value as the DQ
and DQS signals.
You can also assign the Output Enable Group logic option to VREF input pins. If the
VREF input pins are not active during the time the outputs are driving, add the VREF
input pins to the output enable group, thus removing the VREF input pins from the
VREF analysis. For example, the QVLD signal for an RLDRAM II interface is active
only during a read. During a write, the QVLD pin is not active and does not count as
an active VREF input pin in the VREF group. You can place the QVLD pins in the
same output enable group as the RLDRAM II data pins.
Understanding the I/O Assignment Analysis Report
When I/O assignment analysis is complete, you can view detailed analysis reports
and a .pin. The detailed messages in the reports help you quickly understand and
resolve pin assignment errors. Each message includes a related node name and a
description of the problem.
The Fitter section of the Compilation report contains information generated during
I/O assignment analysis, including the following reports:
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The I/O Assignment Warnings report provides a list of pins and the Fitter warnings
generated for the pins during I/O assignment analysis
The Resource Section contains reports that categorize the pins as input pins, output
pins, and bidirectional pins. You can view the utilization of each I/O bank in your
device in the I/O Bank Usage report.
The I/O Rules Section includes detailed information about the I/O rules tested
during I/O assignment analysis and contains the following reports:
The I/O Rules Summary report provides a quick summary of the number of I/O rules
tested and how many applicable rules passed, failed, or were not checked due to other
failing rules.
The I/O Rules Details report provides detailed information on all I/O rules. The
Status column indicates whether applicable rules passed, failed, or could not be
checked. All rules are given a level of severity rating to indicate their level of
importance for an effective analysis.
The I/O Rules Matrix report (refer to Figure 416) provides a list of the I/O rules
checked by the Fitter for each pin in the design. Rules that apply to the target device
family either pass or fail for each pin. Rules marked Inapplicable are rules that do not
apply to the target device family. You can ignore any rule marked Inapplicable.
Figure 416. I/O Rules Matrix
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For devices that support advanced I/O timing, it is the default method of I/O timing
analysis. For all other devices, you must use a default or user-specified capacitive load
assignment to determine tCO and power measurements.
f For more information about advanced I/O timing support, refer to the appropriate
device handbook available on the Literature and Technical Documentation page of the
Altera website. For more information about board-level signal integrity and tips on
how to improve signal integrity in your high-speed designs, refer to the Altera Signal
Integrity Center page of the Altera website.
f For information about creating IBIS and HSPICE models with the Quartus II software
and integrating those models into HyperLynx and HSPICE simulations, refer to the
Signal Integrity Analysis with Third-Party Tools chapter in volume 2 of the Quartus II
Handbook.
433
Custom component value changes you make to selected pins in the Pin Planner take
priority and are not affected by subsequent changes to a specific components for the
entire design. Similarly, any changes you make to specific pins do not affect the
component settings for the entire design.
When you define an overall board trace model you can specify the board trace,
termination, and capacitive load parameters for each I/O standard. The default
settings for components in the model for each I/O standard are device-specific and
match the default test model used for calculating delay without advanced I/O timing.
For differential I/O standards, the component values you set are used for both the
positive and negative signals of a differential pin pair.
All the assignments for board trace models you specify are saved to the .qsf. You can
also use Tcl commands to create board trace model assignments. Example 48 shows
Tcl commands for specifying board trace model assignments.
h For more information about defining a board trace model for your entire design, refer
to Using Advanced I/O Timing in Quartus II Help. For more information about
configuring component values for a board trace model, including a complete list of
the supported unit prefixes and setting the values with Tcl scripts, refer to Board Trace
Model Quartus II Help.
f For more information about the default models used for measuring I/O delay, refer to
the appropriate device handbook available on the Literature and Technical
Documentation page of the Altera website.
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Figure 418 shows the template for the LVDS I/O standard. The far-end capacitance
(Cf) represents the external-device or multiple-device capacitive load. If you have
multiple devices on the far-end, you must find the equivalent capacitance at the
far-end, taking into account all receiver capacitances. The far-end capacitance can be
the sum of all the receiver capacitances.
f For more information about the specifications for external device capacitance values,
refer to the appropriate device handbook available on the Literature and Technical
Documentation page of the Altera website.
435
The Quartus II software models lossless transmission lines, and does not require a
transmission-line resistance value. Only distributed inductance (L) and capacitance
(C) values are needed. The distributed L and C values of transmission lines must be
entered on a per-inch basis, and can be obtained from the PCB vendor or
manufacturer, the CAD Design tool, or a signal integrity tool such as the Mentor
Graphics Hyperlynx software.
Figure 418. Differential Board Trace Model
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The Board Trace Model Assignments report summarizes the board trace model
component settings for each output and bidirectional signal.
The Signal Integrity Metrics report contains all the signal integrity metrics calculated
during advanced I/O timing analysis based on the board trace model settings for each
output or bidirectional pin. The reports contain many metrics, including
measurements at both the FPGA pin and at the far-end load of board delay, steady
state voltages, and rise and fall times.
1
h For more information about the reports generated during advanced I/O timing
analysis, refer to About TimeQuest Timing Analysis in Quartus II Help. For more
information about the metrics calculated during advanced I/O timing analysis,
including diagrams illustrating the metrics on output waveforms, refer to Signal
Integrity Metrics in Quartus II Help. For more information about changing the delay
model, refer to the Create Timing Netlist Dialog Box in Quartus II Help.
f For information about the configuration and use of the TimeQuest analyzer, refer to
The Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II
Handbook.
437
Scripting Support
A Tcl script allows you to run procedures and determine settings described in this
chapter. You can also run some of these procedures at a command prompt.
For detailed information about specific scripting command options and Tcl API
packages, type the following command at a system command prompt to run the
Quartus II Command-Line and Tcl API Help browser:
quartus_sh --qhelp r
f For more information about Quartus II scripting support, including examples, refer to
the Tcl Scripting and Command-Line Scripting chapters in volume 2 of the Quartus II
Handbook.
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Reserving Pins
You can reserve pins with a Tcl command.
Use the following Tcl command to reserve a pin:
set_instance_assignment -name RESERVE_PIN <value> -to <signal name>
"AS BIDIRECTIONAL"
Ensure you include the quotation marks when specifying the reserved pin value.
Valid locations are pin locations, I/O bank locations, or edge locations. Pin locations
include pin names, such as PIN_A3. I/O bank locations include IOBANK_1 up to
IOBANK_n, in which n is the number of I/O banks in the device.
Use one of the following valid edge location values:
EDGE_BOTTOM
EDGE_LEFT
EDGE_TOP
EDGE_RIGHT
439
For more information about exclusive I/O group assignments, refer to Creating
Exclusive I/O Group Assignments on page 417.
For more information about slew rate and drive strength assignments, refer to
Creating Pin Assignments with the Chip Planner on page 419.
Conclusion
The Quartus II software provides many tools and features to help you with I/O
planning, including the ability to validate pin assignments in all design stages, even
before the development of your design. The ability to import and export assignments
between the Quartus II software and other PCB tools allows you to make iterative
changes efficiently. Finally, the ability to enter a board trace model and create
advanced timing reports based on how I/O signals are routed on a board truly makes
the Quartus II software board-aware.
f For more information about the Altera resources available for I/O planning, refer to
the I/O Management, Board Development Support, and Signal Integrity Analysis
Resource Center of the Altera website.
f For more information about PCB designs for Altera high-speed FPGAs, refer to
AN 315: Guidelines for Designing High-Speed FPGA PCBs, and the Board Design
Resource Center of the Altera website.
Version
Changes
May 2013
13.0.0
November 2012
12.1.0
Updated Pin Planner description for new task and report windows.
June 2012
12.0.0
November 2011
11.1.0
December 2010
10.0.1
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Template update
440
Version
July 2010
10.0.0
November 2009
March 2009
Changes
Added links to Quartus II Help for procedural information previously included in the
chapter
Added information on rules marked Inapplicable in the I/O Rules Matrix Report
Added information on assigning slew rate and drive strength settings to pins to fix I/O
assignment warnings
Reorganized entire chapter to include links to Quartus II help for procedural information
previously included in the chapter
9.1.0
9.0.0
Figure 515
Figure 516
Added new section Viewing Simultaneous Switching Noise (SSN) Results on page 517
Added new section Creating Exclusive I/O Group Assignments on page 518
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
FPGA design has evolved from small programmable circuits to designs that compete
with multimillion-gate ASICs. At the same time, the I/O counts on FPGAs and logic
density requirements of designs have increased exponentially. The higher-speed
interfaces in FPGAs, including high-speed serial interfaces and memory interfaces,
require careful interface design on the PCB. Designers must address the timing and
signal integrity requirements of these interfaces early in the design cycle.
Simultaneous switching noise (SSN) often leads to the degradation of signal integrity
by causing signal distortion, thereby reducing the noise margin of a system.
Todays complex FPGA system design is incomplete without addressing the integrity
of signals coming in to and out of the FPGA. Altera recommends that you perform
SSN analysis early in your FPGA design and prior to the layout of your PCB with
complete SSN analysis of your FPGA in the Quartus II software. This chapter
describes the Quartus II SSN Analyzer tool and covers the following topics:
Definitions
Definitions
The terminology used in this chapter includes the following terms:
Aggressor: An output or bidirectional signal that contributes to the noise for a victim
I/O pin
PDN: Power distribution network
QH: Quiet high signal level on a pin
QHN: Quiet high noise on a pin, measured in volts
QL: Quiet low signal level on a pin
QLN: Quiet low noise on a pin, measured in volts
SI: Signal integrity (a superset of SSN, covering all noise sources)
SSN: Simultaneous switching noise
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are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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SSO: Simultaneous switching output (which are either the output or bidirectional
pins)
Victim: An input, output, or bidirectional pin that is analyzed during SSN analysis.
During SSN analysis, each pin is analyzed as a victim. If a pin is an output or
bidirectional pin, the same pin acts as an aggressor signal for other pins.
Understanding SSN
SSN is defined as a noise voltage induced onto a single victim I/O pin on a device due
to the switching behavior of other aggressor I/O pins on the device. SSN can be
divided into two types of noise: voltage noise and timing noise.
Figure 51 shows a system with three pins. Two of the pins (A and C) are switching,
while one pin (B) is quiet. If the pins are driven in isolation, the voltage waveforms at
the output of the buffers appear without noise interference, as shown by the solid
curves at the left of the figure. However, when the pins are switched simultaneously,
the noise generated by pins A and C switching is injected onto the other pins,
manifesting itself as a voltage noise on pin B and timing noise on pins A and C, as
shown by the dotted curves in the figure.
Figure 51. System with Three Pins
Voltage noise is measured as the worst-case change in voltage of a signal due to SSN.
When a signal is QH, it is measured as the change in voltage toward 0 V. When a
signal is QL, it is measured as the change in voltage toward VCC.
In the Quartus II software, only voltage noise is analyzed. Voltage noise can be caused
by SSOs under two worst-case conditions:
The victim pin is high and the aggressor pins (SSOs) are switching from low to
high
The victim pin is low and the aggressor pins (SSOs) are switching from high to low
53
For outputs, the noise is computed at the far-end receiver for pin B (refer to
Figure 52).
Figure 52. Quiet High Output Noise Estimation
For inputs, the noise is computed at the FPGA bumps as shown in for pin D (refer to
Figure 53).
Figure 53. Quiet Low Input Noise Estimation
SSN can occur in any system, but the induced noise does not always result in failures.
Voltage functional errors are caused by SSN on quiet victim pins only when the
voltage values on the quiet pins change by a large enough voltage that the logic
listening to that signal reads a change in the logic value. For QH signals, a voltage
functional error occurs when noise events cause the voltage to fall below VIH.
Similarly, for QL signals, a voltage functional error occurs when noise events cause
the voltage to rise above VIL (refer to Figure 54). Because VIH and VIL are different for
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different I/O standards, and because signals have different quiet voltage values, the
absolute amount of SSN, measured in volts, cannot be used to determine if a voltage
failure occurs. Instead, to quantify whether an SSN event will cause a voltage error,
the Quartus II software uses the amount of noise as a percent of signal margin when
reporting noise margins in SSN analysis (refer to Figure 54).
Figure 54. Reporting Noise Margins
Figure 54 shows four noise events, two on QH signals and two on QL signals. The
two noise events on the right-side of the figure consume 50 percent of the signal
margin and do not cause voltage functional errors. However, the two noise events on
the left side of the figure consume 100 percent of the signal margin and can cause a
voltage functional error.
Figure 55 illustrates a synchronous voltage noise event that does not result in a
voltage functional error. Noise or glitches caused by aggressor signals are
synchronously related to the victim pin outside of the sampling window of a receiver.
The noise or glitches affect the switching time of a victim pin, but are not considered
an input threshold violation failure.
Figure 55. Synchronous Voltage Noise
For more information about the design factors that affect the noise margins during
SSN analysis in the Quartus II software, refer to SSN Analysis Overview.
55
f For more information about the SSN characterization reports and the ESE tool,
including device support information, refer to the Signal Integrity Center page of the
Altera website.
h For more information about the devices for which you can run the SSN Analyzer, refer
to About the SSN Analyzer in Quartus II Help.
The ESE tool is useful for preliminary SSN analysis of your FPGA design; for more
accurate results, however, you must use the SSN Analyzer in the Quartus II software.
Table 51 compares some of the differences between the ESE tool and the SSN
Analyzer.
Table 51. Comparison of ESE Tool and SSN Analyzer Tool
ESE Tool
SSN Analyzer
No graphical representation.
Good for doing an early SSN estimate. Does not require you
to use the Quartus II software.
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pin-out flow. The pass criteria you define is specific to your design requirements. For
example, a pass criterion you might define is a condition that verifies you have
sufficient SSN margins in your design. You may require that the acceptable voltage
noise on a pin must be below 70% of the voltage level for that pin. The pass criteria for
the early-pin out flow may be higher than the final pin-out flow criteria, so that you
do not spend too much time optimizing the on-FPGA portions of your design when
the SSN metrics for the design may improve after the design is fully specified.
Figure 56. Pin-Out Analysis (1)
Start
Yes
Done
Yes
No
No
Yes
Manual optimization
Yes
Can we further
constrain PCB?
No
No
Yes
Done
Design is unlikely to
pass final SSN Analysis
57
5. If you do not have completed design files and timing constraints, run I/O
assignment analysis.
1
During I/O assignment analysis, the Fitter places all the unplaced pins on
the device, and checks all the I/O placement rules.
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59
The SSN Analyzer also models the package and vias in the design. Models for the
different packages that Altera devices support are integrated into the Quartus II
software. In the Quartus II software, you can specify different layers on which signals
break out, each with its own thickness, and then specify which signal breaks out on
which layer.
Figure 57 shows the circuit topology the SSN Analyzer automatically constructs.
After constructing the circuit topology, the SSN Analyzer uses a simulation-based
methodology to determine the SSN for each victim pin in the design.
Figure 57. Circuit Topology for SSN Analysis
June 2012
In order to use the SSN Optimization logic option, Altera recommends that you do
not create location assignments for your pins; instead, let the Fitter place the pins
during compilation so that it places the pins to meet the timing performance of your
design. To display the Fitter-placed pins use the Show Fitter Placements feature in the
Pin Planner. To accept these suggested pin locations, you must back-annotate your pin
assignments.
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Figure 58 shows the results of turning on the SSN Optimization logic option for a
design. The image on the left shows the placement of the pins without the SSN
Optimization logic option, and the image on the right shows the adjustments the
Fitter made to pin placements to reduce the amount of SSN in the design when the
SSN Optimization logic option is turned on.
Figure 58. SSN Analysis Results Before and After Using the SSN Optimization Logic Option
h For more information about creating project-wide logic option assignments, refer to
Setting Up and Running the Fitter in Quartus II Help. For more information about the
Show Fitter Placements feature, refer to Show Commands in Quartus II Help. For more
information about back-annotating assignments, refer to Back-Annotating Assignments
for A Project in Quartus II Help.
f For more information about design optimization features, refer to the Area, Timing,
and Compilation Time Optimization section in volume 2 of the Quartus II Handbook.
511
You can define an overall board trace model for each I/O standard in your design; this
overall board trace model is the default model for all pins that use a particular I/O
standard. After configuring the overall board trace model, you can customize the
model for specific pins. The parameters you specify for the board trace model are also
used in during advanced I/O timing analysis with the TimeQuest Timing Analyzer. If
you already specified the board trace models as part of your advanced I/O timing
assignments, the same parameters are used during SSN analysis.
h For more information about defining a board trace model for your entire design, refer
to Using Advanced I/O Timing in Quartus II Help. For more information about
configuring component values for a board trace model, including a complete list of
the supported unit prefixes and setting the values with Tcl scripts, refer to Board Trace
Model in Quartus II Help.
All the assignments for board trace models you specify are saved to the .qsf. You can
also use Tcl commands to create board trace model assignments. Example 51 shows
Tcl commands for specifying transmission line parameters.
Example 51. Specifying Board Trace Models
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH "3.041E-7" -to e[0]
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH 0.1391 -to e[0]
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH "1.463E-10" -to e[0]
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All the assignments you create for the PCB layers are saved to the .qsf. You can also
use Tcl commands to create PCB layer assignments. You can create any number of
PCB layers, however, the layers must be consecutive. Example 52 shows Tcl
commands for specifying PCB layer assignments.
Example 52. Specifying PCB Layer Assignments
set_global_assignment -name PCB_LAYER_THICKNESS 0.00099822M -section_id 1
set_global_assignment -name PCB_LAYER_THICKNESS 0.00034036M -section_id 2
set_global_assignment -name PCB_LAYER_THICKNESS 0.00034036M -section_id 3
Figure 59 shows the layout cross-section of a PCB in the Cadence Allegro PCB tool.
The cross-section shows the stackup information of a PCB, which tells you the
number of layers used in your PCB. The PCB shown in this example consists of
various signal and circuit layers on which FPGA pins are routed, as well as the power
and ground layers.
Figure 59. Snapshot of Stackup of a PCB Shown in the Allegro Board Design Environment
In this example, each of the four signal layers are a different thickness, with the depths
shown in the Thickness (MIL) column. The layer thickness for each signal layer is
computed as follows:
513
Figure 510 shows the results in the Quartus II software after you enter these PCB
signal layers and thickness assignments.
Figure 510. PCB Layers Specified in the Quartus II Software
June 2012
When you create PCB breakout layer assignments in the Pin Planner, you can assign
the pin to any layer, even if you did not yet define the PCB layer.
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The SSN Analyzer does not support differential I/O standards, such as the LVDS I/O
standard and its variations, because differential I/O standards contribute a small
amount of SSN.
f For more information about supported I/O standards, refer to the appropriate device
handbook available on the Literature and Technical Documentation page of the Altera
website.
f For more information about creating and managing I/O assignments, refer to the I/O
Management chapter in volume 2 of the Quartus II Handbook.
Assign pins to an output enable groupAll pins in an output enable group must
be either all input pins or all output pins. If all the pins in a group are always either
all inputs or all outputs, it is impossible for an output pin in the group to cause
SSN noise on an input pin in the group. You can assign pins to an output enable
group with the Output Enable Group logic option.
In some cases, the SSN Analyzer can detect the grouping for bidirectional pins by
looking at the output enable signal of the bidirectional pins. However, Altera
recommends that you explicitly specify the bidirectional groups and output groups in
your design.
515
h For more information about creating logic option assignments, refer to Assigning
Device I/O Pins in Quartus II Help.
A pin that is a complement of the victim pin. For example, any pin that is assigned
a differential I/O standard cannot be an aggressor pin.
A programming pin or JTAG pin because these pins are not active in user mode.
Pins that have the same output enable signal as a bidirectional victim pin that the
SSN Analyzer analyzes as an input pin. Pins with the same output enable signal
also act as input pins and therefore cannot be aggressor pins at the same time. For
information about grouping bidirectional pins, refer to Performing SSN Analysis
and Viewing Results.
Pins in the same synchronous group as a victim output pin. For information about
grouping output pins, refer to Performing SSN Analysis and Viewing Results.
A pin assigned the I/O Maximum Toggle Rate logic option with a frequency
setting of zero. The SSN Analyzer does not consider pins with this setting as
aggressor pins.
h For more information about creating pin assignments with the Pin Planner, refer to
Assigning Device I/O Pins in Quartus II Help.
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Output Pins
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Input Pins
Unanalyzed Pins
Summary Report
The Summary report summarizes the SSN Analyzer status and rates the SSN
Analyzer confidence level as low, medium, or high. The confidence level depends on
the completeness of your board trace model assignments. The more assignments you
complete, the higher the confidence level. However, the confidence level does not
always contribute to the accuracy of the QL and QH noise levels on a victim pin. The
accuracy of QH and QL noise levels depends the accuracy of your board trace model
assignments.
Pins assigned the LVDS I/O standard or any LVDS variations, such as the
mini-LVDS I/O standard
Pins created in the migration flow that cover power and supply pins in other
packages
517
When you view the SSN map, you can customize which details to display, including
input pins, output pins, QH signals, QL signals, and noise levels. You can also adjust
the threshold levels for QH and QL noise voltages. Adjusting the threshold levels in
the Pin Planner does not change the threshold levels reported during SSN analysis
and does not change the data in any of the SSN reports.
You can also you change I/O assignments and board trace information and rerun the
SSN Analyzer to view the SSN analysis results based on those modified settings.
h For more information, refer to Show SSN Analyzer Results and Running the SSN
Analyzer in Quartus II Help.
Direct the Quartus II software to use more than one processor for parallel
executables, including the SSN Analyzer
Perform SSN analysis after I/O assignment analysis if your design files and
constraints are complete, and you are interested in generating the SSN results
early in the design process and want to adjust I/O placements to see if you can
obtain better results
Perform SSN analysis after fitting if you want to view preliminary SSN results that
do not take into account complete I/O assignment and I/O timing results
h For more information about using parallel processors, refer to Setting Up and Running
Analysis and Synthesis and Compilation Process Settings Page in Quartus II Help. For
more information about performing I/O assignment analysis, refer to Assigning
Device I/O Pins in Quartus II Help. For more information about running the Fitter,
refer to Setting Up and Running the Fitter in Quartus II Help.
f For more information about performing ECOs on your design, refer to the Engineering
Change Management with the Chip Planner chapter in volume 2 of the Quartus II
Handbook.
Scripting Support
A Tcl script allows you to run procedures and determine settings described in this
chapter. You can also run some of these procedures at a command prompt. The
Quartus II software provides several packages to compile your design and create I/O
assignments for analysis and fitting. You can create a custom Tcl script that maps the
design and runs SSN analysis on your design.
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For detailed information about specific scripting command options and Tcl API
packages, type the following command at a system command prompt to run the
Quartus II Command-Line and Tcl API Help browser:
quartus_sh --qhelp r
f For more information about Quartus II scripting support, including examples, refer to
the Tcl Scripting and Command-Line Scripting chapters in volume 2 of the Quartus II
Handbook and API Functions for Tcl in Quartus II Help.
For more information, refer to Optimizing Pin Placements for Signal Integrity on
page 59.
-name
-name
-name
-name
-name
-name
-name
PCB_LAYER_THICKNESS
PCB_LAYER_THICKNESS
PCB_LAYER_THICKNESS
PCB_LAYER_THICKNESS
PCB_LAYER_THICKNESS
PCB_LAYER_THICKNESS
PCB_LAYER_THICKNESS
0.00099822M
0.00034036M
0.00034036M
0.00055372M
0.00034036M
0.00034036M
0.00082042M
-section_id
-section_id
-section_id
-section_id
-section_id
-section_id
-section_id
1
2
3
4
5
6
7
These Tcl commands specify that there are seven PCB layers in the design, each with a
different thickness. In each assignment, the letter M indicates the unit of measurement
is millimeters. When you specify PCB layer assignments with Tcl commands, you
must list the layers in consecutive order. For example, you would receive an error
during SSN Analysis if your Tcl commands created the following assignments:
set_global_assignment -name PCB_LAYER_THICKNESS 0.00099822M -section_id 1
set_global_assignment -name PCB_LAYER_THICKNESS 0.00082042M -section_id 7
To create assignments with the unit of measurement in mils, refer to the syntax in the
following Tcl commands. These Tcl commands specify the same settings as shown in
Figure 510 on page 513.
set_global_assignment
set_global_assignment
set_global_assignment
set_global_assignment
-name
-name
-name
-name
PCB_LAYER_THICKNESS
PCB_LAYER_THICKNESS
PCB_LAYER_THICKNESS
PCB_LAYER_THICKNESS
14.9MIL -section_id 1
6.6MIL -section_id 2
14MIL -section_id 3
6.6MIL -section_id 4
519
For more information, refer to Defining PCB Layers and PCB Layer Thickness on
page 511.
When you create PCB breakout layer assignments with Tcl commands, if you do not
specify a PCB layer, or if you specify a PCB layer that does not exist, the SSN Analyzer
breaks out the signal at the bottommost PCB layer.
1
If you create a PCB layer breakout assignment to a layer that does not exist, the SSN
Analyzer will generate a warning message.
For more information, refer to Specifying Signal Breakout Layers on page 513.
The following Tcl command assigns the bus PCI_ADD_io to a synchronous group:
set_instance_assignment -name SYNCHRONOUS_GROUP 1 -to PCI_AD_io
For more information, refer to Decreasing Pessimism in SSN Analysis on page 514.
To analyze just one I/O bank, type the following command at a system command
prompt:
quartus_si <project revision> <--bank = bank id> r
For example, to run analyze the I/O bank 2A type the following command:
quartus_si counter --bank=2A r
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For more information, refer to Performing SSN Analysis and Viewing Results on
page 515.
f For more information about the quartus_si package, type quartus_si -h at a system
command prompt.
Conclusion
To assist you with SSN Analysis, you can use the fast and accurate SSN Analyzer to
help you estimate the SSN performance of your FPGA both early in the design cycle
and when your PCB is complete. The SSN methodology discussed in this chapter
gives you the tools you need to ensure your FPGA design meets your SSN
requirements.
Version
Changes
June 2012
12.0.0
November 2011
10.0.2
Template update
December 2010
10.0.1
Template update
July 2010
10.0.0
November 2009
March 2009
Added links to Quartus II Help for procedural information previously included in the
chapter
Added Figure 69 shows the layout cross-section of a PCB in the Cadence Allegro PCB
tool. The cross-section shows the stackup information of a PCB, which tells you the
number of layers used in your PCB. The PCB shown in this example consists of various
signal and circuit layers on which FPGA pins are routed, as well as the power and ground
layers. on page 612
9.1.0
9.0.0
Initial release
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
Introduction
With the ever-increasing operating speed of interfaces in traditional FPGA design, the
timing and signal integrity margins between the FPGA and other devices on the
board must be within specification and tolerance before a single PCB is built. If the
board trace is designed poorly or the route is too heavily loaded, noise in the signal
can cause data corruption, while overshoot and undershoot can potentially damage
input buffers over time.
As FPGA devices are used in high-speed applications, signal integrity and timing
margin between the FPGA and other devices on the printed circuit board (PCB) are
important aspects to consider to ensure proper system operation. To avoid
time-consuming redesigns and expensive board respins, the topology and routing of
critical signals must be simulated. The high-speed interfaces available on current
FPGA devices must be modeled accurately and integrated into timing models and
board-level signal integrity simulations. The tools used in the design of an FPGA and
its integration into a PCB must be board-awareable to take into account
properties of the board routing and the connected devices on the board.
This chapter contains the following topics:
I/O timing with a default or user-specified capacitive load and no signal integrity
analysis (default)
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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9001:2008
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62
I/O timing using a specified capacitive test load requires no special configuration
other than setting the size of the load. I/O timing reports from the Quartus II
TimeQuest or the Quartus II Classic Timing Analyzer are generated based only on
point-to-point delays within the I/O buffer and assume the presence of the capacitive
test load with no other details about the board specified. The default size of the load is
based on the I/O standard selected for the pin. Timing is measured to the FPGA pin
with no signal integrity analysis details.
The Enable Advanced I/O Timing option expands the details in I/O timing reports
by taking board topology and termination components into account. A complete
point-to-point board trace model is defined and accounted for in the timing analysis.
This ability to define a board trace model is an example of how the Quartus II
software is board-aware.
In this case, timing and signal integrity metrics between the I/O buffer and the
defined far end load are analyzed and reported in enhanced reports generated by the
Quartus II TimeQuest Timing Analyzer.
f For more information about defining capacitive test loads or how to use the Enable
Advanced I/O Timing option to configure a board trace model, refer to the I/O
Management chapter in volume 2 of the Quartus II Handbook.
This chapter focuses on the third type of analysis. The Quartus II software can export
accurate HSPICE models with the built-in HSPICE Writer. You can run signal integrity
simulations with these complete HSPICE models in Synopsys HSPICE. IBIS models of
the FPGA I/O buffers are also created easily with the Quartus II IBIS Writer. You can
integrate IBIS models into any third-party simulation tool that supports them, such as
the Mentor Graphics Hyperlynx software. With the ability to create
industry-standard model definition files quickly, you can build accurate simulations
that can provide data to help improve board-level signal integrity.
The I/Os IBIS and HSPICE model creation available in the Quartus II software can
help prevent problems before a costly board respin is required. In general, creating
and running accurate simulations is difficult and time consuming. The tools in the
Quartus II software automate the I/O model setup and creation process by
configuring the models specifically for your design. With these tools, you can set up
and run accurate simulations quickly and acquire data that helps guide your FPGA
and board design.
The information about signal integrity in this chapter refers to board-level signal
integrity based on I/O buffer configuration and board parameters, not simultaneous
switching noise (SSN), also known as ground bounce or VCC sag. SSN is a product of
multiple output drivers switching at the same time, causing an overall drop in the
voltage of the chips power supply. This can cause temporary glitches in the specified
level of ground or VCC for the device.
f For a more information about SSN and ways to prevent it, refer to AN 315: Guidelines
for Designing High-Speed FPGA PCBs.
63
This chapter is intended for FPGA and board designers and includes details about the
concepts and steps involved in getting designs simulated and how to adjust designs
to improve board-level timing and signal integrity. Also included is information about
how to create accurate models from the Quartus II software and how to use those
models in simulation software.
The information in this chapter is meant for those who are familiar with the
Quartus II software and basic concepts of signal integrity and the design techniques
and components in good PCB design. Finally, you should know how to set up
simulations and use your selected third-party simulation tool.
f For information about basic signal integrity concepts and signal integrity details
pertaining to Altera FPGA devices, refer to the Altera Signal Integrity Center.
IBIS Model
HSPICE Model
I/O Buffer
Description
Model
Customization
Simulation Set Up
and Run Time
Simulation
Accuracy
Third-Party Tool
Support
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f For more information about IBIS files created by the Quartus II IBIS Writer and IBIS
files in general, as well as links to websites with detailed information, refer to AN 283:
Simulating Altera Devices with IBIS Models.
65
This chapter is organized around the type of model, IBIS or HSPICE, that you use for
your simulations. When you understand the steps in the analysis flow, refer to the
section of this chapter that corresponds to the model type you are using.
Figure 61. Third-Party Board Signal Integrity Analysis Flow
Create a Quartus II Project
Customize Files
No
IBIS
IBIS or
HSPICE?
Changes
to FPGA I/O
required?
HSPICE
Run Simulations as
Defined in HSPICE Deck
Run Simulation
Results
OK?
No
Make Adjustments to
Models or Simulation Parameters
and Simulate Again
Yes
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To configure a board trace model, in the Settings dialog box, in the TimeQuest
Timing Analyzer page, turn on the Enable Advanced I/O Timing option and
configure the board trace model assignment settings for each I/O standard used in
your design. You can add series or parallel termination, specify the transmission line
length, and set the value of the far-end capacitive load. You can configure these
parameters either in the Board Trace Model view of the Pin Planner, or click Device
and Pin Options in the Device page of the Settings dialog box.
f For information about how to use the Enable Advanced I/O Timing option and
configure board trace models for the I/O standards used in your design, refer to the
I/O Management chapter in volume 2 of the Quartus II Handbook.
The Quartus II software can generate IBIS models and HSPICE decks without having
to configure a board trace model with the Enable Advanced I/O Timing option. In
fact, IBIS models ignore any board trace model settings other than the far-end
capacitive load. If any load value is set other than the default, the delay given by IBIS
models generated by the IBIS Writer cannot be used to account correctly for the
double counting problem. The load value mismatch between the IBIS delay and the
tCO measurement of the Quartus II software prevents the delays from being safely
added together. Warning messages displayed when the EDA Netlist Writer runs
indicate when this mismatch occurs.
67
describes your board design more accurately. A default simulation included in the
generated HSPICE decks measures delay between the FPGA and the far-end device.
You can make additions or adjustments to the default simulation in the generated files
to change the parameters of the default simulation or to perform additional
measurements.
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4
Rise
Fall
L_pkg
C_comp
R_pkg
C_pkg
69
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If you made any changes from the default load settings, the delay in the generated
IBIS model cannot safely be added to the Quartus II tCO measurement to account for
the double counting problem. This is because the load values between the two delay
measurements do not match. When this happens, the Quartus II software displays
warning messages when the EDA Netlist Writer runs to remind you about the load
value mismatch.
h For step-by-step instructions on how to generate IBIS models with the Quartus II
software, refer to Generating IBIS Output Files with the Quartus II Software in Quartus II
Help.
f For more information about IBIS model generation, refer to the AN 283: Simulating
Altera Devices with IBIS Models or to the Quartus II Help.
611
A more robust and expandable way to create a circuit schematic for simulation is to
use the free-form schematic format in LineSim as shown in Figure 63. The free-form
schematic format makes it easy to place parts into any configuration and edit them as
required. This section describes the use of IBIS models with free-form schematics, but
the process is nearly identical for cell-based schematics.
Figure 63. HyperLynx LineSim Free-Form Schematic Editor
When you use HyperLynx software to perform simulations, you typically perform the
following steps:
1. Create a new LineSim free-form schematic document and set up the board stackup
for your PCB using the Stackup Editor. In this editor, specify board layer
properties including layer thickness, dielectric constant, and trace width.
2. Create a circuit schematic for the net you want to simulate. The schematic
represents all the parts of the routed net including source and destination I/O
buffers, termination components, transmission line segments, and representations
of impedance discontinuities such as vias or connectors.
3. Assign IBIS models to the source and destination I/O buffers to represent their
behavior during operation.
4. Attach probes from the digital oscilloscope that is built in to LineSim to points in
the circuit that you want to monitor during simulation. Typically, at least one
probe is attached to the pin of a destination I/O buffer. For differential signals, you
can attach a differential probe to both the positive and negative pins at the
destination.
5. Configure and run the simulation. You can simulate a rising or falling edge and
test the circuit under different drive strength conditions.
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6. Interpret the results and make adjustments. Based on the waveforms captured in
the digital oscilloscope, you can adjust anything in the circuit schematic to correct
any signal integrity issues, such as overshoot or ringing. If necessary, you can
make I/O assignment changes in the Quartus II software, regenerate the IBIS file
with the IBIS Writer, and apply the updated IBIS model to the buffers in your
HyperLynx software schematic.
7. Repeat the simulations and circuit adjustments until you are satisfied with the
results. When the operation of the net meets your design requirements, implement
changes to your I/O assignments in the Quartus II software and/or adjust your
board routing constraints, component values, and placement to match the
simulation.
f For more information about HyperLynx software, including schematic creation,
simulation setup, model usage, product support, licensing, and training, refer to
HyperLynx Help or the Mentor Graphics website at www.mentor.com.
613
2. Click Edit. A dialog box appears where you can add directories and adjust the
order in which LineSim searches them (Figure 65).
Figure 65. LineSim Select Directories Dialog Box
3. Click Add
4. Browse to the default IBIS model location, <project directory>/board/ibis. Click OK.
5. Click Up to move the IBIS model directory to the top of the list. Click Generate
Model Index to update LineSims model database with the models found in the
added directory.
6. Click OK. The IBIS model directory for your project is added to the top of the
Model-library file path(s) list.
7. To close the Set Directories dialog box, click OK.
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1. Double-click a buffer symbol in your schematic to open the Assign Models dialog
box (Figure 66). You can also click Assign Models from the buffer symbols
right-click menu.
Figure 66. LineSim Assign Model Dialog Box
2. The pin of the buffer symbol you selected should be highlighted in the Pins list. If
you want to assign a model to a different symbol or pin, select it from the list.
3. Click Select. The Select IC Model dialog box appears (Figure 67).
Figure 67. LineSim Select IC Model Dialog Box
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4. To filter the list of available libraries to display only IBIS models, select .IBS. Scroll
through the Libraries list, and click the name of the library for your design. By
default, this is <project name>.ibs.
5. The device for your design should be selected as the only item in the Devices list.
If not, select your device from the list.
6. From the Signal list, select the name of the signal you want to simulate. You can
also choose to select by device pin number.
7. Click OK. The Assign Models dialog box displays the selected .ibs file and signal.
8. If applicable to the signal you chose, adjust the buffer settings as required for the
simulation.
9. Select and configure other buffer pins from the Pins list in the same manner.
10. Click OK when all I/O models are assigned.
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If you see a discontinuity or other anomalies at the destination, such as slow rise and
fall times (as shown in Figure 69), adjust the termination scheme or termination
component values. After making these changes, rerun the simulation to check
whether your adjustments solved the problem. In this case, it is not necessary to
regenerate the .ibs file.
Figure 69. Example of Signal Integrity Anomaly in HyperLynx with IBIS Models
f For more information about board-level signal integrity and to learn about ways to
improve it with simple changes to your design, visit the Altera Signal Integrity Center.
617
Output
Single-Ended
Differential
Stratix III
Stratix II GX
(non-HSSI pins)
Stratix II
Device
HardCopy
II
Cyclone III
If you are using a Stratix II device for your design, you can turn on Enable Advanced
I/O Timing and configure the board trace model for each I/O standard used in your
design. Newer families have this feature turned on by default and it cannot be turned
off. The HSPICE files include the board trace description you create in the Board Trace
Model view in the Pin Planner or the Board Trace Model tab in the Device and Pin
Options dialog box.
f For more information about the Enable Advanced I/O Timing option and
configuring board trace models for the I/O standards in your design, refer to the
I/O Management chapter in volume 2 of the Quartus II Handbook.
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FPGA Output
Buffer
FPGA Pin
Termination Network/
Trace Model
Signal
Destination
Quartus II tCO
HSPICE models for board simulation measure tPD (propagation delay) from an
arbitrary reference point in the output buffer, through the device pin, out along the
board routing, and ending at the signal destination.
It is apparent immediately that if these two delays were simply added together, the
delay between the output buffer and the device pin would be counted twice in the
calculation. A model or simulation that does not account for this double count would
create overly pessimistic simulation results, because the double-counted delay can
limit I/O performance artificially. To fix the problem, it might seem that simply
subtracting the overlap between tCO and tPD would account for the double count.
However, this adjustment would not be accurate because each measurement is based
on a different load.
1
Input signals do not exhibit this problem because the HSPICE models for inputs stop
at the FPGA pin instead of at the input buffer. In this case, simply adding the delays
together produces an accurate measurement of delay timing.
619
FPGA Output
Buffer
FPGA Pin
Quartus
Test Load
Termination Network/
Trace Model
Signal
Destination
Quartus II tCO
Total Delay
With tTESTLOAD known, the total delay for the output signal from the FPGA logic to the
signal destination on the board, accounting for the double count, is calculated as
shown in Equation 61.
Equation 61.
t delay = t CO + ( t PD t TESTLOAD )
The preconfigured simulation files generated by the HSPICE Writer in the Quartus II
software are designed to account for the double-counting problem based on this
calculation automatically. Performing accurate timing simulations is easy without
having to make adjustments for double counting manually.
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You must perform both Analysis & Synthesis and Fitting on a design before invoking
the HSPICE Writer tool.
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The <output_directory> option specifies the location where HSPICE model files are
saved. By default, the <project directory>/board/hspice directory is used.
To invoke the HSPICE Writer tool through the command line, type the syntax shown
in Example 63.
Example 63. Invoke HSPICE Writer
quartus_eda.exe <project_name> --board_signal_integrity=on --format=HSPICE \
--output_directory=<output_directory>
<output_directory> specifies the location where the generated spice decks will be
written (relative to the design directory). This is an optional parameter and defaults to
board/hspice.
You must replace the example load with a load that matches the design of your PCB
board. This includes a trace model, termination resistors, and, for output simulations,
a receiver model. The spice circuit node that represents the pin of the FPGA package is
called pin. The node that represents the far pin of the external device is called load-in
(for output SPICE decks) and source-in (for input SPICE decks).
623
For an input simulation, you must also modify the stimulus portion of the spice file.
The section of the file that must be modified is indicated in the comment block shown
in Example 65.
Example 65. Sample Source Stimulus Section
* Sample source stimulus placeholder
* - Replace this with your I/O driver model
Replace the sample stimulus model with a model for the device that will drive the
FPGA.
Click Open and browse to the location of the HSPICE model files generated by the
Quartus II HSPICE Writer. The default location for HSPICE model files is <project
directory>/board/hspice. Select the .sp file generated by the HSPICE Writer for the
signal you want to simulate. Click OK.
To run the simulation, click Simulate. The status of the simulation is displayed in the
window and saved in an .lis file with the same name as the .sp file when the
simulation is complete. Check the .lis file if an error occurs during the simulation
requiring a change in the .sp file to fix.
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To see the waveforms for the simulation, in the HSPICE user interface window, click
AvanWaves. The AvanWaves viewer opens and displays the Results Browser as
shown in Figure 614.
Figure 614. HSPICE AvanWaves Results Browser
The Results Browser lets you select which waveform to view quickly in the main
viewing window. If multiple simulations are run on the same signal, the list at the top
of the Results Browser displays the results of each simulation. Click the simulation
description to select which simulation to view. By default, the descriptions are
derived from the first line of the HSPICE file, so the description might appear as a line
of asterisks.
Select the type of waveform to view, by performing the following steps:
1. To see the source and destination waveforms with the default simulation, from the
Types list, select Voltages.
2. On the Curves list, double-click the waveform you want to view. The waveform
appears in the main viewing window.
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You can zoom in and out and adjust the view as desired (Figure 615).
Figure 615. AvanWaves Waveform Viewer
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f For more information about board-level signal integrity and to learn about ways to
improve it with simple changes to your FPGA design, refer to the Altera Signal
Integrity Center.
Header Comment
The first block of an input simulation spice deck is the header comment. The purpose
of this block is to provide an easily readable summary of how the simulation file has
been automatically configured by the Quartus II software.
This block has two main components: The first component summarizes the I/O
configuration relevant information such as device, speed grade, and so on. The
second component specifies the exact test condition that the Quartus II software
assumes for the given I/O standard. Example 66 shows a header comment block.
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EP2S60F1020C3
C3
AA4 (out96)
IO Bank 6 (Row I/O)
LVTTL, 12mA
Off
Quartus IIs default I/O timing delays assume the following slow
corner simulation conditions.
Specified Test Conditions For Quartus II Tco
Temperature:
85C (Slowest Temperature Corner)
Transistor Model: TT (Typical Transistor Corner)
Vccn:
3.135V (Vccn_min = Nominal - 5%)
Vccpd:
2.97V (Vccpd_min = Nominal - 10%)
Load:
No Load
Vtt:
1.5675V (Voltage reference is Vccn/2)
Note: The I/O transistors are specified to operate at least as
fast as the TT transistor corner, actual production
devices can be as fast as the FF corner. Any simulations
for hold times should be conducted using the fast process
corner with the following simulation conditions.
Temperature:
0C (Fastest Commercial Temperature Corner **)
Transistor Model: FF (Fastest Transistor Corner)
Vccn:
1.98V (Vccn_hold = Nominal + 10%)
Vccpd:
3.63V (Vccpd_hold = Nominal + 10%)
Vtt:
0.95V (Vtt_hold = Vccn/2 - 40mV)
Vcc:
1.25V (Vcc_hold = Maximum Recommended)
Package Model:
Short-circuit from pad to pin (no parasitics)
Warnings:
Simulation Conditions
The simulation conditions block loads the appropriate process corner models for the
transistors. This condition is automatically set up for the slow timing corner and is
modified only if other simulation corners are desired. Example 67 shows a
simulation conditions block.
Example 67. Simulation Conditions Block
* Process Settings
.options brief
.inc sii_tt.inc * TT process corner
Simulation Options
The simulation options block configures the simulation temperature and configures
HSPICE with typical simulation options. Example 68 shows a simulation options
block.
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brief=0
badchr co=132 scale=1e-6 acct ingold=2 nomod dv=1.0
dcstep=1 absv=1e-3 absi=1e-8 probe csdf=2 accurate=1
converge=1
Constant Definition
The constant definition block of the simulation file instantiates the voltage sources
that controls the configuration modes of the I/O buffer. Example 69 shows a constant
definition block.
Example 69. Constant Definition Block
* Constant Definition
voeb
vopdrain
vrambh
vrpullup
vpcdp5
vpcdp4
vpcdp3
vpcdp2
vpcdp1
vpcdp0
vpcdn4
vpcdn3
vpcdn2
vpcdn1
vpcdn0
vdin din
oeb
opdrain
rambh
rpullup
rpcdp5
rpcdp4
rpcdp3
rpcdp2
rpcdp1
rpcdp0
rpcdn4
rpcdn3
rpcdn2
rpcdn1
rpcdn0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
vc
0
0
0
rp5
rp4
rp3
rp2
rp1
rp0
rn4
rn3
rn2
rn1
rn0
*
*
*
*
*
Set
Set
Set
Set
Set
Where:
Voltage source voeb controls the output enable of the buffer and is set to disabled
for inputs.
The next 11 voltages sources control the I/O standard of the buffer and are
configured through a later library call.
vdin is not used on input pins because it is the data pin for the output buffer.
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Buffer Netlist
The buffer netlist block (Example 610) of the simulation spice deck loads all the load
models required for the corresponding input pin.
Example 610. Buffer Netlist Block
* IO Buffer Netlist
.include vio_buffer.inc
Drive Strength
The drive strength block (Example 611) of the simulation SPICE deck loads the
configuration bits necessary to configure the I/O into the proper I/O standard and
drive strengths. Although these settings are not relevant to an input buffer, they are
provided to allow the SPICE deck to be modifiable to support bidirectional
simulations.
Example 611. Drive Strength Block
* Drive Strength Settings
.lib drive_select_hio.lib 3p3ttl_12ma
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*
*
*
*
*
FPGA core
FPGA core
IO supply
IO ground
Pre-drive
voltage
ground
voltage
supply voltage
Stimulus Model
The stimulus model block of the simulation spice deck is provided only as a place
holder example (shown in Example 614). Replace this block with your own stimulus
model. Options for this include an IBIS or HSPICE model, among others.
Example 614. Stimulus Model Block
* Sample source stimulus placeholder
* - Replace this with your I/O driver model
Vsource source 0 pulse(0 vcn 0s 0.4ns 0.4ns 8.5ns 17.4ns)
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Simulation Analysis
The simulation analysis block (Example 615) of the simulation file is configured to
measure the propagation delay from the source to the FPGA pin. Both the source and
end point of the delay are referenced against the 50% VCCN crossing point of the
waveform.
Example 615. Simulation Analysis Block
* Simulation Analysis Setup
* Print out the voltage waveform at both the source and the pin
.print tran v(source) v(pin)
.tran 0.020ns 17ns
* Measure the propagation delay from the source pin to the pin
* referenced against the 50% voltage threshold crossing point
.measure TRAN
+ TARG v(pin)
.measure TRAN
+ TARG v(pin)
Header Comment
The first block of an output simulation SPICE deck is the header comment, as shown
in Example 616. The purpose of this block is to provide a readable summary of how
the simulation file has been automatically configured by the Quartus II software.
This block has two main components:
The first component summarizes the I/O configuration relevant information such
as device, speed grade, and so on.
The second component specifies the exact test condition that the Quartus II
software assumes when generating tCO delay numbers. This information is used as
part of the double-counting correction circuitry contained in the simulation file.
The SPICE decks are preconfigured to calculate the slow process corner delay but can
also be used to simulate the fast process corner as well. The fast corner conditions are
listed in the header under the notes section.
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The final section of the header comment lists any warning messages that you must
consider when you use the SPICE decks.
Example 616. Header Comment Block
* Quartus II HSPICE Writer I/O Simulation Deck
*
* This spice simulation deck was automatically generated by
* Quartus II for the following IO settings:
*
* Device:
EP2S60F1020C3
* Speed Grade: C3
* Pin:
AA4 (out96)
* Bank:
IO Bank 6 (Row I/O)
* I/O Standard: LVTTL, 12mA
* OCT:
Off
*
* Quartus default I/O timing delays assume the following slow
* corner simulation conditions.
* Specified Test Conditions For Quartus II Tco
*
Temperature:
85C (Slowest Temperature Corner)
*
Transistor Model: TT (Typical Transistor Corner)
*
Vccn:
3.135V (Vccn_min = Nominal - 5%)
*
Vccpd:
2.97V (Vccpd_min = Nominal - 10%)
*
Load:
No Load
*
Vtt:
1.5675V (Voltage reference is Vccn/2)
* For C3 devices, the TT transistor corner provides an
* approximation for worst case timing. However, for functionality
* simulations, it is recommended that the SS corner be simulated
* as well.
*
* Note: The I/O transistors are specified to operate at least as
*
fast as the TT transistor corner, actual production
*
devices can be as fast as the FF corner. Any simulations
*
for hold times should be conducted using the fast process
*
corner with the following simulation conditions.
*
Temperature:
0C (Fastest Commercial Temperature Corner
**)
*
Transistor Model: FF (Fastest Transistor Corner)
*
Vccn:
1.98V (Vccn_hold = Nominal + 10%)
*
Vccpd:
3.63V (Vccpd_hold = Nominal + 10%)
*
Vtt:
0.95V (Vtt_hold = Vccn/2 - 40mV)
*
Vcc:
1.25V (Vcc_hold = Maximum Recommended)
*
Package Model:
Short-circuit from pad to pin
* Warnings:
Simulation Conditions
The simulation conditions block (Example 617) loads the appropriate process corner
models for the transistors. This condition is automatically set up for the slow timing
corner and must be modified only if other simulation corners are desired.
635
Two separate corners cannot be simulated at the same time. Instead, simulate the base
case using the Quartus corner as one simulation and then perform a second
simulation using the desired customer corner. The results of the two simulations can
be manually added together.
Example 617. Simulation Conditions Block
* Process Settings
.options brief
.inc sii_tt.inc * typical-typical process corner
Simulation Options
The simulation options block (Example 618) configures the simulation temperature
and configures HSPICE with typical simulation options.
f For a detailed description of these options, consult your HSPICE manual.
Example 618. Simulation Options Block
* Simulation Options
.options brief=0
.options badchr co=132 scale=1e-6 acct ingold=2 nomod dv=1.0
+
dcstep=1 absv=1e-3 absi=1e-8 probe csdf=2 accurate=1
+
converge=1
.temp 85
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Constraint Definition
The constant definition block (Example 619) of the output simulation SPICE deck
instantiates the voltage sources that controls the configuration modes of the I/O
buffer.
Example 619. Constant Definition Block
* Constant Definition
voeb
vopdrain
vrambh
vrpullup
vpci
vpcdp4
vpcdp3
vpcdp2
vpcdp1
vpcdp0
vpcdn4
vpcdn3
vpcdn2
vpcdn1
vpcdn0
vdin
oeb
opdrain
rambh
rpullup
rpci
rpcdp4
rpcdp3
rpcdp2
rpcdp1
rpcdp0
rpcdn4
rpcdn3
rpcdn2
rpcdn1
rpcdn0
din
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Where:
The next ten voltage sources control the I/O standard of the buffer and are configured through a later
library call. Stratix III and Cyclone III devices have more bits and so might have more voltage sources
listed in the constant definition block. They also have slew rate and delay chain settings.
The edge rate of the input stimulus is automatically set to the correct value by the Quartus II software.
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Drive Strength
The drive strength block (Example 621) of the simulation spice deck loads the
configuration bits for configuring the I/O to the proper I/O standard and drive
strength. These options are set by the HSPICE Writer tool and are not changed for
expected use.
Example 621. Drive Strength Block
* Drive Strength Settings
.lib drive_select_hio.lib 3p3ttl_12ma
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*
*
*
*
*
FPGA core
FPGA core
IO supply
IO ground
Pre-drive
voltage
ground
voltage
supply voltage
639
0
0
0
* Instantiate
vvccn_tl
vvssn_tl
vvccpd_tl
vcn_tl
0
vpd_tl
Power Supplies
vccn_tl
0
vssn_tl
0
vccpd_tl
0
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Simulation Analysis
The simulation analysis block (Example 626) is set up to measure double-counting
corrected delays. This is accomplished by measuring the uncompensated delay of the
I/O buffer when connected to the user load, and when subtracting the simulated
amount of double-counting from the test load I/O buffer.
Example 626. Simulation Analysis Block
*Simulation Analysis Setup
* Print out the voltage waveform at both the pin and far end load
.print tran v(pin) v(load)
.tran 0.020ns 17ns
* Measure the propagation delay to the load pin. This value will
* include some double counting with Quartus IIs Tco
.measure TRAN tpd_uncomp_rise TRIG v(din) val=vc*0.5 rise=1
+ TARG v(load) val=vcn*0.5 rise=1
.measure TRAN tpd_uncomp_fall TRIG v(din) val=vc*0.5 fall=1
+ TARG v(load) val=vcn*0.5 fall=1
* The test load buffer can calculate the amount of double counting
.measure TRAN t_dblcnt_rise TRIG v(din) val=vc*0.5 rise=1
+ TARG v(pin_tl) val=vcn_tl*0.5 rise=1
.measure TRAN t_dblcnt_fall TRIG v(din) val=vc*0.5 fall=1
+ TARG v(pin_tl) val=vcn_tl*0.5 fall=1
* Calculate the true propagation delay by subtraction
.measure TRAN tpd_rise PARAM=tpd_uncomp_rise-t_dblcnt_rise
.measure TRAN tpd_fall PARAM=tpd_uncomp_fall-t_dblcnt_fall
Advanced Topics
The information in this section describes some of the more advanced topics and
methods employed when setting up and running HSPICE simulation files.
PVT Simulations
The automatically generated HSPICE simulation files are set up to simulate the slow
process corner using low voltage, high temperature, and slow transistors. To ensure a
fully robust link, Altera recommends that you run simulations over all process
corners.
To perform process, voltage, and temperature (PVT) simulations, manually modify
the spice decks in a two step process:
641
1. Remove the double-counting compensation circuitry from the simulation file. This
is required as the amount of double-counting is dependant upon how the
Quartus II software calculates delays and is not based on which PVT corner is
being simulated. By default, the Quartus II software provides timing numbers
using the slow process corner.
2. Select the proper corner for the PVT simulation by setting the correct HSPICE
temperature, changing the supply voltage sources, and loading the correct
transistor models.
A more detailed description of HSPICE process corners can be found in the
family-specific HSPICE model documentation. This document is available online with
the HSPICE models as described in Accessing HSPICE Simulation Kits on
page 617.
This method of hold time analysis is recommended only for globally synchronous
buses. Do not apply this method of hold-time analysis to source synchronous buses.
This is because the source synchronous clocking scheme is designed to cancel out
some of the PVT timing effects. If this is not taken into account, the timing results will
not be accurate. Proper source synchronous timing analysis is beyond the scope of this
document.
Correlation Report
Correlation reports for the HSPICE I/O models are located in the family-specific
HSPICE I/O buffer simulation kits. Refer to Accessing HSPICE Simulation Kits on
page 617 for additional information.
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Conclusion
As FPGA devices are used in more high-speed applications, it becomes increasingly
necessary to perform board-level signal integrity analysis simulations. You must run
such simulations to ensure good signal integrity between the FPGA and any
connected devices. The Quartus II software helps to simplify this process with the
ability to automatically generate I/O buffer description models easily with the IBIS
and HSPICE Writers. IBIS models can be integrated into a third-party signal integrity
analysis workflow using a tool such as Mentor Graphics HyperLynx software,
generating quick and accurate simulation results. HSPICE decks include
preconfigured simulations and only require descriptions of board routing and
stimulus models to create highly accurate simulation results using Synopsys HSPICE.
Either type of simulation helps prevent unnecessary board spins, increasing your
productivity and decreasing your costs.
Version
Changes
June 2012
12.0.0
November 2011
10.0.2
Template update.
December 2010
10.0.1
Template update.
July 2010
10.0.0
November 2009
9.1.0
No change to content.
March 2009
9.0.0
November 2008
May 2008
8.1.0
8.0.0
No change to content.
Updated Invoking HSPICE Writer from the Command Line on page 1222.
Added Sample Input for I/O HSPICE Simulation Deck on page 1229.
Added Sample Output for I/O HSPICE Simulation Deck on page 1233.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
This chapter discusses how the Quartus II software interacts with the Mentor
Graphics I/O Designer software and the DxDesigner software to provide a complete
FPGA-to-board design workflow.
With todays large, high-pin-count and high-speed FPGA devices, good and correct
PCB design practices are essential to ensure correct system operation. The PCB design
takes place concurrently with the design and programming of the FPGA. The FPGA
or ASIC designer initially creates signal and pin assignments, and the board designer
must correctly transfer these assignments to the symbols in their system circuit
schematics and board layout. As the board design progresses, Altera recommends
reassigning pins to optimize the PCB layout. Ensure that you inform the FPGA
designer of the pin reassignments so that the new assignments are included in an
updated placement and routing of the design.
The Mentor Graphics I/O Designer software allows you to take advantage of the full
FPGA symbol design, creation, editing, and back-annotation flow supported by the
Mentor Graphics tools.
This chapter covers the following topics:
Performing design flow between the Quartus II software, the Mentor Graphics
I/O Designer software, and the DxDesigner software
Updating signal and pin assignment changes between the I/O Designer software
and the Quartus II software
Creating symbols in the DxDesigner software from the Quartus II software output
files without the use of the I/O Designer software
This chapter is intended for board design and layout engineers who want to start the
FPGA board integration while the FPGA is still in the design phase. Alternatively, the
board designer can plan the FPGA pin-out and routing requirements in the Mentor
Graphics tools and pass the information back to the Quartus II software for placement
and routing. Part librarians can also benefit from this chapter by learning how to use
output from the Quartus II software to create new library parts and symbols.
The procedures in this chapter require the following software:
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Feedback Subscribe
72
f To obtain and license the Mentor Graphics tools and for product information, support,
and training, refer to the Mentor Graphics website (www.mentor.com).
Import Pin
Assignments
Using I/O
Designer?
I/O Designer
No
Yes
Create or Update
I/O Designer
Database (.fpc)
Set Up to Generate
FPGA Xchange File (.fx)
Create or Change
Pin Assignments
Regenerate .fx
Generate Symbol
DxDesigner
Create New or Open
Existing Project
.pin
Generate Symbol
Instantiate Symbol
in Schematic
Forward to Board
Layout Tool
Board Layout Tool
Yes Back-Annotate
Changes
No
End
To perform the design flow shown in Figure 71, follow these steps:
1. In the Quartus II software, set up the board-level assignment settings to generate
an .fx for symbol generation.
2. Compile your design to generate the .fx and Pin-Out File (.pin). You can locate the
generated .fx and .pin files in the Quartus II project directory.
73
3. Create a board design with the DxDesigner software and the I/O Designer
software by performing the following steps:
a. Create a new I/O Designer database based on the .fx and the .pin files.
b. In the I/O Designer software, make adjustments to signal and pin assignments.
c. Regenerate the .fx in the I/O Designer software to export the I/O Designer
software changes to the Quartus II software.
d. Generate a single or fractured symbol for use in the DxDesigner software.
e. Add the symbol to the sym directory of a DxDesigner project, or specify a new
DxDesigner project with the new symbol.
f. Instantiate the symbol in your DxDesigner schematic and export the design to
the board layout tool.
g. Back-annotate pin changes created in the board layout tool to the DxDesigner
software and back to the I/O Designer software and the Quartus II software.
4. Create a board design with the DxDesigner software without the I/O Designer
software by performing the following steps:
a. Create a new DxBoardLink symbol with the Symbol wizard and reference the
.pin from the Quartus II software in an existing DxDesigner project.
b. Instantiate the symbol in your DxDesigner schematic and export the design to
a board layout tool.
1
You can update these symbols with design changes with or without the I/O Designer
software. If you use the Mentor Graphics I/O Designer software and you change
symbols with the DxDesigner software, you must reimport the symbols into
I/O Designer to avoid overwriting your symbol changes.
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Pin number
Signal direction
I/O standard
Voltage
I/O bank
User or Fitter-assigned
The .fx is an input/output file generated by the Quartus II software and the I/O
Designer software that can be imported and exported from both programs. The .fx
generated by the Quartus II software lists only assigned pins and provides the
following advanced information fields for each pin on a device:
Pin number
I/O bank
Signal name
Signal direction
I/O standard
Termination enabling
Slew rate
IOB delay
Swap group
The .fx generated by the I/O Designer software lists all pins, including unused pins.
In addition to the advanced information fields listed above, the .fx generated by the
Mentor Graphics I/O Designer software also includes the following information
fields:
Pin set
75
f For more information about .fx files and the information fields added by the Mentor
Graphics software, refer to FPGA Xchange-Format File (.fx) Definition in Quartus II
Help and Mentor Graphics website (www.mentor.com) respectively.
The I/O Designer software can also read from or update a Quartus II Settings File
(.qsf). The design flow uses the .qsf in a similar manner to the .fx, but does not
transfer pin swap group information between the I/O Designer software and the
Quartus II software.
1
Because the .qsf contains additional information about your project that the Mentor
Graphics I/O Designer software does not use, Altera recommends using the .fx
instead of the .qsf.
h For more information about the .qsf, refer to Quartus II Settings File (.qsf) Definition in
Quartus II Help.
Import Pin
Assignments
Set Up to Generate
.fx
.pin
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f For more information about pin and signal assignment transfer and the files that the
Quartus II software can import and export, refer to the I/O Management chapter in
volume 2 of the Quartus II Handbook.
77
Figure 73 shows the design flow using the I/O Designer software.
Figure 73. Design Flow Using the I/O Designer Software
(1)
I/O Designer
Create or Update
.fpc
Create or Change
Pin Assignments
.fx
Regenerate .fx
Generate Symbol
DxDesigner
Create New or Open
Existing Project (2)
.pin
Instantiate Symbol
in Schematic
Forward to Board
Layout Tool
Board Layout Tool
Yes Back-Annotate
Changes
No
End
f For more information about the I/O Designer software, and to obtain usage, support,
and product updates, use the Help menu in the I/O Designer software or refer to the
Mentor Graphics website (www.mentor.com).
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You can create an I/O Designer database with only a .pin or an .fx. However, if you
are only using a .pin, you cannot import any I/O assignment changes made in the
I/O Designer software back into the Quartus II software without first generating an
.fx. If an .fx creates the I/O Designer database, the database may not contain all the
available I/O assignment information. The .fx generated by the Quartus II software
only lists pins with assigned signals. Because the .pin lists all device pinswhether
signals are assigned to them or notits use, along with the .fx, produces the most
complete set of information for creating the I/O Designer database.
If you skip a step in the following process, you can complete the skipped step later. To
return to a skipped step, on the Properties menu, click File. To create a new
I/O Designer database using the Database wizard, follow these steps:
1. Start the I/O Designer software. The Welcome to I/O Designer dialog box
appears. Select Wizard to create new database and click OK.
1
If the Welcome to I/O Designer dialog box does not appear, you can access
the wizard through the menu. To access the wizard, on the File menu, click
Database Wizard.
If no HDL files are available, or if the .fx contains your signal and pin
assignments, you can skip Step 3 and proceed to Step 4.
f For more information about creating and using HDL files in the Quartus II
software, refer to the Recommended HDL Coding Styles chapter in volume 1
of the Quartus II Handbook, or refer to the I/O Designer Help.
3. If you have created a Verilog HDL or VHDL file in your Quartus II software
design, you can add a top-level Verilog HDL or VHDL file in the I/O Designer
software. Adding a file allows you to create functional blocks or get signal names
from your design. You must create all physical pin assignments in I/O Designer if
you are not using an .fx or a .pin. Click Next. The Database Name page appears.
4. In the Database Name page, type your database file name. Click Next. The
Database Location window appears.
5. Add a path to the new or an existing database in the Location field, or browse to a
database location. Click Next. The FPGA flow page appears.
6. In the Vendor menu, click Altera.
7. In the Tool/Library menu, click Quartus II 5.0, or a later version of the Quartus II
software.
8. Select the appropriate device family, device, package, and speed (if applicable),
from the corresponding menus. Click Next. The Place and route page appears.
1
79
use the latest version listed in the menu. If the device you are targeting does
not appear in the device menu after making this selection, the device may
be new and not yet added to the I/O Designer software. For I/O Designer
software updates, contact Mentor Graphics or refer to their website
(www.mentor.com).
9. In the FPGAX file name field, type or browse to the backup copy of the .fx
generated by the Quartus II software.
10. In the Pin report file name field, type or browse to the .pin generated by the
Quartus II software. Click Next.
You can also select a .qsf for update. The I/O Designer software can update the
pin assignment information in the .qsf without affecting any other information in
the file.
1
You can select a .pin without selecting an .fx for import. The I/O Designer
software does not generate a .pin. To transfer assignment information to the
Quartus II software, select an additional file and file type. Altera
recommends selecting an .fx in addition to a .pin for transferring all the
assignment information in the .fx and .pin files.
In some versions of the I/O Designer software, the standard file picker may
incorrectly look for a .pin instead of an .fx. In this case, select All Files (*.*)
from the Save as type list and select the file from the list.
11. The Synthesis page appears. On the Synthesis page, you can specify an external
synthesis tool and a synthesis constraints file for use with the tool. If you do not
use an external synthesis tool, click Next.
f For more information about third-party synthesis tools, refer to Volume 3:
Verification of the Quartus II Handbook.
12. On the PCB Flow page, you can select an existing schematic project or create a
new project as a symbol information destination.
To select an existing project, select Choose existing project and click Browse
after the Project Path field. The Select project dialog box appears. Select the
project.
To create a new project, in the Select project dialog box, select Create new
empty project. Type the project file name in the Name field and browse to the
location where you want to save the file. Click OK.
If you have not specified a design tool to which you can send symbol information in
the I/O Designer software, click Advanced in the PCB Flow page and select your
design tool. If you select the DxDesigner software, you have the option to specify a
Hierarchical Occurrence Attributes (.oat) file to import into the I/O Designer
software. Click Next and then click Finish to create the database.
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In I/O Designer version 2005 or later, the Update Wizard dialog box (refer to
Figure 77 on page 713) appears if you are creating the database with the Database
wizard. Use the Update Wizard dialog box to confirm creation of the I/O Designer
database using the selected .fx and .pin files.
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Use the I/O Designer software and your newly created database to make pin
assignment changes, create pin swap groups, or adjust signal and pin properties in the
I/O Designer GUI (Figure 74).
Figure 74. Mentor Graphics I/O Designer Main Window
f For more information about using the I/O Designer software and the DxDesigner
software, refer to the Mentor Graphics website (www.mentor.com) or refer to the
I/O Designer software or the DxDesigner Help.
711
(1)
I/O Designer
Create or Update
.fpc
Create or Change
Pin Assignments
.fx
.pin
Regenerate .fx
Generate Symbol
To update the .fx in your selected output directory and the .pin in your project
directory after making changes to the design, perform one of the following tasks:
compile, or
You must rerun the I/O Assignment Analyzer whenever you make I/O changes in
the Quartus II software. To rerun the I/O Assignment Analyzer, perform one of the
following tasks:
f For more information about setting up the .fx and running the I/O Assignment
Analyzer, refer to the I/O Management chapter in volume 2 of the Quartus II Handbook.
c If your I/O Designer database points to the .fx generated by the Quartus II software
instead of a backup copy of the file, updating the file in the Quartus II software
overwrites any changes made to the file by the I/O Designer software. If there are
I/O Designer assignments in the .fx that you want to preserve, create a backup copy
of the file before updating it in the Quartus II software, and verify that your
I/O Designer database points to the backup copy. To point to the backup copy,
perform the steps in the following section.
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Whenever you update the .fx or the .pin in the Quartus II software, the I/O Designer
database imports the changes. You must set up the locations for the files in the
I/O Designer software.
1. To set up the file locations, on the File menu, click Properties. The project
Properties dialog box appears (Figure 76).
Figure 76. Project Properties Dialog Box
2. Under FPGA Xchange, click Browse to select the .fx file name and location.
3. To specify a Pin report file, under Place and Route, click Browse to select the .pin
file name and location.
After you have set up these file locations, the I/O Designer software monitors these
files for changes. If the .fx or .pin changes during the design flow, three indicators
flash red in the lower right corner of the I/O Designer GUI (refer to Figure 74 on
page 710). You can continue working or click on the indicators to open the
I/O Designer Update Wizard dialog box. If you have made changes to your design in
the Quartus II software that result in an updated .fx or .pin and the update indicators
do not flash or you have previously canceled an indicated update, manually open the
Update Wizard dialog box. To open the Update Wizard dialog box, on the File menu,
click Update.
713
The I/O Designer Update Wizard dialog box lists the updated files associated with
the database (Figure 77).
Figure 77. Update Wizard Dialog Box
The paths to the updated files have yellow exclamation points and the Status column
shows Not updated, indicating that the database has not yet been updated with the
newer information contained in the files. A checkmark to the left of any updated file
indicates that the file updates the database. Turn on any files you want to use to
update the I/O Designer database, and click Next. If you are not satisfied with the
database update, on the Edit menu, click Undo.
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You can update the I/O Designer database using the .fx and the .pin files
simultaneously. Turning on the .fx and the .pin files for update causes the Update
Wizard dialog box to provide options for using assignments from one file or the other
exclusively or merging the assignments contained in both files into the I/O Designer
database. Versions of the I/O Designer software older than version 2005 merge
assignments contained in multiple files.
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Import Pin
Assignments
I/O Designer
Set Up to Generate
.fx
Create or Update
.fpc
(1)
(1)
Create or Change
Pin Assignments
.fx
Regenerate .fx
Generate
r
Symbol
(2)
You can make pin assignment changes directly in the I/O Designer software, or the
software can automatically update changes made in a board layout tool that are
back-annotated to a schematic entry program such as the DxDesigner software. You
must update the .fx to reflect these updates in the Quartus II software. To perform this
update in the I/O Designer software, on the Generate menu, click FPGA Xchange
File.
c If your I/O Designer database points to the .fx generated by the Quartus II software
instead of a backup copy, updating the file from the I/O Designer software overwrites
any changes made to the file by the Quartus II software. If there are assignments from
the Quartus II software in the file that you want to preserve, create a backup copy of
the file before updating it in the I/O Designer software, and verify that your
I/O Designer database points to the backup copy. To point to the backup copy,
perform the steps in Updating Pin Assignments from the Quartus II Software on
page 711.
715
You must import the updated .fx into the Quartus II software. To import the file,
follow these steps:
1. Start the Quartus II software and open your project.
2. On the Assignments menu, click Import Assignments.
3. In the File name box, click Browse and from the Files of type list, select FPGA
Xchange Files (*.fx).
4. Select the .fx and click Open.
5. Click OK.
Manually
The I/O Designer Symbol wizard can be used as a design base that allows you to
quickly create a symbol for manual editing at a later time. If you have created symbols
in a DxDesigner project and want to apply a different FPGA design to them, you can
manually import these symbols from the DxDesigner project. To import the symbols,
start the I/O Designer software, and on the File menu, click Import Symbol.
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f For more information about importing symbols from the DxDesigner software into an
I/O Designer database, refer to the I/O Designer Help.
Symbols created in the I/O Designer software are either functional, physical (PCB), or
both. Signals imported into the database, usually from Verilog HDL or VHDL files,
are the basis of a functional symbol. No physical device pins must be associated with
the signals to generate a functional symbol. This section focuses on board-level PCB
symbols with signals directly mapped to physical device pins through assignments in
either the Quartus II Pin Planner or in the I/O Designer database.
f For more information about manually creating, importing, and editing symbols in the
I/O Designer software, as well as the different types of symbols the software can
generate, refer to the I/O Designer Help.
Setting Up the I/O Designer Software to Work with the DxDesigner Software
To verify if you are set up to export symbols to a DxDesigner project, or to manually
set up the I/O Designer software to work with the DxDesigner software, you must set
the path to the DxDesigner executable, set the export type to DxDesigner, and set the
path to a DxDesigner project directory.
To set these options, follow these steps:
1. Start the I/O Designer software.
2. On the Tools menu, click Preferences. The Preferences dialog box appears.
3. Click Paths, double-click on the DxDesigner executable file path field, and click
Browse to select the location of the DxDesigner application (Figure 79).
4. Click Apply.
Figure 79. Path Preferences Dialog Box
5. Click Symbol Editor and click Export. In the Export type menu, under General,
select DxDesigner/PADS-Designer (Figure 710).
717
7. On the File menu, click Properties. The Properties dialog box appears.
8. Click the PCB Flow tab and click Path to a DxDesigner project directory.
9. Click OK.
If you do not have a new DxDesigner project in the Database wizard and a
DxDesigner project, you must create a new database with the DxDesigner software,
and point the I/O Designer software to this new project.
f For more information about creating and working with DxDesigner projects, refer to
the DxDesigner Help.
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2. Click Symbol Wizard in the toolbar, or on the Symbol menu, click Symbol
Wizard. The Symbol Wizard (1 of 6) page appears (Figure 711).
Figure 711. Symbol Wizard
3. On page 1 of the Symbol Wizard page, in the Symbol name field, type the symbol
name. The DEVICE and PKG_TYPE fields are automatically populated with the
device and package information. Under Symbol type, click PCB. Under Use
signals, click All.
4. Click Next. The Symbol Wizard (2 of 6) page appears.
1
If the DEVICE and PKG_TYPE fields are blank or incorrect, cancel the
Symbol wizard and select the correct device information. On the File menu,
click Properties. In the Properties window, click the FPGA Flow tab and
enter the correct device information.
5. On page 2 of the Symbol Wizard page, select fracturing options for your symbol.
If you are using the Symbol wizard to edit a previously created fractured symbol,
you must turn on Reuse existing fractures to preserve your current fractures.
Select other options on this page as appropriate for your symbol.
6. Click Next. The Symbol Wizard (3 of 6) page appears.
7. Additional fracturing options are available on page 3 of the Symbol Wizard page.
After selecting the necessary options, click Next. The Symbol Wizard (4 of 6) page
appears.
8. On page 4 of the Symbol Wizard page, select the options for the appearance of the
symbols. Select the necessary options and click Next. The Symbol Wizard (5 of 6)
page appears.
719
9. On page 5 of the Symbol Wizard page, define what information you want to label
for the entire symbol and for individual pins. Select the necessary options and
click Next. The Symbol Wizard (6 of 6) page appears.
10. On the final page of the Symbol Wizard page, add additional signals and pins that
have not been placed in the symbol. Click Finish when you complete your
selections.
You can view your symbol and any fractures you created with the Symbol Editor
(Figure 712). You can edit parts of the symbol, delete fractures, or rerun the Symbol
wizard.
Figure 712. The I/O Designer Symbol Editor
If assignments in the I/O Designer database are updated, the symbols created in the
I/O Designer software automatically reflect these changes. Assignment changes can
be made in the I/O Designer software, with an updated .fx from the Quartus II
software, or from a back-annotated change in your board layout tool.
Scripting Support
The I/O Designer software features a command line Tcl interpreter. All commands
issued through the GUI in the I/O Designer software translate into Tcl commands run
by the tool. You can view the generated Tcl commands and run scripts, or type
individual commands in the I/O Designer Console window.
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This scripting support section includes commands that perform some of the
operations described in this chapter.
If you want to change the .fx from which the I/O Designer software updates
assignments, type the following command at an I/O Designer Tcl prompt:
set_fpga_xchange_file <file name>
You can type the following command to update the I/O Designer database with
assignment updates made in the Quartus II software after specifying the .fx:
update_from_fpga_xchange_file
You can type the following command to update the .fx with changes made to the
assignments in the I/O Designer software for transfer back into the Quartus II
software:
generate_fpga_xchange_file
You can type the following command if you want to import assignment data from a
.pin created by the Quartus II software:
set_pin_report_file -quartus_pin <file name>
You can run the I/O Designer Symbol wizard with the following command:
symbolwizard
You can set the DxDesigner project directory path where symbols are saved with the
following command:
set_dx_designer_project -path <path>
f For more information about Tcl scripting and Tcl scripting with the Quartus II
software, refer to the Tcl Scripting chapter in volume 2 of the Quartus II Handbook. For
more information about the Tcl scripting capabilities of the I/O Designer software as
well as a list of available commands, refer to the I/O Designer Help.
721
You can only make signal and pin assignment changes in the Quartus II software and
these changes reflect as updated symbols in a DxDesigner schematic. You cannot
back-annotate changes made in a board layout tool or in a DxDesigner symbol to the
Quartus II software. Figure 713 shows the design flow without the I/O Designer
software.
Figure 713. Design Flow Without the I/O Designer Software
(1)
DxDesigner
Create New or Open
Existing Project
.pin
Generate Symbol
Instantiate in
Schematic
Forward to Board
Layout Tool
f For more information about the DxDesigner software, including usage, support,
training, and product updates, refer to the Mentor Graphics website
(www.mentor.com), or choose Schematic Design Help Topics in the DxDesigner Help.
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2. On the File menu, click New and click the Project tab. The New dialog box
appears (Figure 714).
Figure 714. New Project Dialog Box
723
4. On the Wizard Task Selection page, choose to create a new symbol or modify an
existing symbol. If you are modifying an existing symbol, specify the library path
or alias, and select the existing symbol. If you are creating a new symbol, select
DxBoardLink for the symbol source. The DxDesigner block type defaults to
Module because the FPGA design does not have an underlying DxDesigner
schematic. Choose whether or not to fracture the symbol. After making your
selections, click Next. The New Symbol and Library Name page appears.
5. On the New Symbol and Library Name page, type a name for the symbol, an
overall part name for all the symbol fractures, and a library name for the new
library created for this symbol. By default, the part and library names are the same
as the symbol name. Click Next. The Symbol Parameters page appears.
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6. On the Symbol Parameters page, specify the appearance of the generated symbol
and how it matches up with the grid you have set in your DxDesigner project
schematic. After making your selections, click Next. The DxBoardLink Pin List
Import page appears (Figure 717).
Figure 717. DxBoardLink Pin List Import
7. On the DxBoardLink Pin List Import page, in the FPGA vendor list, select Altera
Quartus. In the Pin-Out file to import field, browse to and select the .pin from
your Quartus II design project directory. You can also select choices from the
Fracturing Scheme, Bus pin, and Power pin options. After making your selections,
click Next. The Symbol Attributes page appears.
8. On the Symbol Attributes page, select to create or modify symbol attributes for
use in the DxDesigner software. After making your selections, click Next. The Pin
Settings page appears.
9. On the Pin Settings page, make any final adjustments to pin and label location
and information. Each tabbed spreadsheet represents a fracture of your symbol.
After making your selections, click Save Symbol.
After creating the symbol, you can examine and place any fracture of the symbol in
your schematic. You can locate separate files of all the fractures you created in the
library you specified or created in the /sym directory in your DxDesigner project. You
can add the symbols to your schematics or you can manually edit the symbols or with
the Symbol wizard.
725
Symbols created in the DxDesigner software can be edited and updated with newer
versions of the .pin generated by the Quartus II software. However, you cannot
fracture a symbol again because symbol fracturing is permanent. To create new
fractures for your design, create a new symbol in the Symbol wizard, and perform the
steps in DxDesigner Symbol Wizard on page 723.
f For more information about creating, editing, and instantiating component symbols
in DxDesigner, choose Schematic Design Help Topics from the Help menu in the
DxDesigner software.
Conclusion
Transferring a complex, high-pin-count FPGA design to a PCB for prototyping or
manufacturing is a daunting process that can lead to errors in the PCB netlist or
design, especially when multiple engineers are working on different parts of the
project. The design workflow available when using the Quartus II software with the
Mentor Graphics toolset assists the FPGA designer and the board designer in
preventing errors and focusing their attention on the design.
Version
Changes
June 2012
12.0.0
November 2011
10.0.2
Template update.
December 2010
10.0.1
Template update.
July 2010
10.0.0
November 2009
Removed Figures that were numbered 6-4, 6-6, 6-7, and 6-8 in v8.1.0.
9.1.0
March 2009
9.0.0
November 2008
8.1.0
May 2008
8.0.0
Updated references.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
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This chapter addresses how the Quartus II software interacts with the Cadence
Allegro Design Entry HDL software and the Cadence Allegro Design Entry CIS
(Component Information System) software (also known as OrCAD Capture CIS) to
provide a complete FPGA-to-board integration design workflow.
With todays large, high-pin-count and high-speed FPGA devices, good PCB design
practices are important to ensure the correct operation of your system. The PCB
design takes place concurrently with the design and programming of the FPGA. An
FPGA or ASIC designer initially creates the signal and pin assignments and the board
designer must transfer these assignments to the symbols used in their system circuit
schematics and board layout correctly. As the board design progresses, you must
perform pin reassignments to optimize the layout. You must communicate pin
reassignments to the FPGA designer to ensure the new assignments are processed
through the FPGA with updated placement and routing.
This chapter is intended for board design and layout engineers who want to begin the
FPGA board integration process while the FPGA is still in the design phase. Part
librarians can also benefit from this chapter by learning the method to use output
from the Quartus II software to create new library parts and symbols.
This chapter discusses the following topics:
The general design flow between the Quartus II software and the Cadence Allegro
Design Entry HDL software and the Cadence Allegro Design Entry CIS software.
Generating schematic symbols from your FPGA design for use in the Cadence
Allegro Design Entry HDL software.
Updating Design Entry HDL symbols when making signal and pin assignment
changes in the Quartus II software.
Creating schematic symbols in the Cadence Allegro Design Entry CIS software
from your FPGA design.
Updating symbols in the Cadence Allegro Design Entry CIS software when
making signal and pin assignment changes in the Quartus II software.
Using Altera-provided device libraries in the Cadence Allegro Design Entry CIS
software.
The Cadence Allegro Design Entry HDL software or the Cadence Allegro Design
Entry CIS software version 15.2 or later
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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82
The OrCAD Capture software with the optional CIS option version 10.3 or later
(optional)
These programs are very similar because the Cadence Allegro Design Entry CIS
software is based on the OrCAD Capture software. This chapter refers to the Cadence
Allegro Design Entry CIS software; however, any procedural information can also
apply to the OrCAD Capture software unless otherwise noted.
f For more information about obtaining and licensing the Cadence tools and for
product information, support, and training, refer to the Cadence website
(www.cadence.com). For more information about the OrCAD Capture software and
the CIS option, refer to the Cadence website (www.cadence.com). For more
information about Cadence and OrCAD support and training, refer to the EMA
Design Automation website (www.ema-eda.com).
Product Comparison
The Cadence and OrCAD design tools are different in their function and location of
product information. Table 81 lists the Cadence and OrCAD products described in
this chapter and provides information about changes, product information, and
support.
Table 81. Cadence and OrCAD Product Comparison
Description
Cadence Allegro
Design Entry HDL
Cadence Allegro
Design Entry CIS
Former Name
www.cadence.com
www.cadence.com
www.cadence.com
www.ema-eda.com
www.ema-eda.com
www.ema-eda.com
History
Vendor Design
Flow
Information
and Support
83
Project Manager
Create or Open a Project
Create or Change
Pin Assignments
Part Developer
Run I/O Assignment
Analysis
Run Full
Compilation
End
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Figure 82. Design Flow with the Cadence Allegro Design Entry CIS Software
Start PCB Design
(Allegro Design Entry CIS)
Create or Change
Pin Assignments
Run Full
Compilation
End
Figure 81 and Figure 82 show the possible design flows, depending on your tool
choice. To create FPGA symbols using the Cadence Allegro PCB Librarian Part
Developer tool, you must obtain the Cadence PCB Librarian Expert license. You can
update symbols with changes made to the FPGA design using any of these tools.
To integrate an Altera FPGA design starting in the Quartus II software through to a
circuit schematic in the Cadence Allegro Design Entry HDL software or the Cadence
Allegro Design Entry CIS software, follow these steps:
1. In the Quartus II software, compile your design to generate a Pin-Out File (.pin) to
transfer the assignments to the Cadence software.
2. If you are using the Cadence Allegro Design Entry HDL software for your
schematic design, follow these steps:
a. Open an existing project or create a new project in the Cadence Allegro Project
Manager tool.
b. Construct a new symbol or update an existing symbol using the Cadence
Allegro PCB Librarian Part Developer tool.
c. With the Cadence Allegro PCB Librarian Part Developer tool, edit your symbol
or fracture it into smaller parts (optional).
d. Instantiate the symbol in your Cadence Allegro Design Entry HDL software
schematic and transfer the design to your board layout tool.
or
If you are using the Cadence Allegro Design Entry CIS software for your
schematic design, follow these steps:
a. Generate a new part in a new or existing Cadence Allegro Design Entry CIS
project, referencing the .pin output file from the Quartus II software. You can
also update an existing symbol with a new .pin.
85
Pin number
Signal direction
I/O standard
Voltage
I/O bank
User or Fitter-assigned
f For more information about using the Quartus II Pin Planner to create or change pin
assignment details, refer to the I/O Management chapter in volume 2 of the Quartus II
Handbook.
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f For more information about pin and signal assignment transfer and the files that the
Quartus II software can import and export, refer to the I/O Management chapter in
volume 2 of the Quartus II Handbook.
Routing or pin assignment changes made in a board layout tool or a Cadence Allegro
Design Entry HDL software symbol cannot be back-annotated to the Quartus II
software.
f For more information about the Cadence Allegro Design Entry HDL software and the
Cadence Allegro PCB Librarian Part Developer tool, including licensing, support,
usage, training, and product updates, refer to the Help in the software or to the
Cadence website (www.cadence.com).
Creating Symbols
In addition to circuit simulation, circuit board schematic creation is one of the first
tasks required when designing a new PCB. Schematics must understand how the PCB
works, and to generate a netlist for a board layout tool for board design and routing.
The Cadence Allegro PCB Librarian Part Developer tool allows you to create
schematic symbols based on FPGA designs exported from the Quartus II software.
You can create symbols for the Cadence Allegro Design Entry HDL project with the
Cadence Allegro PCB Librarian Part Developer tool, which is available in the Cadence
Allegro Project Manager tool. Altera recommends using the Cadence Allegro PCB
Librarian Part Developer tool to import FPGA designs into the Cadence Allegro
Design Entry HDL software.
You must obtain a PCB Librarian Expert license from Cadence to run the Cadence
Allegro PCB Librarian Part Developer tool. The Cadence Allegro PCB Librarian Part
Developer tool provides a GUI with many options for creating, editing, fracturing,
and updating symbols. If you do not use the Cadence Allegro PCB Librarian Part
Developer tool, you must create and edit symbols manually in the Symbol Schematic
View in the Cadence Allegro Design Entry HDL software.
87
If you do not have a PCB Librarian Expert license, you can automatically create FPGA
symbols using the programmable IC (PIC) design flow found in the Cadence Allegro
Project Manager tool. For more information about using the PIC design flow, refer to
the Help in the Cadence design tools, or go to the Cadence website
(www.cadence.com).
Before creating a symbol from an FPGA design, you must open a Cadence Allegro
Design Entry HDL project with the Cadence Allegro Project Manager tool. If you do
not have an existing Cadence Allegro Design Entry HDL project, you can create one
with the Cadence Allegro Design Entry HDL software. The Cadence Allegro Design
Entry HDL project directory with the name <project name>.cpm contains your
Cadence Allegro Design Entry HDL projects.
While the Cadence Allegro PCB Librarian Part Developer tool refers to symbol
fractures as slots, the other tools described in this chapter use different names to refer
to symbol fractures. Table 82 lists the symbol fracture naming conventions for each
of the tools addressed in this chapter.
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Cadence Allegro
Design Entry HDL
Software
Cadence Allegro
Design Entry
CIS Software
Slots
Sections
Versions
Parts
88
Part Developer
Import or Update Pin
Assignments
.pin
F ward to Board La
Forw
ayout Tool
T
Board Layout Tool
Layout and Route FPGA
End
To run the Cadence Allegro PCB Librarian Part Developer tool, you must open a
Cadence Allegro Design Entry HDL project in the Cadence Allegro Project Manager
tool. To open the Cadence Allegro PCB Librarian Part Developer tool, on the Flows
menu, click Library Management, and then click Part Developer.
Import and Export Wizard
After starting the Cadence Allegro PCB Librarian Part Developer tool, use the Import
and Export wizard to import your pin assignments from the Quartus II software.
1
Altera recommends using your PCB Librarian Expert license file. To point to your
PCB Librarian Expert license file, on the File menu, click Change Product and then
select the correct product license.
To access the Import and Export wizard, follow these steps:
1. On the File menu, click Import and Export.
2. Select Import ECO-FPGA, and then click Next.
89
3. In the Select Source page of the Import and Export wizard, specify the following
settings:
a. In the Vendor list, select Altera.
b. In the PnR Tool list, select quartusII.
c. In the PR File box, browse to select the .pin in your Quartus II project directory.
d. Click Simulation Options to select simulation input files.
e. Click Next.
4. In the Select Destination dialog box, specify the following settings:
a. Under Select Component, click Generate Custom Component to create a new
component in a library,
or
Click Use standard component to base your symbol on an existing component.
1
b. In the Library list, select an existing library. You can select from the cells in the
selected library. Each cell represents all the symbol versions and part fractures
for a particular part. In the Cell list, select the existing cell to use as a base for
your part.
c. In the Destination Library list, select a destination library for the component.
Click Next.
d. Review and edit the assignments you import into the Cadence Allegro PCB
Librarian Part Developer tool based on the data in the .pin and then click
Finish. The location of each pin is not included in the Preview of Import Data
page of the Import and Export wizard, but input pins are on the left side of the
created symbol, output pins on the right, power pins on the top, and ground
pins on the bottom.
Editing and Fracturing Symbol
After creating your new symbol in the Cadence Allegro PCB Librarian Part Developer
tool, you can edit the symbol graphics, fracture the symbol into multiple slots, and
add or change package or symbol properties.
The Part Developer Symbol Editor contains many graphical tools to edit the graphics
of a particular symbol. To edit the symbol graphics, select the symbol in the cell
hierarchy. The Symbol Pins tab appears. You can edit the preview graphic of the
symbol in the Symbol Pins tab.
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Fracturing a Cadence Allegro PCB Librarian Part Developer package into separate
symbol slots is useful for FPGA designs. A single symbol for most FPGA packages
might be too large for a single schematic page. Splitting the part into separate slots
allows you to organize parts of the symbol by function, creating cleaner circuit
schematics. For example, you can create one slot for an I/O symbol, a second slot for a
JTAG symbol, and a third slot for a power/ground symbol.
Figure 84 shows a part fractured into separate slots.
Figure 84. Splitting a Symbol into Multiple Slots
(2)
DCLK
DATA0
NCONFIG
NCE
clk
clkx2
follow
newt
yvalid
MSEL0
MSEL1
Slot 1
VCCIO4
VCCIO3
filtref
CONF_DONE
NSTATUS
ASDO
NCSO
filtref NCEO
TDO
VCCA_PLL1
VCCA_PLL2
GNDA_PLL1
GNDA_PLL2
GNDG_PLL1
GNDG_PLL2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TDI
TMS
TCK
reset
VCCIO2
filtref
VCCIO1
yn_out[7..0]
VCCINT
d[7..0]
(Notes 1),
Slot 2
Slot 3
To fracture a part into separate slots, or to modify the slot locations of pins on parts
fractured in the Cadence Allegro PCB Librarian Part Developer tool, follow these
steps:
1. Start the Cadence Allegro Design Project Manager.
2. On the Flows menu, click Library Management.
3. Click Part Developer.
4. Click the name of the package you want to change in the cell hierarchy.
5. Click Functions/Slots. If you are not creating new slots but want to change the slot
location of some pins, proceed to Step 6. If you are creating new slots, click Add. A
dialog box appears, allowing you to add extra symbol slots. Set the number of
extra slots you want to add to the existing symbol, not the total number of desired
slots for the part. Click OK.
6. Click Distribute Pins. Specify the slot location for each pin. Use the checkboxes in
each column to move pins from one slot to another. Click OK.
7. After distributing the pins, click the Package Pin tab and click Generate
Symbol(s).
811
8. Select whether to create a new symbol or modify an existing symbol in each slot.
Click OK.
The newly generated or modified slot symbols appear as separate symbols in the cell
hierarchy. Each of these symbols can be edited individually.
c The Cadence Allegro PCB Librarian Part Developer tool allows you to remap pin
assignments in the Package Pin tab of the main Cadence Allegro PCB Librarian Part
Developer window. If signals remap to different pins in the Cadence Allegro PCB
Librarian Part Developer tool, the changes reflect only in regenerated symbols for use
in your schematics. You cannot transfer pin assignment changes to the Quartus II
software from the Cadence Allegro PCB Librarian Part Developer tool, which creates
a potential mismatch of the schematic symbols and assignments in the FPGA design.
If pin assignment changes are necessary, make the changes in the Quartus II Pin
Planner instead of the Cadence Allegro PCB Librarian Part Developer tool, and
update the symbol as described in the following sections.
f For more information about creating, editing, and organizing component symbols
with the Cadence Allegro PCB Librarian Part Developer tool, refer to the Part
Developer Help.
Updating FPGA Symbols
As the design process continues, you must make logic changes in the Quartus II
software, placing signals on different pins after recompiling the design, or use the
Quartus II Pin Planner to make changes manually. The board designer can request
such changes to improve the board routing and layout. To ensure signals connect to
the correct pins on the FPGA, you must carry forward these types of changes to the
circuit schematic and board layout tools. Updating the .pin in the Quartus II software
facilitates this flow. Figure 85 shows this part of the design flow.
Figure 85. Updating the FPGA Symbol in the Design Flow
(1)
Part Developer
Import or Update Pin
Assignments
.pin
End
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To update the symbol using the Cadence Allegro PCB Librarian Part Developer tool
after updating the .pin, follow these steps:
1. On the File menu, click Import and Export. The Import and Export wizard
appears.
2. In the list of actions to perform, select Import ECO - FPGA. Click Next. The Select
Source dialog box appears.
3. Select the updated source of the FPGA assignment information. In the Vendor list,
select Altera. In the PnR Tool list, select quartusII. In the PR File field, click
browse to specify the updated .pin in your Quartus II project directory. Click
Next. The Select Destination window appears.
4. Select the source component and a destination cell for the updated symbol. To
create a new component based on the updated pin assignment data, select
Generate Custom Component. Selecting Generate Custom Component replaces
the cell listed under the Specify Library and Cell name header with a new,
nonfractured cell. You can preserve these edits by selecting Use standard
component and select the existing library and cell. Select the destination library
for the component and click Next. The Preview of Import Data dialog box
appears.
5. Make any additional changes to your symbol. Click Next. A list of ECO messages
appears summarizing the changes made to the cell. To accept the changes and
update the cell, click Finish.
6. The main Cadence Allegro PCB Librarian Part Developer window appears. You
can edit, fracture, and generate the updated symbols as usual from the main
Cadence Allegro PCB Librarian Part Developer window.
1
If the Cadence Allegro PCB Librarian Part Developer tool is not set up to point to your
PCB Librarian Expert license file, an error message appears in red at the bottom of the
message text window of the Part Developer when you select the Import and Export
command. To point to your PCB Librarian Expert license, on the File menu, click
Change Product, and select the correct product license.
Instantiating the Symbol in the Cadence Allegro Design Entry HDL Software
To instantiate the symbol in your Cadence Allegro Design Entry HDL schematic after
saving the new symbol in the Cadence Allegro PCB Librarian Part Developer tool,
follow these steps:
1. In the Cadence Allegro Project Manager tool, switch to the board design flow.
2. On the Flows menu, click Board Design.
3. To start the Cadence Allegro Design Entry HDL software, click Design Entry.
4. To add the newly created symbol to your schematic, on the Component menu,
click Add. The Add Component dialog box appears.
5. Select the new symbol library location, and select the name of the cell you created
from the list of cells.
The symbol attaches to your cursor for placement in the schematic. To fracture the
symbol into slots, right-click the symbol and choose Version to select one of the slots
for placement in the schematic.
813
f For more information about the Cadence Allegro Design Entry HDL software,
including licensing, support, usage, training, and product updates, refer to the Help
in the software or go to the Cadence website (www.cadence.com).
Routing or pin assignment changes made in a board layout tool or a Cadence Allegro
Design Entry CIS symbol cannot be back-annotated to the Quartus II software.
f For more information about the Cadence Allegro Design Entry CIS software,
including licensing, support, usage, training, and product updates, refer to the Help
in the software, go to the Cadence (www.cadence.com) or go to the EMA Design
Automation website (www.ema-eda.com).
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Generating a Part
After you create a new project or open an existing project in the Cadence Allegro
Design Entry CIS software, you can generate a new schematic symbol based on your
Quartus II FPGA design. You can also update an existing symbol. The Cadence
Allegro Design Entry CIS software stores component symbols in OrCAD Library File
(.olb). When you place a symbol in a library attached to a project, it is immediately
available for instantiation in the project schematic.
You can add symbols to an existing library or you can create a new library specifically
for the symbols generated from your FPGA designs. To create a new library, follow
these steps:
1. On the File menu, point to New and click Library in the Cadence Allegro Design
Entry CIS software to create a default library named library1.olb. This library
appears in the Library folder in the Project Manager window of the Cadence
Allegro Design Entry CIS software.
2. To specify a desired name and location for the library, right-click the new library
and select Save As. Saving the new library creates the library file.
You can now create a new symbol to represent your FPGA design in your schematic.
To generate a schematic symbol, follow these steps:
1. Start the Cadence Allegro Design Entry CIS software.
2. On the Tools menu, click Generate Part. The Generate Part dialog box appears
(Figure 86).
Figure 86. Generate Part Dialog Box
3. To specify the .pin from your Quartus II design, in the Netlist/source file type
field, click Browse.
4. In the Netlist/source file type list, select Altera Pin File.
815
f For more information about creating and editing symbols in the Cadence Allegro
Design Entry CIS software, refer to the Help in the software.
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Splitting a Part
After saving a new symbol in a project library, you can fracture the symbol into
multiple parts called sections. Fracturing a part into separate sections is useful for
FPGA designs. A single symbol for most FPGA packages might be too large for a
single schematic page. Splitting the part into separate sections allows you to organize
parts of the symbol by function, creating cleaner circuit schematics. For example, you
can create one slot for an I/O symbol, a second slot for a JTAG symbol, and a third slot
for a power/ground symbol. Figure 88 shows a part fractured into separate sections.
Figure 88. Splitting a Symbol into Multiple Sections (Notes 1),
DCLK
DATA0
NCONFIG
NCE
clk
clkx2
follow
newt
yvalid
MSEL0
MSEL1
Section 1
VCCIO4
VCCIO3
filtref
CONF_DONE
NSTATUS
ASDO
NCSO
filtref NCEO
TDO
VCCA_PLL1
VCCA_PLL2
GNDA_PLL1
GNDA_PLL2
GNDG_PLL1
GNDG_PLL2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TDI
TMS
TCK
reset
VCCIO2
filtref
VCCIO1
yn_out[7..0]
VCCINT
d[7..0]
(2)
Section 2
Section 3
Although symbol generation in the Design Entry CIS software refers to symbol
fractures as sections, the other tools described in this chapter use different names to
refer to symbol fractures.
817
To split a part into sections, select the part in its library in the Project Manager
window of the Cadence Allegro Design Entry CIS software. On the Tools menu, click
Split Part or right-click the part and choose Split Part. The Split Part Section Input
Spreadsheet appears (Figure 89).
Figure 89. Split Part Section Input Spreadsheet
Each row in the spreadsheet represents a pin in the symbol. The Section column
indicates the section of the symbol to which each pin is assigned. You can locate all
pins in a new symbol in section 1. You can change the values in the Section column to
assign pins to various sections of the symbol. You can also specify the side of a section
on the location of the pin by changing the values in the Location column. When you
are ready, click Split. A new symbol appears in the same library as the original with
the name <original part name>_Split1.
View and edit each section individually. To view the new sections of the part,
double-click the part. The Part Symbol Editor window appears and the first section of
the part displays for editing. On the View menu, click Package to view thumbnails of
all the part sections. To edit the section of the symbol, double-click the thumbnail.
f For more information about splitting parts into sections and editing symbol sections
in the Cadence Allegro Design Entry CIS software, refer to the Help in the software.
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Select the new symbol library location and the newly created part name. If you select
a part that is split into sections, you can select the section to place from the Part
pop-up menu. Click OK. The symbol attaches to your cursor for placement in the
schematic. To place the symbol, click on the schematic page.
f For more information about using the Cadence Allegro Design Entry CIS software,
refer to the Help in the software.
Altera Libraries for the Cadence Allegro Design Entry CIS Software
Altera provides downloadable .olb for many of its device packages. You can add
these libraries to your Cadence Allegro Design Entry CIS project and update the
symbols with the pin assignments contained in the .pin generated by the Quartus II
software. You can use the downloaded library symbols as a base for creating custom
schematic symbols with your pin assignments that you can edit or fracture. This
method increases productivity by reducing the amount of time it takes to create and
edit a new symbol.
To use the Altera-provided libraries with your Cadence Allegro Design Entry CIS
project, follow these steps:
1. Download the library of your target device from the Download Center page found
through the Support page on the Altera website (www.altera.com).
819
2. Create a copy of the appropriate .olb to maintain the original symbols. Place the
copy in a convenient location, such as your Cadence Allegro Design Entry CIS
project directory.
3. In the Project Manager window of the Cadence Allegro Design Entry CIS software,
click once on the Library folder to select it. On the Edit menu, click Project or
right-click the Library folder and choose Add File to select the copy of the
downloaded .olb and add it to your project. You can locate the new library in the
list of part libraries for your project.
4. On the Tools menu, click Generate Part. The Generate Part dialog box appears
(Figure 811).
Figure 811. Generate Part Dialog Box
5. In the Netlist/source file field, click Browse to specify the .pin in your Quartus II
design.
6. From the Netlist/source file type list, select Altera Pin File.
7. For Part name, type the name of the target device the same as it appears in the
downloaded library file. For example, if you are using a device from the
CYCLONE06.OLB library, type the part name to match one of the devices in this
library such as ep1c6f256. You can rename the symbol in the Project Manager
window after updating the part.
8. Set the Destination part library to the copy of the downloaded library you added
to the project.
9. Select Update pins on existing part in library. Click OK.
10. Click Yes.
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The symbol is updated with your pin assignments. Double-click the symbol in the
Project Manager window to view and edit the symbol. On the View menu, click
Package if you want to view and edit other sections of the symbol. If the symbol in the
downloaded library is fractured into sections, you can edit each section but you
cannot further fracture the part. You can generate a new part without using the
downloaded part library if you require additional sections.
f For more information about creating, editing, and fracturing symbols in the Cadence
Allegro Design Entry CIS software, refer to the Help in the software.
Conclusion
Transferring a complex, high-pin-count FPGA design to a PCB for prototyping or
manufacturing is a daunting process and can lead to errors in the PCB netlist or
design, especially when different engineers are working on different parts of the
project. The design workflow available when the Quartus II software is used with
tools from Cadence assists the FPGA designer and the board designer in preventing
such errors and focusing all attention on the design.
Version
Changes
June 2012
12.0.0
November 2011
10.0.2
Template update.
December 2010
10.0.1
Template update.
July 2010
10.0.0
November 2009
9.1.0
No change to content.
March 2009
9.0.0
November 2008
8.1.0
May 2008
8.0.0
Updated references.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
This chapter provides guidelines for reviewing printed circuit board (PCB) schematics
with the Quartus II software. Altera FPGAs and CPLDs offer a multitude of
configurable options to allow you to implement a custom application-specific circuit
on your PCB.
Your Quartus II project provides important information specific to your
programmable logic design, which you can use in conjunction with the device
literature available on Altera's website to ensure that you implement the correct
board-level connections in your schematic.
This chapter highlights the important options in the Quartus II software, including
Settings dialog box options, the Fitter report, and Messages window to which you
should refer when creating and reviewing your PCB schematic. The Quartus II
software also provides useful tools, such as the Pin Planner and the SSN Analyzer, to
assist you during your PCB schematic review process.
The Reviewing Quartus II Software Settingssection provides information about the
settings you can make in the Quartus II software to help you review your PCB
schematic. After verifying options in the Quartus II software, you can compile your
design and use the data generated in the Fitter report, which is described in
Reviewing Device Pin-Out Information in the Fitter Report on page 94 to verify
settings in your PCB schematic. You should also ensure that you carefully review
error and warning messages, as described in Reviewing Compilation Error and
Warning Messages on page 96.
In addition to verifying your settings in the Settings dialog box and Fitter report, and
checking messages, you can turn on additional settings, as described in Using
Additional Quartus II Software Features on page 96 and Running the HardCopy
Design Readiness Check on page 96.
Finally, Quartus II software tools, such as the Pin Planner and the SSN Analyzer,
described in Using Additional Quartus II Software Tools on page 97, help you to
verify proper I/O placement.
You should use this chapter in conjunction with Altera's device family-specific
literature.
f For more information, refer to the Schematic Review Worksheets and the Pin
Connection Guidelines pages of the Altera.com website.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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92
Chapter 9: Reviewing Printed Circuit Board Schematics with the Quartus II Software
Reviewing Quartus II Software Settings
Chapter 9: Reviewing Printed Circuit Board Schematics with the Quartus II Software
Reviewing Quartus II Software Settings
93
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Chapter 9: Reviewing Printed Circuit Board Schematics with the Quartus II Software
Reviewing Device Pin-Out Information in the Fitter Report
Chapter 9: Reviewing Printed Circuit Board Schematics with the Quartus II Software
Reviewing Device Pin-Out Information in the Fitter Report
95
Figure 91 shows the pins the Fitter chose for the OCT external calibration resistor
connections (RUP/RDN) and the name of the associated termination block in the
Input Pins report. You should make these types of assignments user assignments.
Figure 91. Resource Section Report
The I/O Bank Usage report provides a high-level overview of the VCCIO and VREF
requirements for your design, based on your I/O assignments. Verify that the
requirements in this report match the settings in your PCB schematic. All unused I/O
banks, and all banks with I/O pins with undefined I/O standards, default the VCCIO
voltage to the voltage defined in the Voltage page of the Device and Pin Options
dialog box.
The All Package Pins report lists all the pins on your device, including unused pins,
dedicated pins and power/ground pins. You can use this report to verify pin
characteristics, such as the location, name, usage, direction, I/O standard and voltage
for each pin with the pin information in your PCB schematic. In particular, you should
verify the recommended voltage levels at which you connect unused dedicated inputs
and I/O and power pins, especially if you selected a migration device. Use the All
Package Pins report to verify that you connected all the device voltage rails to the
voltages reported.
Errors commonly reported include connecting the incorrect voltage to the predriver
supply (VCCPD) pin in a specific bank, or leaving dedicated clock input pins floating.
Unused input pins that should be connected to ground are designated as GND+ in
the Pin Name/Usage column in the All Package Pins report.
You can also use the All Package Pins report to check transceiver-specific pin
connections and verify that they match the PCB schematic. Unused transceiver pins
have the following requirements, based on the pin designation in the Fitter report:
November 2012
GXB_NCUnused GXB transmitter or dedicated clock output pin. This pin must
be disconnected.
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Chapter 9: Reviewing Printed Circuit Board Schematics with the Quartus II Software
Reviewing Compilation Error and Warning Messages
Some transceiver power supply rails have dual voltage capabilities, such as
VCCA_L/R and VCCH_L/R, that depend on the settings you created for the ALTGX
MegaWizard Plug-In Manager. Because these user-defined settings overwrite the
default settings, you should use the All Package Pins report to verify that these power
pins on the device symbol in the PCB schematics are connected to the voltage required
by the transceiver. An incorrect connection may cause the transceiver to function not
as expected.
If your design includes a memory interface, the DQS Summary report provides an
overview of each DQ pin group. You can use this report to quickly confirm that the
correct DQ/DQS pins are grouped together. This section also provides information on
DLL usage.
Finally, the Fitter Device Options report summarizes some of the settings made in the
Device and Pin Options dialog box. Verify that these settings match your PCB
schematics.
Chapter 9: Reviewing Printed Circuit Board Schematics with the Quartus II Software
Using Additional Quartus II Software Tools
97
f For more information about signal integrity analysis in the Quartus II software, refer
to the Signal Integrity Analysis with Third-Party Tools chapter in volume 3 of the
Quartus II Handbook.
Additionally, using advanced I/O timing allows you to enter physical PCB
information to accurately model the load seen by an output pin. This feature
facilitates accurate I/O timing analysis.
f For more information about advanced I/O timing, refer to the I/O Management
chapter in volume 2 of the Quartus II Handbook.
Pin Planner
The Quartus II Pin Planner helps you visualize, plan, and assign device I/O pins in a
graphical view of the target device package. You can quickly locate various I/O pins
and assign them design elements or other properties to ensure compatibility with
your PCB layout.
You can use the Pin Planner to verify the location of clock inputs, and whether they
have been placed on dedicated clock input pins, which is recommended when your
design uses PLLs.
You can also use the Pin Planner to verify the placement of dedicated SERDES pins.
SERDES receiver inputs can be placed only on DIFFIO_RX pins, while SERDES
transmitter outputs can be placed only on DIFFIO_TX pins.
The Pin Planner gives a visual indication of signal-to-signal proximity in the Pad View
window, and also provides information about differential pin pair placement, such as
the placement of pseudo-differential signals.
f For more information about the Pin Planner, refer to the I/O Management chapter in
volume 2 of the Quartus II Handbook.
SSN Analyzer
The SSN Analyzer supports pin planning by estimating the voltage noise caused by
the simultaneous switching of output pins on the device. Because of the importance of
the potential SSN performance for a specific I/O placement, you can use the SSN
Analyzer to analyze the effects of aggressor I/O signals on a victim I/O pin.
f For more information about the SSN Analyzer, refer to the Simultaneous Switching
Noise (SSN) Analysis and Optimizations chapter in volume 2 of the Quartus II Handbook.
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Chapter 9: Reviewing Printed Circuit Board Schematics with the Quartus II Software
Conclusion
Conclusion
This chapter describes guidelines and descriptions of settings to verify when
reviewing your PCB schematic with the Quartus II software. You can use settings in
the Settings dialog box; information in the Fitter report and Messages window; and
the Pin Planner and SSN Analyzer during the PCB schematic review process.
Version
November 2012
12.1.0
Changes
Minor update of Pin Planner description for task and report windows.
June 2012
12.0.0
November 2011
10.0.2
Template update.
December 2010
10.0.1
July 2010
10.0.0
Initial release.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
This section introduces features in the Quartus II software that you can use to
optimize area, timing, power, and compilation time when you design for
programmable logic devices (PLDs).
This section includes the following chapters:
Chapter 15, Analyzing and Optimizing the Design Floorplan with the Chip
Planner
You can use the Chip Planner to perform design analysis and create a design
floorplan. This chapter discusses how to analyze and optimize the design
floorplan with the Chip Planner.
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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Registered
This chapter introduces features in Alteras Quartus II software that you can use to
achieve the highest design performance when you design for programmable logic
devices (PLDs), especially high density FPGAs.
Introduction
Physical implementation can be an intimidating and challenging phase of the design
process. The Quartus II software provides a comprehensive environment for FPGA
designs, delivering unmatched performance, efficiency, and ease-of-use.
In a typical design flow, you must synthesize your design with Quartus II integrated
synthesis or a third-party tool, place and route your design with the Fitter, and use the
TimeQuest timing analyzer to ensure your design meets the timing requirements.
With the PowerPlay Power Analyzer, you ensure the designs power consumption is
within limits.
Device Settings
Device assignments determine the timing model that the Quartus II software uses
during compilation. Choose the correct speed grade to obtain accurate results and the
best optimization. The device size and the package determine the device pin-out and
the available resources in the device.
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I/O Assignments
The I/O standards and drive strengths specified for a design affect I/O timing.
Specify I/O assignments so that the Quartus II software uses accurate I/O timing
delays in timing analysis and Fitter optimizations.
If there is no PCB layout requirement, then you do not need to specify pin locations. If
your pin locations are not fixed due to PCB layout requirements, then leave the pin
locations unconstrained. If your pin locations are already fixed, then make pin
assignments to constrain the compilation appropriately.
f For more information about recommendations for making pin assignments that can
have a large effect on your results in smaller macrocell-based architectures, refer to
Optimizing Resource Utilization (Macrocell-Based CPLDs) in the Timing Closure and
Optimization chapter in volume 2 of the Quartus II Handbook.
Use the Assignment Editor and Pin Planner to assign I/O standards and pin locations.
f For more information about I/O standards and pin constraints, refer to the
appropriate device handbook. For more information about planning and checking
I/O assignments, refer to the I/O Management chapter in volume 2 of the Quartus II
Handbook.
h For information about using the Assignment Editor, refer to About the Assignment
Editor in Quartus II Help.
Correct timing assignments enable the software to work hardest to optimize the
performance of the timing-critical parts of your design and make trade-offs for
performance. This optimization can also save area or power utilization in
non-critical parts of your design.
Depending on the Fitter Effort setting, the Fitter can reduce runtime if your design
meets the timing requirements.
f For more information about optimization with physical synthesis, refer to Physical
Synthesis Optimization in the Timing Closure and Optimization chapter in volume 2 of
the Quartus II Handbook.
h For more information about reducing runtime by changing Fitter effort, refer to Fitter
Settings Page in the Quartus II Help.
Use your real requirements to get the best results. If you apply more demanding
timing requirements than you need, then increased resource usage, higher power
utilization, increased compilation time, or all of these may result.
103
If you already have an .sdc in your project, using the write_sdc command from the
command line or using the Write SDC File option from the TimeQuest GUI allows
you to create a new .sdc that combines the constraints from your current .sdc and any
new constraints added through the GUI or command window, or overwrites the
existing .sdc with your newly applied constraints.
Ensure that every clock signal has an accurate clock setting constraint. If clocks arrive
from a common oscillator, then they are related. Ensure that you set up all related or
derived clocks in the constraints correctly. You must constrain all I/O pins that require
I/O timing optimization. Specify both minimum and maximum timing constraints as
applicable. If your design contains more than one clock or contains pins with different
I/O requirements, make multiple clock settings and individual I/O assignments
instead of using a global constraint. 1
Make any complex timing assignments required in your design, including false path
and multicycle path assignments. Common situations for these types of assignments
include reset or static control signals (when the time required for a signal to reach a
destination is not important) or paths that have more than one clock cycle available
for operation in a design. These assignments enable the Quartus II software to make
appropriate trade-offs between timing paths and can enable the Compiler to improve
timing performance in other parts of your design.
f For more information about timing assignments and timing analysis, refer to The
Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook
and the Quartus II TimeQuest Timing Analyzer Cookbook.
1
To ensure that you apply constraints or assignments to all design nodes, you can
report all unconstrained paths in your design with the Report Unconstrained Paths
command in the Task pane of the Quartus II TimeQuest Timing Analyzer or the
report_ucp Tcl command.
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Using incremental compilation for your design with good design partitioning
methodology helps to achieve timing closure. Creating design partitions on some of
the major blocks in your design and assigning them to LogicLock regions, reduces
Fitter time and improves the quality and repeatability of the results. LogicLock
regions are flexible, reusable floorplan location constraints that help you place logic
on the target device. When you assign entity instances or nodes to a LogicLock region,
you direct the Fitter to place those entity instances or nodes inside the region during
fitting.
h For more information about LogicLock regions, refer to About LogicLock Regions in
Quartus II Help.
Using incremental compilation helps you achieve timing closure block by block and
preserve the timing performance between iterations, which aid in achieving timing
closure for the entire design. Incremental compilation may also help reduce
compilation times.
f For more information, refer to the Incremental Compilation section in the Reducing
Compilation Time chapter in volume 2 of the Quartus II Handbook.
1
If you plan to use incremental compilation, you must create a floorplan for your
design. If you are not using incremental compilation, creating a floorplan is optional.
f For more information about guidelines to create partition and floorplan assignments
for your design, refer to the Best Practices for Incremental Compilation Partitions and
Floorplan Assignments chapter in volume 1 of the Quartus II Handbook.
Physical Implementation
Most optimization issues involve preserving previous results, reducing area, reducing
critical path delay, reducing power consumption, and reducing runtime. The
Quartus II software includes advisors to address each of these issues and helps you
optimize your design. Run these advisors during physical implementation for advice
about your specific design.
You can reduce the time spent on design iterations by following the recommended
design practices for designing with Altera devices. Design planning is critical for
successful design timing implementation and closure.
f For more information, refer to the Design Planning with the Quartus II Software chapter
in volume 1 of the Quartus II Handbook.
105
In addition, system cost and time-to-market considerations can affect the choice of
device. For example, a device with a higher speed grade or more clock networks can
facilitate timing closure at the expense of higher power consumption and system cost.
Finally, not all designs can be realized in a hardware circuit with limited resources and
given constraints. If you encounter resource limitations, timing constraints, or power
constraints that cannot be resolved by the Fitter, consider rewriting parts of the HDL
code.
f For more information, refer to the Timing Closure and Optimization and Area
Optimization chapters in volume 2 of the Quartus II Handbook.
Reducing Area
By default, the Quartus II Fitter might physically spread a design over the entire
device to meet the set timing constraints. If you prefer to optimize your design to use
the smallest area, you can change this behavior. If you require reduced area, you can
enable certain physical synthesis options to modify your netlist to create a more
area-efficient implementation, but at the cost of increased runtime and decreased
performance.
f For more information, refer to the Netlist Optimizations and Physical Synthesis, Timing
Closure and Optimization, and Area Optimization chapters in volume 2 and
the Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook.
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Reducing Runtime
Many Fitter settings influence compilation time. Most of the default settings in the
Quartus II software are set for reduced compilation time. You can modify these
settings based on your project requirements.
107
Design Analysis
The Quartus II software provides tools that help with a visual representation of your
design. You can use the RTL Viewer to see a schematic representation of your design
before synthesis and place-and-route. The Technology Map Viewer provides a
schematic representation of the design implementation in the selected device
architecture after synthesis and place-and-route. It can also include timing
information.
With incremental compilation, the Design Partition Planner and the Chip Planner
allow you to partition and layout your design at a higher level. In addition, you can
perform many different tasks with the Chip Planner, including: making floorplan
assignments, implementing engineering change orders (ECOs), and performing
power analysis. Also, you can analyze your design and achieve a faster timing closure
with the Chip Planner. The Chip Planner provides physical timing estimates, critical
path display, and a routing congestion view to help guide placement for optimal
performance.
f For more information, refer to the Quartus II Incremental Compilation for Hierarchical
and Team-Based Designs and Best Practices for Incremental Compilation Partitions and
Floorplan Assignments chapters in volume 1 and the Engineering Change Management
with the Chip Planner chapter in volume 2 of the Quartus II Handbook.
Advisors
The Quartus II software includes several advisors to help you optimize your design
and reduce compilation time. You can complete your design faster by following the
recommendations in the Compilation Time Advisor, Incremental Compilation
Advisor, Timing Optimization Advisor, Area Optimization Advisor, Resource
Optimization Advisor, and Power Optimization Advisor. These advisors give
recommendations based on your project settings and your design constraints.
h For more information about advisors, refer to Running Advisors in the Quartus II
Software in Quartus II Help.
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Conclusion
The Quartus II software includes a number of features and tools that you can use to
optimize area, timing, power, and compilation time when you design for
programmable logic devices (PLDs).
Version
Changes
13.0.0
Added the Initial Compilation: Required Settings on page 101 section. This section
was moved from the Area Optimization chapter of the Quartus II Handbook.
Minor updates to delineate division of Timing and Area optimization chapters.
June 2012
12.0.0
November 2011
10.0.3
Template update.
December 2010
10.0.2
August 2010
10.0.1
Corrected link
July 2010
10.0.0
Initial release. Chapter based on topics and text in Section III of volume 2.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
The Quartus II software offers several features and techniques to help reduce
compilation time.
This chapter describes techniques to reduce compilation time when designing for
Altera devices, and includes the following topics:
Reducing Synthesis Time and Synthesis Netlist Optimization Time on page 115
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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112
Example 111 shows examples of messages with each time component in two-digit
format, and days shown only if applicable:
Example 111.
Info: Fitter placement operations ending: elapsed time =
<days:hours:minutes:seconds>
Info: Fitter routing operations ending: elapsed time =
<days:hours:minutes:seconds>
Example 112 shows an info message displayed while the Fitter is running (including
Placement and Routing). The Message window displays this message every hour to
indicate Fitter operations are progressing normally.
Example 112.
Info: Placement optimizations have been running for 4 hour(s)
Do not consider processors with Intel Hyper-Threading as more than one processor. If
you have a single processor with Intel Hyper-Threading enabled, you should set the
number of processors to one. Altera recommends that you do not use the Intel
Hyper-Threading feature for Quartus II compilations, because it can increase
runtimes.
113
The software does not necessarily use all the processors that you specify during a
given compilation. Additionally, the software never uses more than the specified
number of processors, enabling you to work on other tasks on your computer without
it becoming slow or less responsive.
If you have partitioned your design and enabled parallel compilation, the Quartus II
software can use different processors to compile those partitions simultaneously
during Analysis and Synthesis. This can cause higher peak memory usage during
Analysis and Synthesis.
You can reduce the compilation time by up to 10% on systems with two processing
cores and by up to 20% on systems with four cores. With certain design flows in which
timing analysis runs alone, multiple processors can reduce the time required for
timing analysis by an average of 10% when using two processors. This reduction can
reach an average of 15% when using four processors.
The actual reduction in compilation time when using incremental compilation
partitions depends on your design and on the specific compilation settings. For
example, compilations with multi-corner optimization turned on benefit more from
using multiple processors than do compilations without multi-corner optimization.
The runtime requirement is not reduced for some other compilation goals, such as
Analysis and Synthesis. The Fitter (quartus_fit) and the Quartus II TimeQuest
Timing Analyzer (quartus_sta) stages in the compilation can, in certain cases, benefit
from the use of multiple processors. The Flow Elapsed Time panel of the Compilation
Report shows the average number of processors for these stages. The Parallel
Compilation panel of the appropriate report, such as the Fitter report, shows a more
detailed breakdown of processor usage. This panel is displayed only if parallel
compilation is enabled.
Parallel compilation is available for Arria series, Cyclone, HardCopy III, HardCopy
IV, MAX II, MAX V (limited support), and Stratix series devices.
h For more information, refer to Processing Page (Options Dialog Box) in Quartus II Help.
h For more information about how to control the number of processors used during
compilation for a specific project, refer to Compilation Process Settings Page (Settings
Dialog Box) in Quartus II Help.
You can also set the number of processors available for Quartus II compilation using
the following Tcl command in your script:
set_global_assignment -name NUM_PARALLEL_PROCESSORS <value> r
The use of multiple processors does not affect the quality of the fit. For a given Fitter
seed on a specific design, the fit is exactly the same, regardless of whether the
Quartus II software uses one processor or multiple processors. The only difference
between compilations using a different number of processors is the compilation time.
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115
May 2013
Use incremental compilation to preserve the placement for the unchanged parts of
your design.
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Sometimes there is a trade-off between placement time and routing time. Routing
time can increase if the placer does not run long enough to find a good placement.
When you reduce placement time, ensure that it does not increase routing time and
negate the overall time reduction.
117
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If you do not specify false paths and multicycle paths in your design, the
TimeQuest analyzer may analyze paths that are not relevant to your design.
If you redefine constraints in the .sdc files, the TimeQuest analyzer may spend
additional time processing them. To avoid this situation, look for indications that
Synopsis design constraints are being redefined in the compilation messages, and
update the .sdc file.
Ensure that you provide the correct timing constraints to your design, because the
software cannot assume design intent, such as which paths to consider as false
paths or multicycle paths. When you specify these assignments correctly, the
TimeQuest analyzer skips analysis for those paths, and the Fitter does not spend
additional time optimizing those paths.
May 2013
Version
Changes
13.0.0
Removed the Limit to One Fitting Attempt, Using Early Timing Estimation,
Final Placement Optimizations, and Using Rapid Recompile sections.
June 2012
12.0.0
November 2011
11.0.1
Template update.
May 2011
11.0.0
119
Version
December 2010
July 2010
10.1.0
10.0.0
Changes
Template update.
Initial release.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
May 2013
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This chapter describes techniques to improve timing performance when designing for
Altera devices.
The application techniques vary between designs. Applying each technique does not
always improve results. Settings and options in the Quartus II software have default
values that provide the best trade-off between compilation time, resource utilization,
and timing performance. You can adjust these settings to determine whether other
settings provide better results for your design.
Hold times (tH) from the device input pins to the registers
Minimum delays from I/O pins to I/O registers or from I/O registers to I/O pins
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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122
If you select All Paths, the Fitter also works to meet hold requirements from registers
to registers, shown in Figure 121, in which a derived clock generated with logic
causes a hold time problem on another register. However, if your design has internal
hold time violations between registers, correct the problems by making changes to
your design, such as using a clock enable signal instead of a derived or gated clock.
Figure 121. Optimize Hold Timing Option Fixing an Internal Hold Time Violation
f For design practices that helps eliminate internal hold time violations, refer to the
Recommended Design Practices chapter of the Quartus II Handbook.
123
Design Analysis
The initial compilation establishes whether the design achieves a successful fit and
meets the specified timing requirements. This section describes how to analyze your
design results in the Quartus II software.
You must analyze any constraints that the Quartus II software ignores. If necessary,
correct the constraints and recompile your design before proceeding with design
optimization.
f For more information about the report_sdc command and its options, refer to The
Quartus II TimeQuest Timing Analyzer chapter of the Quartus II Handbook.
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Register-to-Register Timing
This section contains the following sections:
Tips for Analyzing Failing Clock Paths that Cross Clock Domains on page 125
Tips for Analyzing Paths from/to the Source and Destination of Critical Path on
page 126
Tips for Locating Multiple Paths to the Chip Planner on page 128
Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles on
page 128
125
f For more information about netlist viewers, refer to the Analyzing Designs with
Quartus II Netlist Viewers chapter of the Quartus II Handbook.
Tips for Analyzing Failing Clock Paths that Cross Clock Domains
When analyzing clock path failures, check whether these paths cross two clock
domains. This is the case if the From Clock and To Clock in the timing analysis report
are different. There can also be paths that involve a different clock in the middle of the
path, even if the source and destination register clock are the same.
When you run Report Timing on your design, the report shows the launch clock and
latch clock for each failing path. Check whether these failing paths between these
clock domains should be analyzed synchronously. If the failing paths are not to be
analyzed synchronously, they must be set as false paths. Also check the relationship
between the launch clock and latch clock to make sure it is realistic and what you
expect from your knowledge of the design. For example, the path can start at a rising
edge and end at a falling edge, which reduces the setup relationship by one half clock
cycle.
Review the clock skew reported in the Timing Report. A large skew may indicate a
problem in your design, such as a gated clock or a problem in the physical layout (for
example, a clock using local routing instead of dedicated clock routing). When you
have made sure the paths are analyzed synchronously and that there is no large skew
on the path, and that the constraints are correct, you can analyze the data path.These
steps help you fine tune your constraints for paths across clock domains to ensure you
get an accurate timing report.
Check if the PLL phase shift is reducing the setup requirement. You might be able to
adjust this using PLL parameters and settings.
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Paths that cross clock domains are generally protected with synchronization logic (for
example, FIFOs or double-data synchronization registers) to allow asynchronous
interaction between the two clock domains. In such cases, you can ignore the timing
paths between registers in the two clock domains while running timing analysis, even
if the clocks are related.
The Fitter attempts to optimize all failing timing paths. If there are paths that can be
ignored for optimization and timing analysis, but the paths do not have constraints
that instruct the Fitter to ignore them, the Fitter tries to optimize those paths as well.
In some cases, optimizing unnecessary paths can prevent the Fitter from meeting the
timing requirements on timing paths that are critical to the design. It is beneficial to
specify all paths that can be ignored, so that the Fitter can put more effort into the
paths that must meet their timing requirements instead of optimizing paths that can
be ignored.
f For more details about how to ignore timing paths that cross clock domains, refer to
The Quartus II TimeQuest Timing Analyzer chapter of the Quartus II Handbook.
Evaluate the clock skew between the source clock and the destination clock to
determine if that is reducing the available setup time. You can check the shortest and
longest clock path reports to view what is causing the clock skew. Avoid using
combinational logic in clock paths because it contributes to clock skew. Differences in
the logic or in its routing between the source and destination can cause clock skew
problems and result in warnings during compilation.
Tips for Analyzing Paths from/to the Source and Destination of Critical Path
In the project directory, run the Tcl command shown in Example 121 in a .tcl file to
analyze the nodes in a critical path.
Example 121. report_timing Command
set wrst_src <insert_source_of_worst_path_here>
set wrst_dst <insert_destination_of_worst_path_here>
report_timing -setup -npaths 50 -detail path_only -from $wrst_src -panel_name "Worst
Path||wrst_src -> *"
report_timing -setup -npaths 50 -detail path_only -to $wrst_dst -panel_name "Worst
Path||* -> wrst_dst"
report_timing -setup -npaths 50 -detail path_only -to $wrst_src -panel_name "Worst
Path||* -> wrst_src"
report_timing -setup -npaths 50 -detail path_only -from $wrst_dst -panel_name "Worst
Path||wrst_dst -> *"
Copy the node name from the From Node and To Node columns of the worst path
into the first two variables, and then in the TimeQuest timing analyzer, in the Script
menu, source the .tcl script.
127
Source Register
of Worst Path
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
Legend
wrst_src -> *
* -> wrst_dst
* -> wrst_src
wrst_dst -> *
Critical Path
LUT
Destination
Register of
Worst Path
LUT
The critical path of the design is in red. The script analyzes the path between the worst
source and destination registers. The first report_timing command analyzes other
path that the source is driving, as shown in green. The second report_timing
command analyzes the critical path and other path going to the destination, shown in
yellow. These commands report everything inside these two endpoints that are
pulling them in different directions. The last two report_timing commands show
everything outside of the endpoints pulling them in other directions. If any of these
reports have slacks near the critical path, then the Fitter is balancing these paths with
the critical path, trying to achieve the best slack. Figure 122 is quite simple compared
to the critical path in most designs, but it is easy to see how this can get very
complicated quickly.
These timing reports are useful for analyzing what is competing with the critical path,
but not always good for examining how they might pull in different directions.
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Although you can select multiple rows, you can only select a single column.
Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles
Many designs have the same critical paths show up after each compile, but some
suffer from having critical paths bounce around between different hierarchies,
changing with each compile.
In designs like this, create a TQ_critical_paths.tcl script in the project directory. For a
given compile, view the critical paths and then write a generic report_timing
command to capture those paths. For example, if several paths fail in a low-level
hierarchy, you can add the following command as shown in Example 122:
Example 122. report_timing Command
report_timing setup npaths 50 detail path_only to main_system:
main_system_inst|app_cpu:cpu|*
panel_name Critical Paths||s: * -> app_cpu
This tip helps you monitor paths that consistently fail and paths that are only
marginal, so you can prioritize effectively.
129
f For details about the number and types of global routing resources available, refer to
the relevant device handbook.
Check the global signal utilization in your design to ensure that the appropriate
signals have been placed on the global routing resources. In the Compilation Report,
open the Fitter report and click Resource Section. Analyze the Global & Other Fast
Signals and Non-Global High Fan-out Signals reports to determine whether any
changes are required.
You might be able to reduce skew for high fan-out signals by placing them on global
routing resources. Conversely, you can reduce the insertion delay of low fan-out
signals by removing them from global routing resources. Doing so can improve clock
enable timing and control signal recovery/removal timing, but increases clock skew.
Use the Global Signal setting in the Assignment Editor to control global routing
resources.
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You will see recommendations that may help you fix the failing paths. For detailed
analysis of the critical paths, run the report_timing command on specified paths. In
the Extra Fitter Information tab of the Path report panel, you will also see detailed
Fitter-related information that may help you visualize the issue and take the
appropriate action if your constraints cause a specific placement.
h For more information about the Report Timing Closure Recommendations dialog
box, refer to Report Timing Closure Recommendations Dialog Box in Quartus II Help.
When you expand one of the categories in the Timing Optimization Advisor, such as
Maximum Frequency (fmax) or I/O Timing (tsu, tco, tpd), the recommendations are
divided into stages. The stages show the order in which to apply the recommended
settings. The first stage contains the options that are easiest to change, make the least
drastic changes to your design optimization, and have the least effect on compilation
1211
time. Icons indicate whether each recommended setting has been made in the current
project. In Figure 123, the checkmark icons in the list of recommendations for Stage 1
indicate recommendations that are already implemented. The warning icons indicate
recommendations that are not followed for this compilation. The information icons
indicate general suggestions. For these entries, the advisor does not report whether
these recommendations were followed, but instead explains how you can achieve
better performance. For a legend that provides more information for each icon, refer
to the How to use page in the Timing Optimization Advisor.
There is a link from each recommendation to the appropriate location in the
Quartus II GUI where you can change the settings. For example, consider the
Synthesis Netlist Optimizations page of the Settings dialog box or the Global
Signals category in the Assignment Editor. This approach provides the most control
over which settings are made and helps you learn about the settings in the software.
In some cases, you can also use the Correct the Settings button to automatically make
the suggested change to global settings.
For some entries in the Timing Optimization Advisor, a button appears that allows
you to further analyze your design and gives you more information. The advisor
provides a table with the clocks in the design and indicates whether they have been
assigned a timing constraint.
Affects tCO
Ensure that the appropriate constraints are set for the failing I/Os (refer to the Initial
Compilation: Required Settings section in the Design Optimization Overview chapter of the
Quartus II Handbook.)
Use fast output register, fast output enable register, and fast OCT register (page 1213)
Technique
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Altera Corporation
1212
Affects tCO
Decrease the value of Input Delay from Pin to Input Register or set Decrease Input Delay to
Input Register = ON
Decrease the value of Input Delay from Pin to Internal Cells or set Decrease Input Delay to
Internal Cells = ON
Decrease the value of Delay from Output Register to Output Pin or set Increase Delay to
Output Pin = OFF (page 1212)
Increase the value of Input Delay from Dual-Purpose Clock Pin to Fan-Out Destinations
(page 1212)
For MAX II or MAX V family devices, set Guarantee I/O Paths Have Zero Hold Time at Fast
Corner to OFF, or When TSU and TPD Constraints Permit (page 1215)
Increase the value of Delay to output enable pin or set Increase delay to output enable pin
(page 1214)
Technique
Timing-Driven Compilation
This option moves registers into I/O elements if required to meet tSU or tCO
assignments, duplicating the register if necessary (as in the case in which a register
fans out to multiple output locations). This option is turned on by default and is a
global setting. The option does not apply to MAX II series devices because they do not
contain I/O registers.
The Optimize IOC Register Placement for Timing option affects only pins that have
a tSU or tCO requirement. Using the I/O register is possible only if the register directly
feeds a pin or is fed directly by a pin. This setting does not affect registers with any of
the following characteristics:
Use the asynchronous load port and the value is not 1 (in device families where the
port is available)
Registers with the characteristics listed are optimized using the regular Quartus II
Fitter optimizations.
h For more information, refer to Optimize IOC Register Placement for Timing logic option in
Quartus II Help.
1213
h For more information about the Fast Input Register option, Fast Output Register
option, Fast Output Enable Register option, and Fast OCT (on-chip termination)
Register option, refer to Quartus II Help.
In MAX II series devices, which have no I/O registers, these assignments lock the
register into the LAB adjacent to the I/O pin if there is a pin location assignment for
that I/O pin.
If the fast I/O setting is on, the register is always placed in the I/O element. If the fast
I/O setting is off, the register is never placed in the I/O element. This is true even if
the Optimize IOC Register Placement for Timing option is turned on. If there is no
fast I/O assignment, the Quartus II software determines whether to place registers in
I/O elements if the Optimize IOC Register Placement for Timing option is turned
on.
You can also use the four fast I/O options (Fast Input Register, Fast Output Register,
Fast Output Enable Register, and Fast OCT Register) to override the location of a
register that is in a LogicLock region and force it into an I/O cell. If you apply this
assignment to a register that feeds multiple pins, the register is duplicated and placed
in all relevant I/O elements. In MAX II series devices, the register is duplicated and
placed in each distinct LAB location that is next to an I/O pin with a pin location
assignment.
Programmable Delays
You can use various programmable delay options to minimize the tSU and tCO times.
For Arria, Cyclone, MAX II, MAX V, and Stratix series devices, the Quartus II
software automatically adjusts the applicable programmable delays to help meet
timing requirements. Programmable delays are advanced options to use only after
you compile a project, check the I/O timing, and determine that the timing is
unsatisfactory. For detailed information about the effect of these options, refer to the
device family handbook or data sheet.
After you have made a programmable delay assignment and compiled the design,
you can view the implemented delay values for every delay chain for every I/O pin in
the Delay Chain Summary section of the Compilation Report.
You can assign programmable delay options to supported nodes with the Assignment
Editor. You can also view and modify the delay chain setting for the target device with
the Chip Planner and Resource Property Editor. When you use the Resource Property
Editor to make changes after performing a full compilation, recompiling the entire
design is not necessary; you can save changes directly to the netlist. Because these
changes are made directly to the netlist, the changes are not made again automatically
when you recompile the design. The change management features allow you to
reapply the changes on subsequent compilations.
Although the programmable delays in newer devices are user-controllable, Altera
recommends their use for advanced users only. However, the Quartus II software
might use the programmable delays internally during the Fitter phase.
f For more information about Stratix III programmable delays, refer to the Stratix III
Device Handbook and AN 474: Implementing Stratix III Programmable I/O Delay Settings
in the Quartus II Software. For more information about using the Chip Planner and
Resource Property Editor, refer to the Engineering Change Management with the Chip
Planner chapter of the Quartus II Handbook.
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h For details about the programmable delay logic options available for Altera devices,
refer to the following Quartus II Help topics:
Input Delay from Dual-Purpose Clock Pin to Fan-Out Destinations logic option
You can achieve the same type of effect in certain devices by using the programmable
delay called Input Delay from Dual Purpose Clock Pin to Fan-Out Destinations.
h For more information, refer to Input Delay from Dual-Purpose Clock Pin to Fan-Out
Destinations logic option in Quartus II Help.
1215
f For the number of clocking resources available in your target device, refer to the
appropriate device handbook.
In general, fast regional clocks have less delay to I/O elements than regional and
global clocks, and are used for high fan-out control signals. Regional clocks provide
the lowest clock delay and skew for logic contained in a single quadrant. Placing
clocks on these low-skew and low-delay clock nets provides better tCO performance.
If your design does not use LogicLock regions, or if the LogicLock regions are not
aligned to your clock region boundaries, create additional LogicLock regions and
further constrain your logic.
1
Some periphery features may ignore LogicLock region assignments. When this
happens, the global promotion process may not function properly. To ensure that
the global promotion process uses the correct locations, assign specific pins to the
I/Os using these periphery features.
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1217
f For coding style guidelines including examples of HDL code for inferring memory,
functions, guidelines, and sample HDL code for state machines, refer to the
Recommended HDL Coding Styles chapter of the Quartus II Handbook.
f For additional HDL coding examples, refer to AN 584: Timing Closure Methodology for
Advanced FPGA Designs.
For details and to fix any of these problems before proceeding with
optimization, refer to the Design Optimization Overview chapter of the
Quartus II Handbook.
Use Other Synthesis Options Available in Your Synthesis Tool on page 1222
6. Try different Fitter seeds (page 1222). If there are very few paths that are failing
by small negative slack, then you can try with a different seed to see if there is a fit
that meets constraints in the Fitter seed noise.
1
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Altera Corporation
Omit this step if a large number of critical paths are failing or if the paths
are failing badly.
1218
1219
The following physical synthesis optimizations are available during the Fitter stage
for improving performance:
Register duplication
Register retiming
If you want the performance gain from physical synthesis only on parts of your
design, you can apply the physical synthesis options on specific instances.
h For more information, refer to Physical Synthesis Optimizations Page (Settings Dialog
Box) in Quartus II Help.
To apply physical synthesis assignments for fitting on a per-instance basis, use the
Quartus II Assignment Editor. The following assignments are available as instance
assignments:
h For information about making assignments, refer to Working With Assignments in the
Assignment Editor in Quartus II Help.
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Some synthesis tools offer an easy way to instruct the tool to focus on speed instead of
area.
h For more information, refer to Optimization Technique logic option in Quartus II Help
You can also specify this logic option for specific modules in your design with the
Assignment Editor while leaving the default Optimization Technique setting at
Balanced (for the best trade-off between area and speed for certain device families) or
Area (if area is an important concern). You can also use the Speed Optimization
Technique for Clock Domains option in the Assignment Editor to specify that all
combinational logic in or between the specified clock domain(s) is optimized for
speed.
To achieve best performance with push-button compilation, follow the
recommendations in the following sections for other synthesis settings. You can use
the DSE to experiment with different Quartus II synthesis options to optimize your
design for the best performance.
f For information about setting timing requirements and synthesis options in
Quartus II integrated synthesis and third-party synthesis tools, refer to the
appropriate chapter in Synthesis of the Quartus II Handbook, or refer to your synthesis
software documentation.
h For more information about the Design Space Explorer, refer to About Design Space
Explorer in Quartus II Help.
1221
Various Fitter optimizations may cause a small violation to the Maximum Fan-Out
assignments to improve timing.
h For more information, refer to Manual Logic Duplication logic option in Quartus II Help.
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1222
These options can increase performance, but typically increase the resource utilization
of your design.
Fitter Seed
The Fitter seed affects the initial placement configuration of the design. Changing the
seed value changes the Fitter results because the fitting results change whenever there
is a change in the initial conditions. Each seed value results in a somewhat different
fit, and you can experiment with several different seeds to attempt to obtain better
fitting results and timing performance.
When there are changes in your design, there is some random variation in
performance between compilations. This variation is inherent in placement and
routing algorithmsthere are too many possibilities to try them all and get the
absolute best result, so the initial conditions change the compilation result.
1
Any design change that directly or indirectly affects the Fitter has the same type of
random effect as changing the seed value. This includes any change in source files,
Analysis & Synthesis Settings, Fitter Settings, or Timing Analyzer Settings. The
same effect can appear if you use a different computer processor type or different
operating system, because different systems can change the way floating point
numbers are calculated in the Fitter.
If a change in optimization settings slightly affects the register-to-register timing or
number of failing paths, you cannot always be certain that your change caused the
improvement or degradation, or whether it could be due to random effects in the
Fitter. If your design is still changing, running a seed sweep (compiling your design
with multiple seeds) determines whether the average result has improved after an
optimization change and whether a setting that increases compilation time has
benefits worth the increased time (such as setting the Physical Synthesis Effort to
Extra). The sweep also shows the amount of random variation to expect for your
design.
If your design is finalized, you can compile your design with different seeds to obtain
one optimal result. However, if you subsequently make any changes to your design,
you might need to perform seed sweep again.
On the Assignments menu, select Fitter Settings to control the initial placement with
the seed. You can use the DSE to perform a seed sweep easily.
1223
You can use the following Tcl command from a script to specify a Fitter seed:
set_global_assignment -name SEED <value> r
h For more information about compiling your design with different seeds using the
Design Space Explorer (DSE seed sweep), refer to About Design Space Explorer in
Quartus II Help.
LogicLock Assignments
Using LogicLock assignments to improve timing performance is only recommended
for older Altera devices, such as the MAX II family. For other device families,
especially for larger devices such as Arria and Stratix series devices, Altera does not
recommend using LogicLock assignments to improve timing performance. For these
devices, use the LogicLock feature for performance preservation and to floorplan
your design.
LogicLock assignments do not always improve the performance of the design. In
many cases, you cannot improve upon results from the Fitter by making location
assignments. If there are existing LogicLock assignments in your design, remove the
assignments if your design methodology permits it. Recompile the design, and then
check if the assignments are making the performance worse.
When making LogicLock assignments, it is important to consider how much
flexibility to give the Fitter. LogicLock assignments provide more flexibility than hard
location assignments. Assignments that are more flexible require higher Fitter effort,
but reduce the chance of design overconstraint. The following types of LogicLock
assignments are available, listed in the order of decreasing flexibility:
f For more information about using LogicLock regions, refer to the Analyzing and
Optimizing the Design Floorplan with the Chip Planner chapter of the Quartus II
Handbook.
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If you are unsure of how big or where a LogicLock region should go, the
Auto/Floating options are useful for your first pass. After you determine where a
LogicLock region must go, modify the Fixed/Locked regions, as Auto/Floating
LogicLock regions can hurt your overall performance. To determine what to put into a
LogicLock region, refer to the timing analysis results and analyze the critical paths in
the Chip Planner. The register-to-register timing paths in the Timing Analyzer section
of the Compilation Report help you recognize patterns.
The following sections describe cases in which LogicLock regions can help to
optimize a design.
Hierarchy Assignments
For a design with the hierarchy shown in Figure 125, which has failing paths in the
timing analysis results similar to those shown in Table 122, mod_A is probably a
problem module. In this case, a good strategy to fix the failing paths is to place the
mod_A hierarchy block in a LogicLock region so that all the nodes are closer together in
the floorplan.
Figure 125. Design Hierarchy
Top
mod_A
mod_B
To
|mod_A|reg1
|mod_A|reg9
|mod_A|reg3
|mod_A|reg5
|mod_A|reg4
|mod_A|reg6
|mod_A|reg7
|mod_A|reg10
|mod_A|reg0
|mod_A|reg2
Hierarchical LogicLock regions are also important if you are using an incremental
compilation flow. Place each design partition for incremental compilation in a
separate LogicLock region to reduce conflicts and ensure good results as the design
develops. You can use the auto size and floating location regions to find a good design
floorplan, but fix the size and placement to achieve the best results in future
compilations.
1225
f For more information about using incremental compilation and recommendations for
creating a design floorplan using LogicLock regions, refer to the Quartus II Incremental
Compilation for Hierarchical and Team-Based Design and Best Practices for Incremental
Compilation and Floorplan Assignments chapters of the Quartus II Handbook, and
Analyzing and Optimizing the Design Floorplan with the Chip Planner chapter of the
Quartus II Handbook.
Location Assignments
If a small number of paths are failing to meet their timing requirements, you can use
hard location assignments to optimize placement. Location assignments are less
flexible for the Quartus II Fitter than LogicLock assignments. In some cases, when you
are familiar with your design, you can enter location constraints in a way that
produces better results.
1
Improving fitting results, especially for larger devices, such as Arria and Stratix series
devices, can be difficult. Location assignments do not always improve the
performance of the design. In many cases, you cannot improve upon the results from
the Fitter by making location assignments.
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Pin-to-pin delays (tPD)the time required for a signal from an input pin to
propagate through combinational logic and appear at an external output pin
This section provides guidelines to improve the timing if the timing requirements are
not met. Figure 126 shows the parts of the design that determine the tSU, tH, tCO, tPD,
and fMAX timing parameters.
Figure 126. Main Timing Parameters that Determine the Systems Performance
Setup and Hold Time
DFF
Input
Logic
PRN
Q
DFF
Logic
CLRN
PRN
Q
Clock-to-Output Time
Output
Logic
CLRN
Clock Frequency
Input
When you are analyzing a design to improve performance, be sure to consider the two
major contributors to long delay paths:
When a MAX 7000 or MAX 3000 device signal drives more than one LAB, the
programmable interconnect array (PIA) delay increases by 0.1 ns per additional LAB
fan-out. Therefore, to minimize the added delay, concentrate the destination
macrocells into fewer LABs, minimizing the number of LABs that are driven. The
main cause of long delays in circuit design is excessive levels of logic.
1227
Turn on the Fast Input Register option using the Assignment Editor. The Fast
Input Register option allows input pins to directly drive macrocell registers by
way of the fast-input path, thus minimizing the pin-to-register delay. This option
is useful when a pin drives a D-type flipflop and there is no combinational logic
between the pin and the register.
Reduce the amount of logic between the input and the register. Excessive logic
between the input pin and the register causes more delays. To improve setup time,
Altera recommends reducing the amount of logic between the input pin and the
register whenever possible.
Reduce fan-out. The delay from input pins to macrocell registers increases when
the fan-out of the pins increases. To improve the setup time, minimize the fan-out.
Use the global clock. In addition to minimizing the delay from a register to an
output pin, minimizing the delay from the clock pin to the register can also
improve tCO timing. Always use the global clock for low-skew and speed-critical
signals.
Reduce the amount of logic between the register and output pin. Excessive logic
between the register and the output pin causes more delay. Always minimize the
amount of logic between the register and the output pin for faster clock-to-output
time.
Table 123 lists the timing results for an EPM7064AETC100-4 device when you use a
combination of the Fast Input Register option, global clock, and minimal logic. When
you turn on the Fast Input Register option, tSU is improved (tSU decreases from 1.6 ns
to 1.3 ns and from 2.8 ns to 2.5 ns). The tCO timing is improved when you use the
global clock for low-skew and speed-critical signals (tCO decreases from 4.3 ns to
3.1 ns). However, if there is additional logic used between the input pin and the
register or the register and the output pin, the tSU and tCO delays increase.
Table 123. EPM7064AETC100-4 Device Timing Results (Part 1 of 2)
Additional Logic Between:
Number of
Registers
tSU
(ns)
tH
(ns)
tCO
(ns)
Global
Clock Used
Fast Input
Register
Option
1.3
1.2
4.3
On
LAB A
LAB A
1.6
0.3
4.3
Off
LAB A
LAB A
2.5
3.1
On
LAB A
LAB A
2.8
3.1
Off
LAB A
LAB A
3.6
3.1
Off
LAB A
LAB A
2.8
7.0
Off
LAB D
LAB A
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Altera Corporation
D Input
Location
Q Output
Location
D Input
Location &
Register
Register & Q
Output
Location
1228
tSU
(ns)
tH
(ns)
tCO
(ns)
Global
Clock Used
Fast Input
Register
Option
D Input
Location
Q Output
Location
D Input
Location &
Register
Register & Q
Output
Location
16 with the
same D and
clock inputs
2.8
All
6.2
Off
LAB D
LAB A, B
32 with the
same D and
clock inputs
2.8
All
6.4
Off
LAB C
LAB A, B, C
On the Assignments menu, click Settings. In the Category list, select Analysis &
Synthesis Settings, and turn on Auto Parallel Expanders. Turning on the parallel
expanders for individual nodes or sub-designs can increase the performance of
complex logic functions. However, if the projects pin or logic cell assignments use
parallel expanders placed physically together with macrocells (which can reduce
routability), parallel expanders can cause the Quartus II Fitter to have difficulties
finding and optimizing a fit. Additionally, the number of macrocells required to
implement the design increases and results in a no-fit error during compilation if
the device resources are limited. For more information about turning on the Auto
Parallel Expanders option, refer to the Area Optimization chapter of the Quartus II
Handbook.
Set Optimization Technique to Speed. By default, the Quartus II software sets the
Optimization Technique option to Speed for MAX 7000 and MAX 3000 devices.
Reset the Optimization Technique option to Speed only if you previously set it to
Area. On the Assignments menu, click Settings. In the Category list, select
Analysis & Synthesis Settings, and turn on Speed under Optimization
Technique.
1229
On the Assignments menu, click Settings. In the Category list, select Analysis &
Synthesis Settings, click More Settings, and turn on Auto Parallel Expanders.
Turning on the parallel expanders for individual nodes or subdesigns can increase
the performance of complex logic functions. However, if the projects pin or logic
cell assignments use parallel expanders placed physically together with macrocells
(which can reduce routability), parallel expanders can cause the Quartus II
compiler to have difficulties finding and optimizing a fit. Additionally, the number
of macrocells required to implement the design also increases and can result in a
no-fit error during compilation if the devices resources are limited.
f For more information about using the Auto Parallel Expanders option,
refer to refer to the Area Optimization chapter of the Quartus II Handbook.
Use global signals or dedicated inputs. Altera MAX 7000 and MAX 3000 devices
have dedicated inputs that provide low skew and high speed for high fan-out
signals. Minimize the number of control signals in the design and use the
dedicated inputs to implement them.
Set Optimization Technique to Speed. By default, the Quartus II software sets the
Optimization Technique option to Speed for MAX 7000 and MAX 3000 devices.
Reset the Optimization Technique option to Speed only if you have previously
set it to Area. You can reset the Optimization Technique option. In the Category
list, select Analysis & Synthesis Settings, and turn on Speed under Optimization
Technique.
Pipeline the design. Pipelining, which increases clock frequency (fMAX), refers to
dividing large blocks of combinational logic by inserting registers. When using
RAM or DSP blocks, always enable the optional input and output registers.
Scripting Support
You can run procedures and make settings described in this chapter in a Tcl script.
You can also run some procedures at a command prompt. For detailed information
about scripting command options, refer to the Quartus II command-line and Tcl API
Help browser. To run the Help browser, type the following command at the command
prompt:
quartus_sh --qhelp r
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f For more information about Tcl scripting, refer to the Tcl Scripting chapter of the
Quartus II Handbook. For more information about all settings and constraints in the
Quartus II software, refer to the Quartus II Settings File Manual. For more information
about command-line scripting, refer to the Command-Line Scripting chapter of the
Quartus II Handbook.
You can specify many of the options described in this section either in an instance, or
at a global level, or both.
Use the following Tcl command to make a global assignment:
set_global_assignment -name <.qsf variable name> <value> r
If the <value> field includes spaces (for example, Standard Fit), you must enclose the
value in straight double quotation marks.
Values
Type
OPTIMIZE_IOC_REGISTER_
PLACEMENT_FOR_TIMING
ON, OFF
Global
OPTIMIZE_HOLD_TIMING
Global
Values
Type
Global
1231
Values
Type
Auto Packed
Registers (1)
Global,
Instance
Perform WYSIWYG
Primitive
Resynthesis
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
ON, OFF
Global,
Instance
Physical Synthesis
for Combinational
Logic for Reducing
Area
PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA
ON, OFF
Global,
Instance
Physical Synthesis
for Mapping Logic
to Memory
Global,
Instance
Optimization
Technique
Global,
Instance
Speed Optimization
Technique for Clock
Domains
SYNTH_CRITICAL_CLOCK
ON, OFF
Instance
State Machine
Encoding
STATE_MACHINE_PROCESSING
Global,
Instance
Auto RAM
Replacement
AUTO_RAM_RECOGNITION
ON, OFF
Global,
Instance
Auto ROM
Replacement
AUTO_ROM_RECOGNITION
ON, OFF
Global,
Instance
AUTO_SHIFT_REGISTER_RECOGNITION
ON, OFF
Global,
Instance
Auto Block
Replacement
AUTO_DSP_RECOGNITION
ON, OFF
Global,
Instance
Number of
Processors for
Parallel Compilation
NUM_PARALLEL_PROCESSORS
Global
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Values
Type
OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING
ON, OFF
Global
FAST_INPUT_REGISTER
ON, OFF
Instance
FAST_OUTPUT_REGISTER
ON, OFF
Instance
FAST_OUTPUT_ENABLE_REGISTER
ON, OFF
Instance
FAST_OCT_REGISTER
ON, OFF
Instance
Values
Type
Perform WYSIWYG
Primitive Resynthesis
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
ON, OFF
Global,
Instance
PHYSICAL_SYNTHESIS_COMBO_LOGIC
ON, OFF
Global,
Instance
Perform Register
Duplication
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION
ON, OFF
Global,
Instance
PHYSICAL_SYNTHESIS_REGISTER_RETIMING
ON, OFF
Global,
Instance
Perform Automatic
Asynchronous Signal
Pipelining
Global,
Instance
PHYSICAL_SYNTHESIS_EFFORT
NORMAL, EXTRA,
Global
FAST
Fitter Seed
SEED
<integer>
Global
Maximum Fan-Out
MAX_FANOUT
<integer>
Instance
DUPLICATE_ATOM
<node name>
Instance
OPTIMIZE_POWER_DURING_SYNTHESIS
NORMAL, OFF
EXTRA_EFFORT
Global
OPTIMIZE_POWER_DURING_FITTING
NORMAL, OFF
EXTRA_EFFORT
Global
1233
May 2013
November 2012
June 2012
November 2011
May 2011
May 2013
Version
Changes
Renamed chapter title from Area and Timing Optimization to Timing Closure and
Optimization
13.0.0
Altera Corporation
Tips for Analyzing Paths from/to the Source and Destination of Critical Path on
page 126,
Tips for Locating Multiple Paths to the Chip Planner on page 128,
Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles on
page 128
Updated Initial Compilation: Optional Fitter Settings on page 132, I/O Assignments
on page 132, Initial Compilation: Optional Fitter Settings on page 132, Resource
Utilization on page 139, Routing on page 1321, and Resolving Resource
Utilization Problems on page 1343.
Updated the Timing Requirement Settings, Standard Fit, Fast Fit, Optimize MultiCorner Timing, Timing Analysis with the TimeQuest Timing Analyzer, Debugging
Timing Failures in the TimeQuest Analyzer, LogicLock Assignments, Tips for
Analyzing Failing Clock Paths that Cross Clock Domains, Flatten the Hierarchy During
Synthesis, Fast Input, Output, and Output Enable Registers, and Hierarchy
Assignments sections
12.0.0
11.0.0
12.1.0
11.1.0
1234
Version
December 2010
August 2010
July 2010
10.1.0
10.0.1
10.0.0
Changes
Corrected link
Moved Smart Compilation Setting and Early Timing Estimation sections to new
Reducing Compilation Time chapter
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
f For more information about power optimization techniques available for Stratix III
devices, refer to AN 437: Power Optimization in Stratix III FPGAs. For more information
about power optimization techniques available for Stratix IV devices, refer to AN 514:
Power Optimization in Stratix IV FPGAs.
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
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132
Power Dissipation
This section describes the sources of power dissipation in Stratix III and Cyclone III
devices. You can refine techniques that reduce power consumption in your design by
understanding the sources of power dissipation.
Figure 131 shows the power dissipation of Stratix III and Cyclone III devices in
different designs. All designs were analyzed at a fixed clock rate of 100 MHz and
exhibited varied logic resource utilization across available resources.
Figure 131. Average Core Dynamic Power Dissipation
Average Core Dynamic Power Dissipation by Block
Type in Stratix III Devices at a 12.5% Toggle Rate (1)
Routing
29%
Memory
21%
Memory
20%
DSP Blocks
1% (3)
Combinational Logic
16%
Combinational Logic
11%
Multipliers
1% (3)
Registered Logic
18%
Registered Logic
23%
133
Memory and clock resources are other major consumers of power in FPGAs. Stratix II
devices feature the TriMatrix memory architecture. TriMatrix memory includes
512-bit M512 blocks, 4-Kbit M4K blocks, and 512-Kbit M-RAM blocks, which are
configurable to support many features. Stratix IV and Stratix III TriMatrix on-chip
memory is an enhancement based upon the Stratix II FPGA TriMatrix memory and
includes three sizes of memory blocks: MLAB blocks, M9K blocks, and M144K blocks.
Stratix III, Stratix IV, and Stratix V devices feature Programmable Power Technology,
an advanced architecture that enables a smooth trade-off between speed and power.
The core of each Stratix III, Stratix IV, and Stratix V device is divided into tiles, each of
which may be put into a high-speed or low-power mode. The primary benefit of
Programmable Power Technology is to reduce static power, with a secondary benefit
being a small reduction in dynamic power. Cyclone II devices have 4-Kbit M4K
memory blocks, and Cyclone III and Cyclone IV GX devices have 9-Kbit M9K
memory blocks.
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134
The Search for Lowest Power option, under Exploration Settings, uses a predefined
exploration space that targets overall design power improvements. This setting
focuses on applying different options that specifically reduce total design thermal
power.
By default, the Quartus II PowerPlay Power Analyzer is run for every exploration
performed by the DSE when the Search for Lowest Power option is selected. This
helps you debug your design and determine trade-offs between power requirements
and performance optimization.
h For more information about the DSE, refer to About Design Space Explorer in Quartus II
Help.
Power-Driven Compilation
The standard Quartus II compilation flow consists of Analysis and Synthesis,
placement and routing, Assembly, and Timing Analysis. Power-driven compilation
takes place at the Analysis and Synthesis and Place-and-Route stages.
Quartus II software settings that control power-driven compilation are located in the
PowerPlay power optimization list on the Analysis & Synthesis Settings page, and
the PowerPlay power optimization list on the Fitter Settings page. The following
sections describes these power optimization options at the Analysis and Synthesis
and Fitter levels.
Power-Driven Synthesis
Synthesis netlist optimization occurs during the synthesis stage of the compilation
flow. The optimization technique makes changes to the synthesis netlist to optimize
your design according to the selection of area, speed, or power optimization. This
section describes power optimization techniques at the synthesis level.
135
The Analysis & Synthesis Settings page allows you to specify logic synthesis
options. The PowerPlay power optimization option is available for all devices
supported by the Quartus II software except MAX 3000 and MAX 7000 devices.
(Figure 133).
Figure 133. Analysis & Synthesis Settings Page
Table 131 shows the settings in the PowerPlay power optimization list. You can
apply these settings on a project or entity level.
Table 131. Optimize Power During Synthesis Options
Settings
Description
Off
Normal compilation Low compute effort algorithms are applied to minimize power through netlist
(Default)
optimizations as long as they are not expected to reduce design performance.
Extra effort
High compute effort algorithms are applied to minimize power through netlist
optimizations. Max performance might be impacted.
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136
Memory blocks can represent a large fraction of total design dynamic power as
described in Reducing Memory Power Consumption on page 1314. Minimizing
the number of memory blocks accessed during each clock cycle can significantly
reduce memory power. Memory optimization involves effective movement of
user-defined read/write enable signals to associated read-and-write clock enable
signals for all memory types (Figure 134).
Figure 134. Memory Transformation
Data
Data
VCC
Wr Clk
Enable
Rd Clk
Enable
Wren
Write
Enable
Read
Enable
Write
Address
Read
Address
Switch
Write
Address
Clock
Data
Data
VCC
Wren
Wr Clk
Enable
Rd Clk
Enable
Rden
Rden
VCC
Write
Enable
Read
Enable
VCC
Write
Address
Read
Address
Read
Address
Switch
Write
Address
Read
Address
Clock
137
The Extra effort setting also performs power-aware memory balancing. Power-aware
memory balancing automatically chooses the best memory configuration for your
memory implementation and provides optimal power saving by determining the
number of memory blocks, decoder, and multiplexer circuits required. If you have not
previously specified target-embedded memory blocks for your designs memory
functions, the power-aware balancer automatically selects them during memory
implementation.
Figure 135 shows an example of a 4k 4 (4k deep and 4 bits wide) memory
implementation in two different configurations using M4K memory blocks available
in Stratix II devices. The minimum logic area implementation uses M4K blocks
configured as 4k 1. This implementation is the default in the Quartus II software
because it has the minimum logic area (0 logic cells) and the highest speed. However,
all four M4K blocks are active on each memory access in this implementation, which
increases RAM power. The minimum RAM power implementation is created by
selecting Extra effort in the PowerPlay power optimization list. This implementation
automatically uses four M4K blocks configured as 1k 4 for optimal power saving.
An address decoder is implemented by the RAM megafunction to select which of the
four M4K blocks should be activated on a given cycle, based on the state of the top
two user address bits. The RAM megafunction automatically implements a
multiplexer to feed the downstream logic by choosing the appropriate M4K output.
This implementation reduces RAM power because only one M4K block is active on
any cycle, but it requires extra logic cells, costing logic area and potentially impacting
design performance.
There is a trade-off between power saved by accessing fewer memories and power
consumed by the extra decoder and multiplexor logic. The Quartus II software
automatically balances the power savings against the costs to choose the lowest
power configuration for each logical RAM. The benchmark data shows that the
power-driven synthesis can reduce memory power consumption by as much as 60%
in Stratix devices.
Figure 135. 4K 4 Memory Implementation Using Multiple M4K Blocks
4K Words Deep &
4 Bits Wide
Minimum RAM Power
(Power Efficient)
Addr[10:11]
Addr
Decoder
4K Deep 1 Wide
M4K RAM
1K Deep 4 Wide
M4K RAM
Addr[0:11]
Addr[0:9]
Data[0:3]
Addr[10:11]
Data[0:3]
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139
Power-Driven Fitter
The Fitter Settings page enables you to specify options for fitting (Figure 136). The
PowerPlay power optimization option is available for Arria GX, Arria II GX,
Cyclone II, Cyclone III, Cyclone IV, HardCopy series, Stratix II, Stratix II GX,
Stratix III, Stratix IV, and Stratix V devices.
Figure 136. Fitter Settings Page
Table 132 lists the settings in the PowerPlay power optimization list. These settings
can only be applied on a project-wide basis. The Extra effort setting for the Fitter
requires extensive effort to optimize the design for power and can increase the
compilation time.
Table 132. Power-Driven Fitter Option
Settings
Off
Description
No netlist, placement, or routing optimizations are performed to minimize power.
Normal compilation Low compute effort algorithms are applied to minimize power through placement and routing
(Default)
optimizations as long as they are not expected to reduce design performance.
Extra effort
May 2013
High compute effort algorithms are applied to minimize power through placement and routing
optimizations. Max performance might be impacted.
Altera Corporation
1310
Only the Extra effort setting in the PowerPlay power optimization list for the Fitter
option uses the signal activities (from .vcd files) during fitting. The settings made in
the PowerPlay Power Analyzer Settings page in the Settings dialog box are used to
calculate the signal activity of your design.
f For more information about .vcd files and how to create them, refer to the PowerPlay
Power Analysis chapter in volume 3 of the Quartus II Handbook.
h For step-by-step instructions on how to perform power-driven fitting, refer to
Running a Power-Optimized Compilation in Quartus II Help.
1311
Area-Driven Synthesis
Using area optimization rather than timing or delay optimization during synthesis
saves power because you use fewer logic blocks. Using less logic usually means less
switching activity. The Quartus II integrated synthesis tool provides Speed, Balanced,
or Area for the Optimization Technique option. You can also specify this logic option
for specific modules in your design with the Assignment Editor in cases where you
want to reduce area using the Area setting (potentially at the expense of register-toregister timing performance) while leaving the default Optimization Technique
setting at Balanced (for the best trade-off between area and speed for certain device
families). The Speed Optimization Technique can increase the resource usage of your
design if the constraints are too aggressive, and can also result in increased power
consumption.
The benchmark data shows that the area-driven technique can reduce power
consumption by as much as 31% in Stratix devices and as much as 15% in Cyclone
devices.
10 ns
5 ns
8 ns
After
D
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7 ns
1312
Gate-level register retiming makes changes at the gate level. If you are using an atom
netlist from a third-party synthesis tool, you must also select the Perform WYSIWYG
primitive resynthesis option to undo the atom primitives to gates mapping (so that
register retiming can be performed), and then to remap gates to Altera primitives.
When using Quartus II integrated synthesis, retiming occurs during synthesis before
the design is mapped to Altera primitives. The benchmark data shows that the
combination of WYSIWYG remapping and gate-level register retiming techniques can
reduce power consumption by as much as 6% in Stratix devices and as much as 21%
in Cyclone devices.
f For more information about register retiming, refer to the Netlist Optimizations and
Physical Synthesis chapter in volume 2 of the Quartus II Handbook.
Design Guidelines
Several low-power design techniques can reduce power consumption when applied
during FPGA design implementation. This section provides detailed design
techniques for Cyclone II, Cyclone III, Cyclone IV GX, Stratix II, and Stratix III devices
that affect overall design power. The results of these techniques might be different
from design to design.
1313
Stratix IV, and Stratix V devices have clock control blocks for regional clock networks.
The dynamic clock enable feature lets internal logic control the clock network. When a
clock network is powered down, all the logic fed by that clock network does not
toggle, thereby reducing the overall power consumption of the device. Figure 138
shows a 4-input clock control block diagram.
Figure 138. Clock Control Block Diagram
ena
inclk 3
inclk 2
inclk 1
inclk 0
outclk
clkselect[1..0]
The enable signal is applied to the clock signal before being distributed to global
routing. Therefore, the enable signal can either have a significant timing slack (at least
as large as the global routing delay) or it can reduce the fMAX of the clock signal.
f For more information about using clock control blocks, refer to the Clock Control Block
Megafunction User Guide (ALTCLKCTRL).
Another contributor to clock power consumption is the LAB clock that distributes a
clock to the registers within a LAB. LAB clock power can be the dominant contributor
to overall clock power. For example, in Cyclone III devices, each LAB can use two
clocks and two clock enable signals, as shown in Figure 139. Each LABs clock signal
and clock enable signal are linked. For example, an LE in a particular LAB using the
labclk1 signal also uses the labclkena1 signal.
Figure 139. LAB-Wide Control Signals
Dedicated
LAB Row
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
labclkena1
labclk1
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labclkena2
labclk2
labclr1
syncload
synclr
labclr2
1314
To reduce LAB-wide clock power consumption without disabling the entire clock tree,
use the LAB-wide clock enable to gate the LAB-wide clock. The Quartus II software
automatically promotes register-level clock enable signals to the LAB-level. All
registers within an LAB that share a common clock and clock enable are controlled by
a shared gated clock. To take advantage of these clock enables, use a clock enable
construct in the relevant HDL code for the registered logic.
f For more information about LAB-wide control signals, refer to the Stratix II
Architecture, Cyclone III Device Family Overview, or Cyclone II Architecture chapters in
the respective device handbook.
Clk
1315
Using the clock enable signal enables the memory only when necessary and shuts it
down for the rest of the time, reducing the overall memory power consumption. You
can use the MegaWizard Plug-In Manager to create these enable signals by selecting
the Clock enable signal option for the appropriate port when generating the memory
block function (Figure 1311).
Figure 1311. MegaWizard Plug-In Manager RAM 2-Port Clock Enable Signal Selectable Option
For example, consider a design that contains a 32-bit-wide M4K memory block in
ROM mode that is running at 200 MHz. Assuming that the output of this block is only
required approximately every four cycles, this memory block will consume 8.45 mW
of dynamic power according to the demands of the downstream logic. By adding a
small amount of control logic to generate a read clock enable signal for the memory
block only on the relevant cycles, the power can be cut 75% to 2.15 mW.
You can also use the MAXIMUM_DEPTH parameter in your memory megafunction to save
power in Cyclone II, Cyclone III, Cyclone IV GX, Stratix II, Stratix III, Stratix IV, and
Stratix V devices; however, this approach might increase the number of LEs required
to implement the memory and affect design performance.
You can set the MAXIMUM_DEPTH parameter for memory modules manually in the
megafunction instantiation or in the MegaWizard Plug-In Manager (Figure 1312).
The Quartus II software automatically chooses the best design memory configuration
for optimal power, as described in Power-Driven Compilation on page 134.
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1316
Figure 1312. MegaWizard Plug-In Manager RAM 2-Port Maximum Depth Selectable Option
ALUTs
4K 1 (Default setting)
36
2K 2
36
40
1K 4
36
62
512 9
32
143
256 18
32
302
128 36
32
633
1317
Figure 1313 shows the amount of power saved using the MAXIMUM_DEPTH parameter.
For all implementations, a user-provided read enable signal is present to indicate
when read data is required. Using this power-saving technique can reduce power
consumption by as much as 60%.
Power Savings
4K 1
2K 2
1K 4
512 9
M4K Configuration
256 18
128 36
As the memory depth becomes more shallow, memory dynamic power decreases
because unaddressed M4K blocks can be shut off using a decoded combination of
address bits and the read enable signal. For a 128-deep memory block, power used by
the extra LEs starts to outweigh the power gain achieved by using a more shallow
memory block depth. The power consumption of the memory blocks and associated
LEs depends on the memory configuration.
1
The SOPC Builder and Qsys system do not offer specific power savings control for
on-chip memory block. There is no read enable, write enable, or clock enable that you
can enable in the on-chip RAM megafunction to shut down the RAM block in the
SOPC Builder and Qsys system.
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1318
produced before the output becomes stable, as shown in Figure 1314. This glitch can
propagate to subsequent logic and create unnecessary switching activity, increasing
power consumption. Circuits with many XOR functions, such as arithmetic circuits or
cyclic redundancy check (CRC) circuits, tend to have many glitches if there are several
levels of combinational logic between registers.
Figure 1314. XOR Gate Showing Glitch at the Output
A
A
Glitch
t
Timing Diagram for the 2-Input XOR Gate
Pipelining can reduce design glitches by inserting flipflops into long combinational
paths. Flipflops do not allow glitches to propagate through combinational paths.
Therefore, a pipelined circuit tends to have less glitching. Pipelining has the
additional benefit of generally allowing higher clock speed operations, although it
does increase the latency of a circuit (in terms of the number of clock cycles to a first
result). Figure 1315 shows an example where pipelining is applied to break up a long
combinational path.
Figure 1315. Pipelining Example
Non-Pipelined
Combinational
Logic
Long Logic
Depth
Pipelined
Combinational
Logic
Short Logic
Depth
Combinational
Logic
Short Logic
Depth
1319
Architectural Optimization
You can use design-level architectural optimization by taking advantage of specific
device architecture features. These features include dedicated memory and DSP or
multiplier blocks available in FPGA devices to perform memory or arithmetic-related
functions. You can use these blocks in place of LUTs to reduce power consumption.
For example, you can build large shift registers from RAM-based FIFO buffers instead
of building the shift registers from the LE registers.
The Stratix device family allows you to efficiently target small, medium, and large
memories with the TriMatrix memory architecture. Each TriMatrix memory block is
optimized for a specific function. The M512 memory blocks available in Stratix II
devices are useful for implementing small FIFO buffers, DSP, and clock domain
transfer applications. M512 memory blocks are more power-efficient than the
distributed memory structures in some competing FPGAs. The M4K memory blocks
are used to implement buffers for a wide variety of applications, including processor
code storage, large look-up table implementation, and large memory applications.
The M-RAM blocks are useful in applications where a large volume of data must be
stored on-chip. Effective utilization of these memory blocks can have a significant
impact on power reduction in your design.
The latest Stratix and Cyclone device families have configurable M9K memory blocks
that provide various memory functions such as RAM, FIFO buffers, and ROM.
f For more information about using DSP and memory blocks efficiently, refer to the
Area and Timing Optimization chapter in volume 2 of the Quartus II Handbook.
In this equation, F is the output transition frequency and C is the total load
capacitance being switched. V is equal to VCCIO supply voltage. Because of the
quadratic dependence on VCCIO, lower voltage standards consume significantly less
dynamic power.
Transistor-to-transistor logic (TTL) I/O buffers consume very little static power. As a
result, the total power consumed by a LVTTL or LVCMOS output is highly dependent
on load and switching frequency.
When using resistively terminated I/O standards like SSTL and HSTL, the output
load voltage swings by a small amount around some bias point. The same dynamic
power equation is used, where V is the actual load voltage swing. Because this is
much smaller than VCCIO, dynamic power is lower than for nonterminated I/O under
similar conditions. These resistively terminated I/O standards dissipate significant
static (frequency-independent) power, because the I/O buffer is constantly driving
May 2013
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1320
current into the resistive termination network. However, the lower dynamic power of
these I/O standards means they often have lower total power than LVCMOS or
LVTTL for high-frequency applications. Use the lowest drive strength I/O setting that
meets your speed and waveform requirements to minimize I/O power when using
resistively terminated standards.
You can save a small amount of static power by connecting unused I/O banks to the
lowest possible VCCIO voltage of 1.2 V.
Table 134 shows the total supply and thermal power consumed by outputs using
different I/O standards for Stratix II devices. The numbers are for an I/O pin
transmitting random data clocked at 200 MHz with a 10 pF capacitive load.
For this configuration, nonterminated standards generally use less power, but this is
not always the case. If the frequency or the capacitive load is increased, the power
consumed by nonterminated outputs increases faster than the power of terminated
outputs.
Table 134. I/O Power for Different I/O Standards in Stratix II Devices
Standard
3.3-V LVTTL
2.42
9.87
2.5-V LVCMOS
1.9
6.69
1.8-V LVCMOS
1.34
4.18
1.5-V LVCMOS
1.18
3.58
3.3-V PCI
2.47
10.23
SSTL-2 class I
6.07
4.42
SSTL-2 class II
10.72
5.1
SSTL-18 class I
5.33
3.28
SSTL-18 class II
8.56
4.06
HSTL-15 class I
6.06
3.49
HSTL-15 class II
11.08
4.87
HSTL-18 class I
6.87
4.09
HSTL-18 class II
12.33
5.82
f For more information about I/O standards, refer to the Selectable I/O Standards in
Stratix II Devices and Stratix II GX Devices chapter in volume 2 of the Stratix II Device
Handbook, the Stratix III Device I/O Features chapter in volume 1 of the Stratix III Device
Handbook, the I/O Features in Stratix IV Devices in volume 1 of the Stratix IV Device
Handbook, or the Selectable I/O Standards in Cyclone II Devices chapter in the Cyclone II
Device Handbook, the Cyclone III Device Handbook, or the Cyclone IV GX Handbook.
1321
When calculating I/O power, the PowerPlay Power Analyzer uses the default
capacitive load set for the I/O standard in the Capacitive Loading page of the Device
and Pin Options dialog box. For Stratix II devices, if Enable Advanced I/O Timing is
turned on, I/O power is measured using an equivalent load calculated as the sum of
the near capacitance, the transmission line distributed capacitance, and the far-end
capacitance as defined in the Board Trace Model page of the Device and Pin Options
dialog box or the Board Trace Model view in the Pin Planner. Any other components
defined in the board trace model are not taken into account for the power
measurement.
For Cyclone III, Cyclone IV GX, Stratix III, Stratix IV, and Stratix V, devices, Advanced
I/O Timing, which uses the full board trace model, is always used.
f For information about using Advanced I/O Timing and configuring a board trace
model, refer to the I/O Management chapter in volume 2 of the Quartus II Handbook.
Transmitter
GND
Receiver
The following is an example of power saving for a DDR3 interface using on-chip
parallel termination.
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Altera Corporation
1322
The static current consumed by parallel OCT is equal to the VCCIO voltage divided by
100 . For DDR3 interfaces that use SSTL-15, the static current is 1.5 V/100 = 15 mA
per pin. Therefore, the static power is 1.5 V 15 mA = 22.5 mW. For an interface with
72 DQ and 18 DQS pins, the static power is 90 pins 22.5 mW = 2.025 W. Dynamic
parallel OCT disables parallel termination during write operations, so if writing
occurs 50% of the time, the power saved by dynamic parallel OCT is 50% 2.025 W =
1.0125 W.
f For more information about dynamic OCT in Stratix IV and Stratix III devices, refer to
the Stratix III Device I/O Features chapter in the Stratix III Device Handbook and the
Stratix IV Device I/O Features chapter in the Stratix IV Device Handbook, respectively.
The Power Optimization Advisor shows the recommendations that can reduce power
in your design. The recommendations are split into stages to show the order in which
you should apply the recommended settings. The first stage shows mostly CAD
setting options that are easy to implement and highly effective in reducing design
power. An icon indicates whether each recommended setting is made in the current
1323
project. In Figure 1317, the checkmark icons for Stage 1 shows the recommendations
that are already implemented. The warning icons indicate recommendations that are
not followed for this compilation. The information icon shows the general
suggestions. Each recommendation includes the description, summary of the effect of
the recommendation, and the action required to make the appropriate setting.
There is a link from each recommendation to the appropriate location in the
Quartus II user interface where you can change the setting. You can change the
Power-Driven Synthesis setting by clicking Open Settings dialog box - Analysis &
Synthesis Settings page. The Settings dialog box is shown with the Analysis &
Synthesis Settings page selected, where you can change the PowerPlay power
optimization settings.
After making the recommended changes, recompile your design. The Power
Optimization Advisor indicates with green check marks that the recommendations
were implemented successfully (Figure 1318). You can use the PowerPlay Power
Analyzer to verify your design power results.
Figure 1318. Implementation of Power Optimization Advisor Recommendations
The recommendations listed in Stage 2 generally involve design changes, rather than
CAD settings changes as in Stage 1. You can use these recommendations to further
reduce your design power consumption. Altera recommends that you implement
Stage 1 recommendations first, then the Stage 2 recommendations.
Conclusion
The combination of a smaller process technology, the use of low-k dielectric material,
and reduced supply voltage significantly reduces dynamic power consumption in the
latest FPGAs. To further reduce your dynamic power, use the design
recommendations presented in this chapter to optimize resource utilization and
minimize power consumption.
May 2013
Altera Corporation
1324
Version
Changes
May 2013
13.0.0
Added a note to Memory Power Reduction Example on page 1316 on Qsys and SOPC
Builder power savings limitation for on-chip memory block.
June 2012
12.0.0
November 2011
10.0.2
Template update.
December 2010
10.0.1
Template update.
July 2010
10.0.0
November 2009
March 2009
9.0.0
November 2008
May 2008
9.1.0
8.1.0
8.0.0
Updated references
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
This chapter describes techniques to reduce resource usage when designing for
Altera devices.
This chapter includes the following topics:
Resource Utilization
Determining device utilization is important regardless of whether your design
achieved a successful fit. If your compilation results in a no-fit error, resource
utilization information is important for analyzing the fitting problems in your design.
If your fitting is successful, review the resource utilization information to determine
whether the future addition of extra logic or other design changes might introduce
fitting difficulties. Also, review the resource utilization information to determine if it
is impacting timing performance.
To determine resource usage, refer to the Flow Summary section of the Compilation
Report. This section reports resource utilization, including pins, memory bits, digital
signal processing (DSP) blocks, and phase-locked loops (PLLs). Flow Summary
indicates whether your design exceeds the available device resources. More detailed
information is available by viewing the reports under Resource Section in the Fitter
section of the Compilation Report.
Flow Summary shows the overall logic utilization. The Fitter can spread logic
throughout the device, which may lead to higher overall utilization.
As the device fills up, the Fitter automatically searches for logic functions with
common inputs to place in one ALM. The number of packed registers also increases.
Therefore, a design that has high overall utilization might still have space for extra
logic if the logic and registers can be packed together more tightly.
The reports under the Resource Section in the Fitter section of the Compilation
Report provide more detailed resource information. The Fitter Resource Usage
Summary report breaks down the logic utilization information and provides other
resource information, including the number of bits in each type of memory block. This
panel also contains a summary of the usage of global clocks, PLLs, DSP blocks, and
other device-specific resources.
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are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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142
You can also view reports describing some of the optimizations that occurred during
compilation. For example, if you use Quartus II integrated synthesis, the reports in
the Optimization Results folder in the Analysis & Synthesis section include
information about registers that integrated synthesis removed during synthesis. Use
this report to estimate device resource utilization for a partial design to ensure that
registers were not removed due to missing connections with other parts of the design.
If a specific resource usage is reported as less than 100% and a successful fit cannot be
achieved, either there are not enough routing resources or some assignments are
illegal. In either case, a message appears in the Processing tab of the Messages
window describing the problem.
If the Fitter finishes unsuccessfully and runs much faster than on similar designs, a
resource might be over-utilized or there might be an illegal assignment. If the
Quartus II software seems to run for an excessively long time compared to runs on
similar designs, a legal placement or route probably cannot be found. In the
Compilation Report, look for errors and warnings that indicate these types of
problems.
You can use the Chip Planner to find areas of the device that have routing congestion
on specific types of routing resources. If you find areas with very high congestion,
analyze the cause of the congestion. Issues such as high fan-out nets not using global
resources, an improperly chosen optimization goal (speed versus area), very
restrictive floorplan assignments, or the coding style can cause routing congestion.
After you identify the cause, modify the source or settings to reduce routing
congestion.
h For more information about Fitter Resources Report, refer to Fitter Resources Report in
Quartus II Help. For information about how to view routing congestion, refer to
Displaying Resources and Information in Quartus II Help. For information about using
the Chip Planner tool, refer to About the Chip Planner in Quartus II Help. For details
about using the Chip Planner tool, refer to the Analyzing and Optimizing the Design
Floorplan with the Chip Planner chapter of the Quartus II Handbook.
143
Issues relating to I/O pin utilization or placement, including dedicated I/O blocks
such as PLLs or LVDS transceivers (refer to I/O Pin Utilization or Placement).
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145
f For additional HDL coding examples, refer to AN 584: Timing Closure Methodology for
Advanced FPGA Designs.
In the Quartus II software, the Balanced setting typically produces utilization results
that are very similar to those produced by the Area setting, with better performance
results. The Area setting can give better results in some cases.
f For information about setting the timing requirements and synthesis options in
Quartus II integrated synthesis and other synthesis tools, refer to the appropriate
chapter in Synthesis in volume 1 of the Quartus II Handbook, or your synthesis
softwares documentation.
The Quartus II software provides additional attributes and options that can help
improve the quality of your synthesis results.
Restructure Multiplexers
Multiplexers form a large portion of the logic utilization in many FPGA designs. By
optimizing your multiplexed logic, you can achieve a more efficient implementation
in your Altera device.
h For more information about this option, refer to Restructure Multiplexers logic option in
Quartus II Help.
f For design guidelines to achieve optimal resource utilization for multiplexer designs,
refer to the Recommended HDL Coding Styles chapter in volume 1 of the Quartus II
Handbook.
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The Balanced setting typically produces utilization results that are very similar to the
Area setting with better performance results. The Area setting can give better results
in some cases. Performing WYSIWYG resynthesis for area in this way typically
reduces register-to-register timing performance.
h For information about this logic option, refer to Perform WYSIWYG Primitive
Resynthesis logic option in Quartus II Help.
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Consider the Resource Utilization by Entity report in the report file and determine
whether there is an unusually high register count in any of the modules. Some coding
styles can prevent the Quartus II software from inferring RAM blocks from the source
code because of the blocks architectural implementation, and force the software to
implement the logic in flipflops. As an example, a function such as an asynchronous
reset on a register bank might make the resistor bank incompatible with the RAM
blocks in the device architecture, so that the register bank is implemented in flipflops.
It is often possible to move a large register bank into RAM by slight modification of
associated logic.
f For more information about memory inference control in other synthesis tools, refer to
the appropriate chapter in Synthesis in volume 1 of the Quartus II Handbook, or your
synthesis softwares documentation. For more information about coding styles and
HDL examples that ensure memory inference, refer to the Recommended HDL Coding
Styles chapter in volume 1 of the Quartus II Handbook.
The compilation time might increase considerably when you use physical synthesis
options.
With the Quartus II software, you can apply physical synthesis options to specific
instances, which can reduce the impact on compilation time. Physical synthesis
instance assignments allow you to enable physical synthesis algorithms for specific
portions of your design.
The following physical synthesis optimizations for fitting are available:
h For more information, refer to Physical Synthesis Optimizations Page (Settings Dialog
Box) in Quartus II Help.
149
DSP blocks also can be inferred from your HDL code for multipliers, multiply-adders,
and multiply-accumulators. You can turn off this inference in your synthesis tool.
When you are using Quartus II integrated synthesis, you can disable inference by
turning off the Auto DSP Block Replacement logic option for your entire project. On
the Assignments menu, click Settings. In the Category list, select Analysis &
Synthesis Settings, click More Settings, and turn off Auto DSP Block Replacement.
Alternatively, you can disable the option for a specific block with the Assignment
Editor.
f For more information about disabling DSP block inference in other synthesis tools,
refer to the appropriate chapter in Synthesis in volume 1 of the Quartus II Handbook, or
your synthesis softwares documentation.
The Quartus II software also offers the DSP Block Balancing logic option, which
implements DSP block elements in logic cells or in different DSP block modes. The
default Auto setting allows DSP block balancing to convert the DSP block slices
automatically as appropriate to minimize the area and maximize the speed of the
design. You can use other settings for a specific node or entity, or on a project-wide
basis, to control how the Quartus II software converts DSP functions into logic cells
and DSP blocks. Using any value other than Auto or Off overrides the
DEDICATED_MULTIPLIER_CIRCUITRY parameter used in megafunction variations.
h For more details about the Quartus II logic options described in this section, refer to
Auto DSP Block Replacement logic option and DSP Block Balancing logic option in
Quartus II Help.
Routing
Use the suggestions in the following sections to help you resolve routing resource
problems.
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Any Router Effort Multiplier value greater than 4 only increases by 10% for every
additional 1. For example, a value of 10 is actually 4.6.
h For more information, refer to Router Effort Multiplier logic option in Quartus II Help.
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f For more information about the Routing Congestion task in the Chip Planner, refer to
the Analyzing and Optimizing the Design Floorplan with the Chip Planner chapter in
volume 2 of the Quartus II Handbook. You can also refer to About the Chip Planner in
Quartus II Help.
In the Quartus II software, the Balanced setting typically produces utilization results
that are very similar to those obtained with the Area setting, with better performance
results. The Area setting can yield better results in some unusual cases.
In some synthesis tools, not specifying an fMAX requirement can result in less resource
utilization, which can improve routability.
f For information about setting the timing requirements and synthesis options in
Quartus II integrated synthesis and other synthesis tools, refer to the appropriate
chapter in Synthesis in volume 1 of the Quartus II Handbook, or your synthesis
softwares documentation.
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If the logic-generated control signals have high fan-out, the design can be more
difficult to fit.
By default, the Quartus II software uses dedicated inputs for global control signals
automatically. You can assign control signals to dedicated input pins in one of the
following ways:
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On the Assignments menu, click Settings. On the Analysis & Synthesis Settings
page, click More Settings, and in the Existing Option settings section, select Auto
Global Register Control Signals.
Assign output pins that require parallel expanders to macrocells numbered 4 to 16.
h For more information about the Pin Advisor, refer to Pin Advisor Command (Tools
Menu) in Quartus II Help.
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f To minimize possible fitting errors when assigning the output enable pins for
MAX 7000 and MAX 3000 devices, refer to Pin-Out Files for Altera Devices on the
Altera website (www.altera.com).
LAB A
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
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Messages in the Messages window are also copied in the Report Files. For more
information about the message, right-click a message and click Help.
May 2013
On the Assignments menu, click Settings. In the Category list, select Analysis &
Synthesis Settings, click More Settings, and turn off Auto Parallel Expanders. If
the designs clock frequency (fMAX) is not an important design requirement, turn
off parallel expanders for all or part of the project. The design usually requires
more macrocells if parallel expanders are turned on.
Change Optimization Technique from Speed to Area. Selecting Area instructs the
compiler to give preference to area utilization rather than speed (fMAX). On the
Assignments menu, click Settings. In the Category list, change the Optimization
Technique option in the Analysis & Synthesis Settings page.
Use D-type flipflops instead of latches. Altera recommends always using D-type
flipflops instead of latches in your design because D-type flipflops can reduce the
macrocell fan-in, and thus reduce macrocell usage. The Quartus II software uses
extra logic to implement latches in MAX 7000 and MAX 3000 designs because
MAX 7000 and MAX 3000 macrocells contain D-type flipflops instead of latches.
Use asynchronous clear and preset instead of synchronous clear and preset. To
reduce product term usage, use asynchronous clear and preset in your design
whenever possible. Using other control signals such as synchronous clear
produces macrocells and pins with higher fan-out.
After following the suggestions in this section, if your project still does not fit the
targeted device, consider using a larger device. When upgrading to a different
density, the vertical package-migration feature of the MAX 7000 and MAX 3000
device families allows pin assignments to be maintained.
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Use dedicated inputs/global signals for high fan-out signals. The dedicated inputs
in MAX 7000 and MAX 3000 devices are designed for speed-critical and high
fan-out signals. Always assign high fan-out signals to dedicated inputs/global
signals.
Change the Optimization Technique option from Speed to Area. This option can
resolve routing resource and macrocell usage issues. Refer to Resolving Macrocell
Usage Issues on page 1415.
Reduce the fan-in per cell. If you are not limited by the number of macrocells used
in the design, you can use the Fan-in per cell (%) option to reduce the fan-in per
cell. The allowable values are 20100%; the default value is 100%. Reducing fan-in
can reduce localized routing congestion but increase the macrocell count. You can
set this logic option in the Assignment Editor or under More Settings in the
Analysis & Synthesis Settings page of the Settings dialog box.
On the Assignments menu, click Settings. In the Category list, select Analysis &
Synthesis Settings, click More Options, and turn off Auto Parallel Expanders. By
turning off the parallel expanders, you give the Quartus II software more fitting
flexibility for each macrocell, allowing macrocells to be relocated. For example,
you can move each macrocell (previously grouped together in the same LAB) to a
different LAB to reduce routing constraints.
Insert logic cells. Inserting logic cells reduces fan-in and shared expanders used
per macrocell, increasing routability. By default, the Quartus II software
automatically inserts logic cells when necessary. Otherwise, you can disable Auto
Logic Cell as follows:
Change pin assignments. If you want to discard your pin assignments, you can let
the Quartus II Fitter ignore some or all of the assignments.
1
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Instead of using the Auto Logic Cell Insertion option, you can manually insert logic
cells. However, Altera recommends using the Auto Logic Cell Insertion option unless
you know which part of the design is causing the congestion.
A good location to manually insert LCELL buffers is where a single complex logic
expression feeds multiple destinations in your design. You can insert an LCELL buffer
just after the complex expression; the Fitter extracts this complex expression and
places it in a separate logic cell. Rather than duplicate all the logic for each
destination, the Quartus II software feeds the single output from the logic cell to all
destinations.
To reduce fan-in and prevent no-fit compilations caused by routing resource issues,
insert an LCELL buffer after a NOR gate (Figure 142). The design in Figure 142 was
compiled for a MAX 7000AE device. Without the LCELL buffer, the design requires
two macrocells and eight shareable expanders, and the average fan-in is 14.5
macrocells. However, with the LCELL buffer, the design requires three macrocells and
eight shareable expanders, and the average fan-in is just 6.33 macrocells.
Figure 142. Reducing the Average Fan-In by Inserting LCELL Buffers
Scripting Support
You can run procedures and make settings described in this chapter in a Tcl script.
You can also run some procedures at a command prompt. For detailed information
about scripting command options, refer to the Quartus II command-line and Tcl API
Help browser. To run the Help browser, type the following command at the command
prompt:
quartus_sh --qhelp r
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f For more information about Tcl scripting, refer to the Tcl Scripting chapter in volume 2
of the Quartus II Handbook. For more information about all settings and constraints in
the Quartus II software, refer to the Quartus II Settings File Manual. For more
information about command-line scripting, refer to the Command-Line Scripting
chapter in volume 2 of the Quartus II Handbook.
You can specify many of the options described in this section either in an instance, or
at a global level, or both.
Use the following Tcl command to make a global assignment:
set_global_assignment -name <.qsf variable name> <value> r
If the <value> field includes spaces (for example, Standard Fit), you must enclose the
value in straight double quotation marks.
Values
Type
Placement Effort
Multiplier
PLACEMENT_EFFORT_MULTIPLIER
Global
Router Effort
Multiplier
ROUTER_EFFORT_MULTIPLIER
Global
Router Timing
Optimization level
ROUTER_TIMING_OPTIMIZATION_LEVEL
Global
Final Placement
Optimization
FINAL_PLACEMENT_OPTIMIZATION
Global
Values
Type
Auto Packed
Registers (1)
Global,
Instance
Perform WYSIWYG
Primitive
Resynthesis
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
ON, OFF
Global,
Instance
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Values
Type
Physical Synthesis
for Combinational
Logic for Reducing
Area
PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA
ON, OFF
Global,
Instance
Physical Synthesis
for Mapping Logic
to Memory
Global,
Instance
Optimization
Technique
Global,
Instance
Speed Optimization
Technique for Clock
Domains
SYNTH_CRITICAL_CLOCK
ON, OFF
Instance
State Machine
Encoding
STATE_MACHINE_PROCESSING
Global,
Instance
Auto RAM
Replacement
AUTO_RAM_RECOGNITION
ON, OFF
Global,
Instance
Auto ROM
Replacement
AUTO_ROM_RECOGNITION
ON, OFF
Global,
Instance
AUTO_SHIFT_REGISTER_RECOGNITION
ON, OFF
Global,
Instance
Auto Block
Replacement
AUTO_DSP_RECOGNITION
ON, OFF
Global,
Instance
Number of
Processors for
Parallel Compilation
NUM_PARALLEL_PROCESSORS
Global
May 2013
Version
1.0
Altera Corporation
Changes
Initial release.
1420
As FPGA designs grow larger in density, the ability to analyze the design for
performance, routing congestion, and logic placement to meet the design
requirements becomes critical. This chapter discusses how to analyze the design
floorplan with the Chip Planner.
Design floorplan analysis is a valuable method for achieving timing closure and
optimal performance in highly complex designs. With analysis capability, the
Quartus II Chip Planner helps you close timing quickly on your designs. Using the
Chip Planner together with LogicLock and Incremental Compilation enables you to
compile your designs hierarchically, preserving the timing results from individual
compilation runs. You can use LogicLock regions as part of an incremental
compilation methodology to improve your productivity.
You can perform design analysis, as well as creating and optimizing the design
floorplan with the Chip Planner. To make I/O assignments, use the Pin Planner.
f For information about the Pin Planner, refer to the I/O Management chapter in
volume 2 of the Quartus II Handbook.
f You can use the Design Partition Planner with the Chip Planner to customize the
floorplan of your design. For more information, refer to the Quartus II Incremental
Compilation for Hierarchical and Team-Based Design and the Best Practices for Incremental
Compilation Partitions and Floorplan Assignments chapters in volume 1 of the Quartus II
Handbook.
This chapter includes the following topics:
h For a list of devices supported by the Chip Planner, refer to About the Chip Planner in
Quartus II Help.
f For more information about the Chip Planner, refer to the Altera Training page of the
Altera website.
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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152
Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
Chip Planner Overview
On the Shortcut menu in the following tools, click Locate and then click Locate in
Chip Planner (Floorplan and Chip Editor):
Compilation Report
Node Finder
Simulation Report
RTL Viewer
Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
LogicLock Regions
153
LogicLock Regions
LogicLock regions are floorplan location constraints that help you place logic on the
target device. When you assign entity instances or nodes to a LogicLock region, you
direct the Fitter to place those entity instances or nodes within the region during
fitting. Your floorplan can contain several LogicLock regions.
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Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
LogicLock Regions
A LogicLock region is defined by its height, width, and location; you can specify the
size or location of a region, or both, or the Quartus II software can generate these
properties automatically. The Quartus II software bases the size and location of a
region on the contents of the region and the timing requirements of the module.
Table 151 describes the options for creating LogicLock regions.
Table 151. Types of LogicLock Regions
Property
Value
(1),
State
Floating
Locked
Size
Auto (1),
Fixed
Reserved
Off
On
Origin
Any
Floorplan
Location
(1)
Behavior
Floating allows the Quartus II software to determine the location of the region on the device.
Floating regions are shown with a dashed boundary in the floorplan. Locked allows you to
specify the location of the region. Locked regions are shown with a solid boundary in the
floorplan. A locked region must have a fixed size.
Auto allows the Quartus II software to determine the appropriate size of a region given its
contents. Fixed regions have a shape and size that you define.
Allows you to define whether the Fitter can use the resources within a region for entities that are
not assigned to the region. If the reserved property is turned on, only items assigned to the
region can be placed within its boundaries.
Specifies the location of the LogicLock region on the floorplan. For Arria series, Stratix series,
Cyclone series, MAX II, and MAX V devices, the origin is located at the lower left corner of the
LogicLock region. For other Altera device families, the origin is located at the upper left corner
of the LogicLock region.
The Quartus II software cannot automatically define the size of a region if the location
is locked. Therefore, if you want to specify the exact location of the region, you must
also specify the size.
f You can use the Design Partition Planner in conjunction with LogicLock regions to
create a floorplan for your design. For more information about using the Design
Partition Planner, refer to the Quartus II Incremental Compilation for Hierarchical and
Team-Based Designs and the Best Practices for Incremental Compilation Partition and
Floorplan Assignments chapters in volume 1 of the Quartus II Handbook.
Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
LogicLock Regions
155
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Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
LogicLock Regions
Figure 151 illustrates using the Merge LogicLock Region command to form a
nonrectangular LogicLock region by merging two rectangular LogicLock regions.
Figure 151. Using the Merge LogicLock Region command to create a nonrectangular region
The LogicLock region hierarchy does not have to be the same as the design hierarchy.
You can create both auto-sized and fixed-sized LogicLock regions within a parent
LogicLock region; however, the parent of a fixed-sized child region must also be
fixed-sized. The location of a locked parent region is locked relative to the device; the
location of a locked child region is locked relative to its parent region. If you change
the parents location, the locked childs origin changes, but maintains the same
placement relative to the origin of its parent. The location of a floating child region can
float within its parent. Complex region hierarchies might result in some LABs not
being used, effectively increasing the resource utilization in the device. Do not create
more levels of hierarchy than you need.
Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
LogicLock Regions
157
LogicLock regions with pin assignments must be placed on the periphery of the
device, adjacent to the pins. For the Arria series, Cyclone series, MAX II, MAX V,
and Stratix series of devices, you must also include the I/O block within the
LogicLock Region.
Floating LogicLock regions can overlap with their ancestors or descendants, but
not with other floating LogicLock regions.
Pin assignments to LogicLock regions are effective only in fixed and locked regions.
Pin assignments to floating regions do not influence the placement of the region.
Only one LogicLock region can claim a device resource. If a LogicLock region
boundary includes part of a device resource, the Quartus II software allocates the
entire resource to that LogicLock region. When the Quartus II software places a
floating auto-sized region, it places the region in an area that meets the requirements
of the contents of the LogicLock region.
May 2013
If you want to import multiple instances of a module into a top-level design, you must
ensure that the device has two or more locations with exactly the same device
resources. (You can determine this from the applicable device handbook.) If the device
does not have another area with exactly the same resources, the Quartus II software
generates a fitting error during compilation of the top-level design.
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Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
LogicLock Regions
The LogicLock Region Properties dialog box provides a summary of all LogicLock
regions in your design. Use the LogicLock Region Properties dialog box to obtain
detailed information about your LogicLock region, such as which entities and nodes
are assigned to your region and which resources are required. The LogicLock Region
Properties dialog box shows the properties of the current selected regions and allows
you to modify them. To open the LogicLock Region Properties dialog box,
double-click any region in the LogicLock Regions window, or right-click the region
and click Properties.
1
For designs that target Arria series, Cyclone series, Stratix series, MAX II, and MAX V
devices, the Quartus II software automatically creates a LogicLock region that
encompasses the entire device. This default region is labelled Root_Region, and is
locked and fixed.
For Arria series, Cyclone series, Stratix series, MAX II, and MAX V devices, the origin
of the LogicLock region is located at the lower-left corner of the region. For all other
supported devices, the origin is located at the upper-left corner of the region.
Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
LogicLock Regions
159
Excluded Resources
The Excluded Resources feature allows you to easily exclude specific device resources
such as DSP blocks or M4K memory blocks from a LogicLock region. For example,
you can assign a specific entity to a LogicLock region but allow the DSP blocks of that
entity to be placed anywhere on the device. Use the Excluded Resources feature on a
per-LogicLock region member basis.
To exclude certain device resources from an entity, in the LogicLock Region
Properties dialog box, highlight the entity in the Design Element column, and click
Edit. In the Edit Node dialog box, under Excluded Element Types, click the Browse
button. In the Excluded Resources Element Types dialog box, you can select the
device resources you want to exclude from the entity. When you have selected the
resources to exclude, the Excluded Resources column is updated in the LogicLock
Region Properties dialog box to reflect the excluded resources.
1
The Excluded Resources feature prevents certain resource types from being included
in a region, but it does not prevent the resources from being placed inside the region
unless you set the regions Reserved property to On. To indicate to the Fitter that
certain resources are not required inside a LogicLock region, define a resource filter.
For more information about resource filters, refer to LogicLock Resource Exclusions
in the Best Practices for Incremental Compilation Partitions and Floorplan Assignments
chapter in volume 1 of the Quartus II Handbook.
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Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
LogicLock Regions
Open the Priority dialog box by selecting Priority on the General tab of the
LogicLock Regions Properties dialog box. You can change the priority of path-based
and wildcard assignments with the Up and Down buttons in the Priority dialog box.
To prioritize assignments between regions, you must select multiple LogicLock
regions and then open the Priority dialog box from the LogicLock Regions Properties
dialog box.
Virtual Pins
A virtual pin is an I/O element that is temporarily mapped to a logic element and not
to a pin during compilation, and is then implemented as a LUT. Virtual pins should be
used only for I/O elements in lower-level design entities that become nodes when
imported to the top-level design. You can create virtual pins by assigning the Virtual
Pin logic option to an I/O element.
You might use virtual pin assignments when you compile a partial design, because
not all the I/Os from a partial design drive chip pins at the top level.
The virtual pin assignment identifies the I/O ports of a design module that are
internal nodes in the top-level design. These assignments prevent the number of I/O
ports in the lower-level modules from exceeding the total number of available device
pins. Every I/O port that you designate as a virtual pin becomes mapped to either a
logic cell or an adaptive logic module (ALM), depending on the target device.
Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
Using LogicLock Regions in the Chip Planner
1511
The Virtual Pin logic option must be assigned to an input or output pin. If you assign
this option to a bidirectional pin, tri-state pin, or registered I/O element, Analysis and
Synthesis ignores the assignment. If you assign this option to a tri-state pin, the Fitter
inserts an I/O buffer to account for the tri-state logic; therefore, the pin cannot be a
virtual pin. You can use multiplexer logic instead of a tri-state pin if you want to
continue to use the assigned pin as a virtual pin. Do not use tri-state logic except for
signals that connect directly to device I/O pins.
In the top-level design, you connect these virtual pins to an internal node of another
module. By making assignments to virtual pins, you can place those pins in the same
location or region on the device as that of the corresponding internal nodes in the
top-level module. You can use the Virtual Pin option when compiling a LogicLock
module with more pins than the target device allows. The Virtual Pin option can
enable timing analysis of a design module that more closely matches the performance
of the module after you integrate it into the top-level design.
In the Node Finder, you can set Filter Type to Pins: Virtual to display all assigned
virtual pins in the design. Alternatively, to access the Node Finder from the
Assignment Editor, double-click the To field; when the arrow appears on the right
side of the field, click the arrow and select Node Finder.
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Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
Design Floorplan Analysis Using the Chip Planner
You can view the logical connectivity between entities with the Design Partition
Planner, and the physical placement of those entities with the Chip Planner. In the
Design Partition Planner, you can identify entities that are highly interconnected, and
place those entities in a partition. In the Chip Planner, you can create LogicLock
regions and assign each partition to a LogicLock region, thereby preserving the
placement of the entities.
f For more information about using LogicLock regions with design partitions, refer to
the Quartus II Incremental Compilation for Hierarchical and Team-Based Design and the
Best Practices for Incremental Compilation Partition and Floorplan Assignments chapters in
volume 1 of the Quartus II Handbook. For more information about using the Design
Partition Planner with the Chip Planner, refer to About the Design Partition Planner and
Using the Design Partition Planner in Quartus II Help.
Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
Design Floorplan Analysis Using the Chip Planner
1513
Properties Window
The Properties Window displays detailed properties of the objects (such as atoms,
paths, LogicLock regions, or routing elements) currently selected in the Chip Planner.
To display the Properties Window, click Properties on the View menu in the Chip
Planner.
Device routing resources used by your designView how blocks are connected,
as well as the signal routing that connects the blocks.
I/O configurationView device I/O resource usage. For example, you can view
which components of the I/O resources are used, if the delay chain settings are
enabled, which I/O standards are set, and the signal flow through the I/O.
TimingView the delay between the inputs and outputs of FPGA elements. For
example, you can analyze the timing of the DATAB input to the COMBOUT output.
In addition, you can modify the following device properties with the Chip Planner:
May 2013
I/O cells
PLLs
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Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
Design Floorplan Analysis Using the Chip Planner
Placement of elements
f For more information about LEs, ALMs, and other resources of an FPGA device, refer
to the relevant device handbook.
Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
Design Floorplan Analysis Using the Chip Planner
1515
To display paths in the floorplan, you must first make timing settings and perform a
timing analysis.
f For more information about performing static timing analysis with the Quartus II
TimeQuest Timing Analyzer, refer to The Quartus II TimeQuest Timing Analyzer chapter
in volume 3 of the Quartus II Handbook.
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Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
Design Floorplan Analysis Using the Chip Planner
Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
Design Floorplan Analysis Using the Chip Planner
1517
Highlight Routing
The Show Physical Routing command in the Locate History pane enables you to
highlight the routing resources used by a selected path or connection. Figure 154
shows the routing resources in use between two logic elements.
Figure 154. Highlight Routing
f You can view and edit resources in the FPGA using the Resource Property Editor. For
more information, refer to the Engineering Change Management with the Chip Planner
chapter in volume 2 of the Quartus II Handbook.
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Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
Design Floorplan Analysis Using the Chip Planner
Show Delays
With the Show Delays command, you can view timing delays for paths located from
TimeQuest Timing Analyzer reports. For example, you can view the delay between
two logic resources or between a logic resource and a routing resource. Figure 155
shows the delay associated with a path located from a TimeQuest Timing Analyzer
report.
Figure 155. Show Delays
Locate Path from the Timing Analysis Report to the Chip Planner
To locate a path from the Timing Analysis report to the Chip Planner, perform the
following steps:
1. Select the path you want to locate.
Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
Design Floorplan Analysis Using the Chip Planner
1519
2. Right-click the path in the Timing Analysis report, point to Locate Path, and click
Locate in Chip Planner. The path is displayed with its timing data in the Chip
Planner main window and is listed in the Locate History window.
3. To view the routing resources taken for a path you have located in the Chip
Planner, select the path and then click the Highlight Routing icon in the Chip
Planner toolbar, or from the View menu, click Highlight Routing.
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Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
Design Floorplan Analysis Using the Chip Planner
You can make node and pin location assignments to LogicLock regions and custom
regions using the drag-and-drop method in the Chip Planner. The Fitter applies the
assignments that you create during the next place-and-route operation.
h For more information about managing assignments in the Chip Planner, refer to
Working With Assignments in the Chip Planner in Quartus II Help.
Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
Scripting Support
1521
When you select the Report High-Speed/Low-Power Tiles command for Stratix III,
Stratix IV, or Stratix V devices, the Chip Planner displays low-power and high-speed
tiles in contrasting colors; yellow tiles operate in a high-speed mode, while blue tiles
operate in a low-power mode (see Figure 158). When you select the Power task, you
can perform all floorplanner-related functions for this task; however, you cannot edit
tiles to change the power mode.
Figure 158. Viewing High-Speed and Low Power Tiles in a Stratix III Device
Scripting Support
You can run procedures and specify the settings described in this chapter in a Tcl
script. You can also run some procedures at a command prompt. For detailed
information about scripting command options, refer to the Quartus II command-line
and Tcl API Help browser. To run the Help browser, type the following command at
the command prompt:
quartus_sh --qhelp r
h Information about scripting command options is also available in API Functions for Tcl
in Quartus II Help.
f For more information about Tcl scripting, refer to the Tcl Scripting chapter in volume 2
of the Quartus II Handbook. For more information about command-line scripting, refer
to the Command-Line Scripting chapter in volume 2 of the Quartus II Handbook. For
information about all settings and constraints in the Quartus II software, refer to the
Quartus II Settings File Manual.
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Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
Scripting Support
Use the following Tcl command to uninitialize the LogicLock data structures before
closing your project:
uninitialize_logiclock
The command in the above example sets the size of the region to auto and the state to
floating.
If you specify a region name that does not exist in the design, the command creates
the region with the specified properties. If you specify the name of an existing region,
the command changes all properties you specify and leaves unspecified properties
unchanged.
For more information about creating LogicLock regions, refer to Creating LogicLock
Regions on page 154.
You can also make path-based assignments with the following Tcl command:
set_logiclock_contents -region my_region -from fifo -to ram*
Save a Node-Level Netlist for the Entire Design into a Persistent Source
File
Make the following assignments to cause the Quartus II Fitter to save a node-level
netlist for the entire design into a .vqm file:
set_global_assignment-name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT ON
set_global_assignment-name LOGICLOCK_INCREMENTAL_COMPILE_FILE <file
name>
Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
Document Revision History
1523
Any path specified in the file name is relative to the project directory. For example,
specifying atom_netlists/top.vqm places top.vqm in the atom_netlists subdirectory
of your project directory.
A .vqm file is saved in the directory specified at the completion of a full compilation.
1
The saving of a node-level netlist to a persistent source file is not supported for
designs targeting newer devices such as Arria GX, Arria II, Cyclone III, MAX V,
Stratix III, Stratix IV, or Stratix V.
For more information about assigning virtual pins, refer to Virtual Pins on
page 1510.
f For more information about Tcl scripting, refer to the Tcl Scripting chapter in volume 2
of the Quartus II Handbook.
Version
13.0.0
Changes
Updated Viewing Routing Congestion section
Updated references to Quartus UI controls for the Chip Planner
June 2012
12.0.0
November 2011
11.0.1
Template update.
May 2011
December 2010
May 2013
11.0.0
10.1.0
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Chapter 15: Analyzing and Optimizing the Design Floorplan with the Chip Planner
Document Revision History
Version
July 2010
10.0.0
November 2009
May 2008
Changes
Removed references to Timing Closure Floorplan; removed Design Analysis Using the
Timing Closure Floorplan section
Added Using LogicLock Regions with the Design Partition Planner section
Removed deprecated sections related to the Timing Closure Floorplan for older device
families. (For information on using the Timing Closure Floorplan with older device
families, refer to previous versions of the Quartus II Handbook, available in the Quartus II
Handbook Archive.)
9.1.0
8.0.0
LogicLock Regions
Reserve LogicLock Region Design Analysis Using the Timing Closure Floorplan
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
Because the node names for primitives in the design can change when you use
physical synthesis optimizations, you should evaluate whether your design flow
requires fixed node names. If you use a verification flow that might require fixed node
names, such as the SignalTap II Logic Analyzer, formal verification, or the LogicLock
based optimization flow (for legacy devices), you must turn off physical synthesis
options.
The Perform WYSIWYG primitive resynthesis option has no effect if you are using
Quartus II integrated synthesis to synthesize your design.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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162
163
The Perform WYSIWYG primitive resynthesis option unmaps and remaps only logic
cells, also referred to as LCELL or LE primitives, and regular I/O primitives (which
may contain registers). Double data rate (DDR) I/O primitives, memory primitives,
digital signal processing (DSP) primitives, and logic cells in carry/cascade chains are
not remapped. Logic specified in an encrypted .vqm file or an .edf file, such as
third-party intellectual property (IP), is not touched.
The Perform WYSIWYG primitive resynthesis option can change node names in the
.vqm file or .edf file from your third-party synthesis tool, because the primitives in the
atom netlist are broken apart and then remapped by the Quartus II software. The
remapping process removes duplicate registers, but registers that are not removed
retain the same name after remapping.
Any nodes or entities that have the Netlist Optimizations logic option set to Never
Allow are not affected during WYSIWYG primitive resynthesis. You can use the
Assignment Editor to apply the Netlist Optimizations logic option. This option
disables WYSIWYG resynthesis for parts of your design.
1
Primitive node names are specified during synthesis. When netlist optimizations are
applied, node names might change because primitives are created and removed. HDL
attributes applied to preserve logic in third-party synthesis tools cannot be
maintained because those attributes are not written into the atom netlist read by the
Quartus II software.
If you use the Quartus II software to synthesize, you can use the Preserve Register
(preserve) and Keep Combinational Logic (keep) attributes to maintain certain
nodes in the design.
f For more information about using these attributes during synthesis in the Quartus II
software, refer to the Quartus II Integrated Synthesis chapter in volume 1 of the
Quartus II Handbook.
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If you are migrating your design to a HardCopy II device, you can target physical
synthesis optimizations to the FPGA architecture in the FPGA-first flow or to the
HardCopy II architecture in the HardCopy-first flow. The optimizations are mapped
to the other device architecture during the migration process.
1
To optimize for better fitting, you can choose from the following options:
To view and modify the physical synthesis optimization options, perform the
following steps:
1. On the Assignments menu, click Settings. The Settings dialog box appears.
2. In the Category list, select Physical Synthesis Optimizations under Compilation
Process Settings. The Physical Synthesis Optimizations page appears.
3. Specify the options for performing physical synthesis optimizations.
Some physical synthesis options affect only registered logic and some options affect
only combinational logic. Select options based on whether you want to keep the
registers intact or not. For example, if your verification flow involves formal
verification, you might have to keep the registers intact.
165
All Physical Synthesis optimizations write results to the Netlist Optimizations report,
which provides a list of atom netlist files that were modified, created, and deleted
during physical synthesis. To access the Netlist Optimizations report, perform the
following steps:
1. On the Processing menu, click Compilation Report.
2. In the Compilation Report list, select Netlist Optimizations under Fitter.
Similarly, physical synthesis optimizations performed during synthesis write results
to the synthesis report. To access this report, perform the following steps:
1. On the Processing menu, click Compilation Report.
2. In the Compilation Report list, select Analysis & Synthesis.
3. In the Optimization Results folder, select Netlist Optimizations. The Physical
Synthesis Netlist Optimizations table appears, listing the physical synthesis
netlist optimizations performed during synthesis.
Nodes or entities that have the Netlist Optimizations logic option set to Never Allow
are not affected by the physical synthesis algorithms. You can use the Assignment
Editor to apply the Netlist Optimizations logic option. Use this option to disable
physical synthesis optimizations for parts of your design.
The Perform automatic asynchronous signal pipelining option adds registers to nets
driving the asynchronous clear or asynchronous load ports of registers. These
additional registers add register delays (adds latency) to the reset, adding the same
number of register delays for each destination using the reset. The additional register
delays can change the behavior of the signal in the design; therefore, you should use
this option only if additional latency on the reset signals does not violate any design
requirements. This option also prevents the promotion of signals to global routing
resources.
The Quartus II software performs automatic asynchronous signal pipelining only if
Enable Recovery/Removal analysis is turned on. If you use the TimeQuest Timing
Analyzer, Enable Recovery/Removal analysis is turned on by default. Pipelining is
allowed only on asynchronous signals that have the following properties:
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The Quartus II software does not perform automatic asynchronous signal pipelining
on asynchronous signals that have the Netlist Optimization logic option set to Never
Allow.
If you want to consider logic cells with any of these conditions for physical synthesis,
you can override these rules by setting the Netlist Optimizations logic option to
Always Allow on a given set of nodes.
167
The Quartus II software does not perform register duplication on logic cells that have
the following properties:
Contain registers that are driven by input pins without a tSU constraint
f For more information about virtual I/O pins, refer to the Analyzing and Optimizing the
Design Floorplan chapter in volume 2 of the Quartus II Handbook.
If you want to consider logic cells that meet any of these conditions for physical
synthesis, you can override these rules by setting the Netlist Optimizations logic
option to Always Allow on a given set of nodes.
Retiming can create multiple registers at the input of a combinational block from a
register at the output of a combinational block. In this case, the new registers have the
same clock and clock enable. The asynchronous control signals and power-up level
are derived from previous registers to provide equivalent functionality. Retiming can
also combine multiple registers at the input of a combinational block to a single
register (Figure 163).
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To move registers across combinational logic to balance timing, perform the following
steps:
1. On the Assignments menu, click Settings. The Settings dialog box appears.
2. In the Category list, select Physical Synthesis Optimizations under Compilation
Process Settings. The Physical Synthesis Optimizations page appears.
3. Specify your preferred option under Optimize for performance (physical
synthesis) and Effort level.
4. Click OK.
h For more information about the Optimize for performance (physical synthesis)
options and effort levels, refer to Physical Synthesis Optimizations Page (Settings Dialog
Box) in Quartus II Help.
If you want to prevent register movement during register retiming, you can set the
Netlist Optimizations logic option to Never Allow. You can apply this option to
either individual registers or entities in the design using the Assignment Editor.
In digital circuits, synchronization registers are instantiated on cross clock domain
paths to reduce the possibility of metastability. The Quartus II software detects such
synchronization registers and does not move them, even if register retiming is turned
on.
The following sets of registers are not moved during register retiming:
The Quartus II software assumes that a synchronization register chain consists of two
registers. If your design has synchronization register chains with more than two
registers, you must indicate the number of registers in your synchronization chains so
that they are not affected by register retiming. To do this, perform the following steps:
1. On the Assignments menu, click Settings. The Settings dialog box appears.
2. In the Category list, select Analysis & Synthesis Settings. The Analysis &
Synthesis Setting page appears.
169
3. Click More Settings. The More Analysis & Synthesis Settings dialog box
appears.
4. In the Name list, select Synchronization Register Chain Length and modify the
setting to match the synchronization register length used in your design. If you set
a value of 1 for the Synchronization Register Chain Length, it means that any
registers connected to the first register in a register-to-register connection can be
moved during retiming. A value of n > 1 means that any registers in a sequence of
length 1, 2, n are not moved during register retiming.
The Quartus II software does not perform register retiming on logic cells that have the
following properties:
The Quartus II software does not usually retime registers across different
clock domains; however, if you use the Classic Timing Analyzer and specify
a global fMAX requirement, the Quartus II software interprets all clocks as
related. Consequently, the Quartus II software might try to retime registerto-register paths associated with different clocks.
To avoid this circumstance, provide individual fMAX requirements to each
clock when using Classic Timing Analysis. When you constrain each clock
individually, the Quartus II software assumes no relationship between
different clock domains and considers each clock domain to be asychronous
to other clock domains; hence no register-to-register paths crossing clock
domains are retimed.
When you use the TimeQuest Timing Analyzer, register-to-register paths
across clock domains are never retimed, because the TimeQuest Timing
Analyzer treats all clock domains as asychronous to each other unless they
are intentionally grouped.
Registers that have the Netlist Optimizations logic option set to Never Allow
f For more information about virtual I/O pins, refer to the Analyzing and Optimizing the
Design Floorplan chapter in volume 2 of the Quartus II Handbook.
If you want to consider logic cells that meet any of these conditions for physical
synthesis, you can override these rules by setting the Netlist Optimizations logic
option to Always Allow on a given set of registers.
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1611
If you use the physical synthesis optimizations and want to lock down the location of
all LEs and other device resources in the design with the Back-Annotate Assignments
command, a .vqm file netlist is required. The .vqm file preserves the changes that you
made to your original netlist. Because the physical synthesis optimizations depend on
the placement of the nodes in the design, back-annotating the placement changes the
results from physical synthesis. Changing the results means that node names are
different, and your back-annotated locations are no longer valid.
You should not use a Quartus II-generated .vqm file or back-annotated location
assignments with physical synthesis optimizations unless you have finalized the
design. Making any changes to the design invalidates your physical synthesis results
and back-annotated location assignments. If you require changes later, use the new
source HDL code as your input files, and remove the back-annotated assignments
corresponding to the Quartus II-generated .vqm file.
To back-annotate logic locations for a design that was compiled with physical
synthesis optimizations, first create a .vqm file. When recompiling the design with the
hard logic location assignments, use the new .vqm file as the input source file and
turn off the physical synthesis optimizations for the new compilation.
If you are importing a .vqm file and back-annotated locations into another project that
has any Netlist Optimizations turned on, you must apply the Never Allow
constraint to make sure node names dont change; otherwise, the back-annotated
location or LogicLock assignments are invalid.
1
For newer devices, such as the Arria, Cyclone, or Stratix series, use incremental
compilation to preserve compilation results instead of using logic back-annotation.
Function
When you select this option, the Fitter detects duplicate combinational logic and optimizes
combinational logic to improve the fit.
When you select this option, the Fitter can remap registers and combinational logic in your
design into unused memory blocks and achieves a fit.
h For more information about physical synthesis optimization options, refer to Physical
Synthesis Optimizations Page (Settings Dialog Box) in Quartus II Help.
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Scripting Support
You can run procedures and make settings described in this chapter in a Tcl script.
You can also run some procedures at a command prompt. For detailed information
about scripting command options, refer to the Quartus II Command-Line and Tcl API
Help browser. To run the Help browser, type the following command at the command
prompt:
quartus_sh --qhelp r
f For more information about Tcl scripting, refer to the Tcl Scripting chapter in volume 2
of the Quartus II Handbook and API Functions for Tcl in Quartus II Help. Refer to the
Quartus II Settings File Manual for information about all settings and constraints in the
Quartus II software. For more information about command-line scripting, refer to the
Command-Line Scripting chapter in volume 2 of the Quartus II Handbook.
You can specify many of the options described in this section on either an instance or
global level, or both.
Use the following Tcl command to make a global assignment:
set_global_assignment -name <QSF variable name> <value> r
1613
Values
Type
ADV_NETLIST_OPT_SYNTH_WYSIWYG_
Perform WYSIWYG
Primitive Resynthesis REMAP
ON, OFF
Global,
Instance
Optimization
Technique
AREA, SPEED,
BALANCED
Global,
Instance
ALLOW_POWER_UP_DONT_CARE
ON, OFF
Global
Save a node-level
netlist into a
persistent source file
LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT
ON, OFF
LOGICLOCK_INCREMENTAL_COMPILE_FILE
<file name>
ADV_NETLIST_OPT_ALLOWED
"ALWAYS ALLOW",
DEFAULT, "NEVER
ALLOW"
Allow Netlist
Optimizations
Global
Instance
Values
Type
Physical Synthesis
for Combinational
Logic
PHYSICAL_SYNTHESIS_COMBO_LOGIC
ON, OFF
Global
Automatic
Asynchronous Signal
Pipelining
PHYSICAL_SYNTHESIS_ASYNCHRONOUS_
SIGNAL_PIPELINING
ON, OFF
Global
Perform Register
Duplication
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION
ON, OFF
Global
Perform Register
Retiming
PHYSICAL_SYNTHESIS_REGISTER_RETIMING
ON, OFF
Global
ALLOW_POWER_UP_DONT_CARE
ON, OFF
Global,
Instance
Power-Up Level
POWER_UP_LEVEL
HIGH,LOW
Instance
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Allow Netlist
Optimizations
Save a node-level
netlist into a
persistent source file
Values
ADV_NETLIST_OPT_ALLOWED
"ALWAYS
ALLOW",
DEFAULT,
"NEVER
ALLOW"
LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT
ON, OFF
LOGICLOCK_INCREMENTAL_COMPILE_FILE
<file name>
Type
Instance
Global
Incremental Compilation
For information about scripting and command line usage for incremental compilation
as mentioned in Preserving Your Physical Synthesis Results on page 1610, refer to
the Quartus II Incremental Compilation for Hierarchical and Team-Based Design chapter in
volume 1 of the Quartus II Handbook.
Back-Annotating Assignments
You can use the logiclock_back_annotate Tcl command to back-annotate resources
in your design. This command can back-annotate resources in LogicLock regions, and
resources in designs without LogicLock regions.
For more information about back-annotating assignments, refer to Preserving Your
Physical Synthesis Results on page 1610.
The following Tcl command back-annotates all registers in your design:
logiclock_back_annotate -resource_filter "REGISTER"
Conclusion
Physical synthesis optimizations restructure and optimize your design netlist. You
can take advantage of these Quartus II netlist optimizations to help improve your
quality of results.
Version
Changes
June 2012
12.0.0
November 2011
10.0.2
Template update.
December 2010
10.0.1
Template update.
1615
Version
July 2010
10.0.0
November 2009
March 2009
9.1.0
9.0.0
November 2008
8.1.0
May 2008
8.0.0
Changes
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
June 2012
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1616
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
In addition to making ECOs, the Chip Planner allows you to perform detailed
analysis on routing congestion, relative resource usage, logic placement, LogicLock
regions, fan-ins and fan-outs, paths between registers, and delay estimates for paths.
f For more information about using the Chip Planner for design analysis, refer to the
Analyzing and Optimizing the Design Floorplan chapter in volume 2 of the Quartus II
Handbook.
f ECOs directly apply to atoms in the target device. As such, performing an ECO relies
on your understanding of the device architecture of the target device. For more
information about the architecture of your device, refer to the appropriate device
handbook on the Literature page of the Altera website.
This chapter includes the following topics:
Performing ECOs with the Chip Planner (Floorplan View) on page 176
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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9001:2008
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172
Performance Preservation
Compilation Time
Verification
Performance Preservation
You can preserve the results of previous design optimizations when you make
changes to an existing design with one of the following methods:
Incremental compilation
Rapid recompile
ECOs
Choose the method to modify your design based on the scope of the change. The
methods above are arranged from the larger scale change to the smallest targeted
change to a compiled design.
The incremental compilation feature allows you to preserve compilation results at an
RTL component or module level. After the initial compilation of your design, you can
assign modules in your design hierarchy to partitions. Upon subsequent
compilations, incremental compilation recompiles changed partitions based on the
chosen preservation levels.
The rapid recompilation feature leverages results from the latest post-fit netlist to
determine the changes required to honor modifications you have made to the source
code. If you turn on the rapid recompilation feature, the Compiler attempts to refit
only the portion of the netlist that is related to the code modification.
ECOs provide a finer granularity of control compared to the incremental compilation
and the rapid recompilation feature. All modifications are performed directly on the
architectural elements of the device. You should use ECOs for targeted changes to the
post-fit netlist.
173
In the Quartus II software versions 10.0 and later, the software does not preserve ECO
modifications to the netlist when you recompile a design with the incremental
compilation feature turned on. You can reapply ECO changes made during a previous
compilation with the Change Manager.
f For more information about the incremental compilation feature, refer to the
Quartus II Incremental Compilation for Hierarchical and Team-Based Design chapter in
volume 1 of the Quartus II Handbook.
Compilation Time
In the traditional programmable logic design flow, a small change in the design
requires a complete recompilation of the design. A complete recompilation of the
design consists of synthesis and place-and-route. Making small changes to the design
to reach the final implementation on a board can be a long process. Because the Chip
Planner works only on the post-place-and-route database, you can implement your
design changes in minutes without performing a full compilation.
Verification
After you make a design change, you can verify the impact on your design. To verify
that your changes do not violate timing requirements, perform static timing analysis
with the Quartus II TimeQuest Timing Analyzer after you check and save your netlist
changes in the Chip Planner.
f For more information about the TimeQuest analyzer, refer to the Quartus II TimeQuest
Timing Analyzer chapter in volume 3 of the Quartus II Handbook.
Additionally, you can perform a gate-level or timing simulation of the ECO-modified
design with the post-place-and-route netlist generated by the Quartus II software.
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VHDL
(.vhdl)
Block Design
file
(.bdf)
AHDL
(.tdf)
EDIF Netlist
(.edf)
VQM Netlist
(.vqm)
Partition Top
Partition 1
Partition 2
Partition Merge
Create complete netlist using
appropriate source netlists for each
partition (post-fit or post-synthesis)
ECO performs
partial refit
Fitter
Assembler
Modify
Logic cells, I/O cells,
PLL, Floorplan location
assignments in Chip Planner
Timing Analyzer
Program/Configuration Device
no
Make ECO
at Netlist level
Requirements
Satisfied?
no
yes
For iterative verification cycles, implementing small design changes at the netlist level
can be faster than making an RTL code change. As such, making ECO changes are
especially helpful when you debug the design on silicon and require a fast
turnaround time to generate a programming file for debugging the design.
175
A typical ECO application occurs when you uncover a problem on the board and
isolate the problem to the appropriate nodes or I/O cells on the device. You must be
able to correct the functionality quickly and generate a new programming file. By
making small changes with the Chip Planner, you can modify the
post-place-and-route netlist directly without having to perform synthesis and logic
mapping, thus decreasing the turnaround time for programming file generation
during the verification cycle. If the change corrects the problem, no modification of
the HDL source code is necessary. You can use the Chip Planner to perform the
following ECO-related changes to your design:
For more complex changes that require HDL source code modifications, the
incremental compilation feature can help reduce recompilation time.
June 2012
Compilation Report
Altera Corporation
176
Node Finder
Simulation Report
RTL Viewer
Create atoms
Delete atoms
177
Logic Elements
An Altera LE contains a four-input LUT, which is a function generator that can
implement any function of four variables. In addition, each LE contains a register fed
by the output of the LUT or by an independent function generated in another LE.
You can use the Resource Property Editor to view and edit any LE in the FPGA. To
open the Resource Property Editor for an LE, on the Project menu, point to Locate,
and then click Locate in Resource Property Editor in one of the following views:
RTL Viewer
Node Finder
Chip Planner
f For more information about LE architecture for a particular device family, refer to the
device family handbook or data sheet.
You can use the Resource Property Editor to change the following LE properties:
June 2012
Altera Corporation
178
(1)
179
Modes of Operation
LUTs in an LE can operate in either normal or arithmetic mode.
When an LE is configured in normal mode, the LUT in the LE can implement a
function of four inputs.
When the LE is configured in arithmetic mode, the LUT in the LE is divided into two
3-input LUTs. The first LUT generates the signal that drives the output of the LUT,
while the second LUT generates the carry-out signal. The carry-out signal can drive
only a carry-in signal of another LE.
f For more information about LE modes of operation, refer to volume 1 of the
appropriate device handbook.
June 2012
Altera Corporation
1710
Two 6-input functions, if they share four inputs and share the same functions
1711
You can use the Resource Property Editor to change the following ALM properties:
(1)
June 2012
Altera Corporation
1712
Delay chain
Bus hold
Weak pull up
I/O standard
Current strength
Extend OE disable
PCI I/O
Register power up
Register mode
1713
By default, the Quartus II software displays the used resources in blue and the unused
resources in gray.
Figure 176. Stratix V Device I/O Element Structure
f For more information about I/O elements in Stratix V devices, refer to the Stratix V
Device Handbook.
June 2012
Altera Corporation
1714
f For more information about I/O elements in Stratix and Stratix GX devices, refer to
the Stratix Device Handbook and the Stratix GX Device Handbook.
1715
f For more information about I/O elements in Stratix III and Stratix IV devices, refer to
the Literature page of the Altera website.
f For more information about programmable I/O elements in Stratix III devices, refer to
AN 474: Implementing Stratix III Programmable I/O Delay Settings in the Quartus II
Software.
June 2012
Altera Corporation
1716
f For more information about I/O elements in Cyclone II and Cyclone devices, refer to
the Cyclone II Device Handbook and Cyclone Device Handbook, respectively.
1717
f For more information about I/O elements in Cyclone III devices, refer to the
Cyclone III Device Handbook.
June 2012
Altera Corporation
1718
f For more information about I/O elements in MAX II devices, refer to the MAX II
Device Handbook.
1719
June 2012
Altera Corporation
1720
(1)
1721
Change Manager
The Change Manager maintains a record of every change you perform with the Chip
Planner, the Resource Property Editor, the SignalProbe feature, or a Tcl script. Each
row of data in the Change Manager represents one ECO.
The Change Manager allows you to apply changes, roll back changes, delete changes,
and export change records to a Text File (.txt), a Comma-Separated Value File (.csv),
or a Tcl Script File (.tcl). The Change Manager tracks dependencies between changes,
so that when you apply, roll back, or delete a change, any prerequisite or dependent
changes are also applied, rolled back, or deleted.
h For more information about the Change Manager, refer to About the Change Manager in
Quartus II Help.
Exporting Changes
You can export changes to a .txt, a .csv, or a .tcl. Tcl scripts allow you to reapply
changes that were deleted during compilation.
h For more information about exporting changes, refer to Managing Changes With the
Change Manager in Quartus II Help.
f For more information about netlist types and the Quartus II incremental compilation
feature, refer to the Quartus II Incremental Compilation for Hierarchical and Team-Based
Design chapter in volume 1 of the Quartus II Handbook.
June 2012
Altera Corporation
1722
Scripting Support
You can run procedures and make settings described in this chapter in a Tcl script.
You can also run some procedures at a command prompt. The Tcl commands for
controlling the Chip Planner are located in the chip_planner package of the
quartus_cdb executable.
h A comprehensive list of Tcl commands for the Chip Planner can be found in About
Quartus II Scripting in Quartus II Help.
f For more information about Tcl scripting, refer to the Tcl Scripting chapter in volume 2
of the Quartus II Handbook. For more information about all settings and constraints in
the Quartus II software, refer to the Quartus II Settings File Manual. For more
information about command-line scripting, refer to the Command-Line Scripting
chapter in volume 2 of the Quartus II Handbook.
Modify the PLL properties with the Resource Property Editor (see Modify the
PLL Properties With the Chip Planner on page 1723)
Modify the connectivity between new resource atoms with the Chip Planner and
Resource Property Editor
1723
1. In the Editing Mode list at the top of the Chip Planner, select the ECO editing
mode.
2. Locate the I/O in the Resource Property Editor, as shown in Figure 1714.
Figure 1714. I/O in the Resource Property Editor
3. In the Resource Property Editor, point to the Current Strength option in the
Properties pane and double-click the value to enable the drop-down list.
4. Change the value for the Current Strength option.
5. Right-click the ECO change in the Change Manager and click Check & Save All
Netlist Changes to apply the ECO change.
1
You can change the pin locations of input or output ports with the ECO flow. You can
drag and move the signal from an existing pin location to a new location while in the
Post Compilation Editing (ECO) task in the Chip Planner. You can then click Check &
Save All Netlist Changes to compile the ECO.
June 2012
Altera Corporation
1724
The Resource Property Editor allows you to view and modify PLL properties to meet
your design requirements. Using the Stratix PLL as an example, the rest of this section
describes the adjustable PLL properties and the equations as a function of the
adjustable PLL properties that govern the PLL output parameters.
Figure 1715 shows a Stratix PLL in the Resource Property Editor.
Figure 1715. PLL View in a Stratix Device
PLL Properties
The Resource Property Editor allows you to modify PLL options, such as phase shift,
output clock frequency, and duty cycle. You can also change the following PLL
properties with the Resource Property Editor:
Input frequency
M VCO tap
M initial
M value
N value
M counter delay
N counter delay
M2 value
N2 value
SS counter
Counter delay
Counter high
Counter low
Counter mode
Counter initial
VCO tap
1725
You can also view post-compilation PLL properties in the Compilation Report. To do
so, in the Compilation Report, select Fitter and then select Resource Section.
For normal mode, Tap VCO, Initial VCO, and Period VCO are governed by the following
settings:
Tap V CO = Counter Delay M Tap V CO
Initial V CO = Counter Initial M Initial
Period V CO = In Clock Period N M
For external feedback mode, Tap VCO, Initial VCO, and Period VCO are governed by the
following settings:
Tap V CO = Counter Delay M Tap V CO
Initial V CO = Counter Initial M Initial
In Clock Period N
Period V CO = ----------------------------------------------------------------------------------------------( M + Counter High + Counter Low )
June 2012
Altera Corporation
1726
f For a detailed description of the settings, refer to the Quartus II Help. For more
information about Stratix device PLLs, refer to the Stratix Architecture chapter in
volume 1 of the Stratix Device Handbook. For more information about PLLs in
Arria GX, Cyclone, Cyclone II, and Stratix II devices, refer to the appropriate device
handbook.
Use Equation 174 to adjust the PLL output clock in external feedback mode.
Equation 174.
M value + External Feedback Counter High + External Feedback Counter Low
OUTCLK = --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------N value + Counter High + Counter Low
1727
A successful ECO connection is subject to the available routing resources. You can
view the relative routing utilization by selecting Routing Utilization as the
Background Color Map in the Layers Settings dialog box of the Chip Planner. Also,
you can view individual routing channel utilization from local, row, and column
interconnects with the tooltips created when you position your mouse pointer over
the appropriate resource. Refer to the device data sheet for more information about
the architecture of the routing interconnects of your device.
Conclusion
The Chip Planner allows you to analyze and modify your design floorplan. Also, ECO
changes made with the Chip Planner do not require a full recompilation, eliminating
the lengthy process of RTL modification, resynthesis, and another place-and-route
cycle. In summary, the Chip Planner speeds design verification and timing closure.
June 2012
Altera Corporation
1728
Version
Changes
June 2012
12.0.0
November 2011
10.1.1
Template update.
December 2010
July 2010
10.0.0
November 2009
March 2009
9.1.0
9.0.0
November 2008
May 2008
10.1.0
8.1.0
8.0.0
Combined Creating Atoms, Deleting Atoms, and Moving Atoms sections, and linked
to Help.
Changed heading from Resource Property Editor to Performing ECOs in the Resource
Property Editor on page 1715.
Removed Using Incremental Compilation in the ECO Flow section. Preservation support
for ECOs with the incremental compilation flow has been removed in the Quartus II
software version 10.0.
Corrected preservation attributes for ECOs in the section Using Incremental Compilation
in the ECO Flow on page 1532.
Modified description for ECO support for block RAMs and DSP blocks
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
Additional Information
This chapter provides additional information about the document and Altera.
Contact Method
Address
Website
www.altera.com/support
Website
www.altera.com/training
Email
Website
custrain@altera.com
www.altera.com/literature
nacomp@altera.com
(software licensing)
authorization@altera.com
Note to Table:
(1) You can also contact your local Altera sales office or sales representative.
May 2013
Altera Corporation
Info2
Additional Information
Typographic Conventions
Typographic Conventions
The following table shows the typographic conventions this document uses.
Visual Cue
Meaning
Indicate command names, dialog box titles, dialog box options, and other GUI
labels. For example, Save As dialog box. For GUI elements, capitalization matches
the GUI.
bold type
Indicates directory names, project names, disk drive names, file names, file name
extensions, software utility names, and GUI labels. For example, \qdesigns
directory, D: drive, and chiptrip.gdf file.
italic type
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Indicate keyboard keys and menu names. For example, the Delete key and the
Options menu.
Subheading Title
Courier type
Indicates command line commands and anything that must be typed exactly as it
appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.
Also indicates sections of an actual file, such as a Report File, references to parts of
files (for example, the AHDL keyword SUBDESIGN), and logic function names (for
example, TRI).
Numbered steps indicate a list of items when the sequence of the items is important,
such as the steps listed in a procedure.
Bullets indicate a list of items when the sequence of the items is not important.
The question mark directs you to a software help system with related information.
The feet direct you to another document or website with related information.
A warning calls attention to a condition or possible situation that can cause you
injury.
The envelope links to the Email Subscription Management Center page of the Altera
website, where you can sign up to receive update notifications for Altera documents.
The feedback icon allows you to submit feedback to Altera about the document.
Methods for collecting feedback vary as appropriate for each document.
The social media icons allow you to inform others about Altera documents. Methods
for submitting information vary as appropriate for each medium.
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
ISO
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and 9001:2008
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service Registered
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
May 2013
Altera Corporation
The Quartus II Handbook Volume 3: Verification was revised on the following dates.
Chapter 1.
Chapter 2.
Chapter 3.
Chapter 4.
Chapter 5.
Chapter 6.
Chapter 7.
Chapter 8.
Chapter 9.
Chapter 10. Analyzing and Debugging Designs with the System Console
Revised:
May 2013
Part Number: QII53028-13.0.0
Chapter 11. Debugging Transceiver Links
Revised:
May 2013
Part Number: QII53029-13.0.0
Chapter 12. Quick Design Debugging Using SignalProbe
Revised:
May 2013
Part Number: QII53008-13.0.0
May 2013
Altera Corporation
iv
Section I. Simulation
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Section I: Simulation
This document describes simulating designs that target Altera devices. Simulation
verifies design behavior before device programming. The Quartus II software
supports RTL and gate level design simulation in third-party EDA simulators.
Design Entry
(HDL, Qsys, DSP Builder)
Altera Simulation
Models
Quartus II
Design Flow
Gate-Level Simulation
Fitter
(place-and-route)
RTL Simulation
EDA
Netlist
Writer
Post-synthesis functional
simulation netlist
Post-synthesis
functional
simulation
Post-fit functional
simulation netlist
Post-fit functional
simulation
Post-fit timing
simulation netlist (1)
(Optional)
Post-fit
Post-fit timing
timing
simulation
simulation
(3)
Device Programmer
(1) Timing simulation is not supported for Arria V, Cyclone V, Stratix V, and newer families.
You can use the Quartus II NativeLink feature to automatically generate simulation
files and scripts. NativeLink can launch your simulator a from within the Quartus II
software. Use a custom flow for more control over all aspects of simulation file
generation.
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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12
Simulator Support
The Quartus II software supports specific versions of the following EDA simulators
for RTL and gate-level simulation.
Table 11. Supported Simulators
Vendor
Aldec
Simulator
Platform
Active-HDL
Windows
Aldec
Riviera-PRO
Windows, Linux
Cadence
Incisive Enterprise
Linux
Mentor Graphics
ModelSim-Altera (provided)
Windows, Linux
Mentor Graphics
ModelSim PE
Windows
Mentor Graphics
ModelSim SE
Windows, Linux
Mentor Graphics
QuestaSim
Windows, Linux
Synopsys
VCS/VCS MX
Linux
Simulation Levels
Table 12 describes the supported Quartus II simulation levels.
Table 12. Supported Simulation Levels
Simulation Level
RTL
Gate-level functional
Gate-level timing
Description
Simulation Input
Design source/testbench
IP simulation models
Altera IP BFMs
Qsys-generated models
Verification IP
Testbench
Post-synthesis or post-fit
functional netlist
Testbench
Gate-level timing simulation of an entire design can be slow and should be avoided.
Gate-level timing simulation is not supported for Arria V, Cyclone V, or Stratix V
devices. Rely on TimeQuest static timing analysis rather than on gate-level timing
simulation.
13
Simulation Flows
Table 13 describes the supported Quartus II simulation flows.
Table 13. Simulation Flows
Simulation Flow
Description
The NativeLink automated flow supports a variety of design flows. NativeLink is
not recommended if you require direct control over every aspect of simulation.
NativeLink flow
Design files
Custom flows support manual control of all aspects of simulation, including the
following:
Manually compile and simulate testbench, design, IP, and simulation model
libraries, or write scripts to automate compilation and simulation in your
simulator.
Use the Simulation Library Compiler to compile simulation libraries for all
Altera devices and supported third-party simulators and languages, as
described in Using IP and Qsys Simulation Setup Scripts (Custom Flow) on
page 112.
Custom flows
Altera supports specialized flows for various design variations, including the
following:
Specialized
flows
May 2013
Altera Corporation
For simulation of Altera example designs, refer to the documentation for the
example design or to the IP core user guide on the IP and Megafunctions
Documentation section of the Altera website.
For simulation of Qsys designs, refer to Creating a System with Qsys chapter
of the Quartus II Handbook.
For simulation of designs that include the Nios II embedded processor, refer
to AN 351: Simulating Nios II Embedded Processors Designs.
14
HDL Support
Table 14 describes Quartus II simulation support for hardware description
languages:
Table 14. HDL Support
Language
Description
For VHDL RTL simulation, compile design files directly in your simulator. To use Nativelink
automation, analyze and elaborate your design in the Quartus II software, and then use the Nativelink
simulator scripts to compile the design files in your simulator. You must also compile simulation
models from the Altera simulation libraries and simulation models for the IP cores in your design. Use
the Simulation Library Compiler or Nativelink to compile simulation models.
For gate-level simulation, the EDA Netlist Writer generates a synthesized design netlist VHDL Output
File (.vho). Compile the .vho in your simulator. You may also need to compile models from the Altera
simulation libraries.
IEEE 1364-2005 encrypted Verilog HDL simulation models are encrypted separately for each
Altera-supported simulation vendor. If you want to simulate the model in a VHDL design, you need
either a simulator that is capable of VHDL/Verilog HDL co-simulation, or any Mentor Graphics single
language VHDL simulator.
For RTL simulation in Verilog HDL or SystemVerilog, compile your design files in your simulator. To
use Nativelink automation, analyze and elaborate your design in the Quartus II software, and then use
the Nativelink simulator scripts to compile your design files in your simulator. You must also compile
simulation models from the Altera simulation libraries and simulation models for the IP cores in your
design. Use the Simulation Library Compiler or Nativelink to compile simulation models.
For gate-level simulation, the EDA Netlist Writer generates a synthesized design netlist Verilog Output
File (.vo), Compile the .vo in your simulator.
If your design is a mix of VHDL and Verilog/SystemVerilog files, you must use a mixed language
simulator. Since Altera supports both languages, choose the most convenient language for any Altera
IP in your design.
Mixed HDL
Altera provides Stratix V, Arria V, Cyclone V and newer simulation model libraries and IP simulation
models in Verilog HDL and IEEE encrypted Verilog. Your simulator's co-simulation capabilities
support VHDL simulation of these models using VHDL wrapper files. Altera provides the wrapper
for Verilog models to instantiate these models directly from your VHDL design.
Schematic
You must convert schematics to HDL format before simulation. You can use the converted VHDL or
Verilog HDL files for RTL simulation.
VHDL
Verilog HDL
SystemVerilog
15
<simulator_setup_scripts>
<simulation_model_files>
<EDA_tool_name>
<IEEE_encrypted_Verilog_simulation_models>
The Quartus II software optionally generates the following files for other EDA tools:
Figure 13. Quartus II Generated Files for Other EDA Tools
<Quartus II Project Directory>
simulation - EDA simulation files
<EDA_simulator>
<.vo, .vho, .sv for simulation>
symbols - EDA board-level symbol tool files
<EDA_board_symbol_tool_name>
<.fx or .xml for symbol generation and board-level verification>
board - EDA board-level signal integrity tool files
hspice or ibis
<.sp or .ibs for signal integrity analysis>
timing - EDA board-level timing analysis tool files
<EDA_board_timing_tool_name>
<STAMP model files, .data, .mod, and .lib>
board - EDA board-level boundary scan tool files
bsdl
< Boundary Scan Description Language File (.bsd)>
May 2013
Altera Corporation
16
Use the NativeLink feature to automatically compile your design, Altera IP,
simulation model libraries, and testbench, as described in Running RTL
Simulation (NativeLink Flow) on page 19.
Run the Simulation Library Compiler to compile all RTL and gate-level simulation
model libraries for your device, simulator, and design language, as described in
Using Simulation Library Compiler (Custom Flow) on page 110.
After you compile the simulation model libraries, you can reuse these libraries in
subsequent simulations to avoid having to compile them again.
h For a complete list of the Altera simulation models, refer to Altera Simulation Models in
Quartus II Help.
17
Description
File Name
Cadence
Simulator setup
script
cds.lib
ncsim_setup.sh
hdl.var
Mentor Graphics
msim_setup.tcl
Synopsys
synopsys_sim.setup
vcs_setup.sh
vcsmx_setup.sh
Aldec
rivierapro_setup.tcl
Quartus II Simulation
IP File (.sip)
<design name>.sip
IPFS models
IP Functional Simulation (IPFS) models are cycleaccurate VHDL or Verilog HDL models generated
by the Quartus II software for some Altera IP
cores. IPFS models support fast functional
simulation of IP using industry-standard VHDL
and Verilog HDL simulators. Refer to Generating
IP Functional Simulation Models for RTL
Simulation on page 17.
<design name>.vho
<design name>.vo
IEEE encrypted
models
<design name>.v
Turn on the Generate Simulation Model option when parameterizing the IP core
in the MegaWizard Plug-In Manager.
When you simulate your design, only compile the .vo or .vho for these IP cores in
your simulator, rather than the corresponding HDL file, which may be encrypted
to support only synthesis by the Quartus II software.
1
May 2013
Altera Corporation
Altera IP cores that do not require IPFS models for simulation lack the
Generate Simulation Model option in the IP core parameter editor.
18
Many recently released Altera IP cores support RTL simulation using IEEE
Verilog HDL encryption. IEEE encrypted models are significantly faster than IPFS
models and can be simulated in both Verilog HDL and VHDL designs.
f Generating an IPFS model for some AMPP megafunctions may require a license, refer
to AN 343: OpenCore Evaluation of AMPP Megafunctions.
Path
Mentor Graphics
ModelSim-Altera
Synopsys VCS/VCS MX
Aldec Active-HDL
Aldec Riviera-PRO
3. Click Assignments > Settings and specify options on the Simulation page and
More NativeLink Settings dialog box. Specify default options for simulation
library compilation, netlist and tool command script generation, and for launching
RTL or gate-level simulation automatically following Quartus II processing.
4. If your design includes a testbench, turn on Compile test bench and then click
Test Benches to specify options for each testbench. Alternatively, turn on Use
script to compile testbench and specify the script file.
5. If you want to use a script to setup simulation, turn on Use script to setup
simulation.
19
May 2013
Altera Corporation
110
Use these to compile libraries and generate simulation scripts for custom simulation
flows:
IP and Qsys simulation scriptsuse the scripts generated for Altera IP cores and
Qsys systems as templates to create simulation scripts. If your design includes
multiple IP cores or Qsys systems, you can combine the simulation scripts into a
single script, manually or by using the
ip-make-simscript utility, described in Generating Custom Simulation Scripts
with ip-make-simscript on page 112.
111
Simulation File
Mentor Graphics
ModelSim
QuestaSim
/simulation/modelsim/<design>.do
/simulation/modelsim/<design>.do
/simulation/modelsim/<revision name>_<rtl or
gate>.vcs
Synopsys VCS
/simulation/scsim/<revision
Synopsys VCS MX: name>_vcsmx_<rtl or gate>_<verilog or
vhdl>.tcl
Cadence Incisive
(NC SIM)
May 2013
Use
Altera Corporation
/simulation/ncsim/<revision
name>_ncsim_<rtl or gate>_<verilog or
vhdl>.tcl
112
113
The following are examples of options you can use with the utility:
Table 18.
Option
Description
Status
--spd=<file>
Required
Optional
--compile-to-work
Optional
--use-relativepaths
Optional
f Refer to Aldec Active-HDL and Riviera-PRO Support, Synopsys VCS and VCS MX
Support, Cadence Incisive Enterprise Simulator Support, and Mentor Graphics ModelSim
and QuestaSim Support for simulation script examples.
Version
May 2013
13.0.0
November 2012
12.1.0
Added new section Converting Block Design Files (.bdf) to HDL Format (.v/.vhd)
on page 14
June 2012
12.0.0
November 2011
11.1.0
May 2011
May 2013
11.0.0
Altera Corporation
Changes
114
Version
December 2010
July 2010
10.1.0
10.0.0
November 2009
9.1.0
Changes
Added new section Simulating Qsys and SOPC Builder System Designs.
Updated Running the EDA Simulation Library Compiler Through the GUI on
page 118
Initial release
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
This chapter provides specific guidelines for simulation of Quartus II designs with
Mentor Graphics ModelSim-Altera, ModelSim, or QuestaSim software. Altera
provides the entry-level ModelSim-Altera software, along with precompiled Altera
simulation libraries, to simplify simulation of Altera designs. You can also refer to the
following for more information about EDA simulation:
For overview information, Simulating Altera Designs in the Quartus II Handbook and
About Using EDA Simulators in Quartus II Help.
For detailed GUI steps, Preparing for EDA Simulation and Running EDA Simulators
in Quartus II Help.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Feedback Subscribe
22
In this chapter, ModelSim refers to ModelSim SE, PE, and DE, which share the same
commands as QuestaSim. ModelSim-Altera refers to ModelSim-Altera Starter
Edition and ModelSim-Altera Subscription Edition.
Encrypted Altera simulation model files shipped with the Quartus II software
version 10.1 and later can only be read by ModelSim-Altera Edition Software version
6.6c and later. These encrypted simulation model files are located at the <Quartus II
System directory>/quartus/eda/sim_lib/<mentor> directory.
23
The sequence of the parameters depends on the sequence of the GENERIC in the
VHDL component declaration.
In this mode, module boundaries are flattened and loops are optimized, which
eliminates levels of debugging hierarchy and may result in faster simulation. This
switch is not supported in the ModelSim-Altera simulator.
November 2012
Option
Description
+transport_path_delays
+transport_int_delays
Altera Corporation
24
f For more information about either of these options, refer to the ModelSim-Altera
Command Reference installed with the ModelSim and QuestaSim software.
The following ModelSim and QuestaSim software command shows the command
line syntax to perform a gate-level timing simulation with the device family library:
vsim -t 1ps -L stratixii -sdftyp /i1=filtref_vhd.sdo work.filtref_vhd_vec_tst \
+transport_int_delays +transport_path_delays
25
f For more information about using the timing <filename>.vcd for power estimation,
refer to the PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook.
2. After you convert the .vcd to a .wlf, follow the procedures for viewing a waveform
from a .wlf through ModelSim and QuestaSim.
You can also convert your .wlf to a .vcd by using the wlf2vcd command.
November 2012
Altera Corporation
26
In this example, the top-level simulation files are stored in the same directory as the
original IP core, so this variable is set to the IP-generated directory structure. The
QSYS_SIMDIR variable provides the relative hierarchy path for the generated IP
simulation files. The script calls the generated msim_setup.tcl script and uses the
alias commands from the script to compile and elaborate the IP files required for
simulation along with the top-level simulation testbench. You can specify additional
simulator elaboration command options when you run the elab command, for
example, elab +nowarnTFMPC. The last command run in the example starts the
simulation.
Unsupported Features
The Quartus II software does not support the following simulation features:
The USB software guard is not supported by versions earlier than Mentor
Graphics ModelSim software version 5.8d.
For ModelSim-Altera software versions prior to 5.5b, use the PCLS utility
included with the software to set up the license.
27
Version
Changes
November 2012
12.1.0
June 2012
12.0.0
November 2011
11.1.0
May 2011
11.0.0
December 2010
July 2010
November 2012
10.1.0
10.0.0
Altera Corporation
Changed section name from ModelSim and QuestaSim Error Message Verification
to ModelSim and QuestaSim Error Message Information on page 218
Added other links to Quartus II Help and ModelSim-Altera Help where appropriate
and removed redundant information
28
November 2009
Version
9.1.0
Changes
Removed NativeLink information and referenced new Simulating Designs with EDA
Tools chapter
March 2009
9.0.0
Compile Libraries Using the EDA Simulation Library Compiler on page 217
Table 21, Table 22, Table 25, Table 26, Table 27, Table 28, Table 29,
Table 210
November 2008
8.1.0
Removed steps to include the library when the simulation is run in VHDL mode from
all procedures; this is no longer necessary
Added information about the Altera Simulation Library Compiler throughout the
chapter
May 2008
8.0.0
This chapter provides specific guidelines for simulation of Quartus II designs with
the Synopsys VCS or VCS MX software. You can also refer to the following for more
information about EDA simulation:
For overview and version support information, Simulating Altera Designs in the
Quartus II Handbook and About Using EDA Simulators in Quartus II Help.
For detailed GUI steps, Preparing for EDA Simulation and Running EDA Simulators
in Quartus II Help.
The VCS User Guide installed with the VCS software, and the Synopsys VCS
Simulation Design Example page.
3. Modify the simlib_comp.vcs file to specify your design and testbench files.
4. Run the VCS simulator:
vcs -R -file simlib_comp.vcs
Add -verilog and +verilog2001ext+.v options to make sure all .v files are
compiled as verilog 2001 files, and all other files are compiled as systemverilog
files.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Feedback Subscribe
32
Add the -lca option for Stratix V and later families because they include IEEEencrypted simulation files for VCS and VCS MX.
Option
Description
+transport_path_delays
+transport_int_delays
33
Include the script within the testbench module block. If you include the
script outside of the testbench module block, syntax errors occur during
compilation.
6. Run the simulation with the VCS command. Exit the VCS software when the
simulation is finished and the <revision_name>.vcd file is generated in the
simulation directory.
f For detailed instructions about generating a .vcd file and running power analysis,
refer to the PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook.
November 2012
Altera Corporation
34
You can edit the .sh script to add simulator commands that compile the top-level
simulation HDL file.
Example 32. Example Top-Level Simulation Shell Script for VCS-MX
# Run generated script to compile libraries and IP simulation files
# Skip elaboration and simulation of the IP variation
sh ./ip_top_sim/synopsys/vcsmx/vcsmx_setup.sh SKIP_ELAB=1 SKIP_SIM=1
QSYS_SIMDIR="./ip_top_sim"
#Compile top-level testbench that instantiates IP
vlogan -sverilog ./top_testbench.sv
#Elaborate and simulate the top-level design
vcs lca t ps <elaboration control options> top_testbench
simv <simulation control options>
Version
Changes
November 2012
12.1.0
June 2012
12.0.0
November 2011
11.0.1
May 2011
11.0.0
December 2010
July 2010
November 2009
10.0.1
10.0.0
9.1.0
Template update.
Minor editorial updates.
Removed NativeLink information and referenced new Simulating Designs with EDA
Tools chapter in volume 3 of the Quartus II Handbook
Added RTL Functional Simulation for Stratix IV Devices and Gate-Level Timing
Simulation for Stratix IV Devices sections
35
Version
March 2009
9.0.0
November 2008
8.1.0
Changes
Major revision to Compiling Libraries Using the EDA Simulation Library Compiler on
page 42
Added new section Generating a Simulation Script from the EDA Netlist Writer on
page 316
Added new section Viewing a Waveform from a .vpd or .vcd File on page 413
Added Compile Libraries Using the EDA Simulation Library Compiler on page 33
For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
November 2012
Altera Corporation
36
This chapter provides specific guidelines for simulation of Quartus II designs with
the Cadence Incisive Enterprise (IES) software. You can also refer to the following for
more information about EDA simulation:
For overview and version support information, Simulating Altera Designs in the
Quartus II Handbook and About Using EDA Simulators in Quartus II Help.
For detailed GUI steps, Preparing for EDA Simulation and Running EDA Simulators
in Quartus II Help.
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Feedback Subscribe
42
Table 41 lists the ISE command-line programs supported for IES simulation.
Table 41. ISE Command-Line Programs
Program
ncvlog
ncvhdl
Function
ncvlog compiles your Verilog HDL code and performs syntax and static
semantics checks.
ncvhdl compiles your VHDL code and performs syntax and static semantics
checks.
ncelab
ncsdfc
ncsim
If you use NC-Sim for post-fit VHDL functional simulation of a Stratix V design that
includes RAM, an elaboration error might occur if the component declaration
parameters are not in the same order as the architecture parameters. Use the
-namemap_mixgen option with the ncelab command to match the component
declaration parameter and architecture parameter names.
43
2. Specify the compiled .sdf file for the project by adding the following command to
an ASCII SDF command file for the project:
COMPILED_SDF_FILE = "<project name>.sdf.X" SCOPE = <instance path>
After you compile the .sdf file, type the following command to elaborate the design:
ncelab worklib.<project name>:entity SDF_CMD_FILE <SDF Command File>r
May 2013
Description
-PULSE_R
-PULSE_INT_R
Altera Corporation
44
To perform a gate-level timing simulation with the device family library, type the
following IES software command:
ncelab worklib.<project name>:entity SDF_CMD_FILE <SDF Command File> \
-TIMESCALE 1ps/1ps -PULSE_R 0 -PULSE_INT_R 0r
You cannot view a waveform from a .vcd file in SimVision, and the .vcd file cannot be
converted to a .trn file.
45
Version
Changes
May 2013
13.0.0
November 2012
12.1.0
June 2012
12.0.0
November 2011
11.0.1
May 2011
11.0.0
December 2010
10.0.1
July 2010
10.0.0
November 2009
March 2009
November 2008
May 2008
May 2013
9.1.0
9.0.0
8.1.0
8.0.0.
Altera Corporation
Removed NativeLink information and referenced new Simulating Designs with EDA
Tools chapter in volume 3 of the Quartus II Handbook
Added RTL Functional Simulation for Stratix IV Devices and Gate-Level Timing
Simulation for Stratix IV Devices sections
Added Compile Libraries Using the EDA Simulation Library Compiler on page 45
Added Generate Simulation Script from EDA Netlist Writer on page 435
Added Compile Libraries Using the Altera Simulation Library Compiler on page 45.
Updated Generating a Timing Netlist with Different Timing Models on page 418.
46
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
This chapter provides specific guidelines for simulation of Quartus II designs with
the Aldec Active-HDL or Riviera-PRO software. You can also refer to the following for
more information about EDA simulation:
For overview and version support information, Simulating Altera Designs in the
Quartus II Handbook and About Using EDA Simulators in Quartus II Help.
For detailed GUI steps, Preparing for EDA Simulation and Running EDA Simulators
in Quartus II Help.
Use NativeLink to compile required design files, simulation models, and run
your simulator. Verify results in your simulator. Skip steps 3 through 6.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Feedback Subscribe
52
Option
Description
+transport_path_delays
+transport_int_delays
f For more information about either of these options, refer to the Active-HDL online
documentation installed with the Active-HDL software.
To perform a gate-level timing simulation with the device family library, type the
Active-HDL command shown in Example 51.
Example 51.
vsim -t 1ps -L stratixii -sdftyp /i1=filtref_vhd.sdo \
work.filtref_vhd_vec_tst +transport_int_delays +transport_path_delays
53
For VHDL designs, the back-annotating process is done by adding the sdftyp
option.
Example
vsim +access +r -t 1ps +transport_int_delays +transport_path_delays
-sdftyp <instance path to design>= <path to SDO file> -L adder -L work
-L lpm -L altera_mf work.adder_vhd_vec_tst
Version
November 2012
12.1.0
June 2012
12.0.0
November 2011
11.0.1
May 2011
11.0.0
December 2010
July 2010
November 2012
10.0.1
10.0.0
Altera Corporation
Changes
Template update.
Minor editorial updates.
54
November 2000
March 2009
Version
9.1.0
9.0.0
Changes
Updated Table 61
Removed Simulation Library tables and EDA Simulation Library Compiler sections and
referenced new Simulating Designs with EDA Tools chapter
Added RTL Functional Simulation for Stratix IV Devices and Gate-Level Timing
Simulation for Stratix IV Devices sections
Added Compile Libraries Using the EDA Simulation Library Compiler on page 510
Added Generate Simulation Script from EDA Netlist Writer on page 551
November 2008
May 2008
8.1.0
8.0.0
Compile Libraries Using the Altera Simulation Library Compiler on page 510
Initial release
For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Definition
nodes
Most basic timing netlist unit. Used to represent ports, pins, and registers.
cells
Look-up tables (LUT), registers, digital signal processing (DSP) blocks, memory blocks, input/output elements, and so on. (1)
pins
nets
ports
clocks
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Feedback Subscribe
62
data1
and_inst
reg3
reg2
data2
clk
Figure 62 shows the timing netlist for the sample design in Figure 61, including
how different design elements are divided into cells, pins, nets, and ports.
Figure 62. The TimeQuest Analyzer Timing Netlist
Cells
Cell
Pin
data1
combout
datain
reg1
regout
clk
Cell
and_inst
Port
datac
data2
combout
Net
Pin
reg2
reg3
data_out
datain
datad
regout
Net
Net
Port
clk
clk~clkctrl
inclk0
outclk
Timing Paths
Timing paths connect two design nodes, such as the output of a register to the input of
another register. Understanding the types of timing paths is important to timing
closure and optimization. The TimeQuest analyzer uses the following commonly
analyzed paths:
63
Clock Path
Data Path
clk
CLRN
CLRN
June 2012
Altera Corporation
64
Equation 61 shows the basic calculations for data arrival and data required times
including the launch and latch edges.
Equation 61. Data Arrival and Data Required Time Equations
Data Arrival Time = Launch Edge + Source Clock Delay + t CO + Register-to-Register Delay
Data Required Time = Latch Edge + Destination Clock Delay t SU
10ns
20ns
Launch Clock
Hold relationship
Setup relationship
Latch Clock
If you do not constrain the clocks in your design, the Quartus II software analyzes in
terms of a 1 GHz clock to maximize timing based Fitter effort. To ensure realistic slack
values, you must constrain all clocks in your design with real values.
65
Setup B
Destination Clock
0 ns
8 ns
16 ns
24 ns
32 ns
The TimeQuest analyzer reports the result of clock setup checks as slack values. Slack
is the margin by which a timing requirement is met or not met. Positive slack indicates
the margin by which a requirement is met; negative slack indicates the margin by
which a requirement is not met. Equation 62 shows the TimeQuest analyzer clock
setup slack time calculation for internal register-to-register paths.
Equation 62. Clock Setup Slack for Internal Register-to-Register paths
Clock Setup Slack = Data Required Time Data Arrival Time
Data Arrival Time = Launch Edge + Clock Network Delay to Source Register +
t CO + Register-to-Register Delay
Data Required Time = Latch Edge + Clock Network Delay to Destination Register
t SU Setup Uncertainty
The TimeQuest analyzer performs setup checks using the maximum delay when
calculating data arrival time, and minimum delay when calculating data required
time.
Equation 63 shows the TimeQuest analyzer clock setup slack time calculation if the
data path is from an input port to an internal register.
Equation 63. Clock Setup Slack from Input Port to Internal Register
Clock Setup Slack = Data Required Time Data Arrival Time
Data Arrival Time = Launch Edge + Clock Network Delay +
Input Maximum Delay + Port-to-Register Delay
Data Required Time = Latch Edge + Clock Network Delay to Destination Register
t SU Setup Uncertainty
June 2012
Altera Corporation
66
Equation 64 shows the TimeQuest analyzer clock setup slack time calculation if the
data path is an internal register to an output port.
Equation 64. Clock Setup Slack from Internal Register to Output Port
Clock Setup Slack = Data Required Time Data Arrival Time
Data Required Time = Latch Edge + Clock Network Delay to Output Port
Output Maximum Delay
Data Arrival Time = Launch Edge + Clock Network Delay to Source Register +
t CO + Register-to-Port Delay
Source Clock
Hold
Check A1
Setup A
Hold Setup B
Hold
Check B1
Check A2
Hold
Check B2
Destination Clock
0 ns
8 ns
16 ns
24 ns
32 ns
Equation 65 shows the TimeQuest analyzer clock hold slack time calculation.
Equation 65. Clock Hold Slack for Internal Register-to-Register Paths
Clock Hold Slack = Data Arrival Time Data Required Time
Data Arrival Time = Launch Edge + Clock Network Delay to Source Register +
t CO + Register-to-Register Delay
Data Required Time = Latch Edge + Clock Network Delay to Destination Register +
t H + Hold Uncertainty
67
The TimeQuest analyzer performs hold checks using the minimum delay when
calculating data arrival time, and maximum delay when calculating data required
time.
Equation 66 shows the TimeQuest analyzer hold slack time calculation if the data
path is from an input port to an internal register.
Equation 66. Clock Hold Slack from Input Port to Internal Register
Clock Hold Slack = Data Arrival Time Data Required Time
Data Arrival Time = Launch Edge + Clock Network Delay +
Input Minimum Delay + Pin-to-Register Delay
Data Required Time = Latch Edge + Clock Network Delay to Destination Register + t H
Equation 67 shows the TimeQuest analyzer hold slack time calculation if the data
path is from an internal register to an output port.
Equation 67. Clock Hold Slack from Internal Register to Output Port
Clock Hold Slack = Data Arrival Time Data Required Time
Data Arrival Time = Latch Edge + Clock Network Delay to Source Register +
t CO + Register-to-Pin Delay
Data Required Time = Latch Edge + Clock Network Delay Output Minimum Delay
Equation 69 shows the TimeQuest analyzer recovery slack time calculation if the
asynchronous control signal is not registered.
Equation 69. Recovery Slack if Asynchronous Control Signal not Registered
Recovery Slack Time = Data Required Time Data Arrival Time
Data Required Time = Latch Edge + Clock Network Delay to Destination Register t SU
Data Arrival Time = Launch Edge + Clock Network Delay + Input Maximum Delay +
Port-to-Register Delay
June 2012
Altera Corporation
68
If the asynchronous reset signal is from a device I/O port, you must must create an
input delay constraint for the asynchronous reset port for the TimeQuest analyzer to
perform recovery analysis on the path.
Removal time is the minimum length of time the deassertion of an asynchronous
control signal must be stable after the active clock edge. The TimeQuest analyzer
removal slack calculation is similar to the clock hold slack calculation, but it applies
asynchronous control signals. Equation 610 shows the TimeQuest analyzer removal
slack time calculation if the asynchronous control signal is registered.
Equation 610. Removal Slack if Asynchronous Control Signal Registered
Removal Slack Time = Data Arrival Time Data Required Time
Data Arrival Time = Launch Edge + Clock Network Delay to Source Register +
t CO of Source Register + Register-to-Register Delay
Data Required Time = Latch Edge + Clock Network Delay to Destination Register + t H
Equation 611 shows the TimeQuest analyzer removal slack time calculation if the
asynchronous control signal is not registered.
Equation 611. Removal Slack if Asynchronous Control Signal not Registered
Removal Slack Time = Data Arrival Time Data Required Time
Data Arrival Time = Launch Edge + Clock Network Delay + Input Minimum Delay of Pin +
Minimum Pin-to-Register Delay
Data Required Time = Latch Edge + Clock Network Delay to Destination Register + t H
If the asynchronous reset signal is from a device pin, you must assign the Input
Minimum Delay timing assignment to the asynchronous reset pin for the TimeQuest
analyzer to perform removal analysis on the path.
69
Multicycle Paths
Multicycle paths are data paths that require a non-default setup and/or hold
relationship for proper analysis. For example, a register may be required to capture
data on every second or third rising clock edge. Figure 68 shows an example of a
multicycle path between the input registers of a multiplier and an output register
where the destination latches data on every other clock edge.
Figure 68. Multicycle Path
ENA
ENA
ENA
2 Cycles
Figure 69 shows a register-to-register path used for the default setup and hold
relationship, the respective timing diagrams for the source and destination clocks, and
the default setup and hold relationships, when the source clock, src_clk, has a period
of 10 ns and the destination clock, dst_clk, has a period of 5 ns. The default setup
relationship is 5 ns; the default hold relationship is 0 ns.
Figure 69. Register-to-Register Path and Default Setup and Hold Timing Diagram
reg
data_in
reg
Q
data_out
src_clk
dst_clk
setup
hold
10
20
30
To accommodate the system requirements you can modify the default setup and hold
relationships with a multicycle timing exception.
June 2012
Altera Corporation
610
Figure 610 shows the actual setup relationship after you apply a multicycle timing
exception. The exception has a multicycle setup assignment of two to use the second
occurring latch edge; in this example, to 10 ns from the default value of 5 ns.
Figure 610. Modified Setup Diagram
new setup
default setup
10
20
30
f For more information about creating exceptions with multicycle paths, refer to The
Quartus II TimeQuest Timing Analyzer chapter of the Quartus II Handbook.
Metastability
Metastability problems can occur when a signal is transferred between circuitry in
unrelated or asynchronous clock domains because the designer cannot guarantee that
the signal will meet setup and hold time requirements. To minimize the failures due to
metastability, circuit designers typically use a sequence of registers, also known as a
synchronization register chain, or synchronizer, in the destination clock domain to
resynchronize the data signals to the new clock domain.
The mean time between failures (MTBF) is an estimate of the average time between
instances of failure due to metastability.
The TimeQuest analyzer analyzes the potential for metastability in your design and
can calculate the MTBF for synchronization register chains. The MTBF of the entire
design is then estimated based on the synchronization chains it contains.
In addition to reporting synchronization register chains found in the design, the
Quartus II software also protects these registers from optimizations that might
negatively impact MTBF, such as register duplication and logic retiming. The
Quartus II software can also optimize the MTBF of your design if the MTBF is too low.
f For more information about metastability, its effects in FPGAs, and how MTBF is
calculated, refer to the Understanding Metastability in FPGAs white paper. For more
information about metastability analysis, reporting, and optimization features in the
Quartus II software, refer to the Managing Metastability with the Quartus II Software
chapter in volume 1 of the Quartus II Handbook.
611
Minimum and maximum delay variation can occur when two different delay values
are used for the same clock path. For example, in a simple setup analysis, the
maximum clock path delay to the source register is used to determine the data arrival
time. The minimum clock path delay to the destination register is used to determine
the data required time. However, if the clock path to the source register and to the
destination register share a common clock path, both the maximum delay and the
minimum delay are used to model the common clock path during timing analysis.
The use of both the minimum delay and maximum delay results in an overly
pessimistic analysis since two different delay values, the maximum and minimum
delays, cannot be used to model the same clock path.
Figure 611 shows a typical register-to-register path with the maximum and
minimum delay values shown.
Figure 611. Common Clock Path
B
2.2 ns
2.0 ns
reg1
A
clk
3.2 ns
3.0 ns
5.5 ns
5.0 ns
C
2.2 ns
2.0 ns
reg2
Segment A is the common clock path between reg1 and reg2. The minimum delay is
5.0 ns; the maximum delay is 5.5 ns. The difference between the maximum and
minimum delay value equals the common clock path pessimism removal value; in
this case, the common clock path pessimism is 0.5 ns. The TimeQuest analyzer adds
the common clock path pessimism removal value to the appropriate slack equation to
determine overall slack. Therefore, if the setup slack for the register-to-register path in
Figure 611 equals 0.7 ns without common clock path pessimism removal, the slack
would be 1.2 ns with common clock path pessimism removal.
You can also use common clock path pessimism removal to determine the minimum
pulse width of a register. A clock signal must meet a registers minimum pulse width
requirement to be recognized by the register. A minimum high time defines the
minimum pulse width for a positive-edge triggered register. A minimum low time
defines the minimum pulse width for a negative-edge triggered register.
June 2012
Altera Corporation
612
Clock pulses that violate the minimum pulse width of a register prevent data from
being latched at the data pin of the register. To calculate the slack of the minimum
pulse width, the TimeQuest analyzer subtracts the required minimum pulse width
time from the actual minimum pulse width time. The TimeQuest analyzer determines
the actual minimum pulse width time by the clock requirement you specified for the
clock that feeds the clock port of the register. The TimeQuest analyzer determines the
required minimum pulse width time by the maximum rise, minimum rise, maximum
fall, and minimum fall times. Figure 612 shows a diagram of the required minimum
pulse width time for both the high pulse and low pulse.
Figure 612. Required Minimum Pulse Width
Minimum and
Maximum Rise
Rise Arrival Times
Minimum and
Maximum
Fall Arrival Times
High Pulse
Width
0.8
Low Pulse
Width
0.5
0.9
0.7
0.8
0.5
With common clock path pessimism, the minimum pulse width slack can be increased
by the smallest value of either the maximum rise time minus the minimum rise time,
or the maximum fall time minus the minimum fall time. For Figure 612, the slack
value can be increased by 0.2 ns, which is the smallest value between 0.3 ns (0.8
ns 0.5 ns) and 0.2 ns (0.9 ns 0.7 ns).
h For more information, refer to TimeQuest Timing Analyzer Page (Settings Dialog Box) in
Quartus II Help.
Clock-As-Data Analysis
The majority of FPGA designs contain simple connections between any two nodes
known as either a data path or a clock path. A data path is a connection between the
output of a synchronous element to the input of another synchronous element. A
clock is a connection to the clock pin of a synchronous element. However, for more
complex FPGA designs, such as designs that use source-synchronous interfaces, this
simplified view is no longer sufficient. Clock-as-data analysis is performed in circuits
with elements such as clock dividers and DDR source-synchronous outputs.
613
The connection between the input clock port and output clock port can be treated
either as a clock path or a data path. Figure 613 shows a design where the path from
port clk_in to port clk_out is both a clock and a data path. The clock path is from the
port clk_in to the register reg_data clock pin. The data path is from port clk_in to
the port clk_out.
Figure 613. Simplified Source Synchronous Output
D
reg_data
clk_in
clk_out
D
D
Launch Clock (2 T)
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614
Multicorner Analysis
The TimeQuest analyzer performs multicorner timing analysis to verify your design
under a variety of operating conditionssuch as voltage, process, and temperature
while performing static timing analysis.
To change the operating conditions or speed grade of the device used for timing
analysis, use the set_operating_conditions command.
h For more information about the set_operating_conditions and
get_available_operating_conditions commandsincluding full syntax
information, options, and example usagerefer to set_operating_conditions and
get_available_operating_conditions in Quartus II Help.
If you specify an operating condition Tcl object, the -model, speed, -temperature, and
-voltage options are optional. If you do not specify an operating condition Tcl object,
the -model option is required; the -speed, -temperature, and -voltage options are
optional.
1
To obtain a list of available operating conditions for the target device, use the
get_available_operating_conditions -all command.
To ensure that no violations occur under various conditions during the device
operation, perform static timing analysis under all available operating conditions.
Table 62 shows the operating conditions for the slow and fast timing models for
device families that support only slow and fast operating conditions.
Speed Grade
Voltage
Temperature
Slow
(1)
Fast
(1)
Maximum TJ
(1)
Minimum TJ
(1)
Example 61 shows how to set the operating conditions in Example 62 with a Tcl
object.
Example 61. Setting Operating Conditions with a Tcl Object
set_operating_conditions 3_slow_1100mv_85c
Example 62 shows how to set the operating conditions for a Stratix III design to the
slow timing model, with a voltage of 1100 mV, and temperature of 85 C.
Example 62. Setting Operating Conditions with Individual Values
set_operating_conditions -model slow -temperature 85 -voltage 1100
615
Version
Changes
June 2012
12.0.0
November 2011
11.1.0
Initial release.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
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616
f For more information about basic timing analysis concepts and how they pertain to
the TimeQuest analyzer, refer to the Timing Analysis Overview chapter in volume 3 of
the Quartus II Handbook.
f For more information about Altera resources available for the TimeQuest analyzer,
refer to the TimeQuest Timing Analyzer Resource Center of the Altera website.
f For more information about the TimeQuest analyzer, refer to the Altera Training page
of the Altera website.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its ISO
9001:2008
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
Registered
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
Feedback Subscribe
72
To run the TimeQuest analyzer in command-line mode for easy integration with
scripted design flows, type the following command at a system command prompt:
quartus_sta -sr
Description
-h | --help
-t <script file> |
--script=<script file>
-s | --shell
--do_report_timing
report_timing -hold -npaths 1 -to_clock $clock
report_timing -recovery -npaths 1 -to_clock $clock
report_timing -removal -npaths 1 -to_clock $clock
--force_dat
--lower_priority
--post_map
--sdc=<SDC file>
--report_script=<script>
--speed=<value>
--tq2hc
--tq2pt
-f <argument file>
73
Description
-c <revision name> |
--rev=<revision_name>
--multicorner
Specifies that all slack summary reports be generated for both slow- and
fast-corners.
--multicorner[=on|off]
--voltage=<value_in_mV>
--temperature=
<value_in_C>
Specifies the device temperature in degrees Celsius, used for timing analysis.
--parallel
[=<num_processors>]
--64bit
For more information about steps to perform before opening the TimeQuest analyzer,
refer to Recommended Flow on page 73.
For more information about using Tcl commands to constrain and analyze your
design, refer to Constraining and Analyzing with Tcl Commands on page 77.
Recommended Flow
The Quartus II TimeQuest analyzer performs constraint validation to timing
verification as part of the compilation flow. Figure 71 shows the recommended
design flow to maximize the benefits of the TimeQuest Analyzer.
Figure 71. Design Flow with the TimeQuest Timing Analyzer
Create Quartus II Project
and Specify Design Files
Perform Compilation
Verify Timing
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74
If you are using incremental compilation, you must merge your design partitions after
performing Analysis and Synthesis to create a post-map database.
h For more information, refer to Setting up and Running Analysis and Synthesis and
Setting up and Running a Compilation in Quartus II Help.
The Quartus II software assigns a default frequency of 1 GHz for clocks that have not
been constrained, either in the TimeQuest GUI or an .sdc file, unless any constraint
exists in the design. In that case, all unconstrained clocks remain unconstrained.
The constraints in the .sdc are read in sequence. You must first make a constraint
before making any references to that constraint. For example, if a generated clock
references a base clock, the base clock constraint must be made before the generated
clock constraint.
75
The Quartus II Text Editor provides templates for SDC constraints. For more
information, refer to Using the Quartus II Templates on page 76.
Verifying Timing
The TimeQuest analyzer examines the timing paths in the design, calculates the
propagation delay along each path, checks for timing constraint violations, and
reports timing results as positive slack or negative slack. Negative slack indicates a
timing violation. If you encounter violations along timing paths, use the timing
reports to analyze your design and determine how best to optimize your design. If
you modify, remove, or add constraints, you should perform a full compilation again.
This iterative process helps resolve timing violations in your design.
h For more information, refer to Viewing Timing Analysis Results in Quartus II Help.
Figure 72 shows the recommended flow for constraining and analyzing your design
within the TimeQuest analyzer. Included are the corresponding Tcl commands for
each step.
Figure 72. The TimeQuest Timing Analyzer Flow
Open Project
project_open
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76
Yes
No
Yes
No
Analyze the design
If you type the read_sdc command at the command line without any arguments, the
TimeQuest analyzer reads constraints embedded in HDL files, then follows the .sdc
file precedence order shown in Figure 73.
77
::quartus::sta
::quartus::sdc
::quartus::sdc_ext
h For more information about TimeQuest analyzer Tcl commands and a complete list of
commands, refer to ::quartus::sta in Quartus II Help. For more information about
standard SDC commands and a complete list of commands, refer to ::quartus::sdc in
Quartus II Help. For more information about Altera extensions of SDC commands
and a complete list of commands, refer to ::quartus::sdc_ext in Quartus II Help.
Collection Commands
The TimeQuest analyzer Tcl commands often return port, pin, cell, or node names in a
data set called a collection. In your Tcl scripts you can iterate over the values in
collections to analyze or modify constraints in your design.
The TimeQuest analyzer supports collection commands that provide easy access to
ports, pins, cells, or nodes in the design. Use collection commands with any valid
constraints or Tcl commands specified in the TimeQuest analyzer.
Table 72 describes the collection commands supported by the TimeQuest analyzer.
Table 72. SDC Collection Commands (Part 1 of 2)
Command
all_clocks
all_inputs
all_outputs
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78
all_registers
get_cells
Cells in the design. All cell names in the collection match the specified pattern. Wildcards can be
used to select multiple cells at the same time.
get_clocks
Clocks in the design. When used as an argument to another command, such as the -from or -to
of set_multicycle_path, each node in the clock represents all nodes clocked by the clocks in
the collection. The default uses the specific node (even if it is a clock) as the target of a command.
get_nets
Nets in the design. All net names in the collection match the specified pattern. You can use
wildcards to select multiple nets at the same time.
get_pins
Pins in the design. All pin names in the collection match the specified pattern. You can use
wildcards to select multiple pins at the same time.
get_ports
Wildcard Characters
To apply constraints to many nodes in a design, use the * and ? wildcard
characters. The * wildcard character matches any string; the ? wildcard character
matches any single character.
If you make an assignment to node reg*, the TimeQuest analyzer searches for and
applies the assignment to all design nodes that match the prefix reg with any number
of following characters, such as reg, reg1, reg[2], regbank, and reg12bank.
If you make an assignment to a node specified as reg?, the TimeQuest analyzer
searches and applies the assignment to all design nodes that match the prefix reg and
any single character following; for example, reg1, rega, and reg4.
The add_to_collection command creates a new collection that is the union of the two
specified collections.
79
In the Quartus II software, keepers are I/O ports or registers. An .sdc that includes
get_keepers can only be processed as part of the TimeQuest analyzer flow and is not
compatible with third-party timing analysis flows.
You can also examine collections and experiment with collections using wildcards in
the TimeQuest analyzer by clicking Name Finder from the View menu.
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foo
710
foo|dataa
foo|datab
foo|bar
foo|bar|datac
foo|bar|datad
Search Result
get_pins *|dataa
foo|dataa
get_pins *|datac
<empty> (1)
get_pins *|*|datac
foo|bar|datac
get_pins foo*|*
foo|dataa, foo|datab
<empty>
foo|dataa, foo|datab
foo|bar|datac
<empty>
foo|bar|datac
foo|bar|datac
(1)
(1)
The default method separates hierarchy levels of instances from nodes and pins with
the pipe character (|). A match occurs when the levels of hierarchy match, and the
string values including wildcards match the instance and/or pin names. For example,
the command get_pins <instance_name>|*|datac returns all the datac pins for
registers in a given instance. However, the command get_pins *|datac returns and
empty collection because the levels of hierarchy do not match.
Use the -hierarchical matching scheme to return a collection of cells or pins in all
hierarchies of your design.
For example, the command get_pins -hierarchical *|datac returns all the datac
pins for all registers in your design. However, the command get_pins -hierarchical
*|*|datac returns an empty collection because more than one pipe character (|) is not
supported.
The -compatibility_mode option returns collections matching wildcard strings
through any number of hierarchy levels. For example, an asterisk can match a pipe
character when using -compatibility_mode.
711
Examples of different executable names are quartus_map for Analysis & Synthesis,
quartus_fit for Fitter, and quartus_sta for the TimeQuest analyzer.
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712
inst
lpm_add_sub0
myfifo
inst2
dataout
inst1
data2
clk1
clk2
altpll0
713
Example 77 shows an .sdc file containing basic constraints for the circuit in
Figure 74.
Example 77. Example Basic SDC Constraints
# Create clock constraints
create_clock -name clockone -period 10.000 [get_ports {clk1}]
create_clock -name clocktwo -period 10.000 [get_ports {clk2}]
# Create virtual clocks for input and output delay constraints
create clock -name clockone_ext -period 10.000
create clock -name clockone_ext -period 10.000
derive_pll_clocks
# derive clock uncertainty
derive_clock_uncertainty
# Specify that clockone and clocktwo are unrelated by assinging
# them to seperate asynchronus groups
set_clock_groups \
-asynchronous \
-group {clockone} \
-group {clocktwo \
altpll0|altpll_component|auto_generated|pll1|clk[0]}]
# set input and output delays
set_input_delay -clock { clockone_ext } -max 4 [get_ports {data1}]
set_input_delay -clock { clockone_ext } -min -1 [get_ports {data1}]
set_input_delay -clock { clockone_ext } -max 4 [get_ports {data2}]
set_input_delay -clock { clockone_ext } -min -1 [get_ports {data2}]
set_output_delay -clock { clocktwo_ext } -max 6 [get_ports {dataout}]
set_output_delay -clock { clocktwo_ext } -min -3 [get_ports {dataout}]
The .sdc in Example 77 contains the following basic constraints you should include
for most designs:
Specification of two clock groups, the first containing clockone and its related
clocks, the second containing clocktwo and its related clocks, and the third group
containing the output of the PLL. This specification overrides the default analysis
of all clocks in the design as related to each other. For more information about
asynchronous clock groups, refer to Asynchronous Clock Groups on page 722.
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714
Base clocks
Virtual clocks
Multifrequency clocks
Generated clocks
Clocks are used to specify requirements for synchronous transfers and guide the Fitter
optimization algorithms to achieve the best possible placement for your design.
Specify clock constraints first in the .sdc because other constraints may reference
previously defined clocks. The TimeQuest analyzer reads SDC constraints and
exceptions from top to bottom in the file.
Use the create_clock command to constrain all primary input clocks. The target for
the create_clock command is usually a pin. To specify the pin as the target, use the
get_ports command. Example 79 shows how to specify a 100 MHz requirement on a
clk_sys input clock port.
Example 79. create_clock Command
create_clock -period 10 -name clk_sys [get_ports clk_sys]
You can apply multiple clocks on the same clock node with the -add option.
Example 710 shows how to specify that two oscillators drive the same clock port on
the device.
Example 710. Two Oscillators Driving the Same Clock Port
create_clock -period 10 -name clk_100 [get_ports clk_sys]
create_clock -period 5 -name clk_200 [get_ports clk_sys] -add
715
External Device
datain
reg_a
reg_b
dataout
system_clk
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virt_clk
716
Example 712 shows how to create a 10 ns virtual clock named virt_clk with a 50%
duty cycle where the first rising edge occurs at 0 ns. The virtual clock is then used as
the clock source for an output delay constraint.
Example 712. Virtual Clock Example
#create base clock for the design
create_clock -period 5 [get_ports system_clk]
#create the virtual clock for the external register
create_clock -period 10 -name virt_clk
#set the output delay referencing the virtual clock
set_output_delay -clock virt_clk -max 1.5 [get_ports dataout]
set_output_delay -clock virt_clk -min 0.0 [get_ports dataout]
Altera FPGA
data_in
reg1
reg1
clk_in
100 MHz
717
Example 713 shows the SDC commands to constrain the I/O interface shown in
Figure 76.
Example 713. SDC Commands to Constrain the I/O Interface
# Create the base clock for the clock port
create_clock -period 10 -name clk_in [get_ports clk_in]
# Create a virtual clock with the same properties of the base clock
# driving the source register
create_clock -period 10 -name virt_clk_in
# Create the input delay referencing the virtual clock and not the base
# clock
# DO NOT use set_input_delay -clock clk_in <delay value>
# [get_ports data_in]
set_input_delay -clock virt_clk_in <delay value> [get_ports data_in]
f For more information about clock uncertainty and clock transfers, refer to Clock
Uncertainty on page 723
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718
A common form of generated clock is a clock divider. Example 715 creates a base
clock, clk_sys, then defines a generated clock clk_div_2, which is the clock frequency
of clk_sys divided by two.
Example 715. Clock Divider
create_clock -period 10 -name clk_sys [get_ports clk_sys]
create_generated_clock -name clk_div_2 -divide_by 2 -source
[get_ports clk_sys] [get_pins reg|regout]
Edges 1
clk_sys
clk_div_2
Time
10
20
30
When you use the create_generated_clock command, the -source option specifies a
node with a clock used as a reference for your generated clock. Best practice is to
specify the input clock pin of the target node for your new generated clock. You can
also specify the target node of the reference clock. In Example 715, the -source
option specifies the clock port clk feeding the clock pin of register reg.
If you have multiple base clocks feeding a node that is the source for a generated
clock, you must define multiple generated clocks. Each generated clock is associated
to one base clock using the -master_clock option in each generated clock statement.
The TimeQuest analyzer provides the derive_pll_clocks command to automatically
generate clocks for all PLL clock outputs. The properties of the generated clocks on
the PLL outputs match the properties defined for the PLL. For more information
about deriving PLL clock outputs, refer to Deriving PLL Clocks on page 719.
h For more information about the create_generated_clock and derive_pll_clocks
commandsincluding for full syntax information, options, and example usagerefer
to create_generate_clock and derive_pll_clocks in Quartus II Help.
719
The inverse of a clock divider is a clock multiplier. Figure 77 shows the effect of
applying a multiplication factor to the generated clock.
Figure 77. Multiplying a Generated Clock
create_clock -period 10 -waveform { 0 5 } [get_ports clk]
# Creates a multiply-by-two clock
create_generated_clock -source [get_ports clk] -multiply_by 2 [get_registers \
clkmult|clkreg]
clk
clkmult|clkreg
Time
10
20
30
An uncommon but useful type of generated clock is one with shifted edges.
Figure 78 shows how to modify the generated clock by defining and shifting the
edges.
Figure 78. Edge Shifting a Generated Clock
create_clock -period 10 -waveform { 0 5 } [get_ports clk]
# Creates a divide-by-two clock
create_generated_clock -source [get_ports clk] -edges { 1 3 5 } [get_registers \
clkdivA|clkreg]
# Creates a divide-by-two clock independent of the master clocks duty cycle (now 50%)
create_generated_clock -source [get_ports clk] -edges { 1 1 5 } \
-edge_shift { 0 2.5 0 } [get_registers clkdivB|clkreg]
Edges 1
clk
clkdivA|clkreg
clkdivB|clkreg
Time
10
20
30
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720
Example 716 shows the command to create a base clock for the PLL input clock port
and call derive_pll_clocks to create PLL output clocks.
Example 716. Create Base Clock for PLL input Clock Ports
create_clock -period 10.0 -name fpga_sys_clk [get_ports fpga_sys_clk]
derive_pll_clocks
reg_2
pll_inst
Example 717 shows the messages generated by the TimeQuest analyzer when you
use the derive_pll_clocks command to automatically constrain the PLL for the
design shown in Figure 79.
Example 717. derive_pll_clocks Command Messages
Info:
Info: Deriving PLL Clocks:
Info: create_generated_clock -source
pll_inst|altpll_component|pll|inclk[0] -divide_by 2 -name
pll_inst|altpll_component|pll|clk[0]
pll_inst|altpll_component|pll|clk[0]
Info:
721
If the PLL is in clock switchover mode, multiple clocks are created for the output clock
of the PLL; one for the primary input clock (for example, inclk[0]), and one for the
secondary input clock (for example, inclk[1]). You should create exclusive clock
groups for the primary and secondary output clocks.
For more information about creating exclusive clock groups, refer to Creating Clock
Groups on page 722.
Do not use the derive_clocks command for final timing sign-off; instead, you should
create clocks for all clock sources with the create_clock and
create_generated_clock commands. If your design has more than a single clock, the
derive_clocks command constrains all the clocks to the same specified frequency. To
achieve a thorough and realistic analysis of your designs timing requirements, you
should make individual clock constraints for all clocks in your design.
You can also use the command derive_pll_clocks -create_base_clocks to create
the input clocks for all PLL inputs automatically.
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722
A group is defined with the -group option. The TimeQuest analyzer excludes the
timing paths between clocks for each of the separate groups.
If you apply multiple clocks to the same port, use the set_clock_groups command
with the -exclusive option to place the clocks into separate groups and declare that
the clocks are mutually exclusive. The clocks cannot physically exist in your design at
the same time.
723
Example 720 shows how to create a clock group containing clocks clk_A and clk_B
and a second unrelated clock group containing clk_C.
Example 720. Create Asynchronous Clock Groups
set_clock_groups -asynchronous -group {clk_A clk_B} -group {clk_C}
Clock Latency
There are two forms of clock latency, clock source latency and clock network latency.
Source latency is the propagation delay from the origin of the clock to the clock
definition point (for example, a clock port). Network latency is the propagation delay
from a clock definition point to a registers clock pin. The total latency at a registers
clock pin is the sum of the source and network latencies in the clock path.
To specify source latency to any clock ports in your design, use the
set_clock_latency command.
1
Clock Uncertainty
The TimeQuest analyzer accounts for uncertainty clock effects for three types of
clock-to-clock transfers; intraclock transfers, interclock transfers, and I/O interface
clock transfers.
June 2012
Intraclock transfers occur when the register-to-register transfer takes place in the
core of the device and the source and destination clocks come from the same PLL
output pin or clock port.
I/O interface clock transfers occur when data transfers from an I/O port to the
core of the device or from the core of the device to the I/O port.
Altera Corporation
724
To manually specify clock uncertainty, or skew, for clock-to-clock transfers, use the
set_clock_uncertainty command. You can specify the uncertainty separately for
setup and hold, and you can specify separate rising and falling clock transitions. The
TimeQuest analyzer subtracts setup uncertainty from the data required time for each
applicable path and adds the hold uncertainty to the data required time for each
applicable path.
To automatically apply interclock, intraclock, and I/O interface uncertainties, use the
derive_clock_uncertainty command. The TimeQuest analyzer automatically
applies clock uncertainties to clock-to-clock transfers in the design, and calculates
both setup and hold uncertainties for each clock-to-clock transfer.
Any clock uncertainty constraints applied to source and destination clock pairs with
the set_clock_uncertainty command have a higher precedence than the clock
uncertainties derived with the derive_clock_uncertainty command for the same
source and destination clock pairs. For example, if you use the
set_clock_uncertainty command to set clock uncertainty between clka and clkb,
the TimeQuest analyzer ignores the values for the clock transfer calculated with the
derive_clock_uncertainty command. The TimeQuest analyzer reports the values
calculated with the derive_clock_uncertainty command even if they are not used.
Use set_clock_uncertainty or derive_clock_uncertainty with the -overwrite
option to overwrite previously applied clock uncertainty assignments. Use
set_clock_uncertainty or derive_clock_uncertainty with the -add option to apply
additional clock uncertainty to previously applied clock uncertainty. Use the
remove_clock_uncertainty command to remove previous clock uncertainty
assignments.
h For more information about the set_clock_uncertainty, derive_clock_uncertainty,
and remove_clock_uncertainty commandsincluding full syntax information,
options, and example usagerefer to set_clock_uncertainty, remove_clock_uncertainty
and derive_clock_uncertainty, in Quartus II Help.
Input Constraints
Input constraints allow you to specify all the external delays feeding into the device.
Specify input requirements for all input ports in your design.
725
You can use the set_input_delay command to specify external input delay
requirements. Use the -clock option to reference a virtual clock. Using a virtual clock
allows the TimeQuest analyzer to correctly derive clock uncertainties for interclock
and intraclock transfers. The virtual clock defines the launching clock for the input
port. The TimeQuest analyzer automatically determines the latching clock inside the
device that captures the input data, because all clocks in the device are defined.
Figure 710 shows an example of an input delay referencing a virtual clock.
Figure 710. Input Delay
Altera Device
External Device
dd
tco_ext
Oscillator
cd_ext
cd_altr
Output Constraints
Output constraints allow you to specify all external delays from the device for all
output ports in your design.
You can use the set_output_delay command to specify external output delay
requirements. Use the -clock option to reference a virtual clock. The virtual clock
defines the latching clock for the output port. The TimeQuest analyzer automatically
determines the launching clock inside the device that launches the output data,
because all clocks in the device are defined. Figure 711 shows an example of an
output delay referencing a virtual clock.
Figure 711. Output Delay
Altera Device
External Device
dd
tsu_ext/th_ext
cd_ext
Oscillator
cd_altr
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726
h For more information about using advanced I/O timing, refer to Using Advanced I/O
Timing in Quartus II Help.
f For more information about advanced I/O timing, refer to the I/O Management
chapter in volume 2 of the Quartus II Handbook.
Maximum Skew
To specify the maximum path-based skew requirements for registers and ports in the
design and report the results of maximum skew analysis, use the set_max_skew
command in conjunction with the report_max_skew command.
By default, the set_max_skew command excludes any input or output delay
constraints.
h For more information about the set_max_skew and report_max_skew commands
including full syntax information, options, and example usagerefer to set_max_skew
report_max_skew in Quartus II Help.
727
Precedence
If a conflict of node names occurs between timing exceptions, the following order of
precedence applies:
1. False path
2. Minimum delays and maximum delays
3. Multicycle path
The false path timing exception has the highest precedence. Within each category,
assignments to individual nodes have precedence over assignments to clocks. Finally,
the remaining precedence for additional conflicts is order-dependent, such that the
assignments most recently created overwrite, or partially overwrite, earlier
assignments.
False Paths
Specifying a false path in your design removes the path from timing analysis. Use the
set_false_path command to specify false paths in your design. You can specify
either a point-to-point or clock-to-clock path as a false path. For example, a path you
should specify as false path is a static configuration register that is written once
during power-up initialization, but does not change state again. Although signals
from static configuration registers often cross clock domains, you may not want to
make false path exceptions to a clock-to-clock path, because some data may transfer
across clock domains. However, you can selectively make false path exceptions from
the static configuration register to all endpoints.
Example 722 shows how to make false path exceptions from all registers beginning
with A to all registers beginning with B.
Example 722. False Path
set_false_path -from [get_pins A*] -to [get_pins B*]
The TimeQuest analyzer assumes all clocks are related unless you specify otherwise.
The Creating Clock Groups on page 722 describes how you can use clock groups.
Clock groups are a more efficient way to make false path exceptions between clocks,
compared to writing multiple set_false_path exceptions between every clock
transfer you want to eliminate.
h For more information about the set_false_path commandincluding full syntax
information, options, and example usagerefer to set_false_path in Quartus II Help.
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To report timing with clock filters for output paths with minimum and maximum
delay constraints, you can set the output delay for the output port with a value of
zero. You can use an existing clock from the design or a virtual clock as the clock
reference.
Delay Annotation
To modify the default delay values used during timing analysis, use the
set_annotated_delay and set_timing_derate commands. You must update the
timing netlist to see the results of these commands
To specify different operating conditions in a single .sdc, rather than having multiple
.sdc files that specify different operating conditions, use the set_annotated_delay
command with the -operating_conditions option.
h For more information about the set_annotated_delay and set_timing_derate
commandsincluding full syntax information, options, and example usagerefer to
set_annotated_delay and set_timing_derate in Quartus II Help.
729
Multicycle Paths
By default, the TimeQuest analyzer performs a single-cycle analysis, which is the
most restrictive type of analysis. When analyzing a path, the setup launch and latch
edge times are determined by finding the closest two active edges in the respective
waveforms. For a hold analysis, the timing analyzer analyzes the path against two
timing conditions for every possible setup relationship, not just the worst-case setup
relationship. Therefore, the hold launch and latch times may be completely unrelated
to the setup launch and latch edges. The TimeQuest analyzer does not report negative
setup or hold relationships. When either a negative setup or a negative hold
relationship is calculated, the TimeQuest analyzer moves both the launch and latch
edges such that the setup and hold relationship becomes positive.
A multicycle constraint adjusts setup or hold relationships by the specified number of
clock cycles based on the source (-start) or destination (-end) clock. An end setup
multicycle constraint of 2 extends the worst-case setup latch edge by one destination
clock period. If -start and -end values are not specified, the default constraint is end.
Hold multicycle constraints are based on the default hold position (the default value
is 0). An end hold multicycle constraint of 1 effectively subtracts one destination clock
period from the default hold latch edge.
When the objects are timing nodes, the multicycle constraint only applies to the path
between the two nodes. When an object is a clock, the multicycle constraint applies to
all paths where the source node (-from) or destination node (-to) is clocked by the
clock. When you adjust a setup relationship with a multicycle constraint, the hold
relationship is adjusted automatically.
Table 74 shows the commands you can use to modify either the launch or latch edge
times that the TimeQuest analyzer uses to determine a setup relationship or hold
relationship.
Table 74. Commands to Modify Edge Times
Command
Description of Modification
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In this example, the source clock has a period of 10 ns, but a group of registers are
enabled by a toggling clock, so they only toggle every other cycle. Since they are fed
by a 10 ns clock, the TimeQuest analyzer reports a set up of 10 ns and a hold of 0 ns,
However, since the data is transferring every other cycle, the relationships should be
analyzed as if the clock were operating at 20 ns, which would result in a setup of
20 ns, while the hold remains 0 ns, in essence, extending the window of time when the
data can be recognized.
Example 723 shows a pair of multicycle assignments that relax the setup relationship
by specifying the -setup value of N and the -hold value as N-1. You must specify the
hold relationship with a -hold assignment to prevent a positive hold requirement.
Example 723. Relaxing Setup while Maintaining Hold
set_multicycle_path -setup -from src_reg* -to dst_reg* 2
set_multicycle_path -hold -from src_reg* -to dst_reg* 1
Figure 712 shows how the exception relaxes the setup by two or three cycles.
Figure 712. Relaxing Setup by Multiple Cycles
0 ns
10 ns
20 ns
30 ns
No Multicycles
(Default Relationship)
Setup = 10 ns
Hold = 0 ns
0 ns
10 ns
20 ns
30 ns
Setup = 2
Hold = 1
Setup = 20 ns
Hold = 0 ns
0 ns
10 ns
20 ns
30 ns
Setup = 3
Hold = 2
Setup = 30 ns
Hold = 0 ns
This pattern can be extended to create larger setup relationships in order to ease
timing closure requirements. A common use for this exception is when writing to
asynchronous RAM across an I/O interface. The delay between address, data, and a
write enable may be several cycles. A multicycle exception to I/O ports can allow
extra time for the address and data to resolve before the enable occurs.
Example 724 shows how a relaxing the setup by three cycles can be achieved.
Example 724. Three Cycle I/O Interface Exception
set_multicycle_path -setup -to [get_ports {SRAM_ADD[*] SRAM_DATA[*]} 3
set_multicycle_path -hold -to [get_ports {SRAM_ADD[*] SRAM_DATA[*]} 2
731
The default setup relationship for this phase-shift is 0.2 ns, shown in Figure A,
creating a scenario where the hold relationship is negative, which makes achieving
timing closure nearly impossible.
Figure 713. Phase-Shifted Setup and Hold
-10 ns
0 ns
10 ns
20 ns
No Multicycles
(Default Relationship)
Setup = 0.2 ns
Hold = -9.8 ns
-10 ns
0 ns
10 ns
20 ns
Setup = 2
Setup = 10.2 ns
Hold = 0.2 ns
Adding the constraint shown in Example Y allows the data to transfer to the following
edge.
Example 726. Adjusting the Phase-Shift with a set_multicycle_path Constraint
set_multicycle_path -setup -from [get_clocks clk_a] -to [get_clocks clk_b] 2
The hold relationship is derived from the setup relationship, making a multicyle hold
constraint unnecessary. For a more complete example refer to Same Frequency
Clocks with Destination Clock Offset on page 744.
h For more information about the set_multicycle_path commandincluding full
syntax information, options, and example usagerefer to set_multicycle_path in
Quartus II Help.
June 2012
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732
SET
REG2
Combinational
Logic
Tclk1
SET
Tdata
CLR
CLR
Tclk2
TCO
TSU / TH
CLK
10
20
REG1.CLK
EMS = 1
(default)
EMS = 3
EMS = 2
REG2.CLK
733
A start multicycle setup assignment modifies the launch edge of the source clock by
moving the launch edge the specified number of clock periods to the left of the
determined default launch edge. Figure 716 shows various values of the start
multicycle setup assignment and the resulting launch edge.
Figure 716. Start Multicycle Setup Values
0
10
20
30
40
Source Clock
SMS = 2
SMS = 1
(default)
SMS = 3
Destination Clock
Figure 717 shows the setup relationship reported by the TimeQuest analyzer for the
negative setup relationship shown in Figure 716.
Figure 717. Start Multicycle Setup Values Reported by the TimeQuest Analyzer
-10
10
20
Source Clock
SMS = 1
(default)
SMS = 2
SMS = 3
Destination Clock
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10
20
Source Clock
SMH = 0
(default)
SMH = 1
SMH = 2
Destination Clock
An end multicycle hold assignment modifies the latch edge of the destination clock by
moving the latch edge the specific ed number of clock periods to the left of the
determined default latch edge. Figure 719 shows various values of the end
multicycle hold assignment and the resulting latch edge.
Figure 719. End Multicycle Hold Values
-20
-10
10
20
EMH = 2
Source Clock
EMH = 1
EMH= 0
(default)
Destination Clock
735
Figure 720 shows the hold relationship reported by the TimeQuest analyzer for the
negative hold relationship shown in Figure 719.
Figure 720. End Multicycle Hold Values Reported by the TimeQuest Analyzer
-10
10
20
Source Clock
EMH = 0
default)
EMH = 2
EMH = 1
Destination Clock
Each example explains how the multicycle exceptions affect the default setup and
hold analysis in the TimeQuest analyzer. The multicycle exceptions are applied to a
simple register-to-register circuit. Both the source and destination clocks are set to
10 ns.
Default Settings
By default, the TimeQuest analyzer performs a single-cycle analysis to determine the
setup and hold checks. Also, by default, the TimeQuest analyzer sets the end
multicycle setup assignment value to one and the end multicycle hold assignment
value to zero.
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Altera Corporation
736
Figure 721 shows the source and the destination timing waveform for the source
register and destination register, respectively where HC1 and HC2 are hold checks
one and two and SC is the setup check.
Figure 721. Default Timing Diagram
-10
10
20
Current Launch
REG1.CLK
HC1
REG2.CLK
SC
HC2
Current Latch
10 ns 0 ns
10 ns
The most restrictive setup relationship with the default single-cycle analysis, that is, a
setup relationship with an end multicycle setup assignment of one, is 10 ns.
737
Figure 722 shows the setup report for the default setup in the TimeQuest analyzer
with the launch and latch edges highlighted.
Figure 722. Setup Report
hold check 2
= 10 ns 10 ns
= 0 ns
The most restrictive hold relationship with the default single-cycle analysis, that a
hold relationship with an end multicycle hold assignment of zero, is 0 ns.
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Altera Corporation
738
Figure 723 shows the hold report for the default setup in the TimeQuest analyzer
with the launch and latch edges highlighted.
Figure 723. Hold Report
An end multicycle hold value is not required because the default end multicycle hold
value is zero.
In this example, the setup relationship is relaxed by a full clock period by moving the
latch edge to the next latch edge. The hold analysis is unchanged from the default
settings.
739
Figure 724 shows the setup timing diagram. The latch edge is a clock cycle later than
in the default single-cycle analysis.
Figure 724. Setup Timing Diagram
-10
10
20
Current Launch
REG1.CLK
SC
REG2.CLK
Current Latch
The most restrictive setup relationship with an end multicycle setup assignment of
two is 20 ns.
Figure 725 shows the setup report in the TimeQuest analyzer with the launch and
latch edges highlighted.
Figure 725. Setup Report
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740
Because the multicycle hold latch and launch edges are the same as the results of hold
analysis with the default settings, the multicycle hold analysis in this example is
equivalent to the single-cycle hold analysis. Figure 726 shows the timing diagram for
the hold checks for this example. The hold checks are relative to the setup check.
Usually, the TimeQuest analyzer performs hold checks on every possible setup check,
not only on the most restrictive setup check edges.
Figure 726. Hold Timing DIagram
-10
10
20
Current Launch
REG1.CLK
Data
HC1
SC
HC2
REG2.CLK
Current Latch
hold check 2
The most restrictive hold relationship with an end multicycle setup assignment value
of two and an end multicycle hold assignment value of zero is 10 ns.
741
Figure 727 shows the hold report for this example in the TimeQuest analyzer with
the launch and latch edges highlighted.
Figure 727. Hold Report
In this example, the setup relationship is relaxed by two clock periods by moving the
latch edge to the left two clock periods. The hold relationship is relaxed by a full
period by moving the latch edge to the previous latch edge.
June 2012
Altera Corporation
742
0
Current
Launch
10
20
SRC.CLK
SC
DST.CLK
2
Current
Latch
The most restrictive hold relationship with an end multicycle setup assignment value
of two is 20 ns.
Figure 729 shows the setup report for this example in the TimeQuest analyzer with
the launch and latch edges highlighted.
Figure 729. Setup Report
743
Figure 730 shows the timing diagram for the hold checks for this example. The hold
checks are relative to the setup check.
Figure 730. Hold Timing Diagram
-10
0
Current
Launch
10
20
SRC.CLK
SC
HC1
HC2
DST.CLK
Current
Latch
hold check 2
The most restrictive hold relationship with an end multicycle setup assignment value
of two and an end multicycle hold assignment value of one is 0 ns.
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Figure 731 shows the hold report for this example in the TimeQuest analyzer with
the launch and latch edges highlighted.
Figure 731. Hold Report
Each example explains how the multicycle exceptions affect the default setup and
hold analysis in the TimeQuest analyzer. All of the examples are between related
clock domains. If your design contains related clocks, such as PLL clocks, and paths
between related clock domains, you can apply multicycle constraints.
745
clk0
SET
REG2
Combinational
Logic
CLR
SET
Out
CLR
clk1
Figure 733 shows the timing diagram for default setup check analysis performed by
the TimeQuest analyzer.
Figure 733. Setup Timing Diagram
-10
0
Launch
10
20
REG1.CLK
SC
REG2.CLK
2
Latch
Equation 710 shows the calculation that the TimeQuest analyzer performs to
determine the setup check.
Equation 710. Setup Check
setup check
The setup relationship shown in Figure 733 is too pessimistic and is not the setup
relationship required for typical designs. To correct the default analysis, you must use
an end multicycle setup exception of two. Example 729 shows the multicycle
exception used to correct the default analysis in this example.
Example 729. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst]
-setup -end 2
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Altera Corporation
746
Figure 734 shows the timing diagram for the preferred setup relationship for this
example.
.
0
Launch
10
20
REG1.CLK
SC
REG2.CLK
2
Latch
Figure 735 shows the timing diagram for default hold check analysis performed by
the TimeQuest analyzer with an end multicycle setup value of two.
Figure 735. Default Hold Check
-10
0
Current
Launch
10
20
REG1.CLK
HC1
SC
HC2
REG2.CLK
Current
Latch
Equation 711 shows the calculation that the TimeQuest analyzer performs to
determine the hold check.
Equation 711. Hold Check
hold check 1
hold check 2
In this example, the default hold analysis returns the preferred hold requirements and
no multicycle hold exceptions are required.
747
Figure 736 shows the associated setup and hold analysis if the phase shift is 2 ns. In
this example, the default hold analysis is correct for the negative phase shift of 2 ns,
and no multicycle exceptions are required.
Figure 736. Negative Phase Shift
-10
0
Current
Launch
10
20
REG1.CLK
HC1
SC
HC2
REG2.CLK
Current
Latch
SET
REG2
Combinational
Logic
SET
Out
clk0
CLR
clk
CLR
clk1
June 2012
Altera Corporation
748
Figure 738 shows the timing diagram for default setup check analysis performed by
the TimeQuest analyzer.
Figure 738. Setup Timing Diagram
-10
10
20
Launch
REG1.CLK
SC
REG2.CLK
2
Latch
Equation 712 shows the calculation that the TimeQuest analyzer performs to
determine the setup check.
Equation 712. Setup Check
setup check
The setup relationship shown in Figure 738 demonstrates that the data does not need
to be captured at edge one, but can be captured at edge two; therefore, you can relax
the setup requirement. To correct the default analysis, you must shift the latch edge by
one clock period with an end multicycle setup exception of two. Example 730 shows
the multicycle exception used to correct the default analysis in this example.
Example 730. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst]
-setup -end 2
749
Figure 739 shows the timing diagram for the preferred setup relationship for this
example.
Figure 739. Preferred Setup Analysis
-10
10
20
Launch
REG1.CLK
SC
REG2.CLK
2
Latch
Figure 740 shows the timing diagram for default hold check analysis performed by
the TimeQuest analyzer with an end multicycle setup value of two.
Figure 740. Default Hold Check
-10
0
Current
Launch
10
20
REG1.CLK
SC
HC1
HC2
REG2.CLK
Current
Latch
Equation 713 shows the calculation that the TimeQuest analyzer performs to
determine the hold check.
Equation 713. Hold Check
hold check 1
hold check 2
In this example, hold check one is too restrictive. The data is launched by the edge at
0 ns and should check against the data captured by the previous latch edge at 0 ns,
which does not occur in hold check one. To correct the default analysis, you must use
an end multicycle hold exception of one.
June 2012
Altera Corporation
750
SET
REG2
Combinational
Logic
SET
Out
clk0
CLR
clk
CLR
clk1
Figure 742 shows the timing diagram for default setup check analysis performed by
the TimeQuest analyzer.
Figure 742. Setup Timing Diagram
-10
10
20
Launch
REG1.CLK
SC
REG2.CLK
Latch
Equation 714 shows the calculation that the TimeQuest analyzer performs to
determine the setup check.
.
= 2 ns 0 ns
= 2 ns
The setup relationship shown in Figure 742 demonstrates that the data does not need
to be captured at edge one, but can be captured at edge two; therefore, you can relax
the setup requirement. To correct the default analysis, you must shift the latch edge by
one clock period with an end multicycle setup exception of three.
751
Example 731 shows the multicycle exception used to correct the default analysis in
this example.
Example 731. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst]
-setup -end 3
Figure 743 shows the timing diagram for the preferred setup relationship for this
example.
Figure 743. Preferred Setup Analysis
-10
10
20
Launch
REG1.CLK
SC
REG2.CLK
3
Latch
Figure 744 shows the timing diagram for default hold check analysis performed by
the TimeQuest analyzer with an end multicycle setup value of three.
Figure 744. Default Hold Check
-10
0
Current
Launch
10
20
REG1.CLK
SC
HC2
HC1
REG2.CLK
Current
Latch
June 2012
Altera Corporation
752
Equation 715 shows the calculation that the TimeQuest analyzer performs to
determine the hold check.
Equation 715. Hold Check
hold check 1
hold check 2
In this example, hold check one is too restrictive. The data is launched by the edge at
0 ns and should check against the data captured by the previous latch edge at 2 ns,
which does not occur in hold check one. To correct the default analysis, you must use
an end multicycle hold exception of one.
SET
REG2
Combinational
Logic
SET
Out
clk0
CLR
clk
CLR
clk1
753
Figure 746 shows the timing diagram for default setup check analysis performed by
the TimeQuest analyzer.
Figure 746. Default Setup Check Analysis
-10
10
20
Launch
REG1.CLK
SC
REG2.CLK
Latch
Equation 716 shows the calculation that the TimeQuest analyzer performs to
determine the setup check.
Equation 716. Setup Check
setup check
The setup relationship shown in Figure 746 demonstrates that the data launched at
edge one does not need to be captured, and the data launched at edge two must be
captured; therefore, you can relax the setup requirement. To correct the default
analysis, you must shift the launch edge by one clock period with a start multicycle
setup exception of two.
Example 732 shows the multicycle exception used to correct the default analysis in
this example.
Example 732. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst]
-setup -start 2
June 2012
Altera Corporation
754
Figure 747 shows the timing diagram for the preferred setup relationship for this
example.
Figure 747. Preferred Setup Check Analysis
-10
10
20
Launch
2
REG1.CLK
SC
REG2.CLK
Latch
Figure 748 shows the timing diagram for default hold check analysis performed by
the TimeQuest analyzer with a start multicycle setup value of two.
Figure 748. Default Hold Check
-10
0
Current
Launch
10
20
REG1.CLK
HC1
SC
HC2
REG2.CLK
Current
Latch
Equation 717 shows the calculation that the TimeQuest analyzer performs to
determine the hold check.
.
hold check 2
In this example, hold check two is too restrictive. The data is launched next by the
edge at 10 ns and should check against the data captured by the current latch edge at
10 ns, which does not occur in hold check two. To correct the default analysis, you
must use a start multicycle hold exception of one.
755
SET
REG2
Combinational
Logic
SET
Out
clk0
CLR
clk
CLR
clk1
Figure 750 shows the timing diagram for default setup check analysis performed by
the TimeQuest analyzer.
Figure 750. Setup Timing Diagram
-10
10
20
Launch
REG1.CLK
REG2.CLK
Latch
Equation 718 shows the calculation that the TimeQuest analyzer performs to
determine the setup check.
.
The setup relationship shown in Figure 750 demonstrates that the data is not
launched at edge one, and the data that is launched at edge three must be captured;
therefore, you can relax the setup requirement. To correct the default analysis, you
must shift the launch edge by two clock periods with a start multicycle setup
exception of three.
June 2012
Altera Corporation
756
Example 733 shows the multicycle exception used to correct the default analysis in
this example.
Example 733. Multicycle Exceptions
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst]
-setup -start 3
Figure 751 shows the timing diagram for the preferred setup relationship for this
example.
Figure 751. Preferred Setup Check Analysis
-10
10
20
Launch
3
REG1.CLK
SC
REG2.CLK
Latch
Figure 752 shows the timing diagram for default hold check analysis performed by
the TimeQuest analyzer with a start multicycle setup value of three.
Figure 752. Default Hold Check Analysis
-10
0
Current
Launch
10
20
REG1.CLK
HC2
HC1
SC
REG2.CLK
Current
Latch
Equation 719 shows the calculation that the TimeQuest analyzer performs to
determine the hold check.
Equation 719. Hold Check
hold check 1
0 ns 2 ns
= 2 ns
hold check 2
757
In this example, hold check two is too restrictive. The data is launched next by the
edge at 10 ns and should check against the data captured by the current latch edge at
12 ns, which does not occur in hold check two. To correct the default analysis, you
must use a start multicycle hold exception of one.
Timing Reports
The TimeQuest analyzer provides real-time static timing analysis result reports. The
TimeQuest analyzer does not automatically generate reports; you must create each
report individually in the TimeQuest analyzer GUI or with command-line commands.
You can customize in which report to display specific timing information, excluding
fields that are not required.
Table 75 shows some of the different command-line commands you can use to
generate reports in the TimeQuest analyzer and the equivalent reports shown in the
TimeQuest analyzer GUI.
Table 75. TimeQuest Analyzer Reports
Command-Line Command
Report
report_timing
Timing report
report_exceptions
Exceptions report
report_clock_transfers
report_min_pulse_width
report_ucp
June 2012
Altera Corporation
758
f For more information about timing closure recommendations, refer to the Area and
Timing Optimization chapter in volume 2 of the Quartus II Handbook.
June 2012
November 2011
May 2011
December 2010
July 2010
Version
Changes
Reorganized chapter.
Added Using the Quartus II Templates section on creating an SDC constraints file with
the Insert Template dialog box.
Added Identifying the Quartus II Software Executable from the SDC File section.
Consolidated content from the Best Practices for the Quartus II TimeQuest
Timing Analyzer chapter.
12.0.0
11.1.0
11.0.0
10.1.0
10.0.0
Updated to link to content on SDC commands and the TimeQuest analyzer GUI in Quartus II
Help.
759
Version
Changes
Updated for the Quartus II software version 9.1, including:
November 2009
9.1.0
Added information about commands for adding and removing items from collections
November 2008
8.1.0
Updated the descriptions of the -append and -file <name> options in tables
throughout the chapter
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
June 2012
Altera Corporation
760
As FPGA designs grow larger and processes continue to shrink, power is an everincreasing concern. When designing a PCB, the power consumed by a device must be
accurately estimated to develop an appropriate power budget, and to design the
power supplies, voltage regulators, heat sink, and cooling system.
The Quartus II software allows you to estimate the power consumed by your current
design during timing simulation. The power consumption of your design can be
calculated using the Microsoft Excel-based power calculator, or the Simulation-Based
Power Estimation features in the Quartus II software. This section explains how to use
both.
This section includes the following chapter:
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
This chapter describes how to use the Altera Quartus II PowerPlay Power Analysis
tools to accurately estimate device power consumption.
As designs grow larger and process technology continues to shrink, power becomes
an increasingly important design consideration. When designing a PCB, you must
estimate the power consumption of a device accurately to develop an appropriate
power budget, and to design the power supplies, voltage regulators, heat sink, and
cooling system.
Figure 81 shows the ability of the PowerPlay Power Analysis tools to estimate power
consumption from early design concept through design implementation.
Figure 81. PowerPlay Power Analysis
Higher
PowerPlay Early Power Estimator
Estimation Accuracy
Placement and
Routing
Results
User Input
Quartus II
Design Profile
Design Concept
Lower
Simulation
Results
Design Implementation
Higher
h For more information about the PowerPlay suite of power analysis and optimizations
tools, refer to About Power Estimation and Analysis in Quartus II Help. For more
information about acquiring the PowerPlay EPE spreadsheet, refer to PowerPlay
Early Power Estimators (EPE) and Power Analyzer on the Altera website.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Feedback Subscribe
82
Thermal planningThermal power is the power that dissipates as heat from the
FPGA. You must use a heatsink or fan to act as a cooling solution for your device.
The cooling solution must be sufficient to dissipate the heat that the device
generates. The computed junction temperature must fall within normal device
specifications.
Power supply planningPower supply is the power needed to run your device.
Power supplies must provide adequate current to support device operation.
The two types of analyses are closely related because much of the power supplied to
the device dissipates as heat from the device; however, in some situations, the two
types of analyses are not identical. For example, if you use terminated I/O standards,
some of the power drawn from the power supply of the device dissipates in
termination resistors rather than in the device.
Power analysis also addresses the activity of your design over time as a factor that
impacts the power consumption of the device. Static power is the power consumption
of the device regardless of your design activity. Dynamic power is the additional
power consumption of the device due to signal activity or toggling.
1
For power supply planning, you can use the PowerPlay EPE at the early stages of
your design cycle. Alternatively, you can also use the PowerPlay Power Analyzer
reports when your design is complete to get an estimate of your design power
requirement.
For system-on-a-chip (SoC) power estimation, you can use the HPS Power Calculator
at the design implementation stage of your design cycle to include the hard processor
system (HPS) power.
For more information about the HPS Power Calculator, refer to Using the HPS Power
Calculator on page 87.
83
Device Selection
Device families have different power characteristics. Many parameters affect the
device family power consumption, including choice of process technology, supply
voltage, electrical design, and device architecture.
Power consumption also varies in a single device family. A larger device consumes
more static power than a smaller device in the same family because of its larger
transistor count. Dynamic power can also increase with device size in devices that
employ global routing architectures.
The choice of device package also affects the ability of the device to dissipate heat.
This choice can impact your required cooling solution choice to comply to junction
temperature constraints.
Process variation can affect power consumption. Process variation primarily impacts
static power because sub-threshold leakage current varies exponentially with changes
in transistor threshold voltage. So, you must consult device specifications for static
power and not rely on empirical observation. Process variation has a weak effect on
dynamic power.
Environmental Conditions
Operating temperature primarily affects device static power consumption. Higher
junction temperatures result in higher static power consumption. The device thermal
power and cooling solution that you use must result in the device junction
temperature remaining within the maximum operating range for the device. The main
environmental parameters affecting junction temperature are the cooling solution and
ambient temperature.
Airflow
Airflow is a measure of how quickly the device removes heated air from the vicinity
of the device and replaces air at ambient temperature. You can either specify airflow
as still air when you are not using a fan, or as the linear feet per minute rating of the
fan in the system. Higher airflow decreases thermal resistance.
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84
Junction Temperature
The junction temperature of a device is equal to:
TJunction = TAmbient + PThermal JA
in which JA is the total thermal resistance from the device transistors to the
environment, having units of degrees Celsius per watt. The value JA is equal to the
sum of the junction-to-case (package) thermal resistance ( JC), and the case-to-ambient
thermal resistance (CA) of your cooling solution.
Number and Type of Logic Elements, Multiplier Elements, and RAM Blocks
A design with more logic elements (LEs), multiplier elements, and memory blocks
tends to consume more power than a design with fewer circuit elements. The
operating mode of each circuit element also affects its power consumption. For
example, a DSP block performing 18 18 multiplications and a DSP block performing
multiply-accumulate operations consume different amounts of dynamic power
because of different amounts of charging internal capacitance on each transition. The
operating mode of a circuit element also affects static power.
85
Signal Activities
The final important factor in estimating power consumption is the behavior of each
signal in your design. The two vital statistics are the toggle rate and the static
probability.
The toggle rate of a signal is the average number of times that the signal changes
value per unit of time. The units for toggle rate are transitions per second and a
transition is a change from 1 to 0, or 0 to 1.
The static probability of a signal is the fraction of time that the signal is logic 1 during
the period of device operation that is being analyzed. Static probability ranges from 0
(always at ground) to 1 (always at logic-high).
Dynamic power increases linearly with the toggle rate as you charge the capacitive
load more frequently for logic and routing. The Quartus II software models full
rail-to-rail switching. For high toggle rates, especially on circuit output I/O pins, the
circuit can transition before fully charging the downstream capacitance. The result is a
slightly conservative prediction of power by the PowerPlay Power Analyzer.
Static probabilities of their input signals can sometimes affect the static power that
routing and logic consume. This effect is due to state-dependent leakage and has a
larger effect on smaller process geometries. The Quartus II software models this effect
on devices at 90 nm (or smaller) if it is important to the power estimate. The static
power also varies with the static probability of a logic 1 or 0 on the I/O pin when
output I/O standards drive termination resistors.
1
November 2012
To get accurate results from the power analysis, the signal activities for analysis must
represent the actual operating behavior of your design. Inaccurate signal toggle rate
data is the largest source of power estimation error.
Altera Corporation
86
PowerPlay EPE
(Part 1 of 2)
Any time
Post-fit
Tool requirements
Accuracy
Medium
Data inputs
Post-fit design
Clock requirements
Clock requirements
Environmental conditions
Toggle rate
Environmental conditions
87
Table 81. Comparison of the PowerPlay EPE and Quartus II PowerPlay Power Analyzer
Characteristic
Data outputs
PowerPlay EPE
(1)
(Part 2 of 2)
The result of the PowerPlay Power Analyzer is only an estimation of power. Altera
does not recommend using the result as a specification. The purpose of the estimation
is to help you to establish guidelines for the power budget of your design. Altera
recommends that you measure the actual power on the board. You must measure the
total dynamic current of your design during device operation because the estimate is
design dependent and depends on many variable factors, including input vector
quantity, quality, and exact loading conditions of a PCB design. You must not base
static power consumption on empirical observation. You must use the reported values
by the PowerPlay Power Analyzer or data sheet because the tested devices might not
exhibit worst-case behavior.
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Operating
Conditions (1)
PowerPlay
Power Analyzer
Signal
Activities
Power Analysis
Report
To obtain accurate I/O power estimates, the PowerPlay Power Analyzer requires you
to synthesize your design and then fit your design to the target device. You must
specify the electrical standard on each I/O cell and the capacitive load on each I/O
standard in your design.
89
h For more information, refer to Temperature Page (Settings Dialog Box) in Quartus II
Help.
Simulation results
Vectorless estimation
The PowerPlay Power Analyzer allows you to mix and match the signal-activity data
sources on a signal-by-signal basis. Figure 83 shows the priority scheme. The
following sections describe the data sources.
Figure 83. Signal-Activity Data Source Priority Scheme
Start
No
Node or entity
assignment?
Yes
Simulation
data?
Yes
Use node or
entity assignment
Use simulation
data
No
Is primary
input?
Yes
No
Vectorless
supported and
enabled?
(1)
Yes
Use vectorless
estimation
No
Use default
assignment
Simulation Results
The PowerPlay Power Analyzer directly reads the waveforms generated by a design
simulation. You can calculate the static probability and toggle rate for each signal
from the simulation waveform. Power analysis is most accurate when you use
representative input stimuli to generate simulations.
The PowerPlay Power Analyzer reads results generated by the following simulators:
November 2012
ModelSim
ModelSim-Altera
QuestaSim
Altera Corporation
810
Active-HDL
NCSim
VCS
VCS MX
Riviera-PRO
Signal activity and static probability information derive from a Verilog Value Change
Dump File (.vcd). For more information, refer to Signal Activities on page 85.
For third-party simulators, use the EDA Tool Settings to specify the Generate Value
Change Dump (VCD) file script option in the Simulation page of the Settings dialog
box. These scripts instruct the third-party simulators to generate a .vcd that encodes
the simulated waveforms. The Quartus II PowerPlay Power Analyzer reads this file
directly to derive the toggle rate and static probability data for each signal.
Third-party EDA simulators, other than those listed, can generate a .vcd that you can
use with the PowerPlay Power Analyzer. For those simulators, you must manually
create a simulation script to generate the appropriate .vcd.
1
You can use a .vcd created for power analysis to optimize your design for power
during fitting by utilizing the appropriate settings in the PowerPlay power
optimization list, available in the Fitter Settings page of the Settings dialog box.
f For more information about power optimization, refer to the Power Optimization
chapter in volume 2 of the Quartus II Handbook. For more information about how to
create a .vcd in other third-party EDA simulation tools, refer to Section I. Simulation in
volume 3 of the Quartus II Handbook.
Parameter
Input
Video
Processing
Column
Driver
system.vcd
video_gizmo.vcd
output_driver.vcd
Memory
Interface
Video
Source
Interface
Timing
Control
video_input.vcd
811
When specifying a simulation file, the software provides an associated design entity
name, such that the PowerPlay Power Analyzer imports the signal activities derived
from the simulation file (.vcd) for that design entity. The PowerPlay Power Analyzer
also supports the specification of multiple .vcd files for power analysis, with each
having an associated design entity name to enable the integration of partial design
simulations into a complete design power analysis. When specifying multiple .vcd
files for your design, more than one simulation file should contain signal-activity
information for the same signal. When you apply multiple .vcd files to the same
design entity, the signal activity used in the power analysis is the equal-weight
arithmetic average of each .vcd. When you apply multiple simulation files to design
entities at different levels in your design hierarchy, the signal activity in the power
analysis derives from the simulation file that applies to the most specific design entity.
Figure 85 shows an example of a hierarchical design. The top-level module of your
design, called Top, consists of three 8b/10b decoders, followed by a multiplexer. The
software then encodes the output of the multiplexer again before being the output
from your design. An error-handling module handles any 8b/10b decoding errors.
The Top module contains the top-level entity of your design and any logic not defined
as part of another module. The design file for the top-level module might be a
wrapper for the hierarchical entities below it, or it might contain its own logic. The
following usage scenarios show common ways that you can simulate your design and
import the .vcd into the PowerPlay Power Analyzer.
Figure 85. Example Hierarchical Design
Top
8b10b_dec:decode1
8b10b_rxerr:err1
8b10b_dec:decode2
mux:mux1
8b10b_dec:decode3
8b10b_enc:encode1
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Entity
8b10b_dec.vcd
Top|8b10b_dec:decode1
8b10b_dec.vcd
Top|8b10b_dec:decode2
8b10b_dec.vcd
Top|8b10b_dec:decode3
8b10b_rxerr.vcd
Top|8b10b_rxerr:err1
8b10b_enc.vcd
Top|8b10b_enc:encode1
mux.vcd
Top|mux:mux1
The resulting power analysis applies the simulation vectors in each file to the
assigned entity. Simulation provides signal activities for the pins and for the outputs
of functional blocks. If the inputs to an entity instance are input pins for the entire
design, the simulation file associated with that instance does not provide signal
activities for the inputs of that instance. For example, an input to an entity such as
mux1 has its signal activity specified at the output of one of the decode entities.
Entity
normal.vcd
Top
corner1.vcd
Top
corner2.vcd
Top
The resulting power analysis uses an arithmetic average that the signal activities
calculated from each simulation file to obtain the final signal activities used. If a signal
err_out has a toggle rate of zero toggles per second in normal.vcd, 50 toggles per
second in corner1.vcd, and 70 toggles per second in corner2.vcd, the final toggle rate
in the power analysis is 40 toggles per second.
813
Overlapping Simulations
You can perform a simulation on the entire design, and more exhaustive simulations
on a submodule, such as 8b10b_rxerr. Table 84 lists the import specification for
overlapping simulations.
Table 84. Overlapping Simulation Import Specifications
File Name
Entity
full_design.vcd
Top
error_cases.vcd
Top|8b10b_rxerr:err1
In this case, the software uses signal activities from error_cases.vcd for all the nodes in
the generated .vcd and uses signal activities from full_design.vcd for only those
nodes that do not overlap with nodes in error_cases.vcd. In general, the more specific
hierarchy (the most bottom-level module) derives signal activities for overlapping
nodes.
Partial Simulations
You can perform a simulation in which the entire simulation time is not applicable to
signal-activity calculation. For example, if you run a simulation for 10,000 clock cycles
and reset the chip for the first 2,000 clock cycles. If the PowerPlay Power Analyzer
performs the signal-activity calculation over all 10,000 cycles, the toggle rates are only
80% of their steady state value (because the chip is in reset for the first 20% of the
simulation). In this case, you must specify the useful parts of the .vcd for power
analysis. The Limit VCD Period option enables you to specify a start and end time
when performing signal-activity calculations.
To ensure accuracy, Altera recommends that you use an incremental compilation flow
to preserve the node names of your design.
f For more information about the incremental compilation flow, refer to the Quartus II
Incremental Compilation for Hierarchical and Team-Based Design chapter in volume 1 of
the Quartus II Handbook.
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Glitch Filtering
The PowerPlay Power Analyzer defines a glitch as two signal transitions so closely
spaced in time that the pulse, or glitch, occurs faster than the logic and routing
circuitry can respond. The output of a transport delay model simulator contains
glitches for some signals. The logic and routing structures of the device form a
low-pass filter that filters out glitches that are tens to hundreds of picoseconds long,
depending on the device family.
Some third-party simulators use different models than the transport delay model as
the default model. Different models cause differences in signal activity and power
estimation. The inertial delay model, which is the ModelSim default model, filters out
more glitches than the transport delay model and usually yields a lower power
estimate.
1
Altera recommends that you use the transport simulation model when using the
Quartus II software glitch filtering support with third-party simulators. Simulation
glitch filtering has little effect if you use the inertial simulation model.
h For more information about how to set the simulation model type for your specific
simulator, refer to Quartus II Help.
Glitch filtering in a simulator can also filter a glitch on one LE (or other circuit
element) output from propagating to downstream circuit elements to ensure that the
glitch does not affect simulated results. Glitch filtering prevents a glitch on one signal
from producing non-physical glitches on all downstream logic, which can result in a
signal toggle rate and a power estimate that are too high. Circuit elements in which
every input transition produces an output transition, including multipliers and logic
cells configured to implement XOR functions, are especially prone to glitches.
Therefore, circuits with such functions can have power estimates that are too high
when you do not use glitch filtering.
Altera recommends that you use the glitch filtering feature to obtain the most accurate
power estimates. For .vcd files, the PowerPlay Power Analyzer flows support two
levels of glitch filtering.
To enable the first level of glitch filtering in the Quartus II software for supported
third-party simulators, follow these steps:
1. On the Assignments menu, click Settings.
2. In the Category list, select Simulation under EDA Tool Settings.
3. Select the Tool name to use for the simulation.
4. Turn on Enable glitch filtering.
The second level of glitch filtering occurs while the PowerPlay Power Analyzer is
reading the .vcd generated by a third-party simulator. To enable the second level of
glitch filtering, follow these steps:
1. On the Assignments menu, click Settings.
2. In the Category list, select PowerPlay Power Analyzer Settings.
3. Under Input File(s), turn on Perform glitch filtering on VCD files.
815
The .vcd file reader performs complementary filtering to the filtering performed
during simulation and is often not as effective. While the .vcd file reader can remove
glitches on logic blocks, the file reader cannot determine how a given glitch affects
downstream logic and routing, and may eliminate the impact of the glitch completely.
Filtering the glitches during simulation avoids switching downstream routing and
logic automatically.
1
When running simulation for design verification (rather than to produce input to the
PowerPlay Power Analyzer), Altera recommends that you turn off the glitch filtering
option to produce the most rigorous and conservative simulation from a functionality
viewpoint. When performing simulation to produce input for the PowerPlay Power
Analyzer, Altera recommends that you turn on the glitch filtering to produce the most
accurate power estimates.
If you use the Power Toggle Rate Percentage assignment, and the node does not have
a clock domain, the Quartus II software issues a warning and ignores the assignment.
f For more information about how to use the Assignment Editor in the Quartus II
software, refer to the Constraining Designs chapter in volume 2 of the Quartus II
Handbook.
Assigning toggle rates and static probabilities to individual nodes and entities is
appropriate for signals in which you have knowledge of the signal or entity being
analyzed. For example, if you know that a 100 MHz data bus or memory output
produces data that is essentially random (uncorrelated in time), you can directly enter
a 0.5 static probability and a toggle rate of 50 million transitions per second.
The PowerPlay Power Analyzer treats bidirectional I/O pins differently. The
combinational input port and the output pad for a pin share the same name.
However, those ports might not share the same signal activities. For reading
signal-activity assignments, the PowerPlay Power Analyzer creates a distinct name
<node_name~output> when configuring the bidirectional signal as an output and
<node_name~result> when configuring the signal as an input. For example, if a design
has a bidirectional pin named MYPIN, assignments for the combinational input use the
name MYPIN~result, and the assignments for the output pad use the name
MYPIN~output.
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Altera Corporation
816
When you create the logic assignment in the Assignment Editor, you cannot find the
MYPIN~result and MYPIN~output node names in the Node Finder. Therefore, to create
the logic assignment, you must manually enter the two differentiating node names to
create the assignment for the input and output port of the bidirectional pin.
Vectorless Estimation
For some device families, the PowerPlay Power Analyzer automatically derives
estimates for signal activity on nodes with no simulation or user-entered
signal-activity data. Vectorless estimation statistically estimates the signal activity of a
node based on the signal activities of nodes feeding that node, and on the actual logic
function that the node implements. Vectorless estimation cannot derive signal
activities for primary inputs. Vectorless estimation is accurate for combinational
nodes, but not for registered nodes. Therefore, the PowerPlay Power Analyzer
requires simulation data for at least the registered nodes and I/O nodes for accuracy.
h For more information, refer to Performing Power Analysis with the PowerPlay Power
Analyzer in Quartus II Help.
The PowerPlay Power Analyzer Settings dialog box allows you disable vectorless
estimation. When turned on, vectorless estimation requires priority over default
toggle rates. Vectorless estimation does not override clock assignments.
817
If your design has glitches, the power estimation may not be accurate. Altera
recommends that you use the signal activities from a full post-fit netlist (timing)
simulation to achieve an accurate power estimation of your design.
The following designs might exhibit glitches:
Designs with arithmetic blocks without input and output registers (DSPs and
carry chains)
For more information about creating zero delay simulation signal activities, refer to
Generating a .vcd from Full Post-Fit Netlist (Zero Delay) Simulation on page 820.
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Altera Corporation
818
RTL simulation may not provide signal activities for all registers in the post-fitting
netlist because synthesis loses some register names. For example, synthesis might
automatically transform state machines and counters, thus changing the names of
registers in those structures.
Generating a .vcd
In previous versions of the Quartus II software, you could use either the Quartus II
simulator or an EDA simulator to perform your simulation. The Quartus II software
no longer supports a built-in simulator, and you must use EDA simulators to perform
simulation. Use the .vcd as the input to the PowerPlay Power Analyzer to estimate
power for your design.
f For more information about the supported third-party simulators, refer to
Simulation Results on page 89.
To create a .vcd for your design, follow these steps:
1. On the Assignments menu, click Settings.
2. In the Category list, under EDA Tool Settings, click Simulation.
3. In the Tool name list, select your preferred EDA simulator.
4. In the Format for output netlist list, select Verilog HDL, or SystemVerilog HDL,
or VHDL.
5. Turn on Generate Value Change Dump (VCD) file script.
1
This option turns on the Map illegal HDL characters and Enable glitch
filtering options. The Map illegal HDL characters option ensures that all
signals have legal names and that signal toggle rates are available later in
the PowerPlay Power Analyzer.
6. By turning on Enable glitch filtering, glitch filtering logic is the output when you
generate an EDA netlist for simulation. This option is available regardless of
whether or not you want to generate .vcd scripts. For more information about
glitch filtering, refer to Glitch Filtering on page 814.
819
The file can become extremely large if you write all output signals to the file
because the file size depends on the number of output signals being
monitored and the number of transitions that occur.
8. Click OK.
9. Type a name for your testbench in the Design instance name box.
10. Compile your design with the Quartus II software and generate the necessary
EDA netlist and script that instructs the third-party simulator to generate a .vcd.
f For more information about the NativeLink feature, refer to Section I. Simulation in
volume 3 of the Quartus II Handbook.
11. Perform a simulation with the third-party EDA simulation tool. Call the generated
script in the simulation tool before running the simulation. The simulation tool
generates the .vcd and places it in the project directory.
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Altera Corporation
820
9. Use the .vcd script created in step 6 using the following command:
source <design>_dump_all_vcd_nodes.tcl
10. Run the simulation (for example, run 2000ns or run -all).
11. Quit the simulation using the quit -sim command, if required.
12. Exit the ModelSim software. If you do not exit the software, the ModelSim
software might end the writing process of the .vcd improperly, resulting in a
corrupt .vcd.
Altera recommends that you use the Standard Delay Format Output File
(.sdo) for gate-level timing simulation. The .sdo contains the delay
information of each architecture primitive and routing element in your
design; however, you must exclude the .sdo for zero delay simulation.
821
Summary
The Summary section of the report shows the estimated total thermal power
consumption of your design. This includes dynamic, static, and I/O thermal power
consumption. The I/O thermal power consumption is the total I/O power the VCCIO
power supplies and some portion of the VCCINT contribute. The report also includes a
confidence metric that reflects the overall quality of the data sources for the signal
activities. For example, a Low power estimation confidence value reflects that you
have provided insufficient toggle rate data, or most of the signal-activity information
used for power estimation is from default or vectorless estimation settings. For more
information about the input data, refer to the PowerPlay Power Analyzer Confidence
Metric report.
Settings
The Settings section of the report shows the PowerPlay Power Analyzer settings
information of your design, including the default input toggle rates, operating
conditions, and other relevant setting information.
November 2012
Altera Corporation
822
823
Signal Activities
The Signal Activities section lists toggle rates and static probabilities assumed by
power analysis for all signals with fan-out and pins. This section also lists the signal
type (pin, registered, or combinational) and the data source for the toggle rate and
static probability. By default, this section reports all signal activities, but you can turn
off the report with the Write signal activities to report file option on the PowerPlay
Power Analyzer Settings page.
1
Altera recommends that you turn off the Write signal activities to report file option
for a large design because of the large number of signals present. You can use the
Assignment Editor to specify that activities for individual nodes or entities are
reported by assigning an on value to those nodes for the Power Report Signal
Activities assignment.
Messages
The Messages section lists the messages that the Quartus II software generates during
the analysis.
November 2012
Altera Corporation
824
The default setting and vectorless setting cannot correctly estimate the power
consumption of your design because these settings differ from the user input file
setting, as well as for board measurement, by approximately 30%.
1774.23
1840
1216.62
1120
541.92
720
15.69
Parameters
EPE (m)
1748
1840
1192
1120
556
720
16
825
Scripting Support
You can run procedures and create settings described in this chapter in a Tcl script.
You can also run some procedures at a command prompt. For more information about
scripting command options, refer to the Quartus II Command-Line and Tcl API Help
browser. To run the Help browser, type the following command at the command
prompt:
quartus_sh --qhelpr
f For more information about Tcl scripting, refer to the Tcl Scripting chapter in volume 2
of the Quartus II Handbook and API Functions for Tcl in Quartus II Help. For more
information about all settings and constraints in the Quartus II software, refer to the
Quartus II Settings File Reference Manual. For more information about command-line
scripting, refer to the Command-Line Scripting chapter in volume 2 of the Quartus II
Handbook.
To instruct the PowerPlay Power Analyzer to generate a PowerPlay EPE File, type
the following command at a system command prompt:
quartus_pow sample --output_epe=sample.csv r
To instruct the PowerPlay Power Analyzer to use two .vcd files as input files
(sample1.vcd and sample2.vcd), perform glitch filtering on the .vcd and use a
default input I/O toggle rate of 10,000 transitions per second, type the following
command at a system command prompt:
quartus_pow sample --input_vcd=sample1.vcd --input_vcd=sample2.vcd \
--vcd_filter_glitches=on --\
default_input_io_toggle_rate=10000transitions/s r
November 2012
Altera Corporation
826
To instruct the PowerPlay Power Analyzer to not use an input file, a default input
I/O toggle rate of 60%, no vectorless estimation, and a default toggle rate of 20%
on all remaining signals, type the following command at a system command
prompt:
quartus_pow sample --no_input_file -default_input_io_toggle_rate=60% \
--use_vectorless_estimation=off --default_toggle_rate=20% r
1
The quartus_pow executable creates a report file, <revision name>.pow.rpt. You can
locate the report file in the main project directory. The report file contains the
same information in PowerPlay Power Analyzer Compilation Report on
page 820.
Version
November 2012
12.1.0
June 2012
12.0.0
November 2011
December 2010
July 2010
November 2009
March 2009
10.1.1
10.1.0
10.0.0
9.1.0
9.0.0
Changes
Updated Types of Power Analyses on page 82, and Confidence Metric Details on
page 823.
Added Importance of .vcd on page 820, and Avoiding Power Estimation and
Hardware Measurement Mismatch on page 824
Template update.
Minor edits.
Updated Table 81 on page 86, Table 82 on page 813, and Table 83 on page 814.
Added Signal Activities from Full Post-Fit Netlist (Zero Delay) Simulation on page 819
and Generating a .vcd from Full Post-Fit Netlist (Zero Delay) Simulation on page 821.
Removed Figures 11-10, 11-11, 11-13, 11-14, and 11-17 from 8.1 version.
827
Version
November 2008
May 2008
8.1.0
8.0.0
Changes
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
November 2012
Altera Corporation
828
Chapter 10, Analyzing and Debugging Designs with the System Console
This chapter describes the System Console Toolkit and compares the different
capabilities within the toolkit.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
The Altera system debugging tools help you verify your FPGA designs. As your
product requirements continue to increase in complexity, the time you spend on
design verification continues to rise. This chapter provides a quick overview of the
tools available in the system debugging suite and discusses the criteria for selecting
the best tool for your design.
The Quartus II software provides a portfolio of system design debugging tools for
real-time verification of your design. Each tool in the system debugging portfolio uses
a combination of available memory, logic, and routing resources to assist in the
debugging process. The tools provide visibility by routing (or tapping) signals in
your design to debugging logic. The debugging logic is then compiled with your
design and downloaded into the FPGA or CPLD for analysis. Because different
designs can have different constraints and requirements, such as the number of spare
pins available or the amount of logic or memory resources remaining in the physical
device, you can choose a tool from the available debugging tools that matches the
specific requirements for your design.
Tool
Description
Typical Usage
System Console
Transceiver Toolkit
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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92
Table 91.
Tool
Description
Typical Usage
SignalTap II Logic
Analyzer
SignalProbe
Logic Analyzer
Interface (LAI)
In-System Sources
and Probes
In-System Memory
Content Editor
Virtual JTAG
Interface
With the exception of SignalProbe, each of the on-chip debugging tools uses the JTAG
port to control and read back data from debugging logic and signals under test.
System Console uses JTAG and other interfaces as well. The JTAG resource is shared
among all of the on-chip debugging tools.
For all system debugging tools except System Console, the Quartus II software
compiles logic into your design automatically to distinguish between data and control
information and each of the debugging logic blocks when the JTAG resource is
required. This arbitration logic, also known as the System-Level Debugging (SLD)
infrastructure, is shown in the design hierarchy of your compiled project as
sld_hub:sld_hub_inst. The SLD logic allows you to instantiate multiple debugging
blocks into your design and run them simultaneously. For System Console, you must
explicitly insert IP cores into your design to enable debugging.
To maximize debugging closure, the Quartus II software allows you to use a
combination of the debugging tools in tandem to fully exercise and analyze the logic
under test. All of the tools described in Table 91 have basic analysis features built in;
that is, all of the tools enable you to read back information collected from the design
nodes that are connected to the debugging logic. Out of the set of debugging tools, the
SignalTap II Logic Analyzer, the LAI, and the SignalProbe feature are general purpose
93
debugging tools optimized for probing signals in your register transfer level (RTL)
netlist. In-System Sources and Probes, the Virtual JTAG Interface, System Console,
Transceiver Toolkit, and In-System Memory Content Editor, in addition to being able
to read back data from the debugging breakpoints, allow you to input values into
your design during runtime.
Taken together, the set of on-chip debugging tools form a debugging ecosystem. The
set of tools can generate a stimulus to and solicit a response from the logic under test,
providing a complete debugging solution (Figure 91).
Figure 91. Quartus II Debugging Ecosystem
(1)
Quartus II Software
FPGA
JTAG
Design
Under Test
The tools in the toolchain offer different advantages and different trade-offs. To
understand the selection criteria between the different tools, the following sections
analyze the tools according to their typical applications.
The first section, Analysis Tools for RTL Nodes, compares the SignalTap II Logic
Analyzer, SignalProbe, and the LAI. These three tools are logically grouped since they
are intended for debugging nodes from your RTL netlist at system speed.
The second section, Stimulus-Capable Tools on page 98, compares the System
Console and Transceiver Toolkit, In-System Memory Content Editor, Virtual JTAG
Interface megafunction, and In-System Sources and Probes. These tools are logically
grouped since they offer the ability to both read and write transactions through the
JTAG port.
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The SignalTap II Logic Analyzer is not supported on CPLDs, because there are no
memory resources available on these devices.
Resource Usage
Any debugging tool that requires the use of a JTAG connection requires the SLD
infrastructure logic mentioned earlier, for communication with the JTAG interface and
arbitration between any instantiated debugging modules. This overhead logic uses
around 200 logic elements (LEs), a small fraction of the resources available in any of
the supported devices. The overhead logic is shared between all available debugging
modules in your design. Both the SignalTap II Logic Analyzer and the LAI use a JTAG
connection.
SignalProbe requires very few on-chip resources. Because it requires no JTAG
connection, SignalProbe uses no logic or memory resources. SignalProbe uses only
routing resources to route an internal signal to a debugging test point.
The LAI requires a small amount of logic to implement the multiplexing function
between the signals under test, in addition to the SLD infrastructure logic. Because no
data samples are stored on the chip, the LAI uses no memory resources.
The SignalTap II Logic Analyzer requires both logic and memory resources. The
number of logic resources used depends on the number of signals tapped and the
complexity of the trigger logic. However, the amount of logic resources that the
SignalTap II Logic Analyzer uses is typically a small percentage of most designs. A
baseline configuration consisting of the SLD arbitration logic and a single node with
basic triggering logic contains approximately 300 to 400 Logic Elements (LEs). Each
additional node you add to the baseline configuration adds about 11 LEs. Compared
with logic resources, memory resources are a more important factor to consider for
95
your design. Memory usage can be significant and depends on how you configure
your SignalTap II Logic Analyzer instance to capture data and the sample depth that
your design requires for debugging. For the SignalTap II Logic Analyzer, there is the
added benefit of requiring no external equipment, as all of the triggering logic and
storage is on the chip.
Figure 92 shows a conceptual graph of the resource usage of the three analysis tools
relative to each other.
Figure 92. Resource Usage per Debugging Tool
(1)
Logic Analyzer
Interface
Logic
SignalTap II
Signal
Probe
Memory
The resource estimation feature for the SignalTap II Logic Analyzer and the LAI
allows you to quickly judge if enough on-chip resources are available before
compiling the tool with your design. Figure 93 shows the resource estimation feature
for the SignalTap II Logic Analyzer and the LAI.
Figure 93. Resource Estimator
Pin Usage
The ratio of the number of pins used to the number of signals tapped for the
SignalProbe feature is one-to-one. Because this feature can consume free pins quickly,
a typical application for this feature is routing control signals to spare pins for
debugging.
The ratio of the number of pins used to the number of signals tapped for the LAI is
many-to-one. It can map up to 256 signals to each debugging pin, depending on
available routing resources. The control of the active signals that are mapped to the
spare I/O pins is performed via the JTAG port. The LAI is ideal for routing data buses
to a set of test pins for analysis.
Other than the JTAG test pins, the SignalTap II Logic Analyzer uses no additional
pins. All data is buffered using on-chip memory and communicated to the
SignalTap II Logic Analyzer GUI via the JTAG test port.
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Usability Enhancements
The SignalTap II Logic Analyzer, the SignalProbe feature, and the LAI tools can be
added to your existing design with minimal effects. With the node finder, you can find
signals to route to a debugging module without making any changes to your HDL
files. SignalProbe inserts signals directly from your post-fit database. The SignalTap II
Logic Analyzer and LAI support inserting signals from both pre-synthesis and post-fit
netlists. All three tools allow you to find and configure your debugging setup quickly.
In addition, the Quartus II incremental compilation feature and the Quartus II
incremental routing feature allow for a fast turnaround time for your programming
file, increasing productivity and enabling fast debugging closure.
Both LAI and the SignalTap II Logic Analyzer support incremental compilation. With
incremental compilation, you can add a SignalTap II Logic Analyzer instance or an
LAI instance incrementally into your placed-and-routed design. This has the benefit
of both preserving your timing and area optimizations from your existing design, and
decreasing the overall compilation time when any changes are necessary during the
debugging process. With incremental compilation, you can save up to 70% compile
time of a full compilation.
SignalProbe uses the incremental routing feature. The incremental routing feature
runs only the Fitter stage of the compilation. This also leaves your compiled design
untouched, except for the newly routed node or nodes. With SignalProbe, you can
save as much as 90% compile time of a full compilation.
As another productivity enhancement, all tools in the on-chip debugging tool set
support scripting via the quartus_stp Tcl package. For the SignalTap II Logic
Analyzer and the LAI, scripting enables user-defined automation for data collection
while debugging in the lab.
In addition, the JTAG server allows you to debug a design that is running on a device
attached to a PC in a remote location. This allows you to set up your hardware in the
lab environment, download any new .sof files, and perform any analysis from your
desktop.
Table 92 compares common debugging features between these tools and provides
suggestions about which is the best tool to use for a given feature.
Table 92. Suggested On-Chip Debugging Tools for Common Debugging Features (Part 1 of 2)
Feature
SignalProbe
Large Sample
Depth
Ease in Debugging
Timing Issue
N/A
Logic Analyzer
Interface
(LAI)
v
(1)
SignalTap II
Logic
Analyzer
Description
97
Table 92. Suggested On-Chip Debugging Tools for Common Debugging Features (Part 2 of 2)
Feature
Minimal Effect
on Logic Design
Triggering
Capability
I/O Usage
Acquisition
Speed
SignalProbe
Logic Analyzer
Interface
(LAI)
v (2)
(2)
SignalTap II
Logic
Analyzer
(2)
(2)
N/A
N/A
N/A
Required
No External
Equipment Required
Description
The LAI adds minimal logic to a design,
requiring fewer device resources. The
SignalTap II Logic Analyzer has little effect on
the design, because it is set as a separate
design partition. SignalProbe incrementally
routes nodes to pins, not affecting the design at
all.
No JTAG
Connection
(1)
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Stimulus-Capable Tools
The In-System Memory Content Editor, the In-System Sources and Probes, and the
Virtual JTAG interface each enable you to use the JTAG interface as a general-purpose
communication port. Though all three tools can be used to achieve the same results,
there are some considerations that make one tool easier to use in certain applications
than others. In-System Sources and Probes is ideal for toggling control signals. The
In-System Memory Content Editor is useful for inputting large sets of test data.
Finally, the Virtual JTAG interface is well suited for more advanced users who want to
develop their own customized JTAG solution.
System Console provides system-level debugging at a transaction level, such as with
Avalon-MM slave or Avalon-ST interfaces. You can communicate to a chip through
JTAG, PLI connectivity for simulation models, and TCP/IP protocols. System Console
is a Tcl console that you use to communicate with hardware modules that you have
instantiated into your design.
99
System Console
System Console is a framework that you can launch from the Quartus II software to
start services for performing various debugging tasks. System Console provides you
with Tcl scripts and a GUI to access either the Qsys system integration tool or SOPC
Builder modules to perform low-level hardware debugging of your design, as well as
identify a module by its path, and open and close a connection to a Qsys or SOPC
Builder module. You can access your design at a system level for purposes of loading,
unloading, and transferring designs to multiple devices.
System Console also allows you to access commands that allow you to control how
you generate test patterns, as well as verify the accuracy of data generated by test
patterns. You can use JTAG debug commands in System Console to verify the
functionality and signal integrity of your JTAG chain. You can test clock and reset
signals.
You can use System Console to access programmable logic devices on your
development board, as well as bring up a board and verify stages of setup. You can
also access software running on a Nios II processor, as well as access modules that
produce or consume a stream of bytes.
Transceiver Toolkit runs from the System Console framework, and allows you to run
automatic tests of your transceiver links for debugging and optimizing your
transceiver designs. You can use the Transceiver Toolkit GUI to set up channel links in
your transceiver devices, and then automatically run EyeQ and Auto Sweep testing to
view a graphical representation of your test data.
Conclusion
The Quartus II on-chip debugging tool suite allows you to reach debugging closure
quickly by providing you a with set of powerful analysis tools and a set of tools that
open up the JTAG port as a general purpose communication interface. The Quartus II
software further broadens the scope of applications by giving you a comprehensive
Tcl/Tk API. With the Tcl/Tk API, you can increase the level of automation for all of
the analysis tools. You can also build virtual front panel applications quickly during
the early prototyping phase.
In addition, all of the on-chip debugging tools have a tight integration with the rest of
the productivity features within the Quartus II software. The incremental compilation
and incremental routing features enable a fast turnaround time for programming file
generation. The cross-probing feature allows you to find and identify nodes quickly.
The SignalTap II Logic Analyzer, when used with the TimeQuest Timing Analyzer, is
a best-in-class timing verification suite that allows fast functional and timing
verification.
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910
Date
Version
Changes
June 2012
12.0.0
Maintenance release.
November 2011
10.0.2
December 2010
10.0.1
July 2010
10.0.0
Initial release
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
The System Console performs low-level hardware debugging of Qsys systems. You
can use the System Console to debug systems that include IP cores instantiated in
your Qsys system, as well as for initial bring-up of your printed circuit board, and for
low-level testing. You access the System Console from Qsys, under the Tools menu.
This chapter contains the following sections:
The System Explorer pane allows you to view a hierarchy of the System Console
virtual file system in your design, including connections, devices, designs, design
instances, and scripts.
The Tools pane allows you to launch tools such as the GDB Server Control Panel
and Transceiver Toolkit.
The Tcl Console allows you to run commands and Tcl scripts from within the
System Console.
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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102
Chapter 10: Analyzing and Debugging Designs with the System Console
System Console Overview
h For more information about the System Console GUI, refer to About System Console in
QuartusII Help and the Altera Training page of the Altera website.
The connections folder displays information about the debug cables which are
visible to the System Console.
The designs folder displays information about quartus project designs which have
been loaded into the System Console.
The devices folder contains information about each device connected to the
System Console.
You will be doing most of your work within the devices folder. Within the devices
folder is a folder for each device currently connected to the System Console. Each
device folder contains a (link) folder and sometimes contains a (files) folder.
Chapter 10: Analyzing and Debugging Designs with the System Console
System Console Overview
103
The (link) folder shows debug agents (and other hardware) which the System
Console is able to access, arranged by connection type. The (files) folder contains
information about the design files loaded from the Quartus II project for the device.
Folders under the design_instances folder are linked to the appropriate (files) node.
Figure 102. System Explorer Pane
Figure 102 shows that the EP4SGX230 folder contains a (link) folder. The link
folder contains a JTAG folder. The JTAG folder contains folders that describe the
debug pipes and agents that are connected to the EP4SGX230 device via a JTAG
connection.
The (files) folder contains information about the design files loaded from the
Quartus II project for the device. Instances within the design_instances folder are
linked to the corresponding files in the (files) folder.
Folders that have a context menu available show a small context menu badge
Right-click these folders to view the context menu.
Folders corresponding to debug agents have a clock status badge . The badge
displays a green clock signal if the clock is running or a red clock signal if it is not.
May 2013
System Console commands require service paths to identify the service instance you
want to access. The paths for different components can change between runs of the
tool and between versions. Use get_service_paths and similar commands to obtain
service paths rather then hard coding them into your Tcl scripts.
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Chapter 10: Analyzing and Debugging Designs with the System Console
System Console Overview
Most System Console service instances are automatically discovered when you start
the System Console. The System Console automatically scans for all JTAG and
USB-based service instances and retrieves their service paths. Some other services,
such as those connected by TCP/IP, are not automatically discovered. You can use the
add_service Tcl command to inform the System Console about those services.
Accessing Services
After you have a service path to a particular service instance, you can access the
service for use.
The open_service command tells the System Console to start using a particular
service instance. The open_service command works on every service type. The
open_service command claims a service instance for exclusive use.
c The open_service command does not tell the System Console which part of a service
you are interested in. As such, service instances that you open are not safe for shared
use among multiple users.
The claim_service command tells the System Console to start accessing a particular
portion of a service instance. For example, if you use the master service to access
memory, then use claim_service to tell the System Console that you only want to
access the address space between 0x0 and 0x1000. The System Console then allows
other users to access other memory ranges and denies them access to your claimed
memory range. The claim_service command returns a newly created service path
that you can use to access your claimed resources.
Not all services support the claim_service command.
You can access a service after you open or claim it. When you finish accessing a
service instance, use the close_service command to direct the System Console to
make resources available.
Applying Services
The System Console provides extensive portfolios of services for various applications,
such as real-time on-chip control and debugging, and system measurement. Examples
of how to use these services are provided in this chapter. Table 101 lists example
applications included with the System Console and associated services.
The System Console functions by running Tcl commands that are described in
Table 103 through Table 1017.
Table 101. System Console Example Applications
Application
Services Used
Board Bring-Up
Processor Debug
marker, design
System Monitoring
Chapter 10: Analyzing and Debugging Designs with the System Console
Setting Up the System Console
105
Services Used
transceiver_reconfig_analog, alt_xcvr_reconfig_dfe,
alt_xcvr_reconfig_eye_viewer
transceiver_channel_rx, transceiver_channel_tx,
transceiver_debug_link
Qsys
You can use the System Console to help you debug Qsys systems. The System Console
communicates with debug IP in your system design. You can instantiate debug IP
cores using Qsys or the MegaWizard Plug-In Manager.
f For more information about the Qsys system integration tool, refer to System Design
with Qsys in volume 1 of the Quartus II Handbook.
Table 102 describes some of the IP cores you can use with the System Console to
debug your system. When connected to the System Console, these components enable
you to send commands and receive data.
Table 102. Qsys Components for Communication with the System Console (Part 1 of 2) (1)
Component Name
JTAG UART
TCP/IP
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Chapter 10: Analyzing and Debugging Designs with the System Console
Setting Up the System Console
Table 102. Qsys Components for Communication with the System Console (Part 2 of 2) (1)
Component Name
f For more information about Qsys components, refer to the following web pages and
documents:
SPI Slave/JTAG to Avalon Master Bride Cores chapter in the Embedded Peripherals IP
User Guide
Avalon-ST JTAG Interface Core chapter in the Embedded Peripherals IP User Guide
Chapter 10: Analyzing and Debugging Designs with the System Console
Setting Up the System Console
107
Figure 103 illustrates examples of interfaces of the components that the System
Console can use.
Figure 103. Example Interfaces (Paths) the System Console Uses to Send Commands
Connections You Make
in Qsys
Transparent Connections
Nios II Processor
Avalon-MM
Master
Virtual JTAG
Interface
User Component
Avalon-MM
Slave
or
Avalon-MM
Master
Virtual JTAG
Interface
User Component
Avalon-ST
Source
and Sink
Avalon-ST
Source and
Sink
JTAG Logic
(Quartus II)
Virtual
JTAG Hub
(Soft IP)
JTAG TAP
Controller
(Hard IP)
To
Host PC
Running
System Console
Virtual JTAG
Interface
JTAG UART
Avalon-MM
Slave
Legacy
JTAG
Interface
Altera recommends that you include the following components in your system:
On-chip memory
JTAG UART
System ID core
The System Console provides many different types of services. Different modules can
provide the same type of service. For example, both the Nios II processor and the
JTAG to Avalon Bridge master provide the master service; consequently, you can use
the master commands to access both of these modules.
c If your system includes a Nios II/f core with a data cache, it may complicate the
debugging process. If you suspect the Nios II/f core writes to memory from the data
cache at nondeterministic intervals; thereby, overwriting data written by the System
Console, you can disable the cache of the Nios II/f core while debugging.
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Chapter 10: Analyzing and Debugging Designs with the System Console
Using the System Console
The following describes how to start the System Console from a Nios II command
shell.
1. On the Windows Start menu, point to All Programs, then Altera, then Nios II EDS
<version>, and then click Nios II <version> Command Shell.
2. To start the System Console, type the following command:
system-console r
You can customize your System Console environment by adding commands to the
configuration file called system_console_rc.tcl. This file can be located in either of the
following locations:
<quartus_install_dir>/sopc_builder/system_console_macros/system_console_rc.tcl,
known as the global configuration file, which affects all users of the system
On startup, the System Console automatically runs any Tcl commands in these files.
The commands in the global configuration file run first, followed by the commands in
the user configuration file.
To use the System Console commands, you must connect to a system with a
programming cable and with the proper debugging IP.
Interactive Help
Typing help help into the System Console lists all available commands. Typing
help <command name> provides the syntax of individual commands. The System
Console provides command completion if you type the beginning letters of a
command and then press the Tab key.
1
The System Console interactive help commands only provide help for enabled
services; consequently, typing help help does not display help for commands
supplied by disabled plug-ins.
Console Commands
The console commands enable testing. You can use console commands to identify a
module by its path, and to open and close a connection to it. The path that identifies a
module is the first argument to most of the System Console commands. To exercise a
module, follow these steps:
1. Identify a module by specifying the path to it, using the get_service_paths
command.
Chapter 10: Analyzing and Debugging Designs with the System Console
Using the System Console
109
Arguments
Function
Returns a list of service types that the System Console
manages. Examples of service types include master,
bytestream, processor, sld, jtag_debug, device, and plugin.
Returns a list of paths to nodes that implement the
requested service type.
Note: When this command returns an item in the list that has
only one element and the element has no spaces in it, you
should not pass the element to other commands.
get_service_paths
<service_type>
open_service
<service_type>
<service_path>
claim_service
<service-type>
<service-path>
<claim-group>
<claims>
close_service
<service_type>
<service_path>
is_service_open
<service_type>
<service_path>
get_services_to_add
add_service
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<service-type>
<instance-name>
<optional-parameters>
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Using the System Console
Arguments
Function
add_service dashboard
<name>
<title>
<menu>
add_service gdbserver
<Processor Service>
<port number>
Instantiates a gdbserver.
add_service nios2dpx
add_service
pli_bytestream
<instance_name>
<port_number>
add_service pli_master
<instance_name>
<port_number>
add_service pli_packets
<instance_name>
<port_number>
add_service tcp
<instance_name>
<ip_addr>
<port number>
<data_pattern_checker
path>
<transceiver path>
add_service
transceiver_channel_rx
<transceiver channel
address>
<reconfig path>
<reconfig channel address>
<data_pattern_generator
path>
<transceiver path>
add_service
transceiver_channel_tx
<transceiver channel
address>
<reconfig path>
<reconfig channel address>
add_service
transceiver_debug_link
<transceiver_channel_tx
path>
<transceiver_channel_rx
path>
get_version
add_help
<command>
<help-text>
Adds help text for a given command. Use this when you
write a Tcl script procedure (proc) and then want to provide
help for others to use the script.
get_claimed_services
<claim-group>
Chapter 10: Analyzing and Debugging Designs with the System Console
Using the System Console
1011
Arguments
Function
Scans for available hardware and updates the available
service paths if there have been any changes.
refresh_connections
<level>
<message>
send_message
Plugins
Plugins allow you to customize how you use the System Console services and are
enabled by default. Table 104 lists Plugin commands.
Table 104. Plugin Commands
Command
Arguments
Function
plugin_enable
<plugin-path>
plugin_disable
<plugin-path>
is_plugin_enabled
<plugin-path>
design_load
(1)
design_instantiate
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Arguments
<quartus-project-path>,
<sof-file-path>, or <qpf-file-path>
<design-path>
<instance-name>
Function
Loads a model of a Quartus II design into
the System Console. Returns the design
path.
For example, if your Quartus II Project File
(.qpf) file is in c:/projects/loopback, type
the following command: design_load
{c:\projects\loopback\}
Instantiates a Quartus II design, which
creates an instance. The instance name is
optional. Returns the instance path.
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Using the System Console
Arguments
Function
Creates a design instance if necessary and
then links a Quartus II logical design with a
physical device.
<design-instance-path>
<device-service-path>
design_link
design_extract_debug_files
design_extract_dotty
<design-path>
<zip-file-name>
<design-path>
<dot-file-name>
design_get_warnings
<design-path>
design_update_debug_files
<design-path>
<list-of-files-to-update>
Turn on the Auto Usercode option to have the System Console automatically instantiate and link designs after they have been loaded.
h For more information about Auto Usercode, refer to the General Page (Device and Pin
Options Dialog Box) in Quartus II Help.
Chapter 10: Analyzing and Debugging Designs with the System Console
Using the System Console
1013
Arguments
device_download_sof
<service_path>
<sof-file-path>
Function
Loads the specified .sof file to the device specified
by the path.
device_get_connections
<service_path>
device_get_design
<device_path>
Monitor Commands
You can use the Monitor commands to read many Avalon-MM slave memory
locations at a regular interval. For example, if you want to perform 100 reads per
second, every second, you get much better performance using the monitor service
than if you call 100 separate master_read_memory commands every second. This is the
primary difference between the monitor service and the master service.
Table 107 lists the commands usually called from the main program when setting up
the monitor. Table 108 lists the commands called from within the monitor callback.
To use Monitor commands, you must create a new monitor, set its callback and
interval, add ranges, and then set it to enabled. From within the callback you must use
appropriate read_data commands to extract the data. Note that under heavy load,
one or more monitor callbacks might be skipped.
Table 107. Main Monitoring Commands (Part 1 of 2)
Command
Arguments
Function
Adds a contiguous memory address into the
monitored memory list.
<service-path>
<target-path>
monitor_add_range
<address>
<size>
monitor_set_callback
monitor_set_interval
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<service-path>
<Tcl-expression>
<service-path>
<interval>
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Using the System Console
Arguments
Function
monitor_get_interval
<service-path>
monitor_set_enabled
<service-path>
<enable(1)/disable(0)>
Arguments
<service-path>
<target-path>
<address>
<size>
monitor_add_range
<service-path>
monitor_set_callback
<Tcl-expression>
Function
Adds contiguous memory addresses into the
monitored memory list.
The <target-path> argument is the name of a master
service to read. The address is within the address
space of this service.
Defines a Tcl expression in a single string that will be
evaluated after all the memories monitored by this
service are read. Typically, this expression should be
specified as a Tcl procedure call with necessary
argument passed in.
monitor_read_data
<service-path>
<target-path>
<address>
<size>
monitor_read_all_data
<service-path>
<target-path>
<address>
<size>
<service-path>
monitor_get_read_interv <target-path>
al
<address>
<size>
<service-path>
monitor_get_all_read_in <target-path>
<address>
tervals
<size>
monitor_get_missing_eve
<service-path>
nt_count
Under normal load, the monitor service reads the data after each interval and then
calls the callback. If the value you read is timing sensitive, the
monitor_get_read_interval command can be used to read the exact time between
the intervals at which the data was read.
Under heavy load, or with a callback that takes a long time to execute, the monitor
service skips some callbacks. If the registers you read do not have side effects (for
example, they read the total number of events since reset), skipping callbacks has no
effect on your code. The monitor_read_data command and
monitor_get_read_interval command are adequate for this scenario.
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Using the System Console
1015
If the registers you read have side effects (for example, they return the number of
events since the last read), you must have access to the data that was read, but for
which the callback was skipped. The monitor_read_all_data and
monitor_get_all_read_intervals commands provide access to this data.
Trace Commands
The System Console trace system allows you to identify events of interest in the
hardware and send details of those events to the host system. Table 109 lists the
commands available in the System Console trace system.
To use the trace commands listed in this section and capture the data these commands
produce, instantiate an Altera Trace System and suitable monitors (for example, an
Avalon-ST Video Monitor) in your system. Open the trace system with the
claim_service trace <service-path> <library-name> command. (You can
determine the path to your instantiated trace system by running get_service_paths
trace.)
The claim_service trace command returns a new service path that represents the
instantiated and opened trace system. Use the returned service path in the commands
below to access your hardware and retrieve events of interest.
Table 109. Trace System Commands (Part 1 of 2)
Command
trace_get_monitors
trace_get_monitor_info
trace_read_monitor
Arguments
<service-path>
<service-path>
<monitor-path>
<service-path>
<monitor-path>
<index>
<service-path>
<monitor-path>
trace_write_monitor
Function
<index>
<value>
<service-path>
trace_set_max_db_size
<size>
trace_get_max_db_size
<service-path>
trace_get_db_size
<service-path>
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Using the System Console
Arguments
Function
trace_start
<service-path>
<capture-mode>
trace_stop
<service-path>
<service-path>
trace_get_status
<service-path>
trace_save
<filename>
trace_load
<filename>
The System Console is intended for debugging the basic hardware functionality of
your Nios II processor, including its memories and pinout. If you are writing device
drivers, you may want to use the System Console and the Nios II software build tools
together to debug your code.
f For more information about the hardware functionality and software debugging, refer
to Nios II Software Build Tools Reference in the Nios II Software Developers Handbook.
Chapter 10: Analyzing and Debugging Designs with the System Console
Using the System Console
1017
Arguments
Function
Loops the specified list of bytes through a loopback
of tdi and tdo of a system-level debug (SLD)
node. Returns the list of byte values in the order
that they were received. Blocks until all bytes are
received. Byte values are given with the 0x
(hexadecimal) prefix and delineated by spaces.
<service-path>
<list_of_byte_
jtag_debug_loop
values>
jtag_debug_reset_system
<service-path>
Argument
Function
jtag_debug_sample_clock
<service-path>
Returns the value of the clock signal of the system clock that
drives the module's system interface. The clock value is
sampled asynchronously; consequently, you may need to
sample the clock several times to guarantee that it is
toggling.
jtag_debug_sample_reset
<service-path>
<service-path>
jtag_debug_sense_clock
Avalon-MM Commands
The master service provides commands that allow you to access memory-mapped
slaves via a suitable Avalon-MM master, which can be controlled by the host. You can
use the commands listed in Table 1012 to read and write memory with a master
service.
Master services are provided either by System Console master components such as
the JTAG Avalon Master or the USB Debug Master, by PLI or TCP masters, and by
some processors which typically must be paused before they can be used for general
purpose memory access.
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Using the System Console
SLD Commands
You can use the SLD commands to shift values into the instruction and data registers
of SLD nodes and read the previous value. Table 1012 lists these commands.
EXC or EXCLUSIVE gives read and write access to the specified addresses.
Arguments
Function
<base-address>
<list_of_byte_values>
<service-path>
master_write_8
master_write_16
<base-address>
<list_of_byte_values>
<service-path>
<base-address>
<list_of_16_bit_words>
master_write_from_file
<service-path> <file-name>
<address>
<service-path>
master_write_32
master_read_memory
<base-address>
<list_of_32_bit_words>
<service-path>
<base-address> <size_in_bytes>
<service-path>
master_read_8
<base-address>
<size_in_bytes>
<service-path>
master_read_16
<base-address>
<size_in_multiples_of_
16_bits>
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1019
Arguments
<service-path>
master_read_32
<base-address>
<size_in_multiples_of_32_bits>
<service-path>
<file-name>
master_read_to_file
Function
<address>
<count>
SLD Commands
<service-path>
<ir-value>
sld_access_ir
<delay> (in s)
<service-path>
<size_in_bits>
sld_access_dr
<delay-in-s>,
<list_of_byte_values>
sld_lock
<service-path>
<timeout-in-milliseconds>
sld_unlock
<service-path>
Processor Commands
These commands allow you to start, stop, and step through software running on a
Nios II processor. The commands also allow you to read and write the registers of the
processor. Table 1013 lists the commands.
Table 1013. Processor Commands (Part 1 of 2)
Command
Arguments
Function
elf_download
<processor-service-path>
<master-service-path>
<elf-file-path>
processor_in_debug_mode
<service-path>
processor_reset
<service-path>
processor_run
<service-path>
processor_stop
<service-path>
processor_step
<service-path>
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Using the System Console
Arguments
processor_get_register_nam
<service-path>
es
<service-path>
<register_name>
processor_get_register
<service-path>
<register_name>
processor_set_register
Function
Returns a list with the names of all of the processor's
accessible registers.
Returns the value of the specified register.
<value>
Bytestream Commands
These commands provide access to modules that produce or consume a stream of
bytes. You can use the bytestream service to communicate directly to IP that provides
bytestream interfaces, such as the Altera JTAG UART. Table 1014 lists the commands.
Table 1014. Bytestream Commands
Command
Arguments
<service-path>
bytestream_send
<values>
<service-path>
bytestream_receive
Function
<length>
Marker Commands
These commands provide debugging information. Table 1015 lists the commands.
Table 1015. Marker Commands
Command
Arguments
marker_get_assignments
marker_get_info
marker_get_type
Function
Chapter 10: Analyzing and Debugging Designs with the System Console
Using the System Console
1021
Arguments
Function
Returns a list of the
configurations of the In-System
Sources and Probes instance,
including:
issp_get_instance_info
issp_read_probe_data
issp_read_source_data
issp_write_source_data
<service-path>
instance_index
instance_name
source_width
probe_width
<service-path>
<service-path>
<service-path>
<source-value>
Dashboard Commands
The System Console dashboard allows you to create graphical tools that seamlessly
integrate into the System Console. This section describes how to build your own
dashboard with Tcl commands and the properties that you can assign to the widgets
on your dashboard. The dashboard allows you to create tools that interact with live
instances of an IP core on your device. Table 1017 lists the dashboard Tcl commands
available from the System Console.
Example 101 shows a Tcl command to create a dashboard. Run the Tcl command to
return a path. You can then use the path on the commands listed in Table 1017.
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Chapter 10: Analyzing and Debugging Designs with the System Console
Using the System Console
Arguments
<service-path>
<id>
dashboard_add
Description
Allows you to add a specified
widget to your GUI dashboard.
<type>
<group id>
<service-path>
<id>
dashboard_remove
<service-path>
<id>
dashboard_set_property
<property>
<value>
<service-path>
<id>
dashboard_get_property
<type>
dashboard_get_types
<widget type>
dashboard_get_properties
Specifying Widgets
You can specify the widgets that you add to your dashboard. Table 1018 lists the
widgets.
1
Note that dashboard_add performs a case-sensitive match against the widget type
name.
Description
group
Allows you to add a collection of widgets and control the general layout of
the widgets.
button
tabbedGroup
fileChooserButton
label
text
textField
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1023
Description
list
table
led
dial
timeChart
Allows you to add a chart of historic values, with the X-axis of the chart
representing time.
barChart
checkBox
comboBox
lineChart
pieChart
Example 102 is a Tcl script to instantiate a widget. In this example, the Tcl command
adds a label to the dashboard. The first argument is the path to the dashboard. This
path is returned by the add_service command. The next argument is the ID you
assign to the widget. The ID must be unique within the dashboard. You use this ID
later on to refer to the widget.
Following that argument is the type of widget you are adding, which in this example
is a label. The last argument to this command is the group where you want to put this
widget. In this example, a special keyword self is used. Self refers to the dashboard
itself, the primary group. You can then add a group to self, which allows you to add
other widgets to this group by using the ID of the new group, rather than using the ID
of the self group.
Example 102. Example of Instantiating a Widget
dashboard_add $dash mylabel label self
Customizing Widgets
You can change widget properties at any time. The dashboard_set_property command
allows you to interact with the widgets you instantiate. This functionality is most
useful when you change part of the execution of a callback. Example 103 shows how
to change the text in a label.
In Example 103, the first argument is the path to the dashboard. Next is the unique
ID of the widget, which then allows you to target an arbitrary widget. Following that
is the name of the property. Each type of widget has a defined set of properties,
discussed later. You can change the properties. In this example, mylabel is of the type
label, and the example shows how to set its text property. The last argument is the
value that the property takes when the command is executed.
Example 103. Example of Customizing a Widget
dashboard_set_property $dash mylabel text "Hello World!"
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Using the System Console
Description
enabled
expandable
expandableX
expandableY
Allows the widget to be resized vertically if there's space available in the cell
where it resides.
maxHeight
If the widget's expandableY is set, this is the maximum height in pixels that
the widget can take.
minHeight
If the widget's expandableY is set, this is the minimum height in pixels that
the widget can take.
maxWidth
If the widget's expandableX is set, this is the maximum width in pixels that
the widget can take.
minWidth
If the widget's expandableX is set, this is the minimum width in pixels that
the widget can take.
preferredHeight
preferredWidth
toolTip
A tool tip string that appears once the mouse hovers above the widget.
selected
visible
onChange
Allows for registering a callback function to be called when the value of the
box changes.
options
Description
onClick
A Tcl command to run, usually a proc, every time the button is clicked.
text
Description
text
onChoose
A Tcl command to run, usually a proc, every time the button is clicked.
title
chooserButtonText
The text of file chooser dialog box approval button. By default, it is "Open".
filter
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Using the System Console
1025
Description
Specifies what kind of files or directories can be selected. "files_only", by
default. Possible options are "files_only" and "directories_only".
mode
multiSelectionEnabled
paths
Returns a list of file paths selected in the file chooser dialog box. This
property is read-only. It is most useful when used within the onclick script
or a procedure when the result is freshly updated after the dialog box
closes.
Description
max
min
tickSize
title
value
The value that the dial's needle should mark. It must be between min and
max.
Description
itemsPerRow
The number of widgets the group can position in one row, from left to right,
before moving to the next row.
title
The title of the group. Groups with a title can have a border around them,
and setting an empty title removes the border.
Description
The text to show in the label.
Description
color
The color of the LED. The options are: red_off, red, yellow_off, yellow,
green_off, green, blue_off, blue, and black.
text
Description
editable
htmlCapable
text
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Chapter 10: Analyzing and Debugging Designs with the System Console
Using the System Console
Description
labelX
labelY
latest
maximumItemCount
title
Description
Table-wide Properties
columnCount
rowCount
headerReorderingAllowed
headerResizingAllowed
Controls whether you can resize all column widths. (false, by default). Note,
each column can be individually configured to be resized by using the
columnWidthResizable property.
rowSorterEnabled
Controls whether you can sort the cell values in a column (false, by default).
showGrid
showHorizontalLines
showVerticalLines
rowIndex
Current row index. Zero-based. This value affects some properties below (0,
by default).
columnIndex
Current column index. Zero-based. This value affects all column specific
properties below (0, by default).
cellText
Specifies the text to be filled in the cell specified the current rowIndex and
columnIndex (Empty, by default).
selectedRows
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Description
Column-specific Properties
columnHeader
columnHorizontalAlignment
The cell text alignment in the specified column. Supported types are
"leading"(default), "left", "center", "right", "trailing".
columnRowSorterType
columnWidth
columnWidthResizable
Description
title
Chart title.
labelX
labelY
range
itemValue
Item value. Value is specified in a Tcl list, for example [list bar_category_str
numerical_value].
Description
title
Chart title.
labelX
labelY
range
itemValue
Item value. Value is specified in a Tcl list, for example [list bar_category_str
numerical_value].
Description
title
Chart title.
itemValue
Item value. Value is specified in a Tcl list, for example [list bar_category_str
numerical_value].
f To view all the properties for a widget in the System Console, type:
% dashboard_get_properties <widget_type>r
For example, the System Console returns all the properties for the dial widget when
you type:
%dashboard_get_properties dialr
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Chapter 10: Analyzing and Debugging Designs with the System Console
System Console Examples
The instructions for these examples assume that you are familiar with the Quartus II
software, Tcl commands, and Qsys.
f Download the design files for the example designs from the On-Chip Debugging
Design Examples page on the Altera website.
m
For an online demonstration of how to perform board bring-up using the System
Console, refer to System Console: Faster Board Bring-Up and On-chip Debug on the Altera
website.
Chapter 10: Analyzing and Debugging Designs with the System Console
System Console Examples
1029
Qsys Modules
Figure 104. Qsys Modules For Board Bring-Up Example
The Qsys design for this design example includes the following modules:
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Chapter 10: Analyzing and Debugging Designs with the System Console
System Console Examples
3. Verify the device name in the Project Navigator, Cyclone III: EP3C25, matches
your device. If it does not match, change the pin assignments (LED, clock, and
reset pins) in the Systemconsole_design_example.qsf file.
4. Compile the design. Right-click Compile Design under Task and click Start.
5. Program your device.
a. On the Tools menu, click Programmer.
b. Click Hardware Setup.
c. Click the Hardware Settings tab.
d. Under Currently selected hardware, click USB-Blaster, and click Close.
If you do not see the USB-Blaster option, then your device was not detected.
Verify that the USB-Blaster driver is installed, the NEEK board is powered off,
and the USB-Blaster connecting wire is intact.
This design example has been validated using a USB-Blaster cable. If you do
not have a USB-Blaster cable and you are using a different cable type, then
select your cable from the Currently selected hardware options.
e. Click Auto Detect, select EP3C25 device.
f. Double-click your device under File, browse to your project folder from step 1
and open Systemconsole_design_example.sof.
g. Turn on the Program/Configure option.
h. Click Start.
i. Close the Programmer.
6. Open Qsys. On the Tools menu, click Qsys.
7. Open the Systemconsole_design_example.qsys file in your project folder from
step 1.
It takes about 2 minutes for the design to load.
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System Console Examples
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Chapter 10: Analyzing and Debugging Designs with the System Console
System Console Examples
Chapter 10: Analyzing and Debugging Designs with the System Console
System Console Examples
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Chapter 10: Analyzing and Debugging Designs with the System Console
System Console Examples
1. Pass base address of the memory buffer and data length to the Checksum
Accelerator.
a. Type master_write_32 $master_service_path 0x24 0x80 r
b. Type master_write_32 $master_service_path 0x2C 0x20 r
Chapter 10: Analyzing and Debugging Designs with the System Console
System Console Examples
1035
If the result is zero and the JTAG chain works properly, the clock and reset
signals work properly, and the memory works properly, then the problem is
the Checksum Accelerator component.
6. Confirm if the DONE bit in the status register (bit 0) and interrupt signal are
asserted.
a. Type master_read_32 $master_service_path 0x20 0x1 r
The check DONE bit should return a one.
b. Type master_write_32 $master_service_path 0x38 0x18 r
c. Check the Control Enable to see the interrupt signal. LED 3 (MSB) should be
off. This indicates the interrupt signal is asserted.
You have narrowed down the problem to the data path. View the RTL to check the
data path.
7. Open the Checksum_transform.v file from your project folder.
<unzip
dir>/Debugging_using_SystemConsole/ip/checksum_accelerator/checksum_ac
celerator.v
8. Notice that the data_out signal is grounded, uncommented line 87 and comment
line 88. Fix the problem.
9. Save the file and regenerate the Qsys system.
10. Re-compile the design and reprogram your device.
11. Redo the above steps, starting with Verifying Memory and Other Peripheral
Interfaces on page 1032 or run the Tcl script included with this design example.
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System Console Examples
Chapter 10: Analyzing and Debugging Designs with the System Console
System Console Examples
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Chapter 10: Analyzing and Debugging Designs with the System Console
System Console Examples
6. Using Nios II Software Build Tools for Eclipse, create a new Nios II Application
and BSP from Template using the Count Binary template and targeting the Nios II
Ethernet Standard Design Example.
7. To build the executable and linkable format (ELF) file (.elf) for this application,
right-click the Count Binary project and select Build Project.
Chapter 10: Analyzing and Debugging Designs with the System Console
On-Board USB Blaster II Support
1039
f For more information about creating Nios II applications, refer to the Nios II Software
Build Tools chapter in the Nios II Software Developers Handbook.
8. Download the .elf file to your board by right-clicking Count Binary project and
selecting Run As, Nios II Hardware.
The LEDs on your board provide a new light show.
9. Start the System Console by typing system-console in your Nios II command
shell.
10. Set the processor service path to the Nios II processor by typing the following
command:
set niosii_proc [lindex [get_service_paths processor] 0] r
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Not all Stratix V boards support the On-Board USB-Blaster II. For example,
the transceiver signal integrity board does not support the On-Board
USB-Blaster II.
1040
Chapter 10: Analyzing and Debugging Designs with the System Console
Document Revision History
Version
Changes
June 2013
13.0.0
Updated Tcl command tables. Added board bring-up design example. Removed SOPC
Builder content.
November 2012
12.1.0
Re-organization of content.
August 2012
12.0.1
June 2012
12.0.0
November 2011
11.1.0
May 2011
11.0.0
December 2010
10.1.0
Maintenance release. This chapter adds new commands and references for Qsys.
July 2010
10.0.0
Initial release. Previously released as the System Console User Guide, which is being
obsoleted. This new chapter adds new commands.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
This chapter describes using the Transceiver Toolkit to optimize high-speed serial
links in your board design. The Transceiver Toolkit provides real-time control,
monitoring, and debugging of the transceiver links running on your board.
Quick Start
Get started quickly with the following steps by downloading Transceiver Toolkit
design examples from the On-Chip Debugging Design Examples website.
1. Configuring the System
2. Loading a Design in Transceiver Toolkit
3. Identifying Transceiver Channels
4. Running Link Tests
System Explorerdisplays
the main components and
hardware connections for
your design
Transeiver Toolkitdisplays
Transmitter Channel,
Receiver Channel, and
Transceiver Link control
settings, tests, and results
Messagesdisplays
messages about Transceiver
Toolkit processes
Tcl Consolesupports
scripting control of
Transceiver Toolkit
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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9001:2008
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112
An EyeQ graph displays the receiver horizontal and vertical eye margin during
testing. The toolkit supports testing of multiple devices across one or more boards
simultaneously.
f For more information about the System Console platform that supports Transceiver
Toolkit and PCB bring-up, refer to Analyzing and Debugging Designs with the System
Console in the Quartus II Handbook.
2. Use the Pin Planner to assign device I/O pins to match your device and board.
3. Compile your design with the Quartus II software.
4. Configure your development board correctly.
5. Use the Quartus II Programmer to program the device.
1. Open the Transceiver Toolkit and load your design.
2. Link your design to the hardware you want to test. The toolkit automatically
discovers links between transmitter and receiver of the same channel.
3. (Optional) Create any additional links between transceiver and receiver
channels.
Link
debugging
steps
4. Save actions in a Tcl script to save time. The save feature only saves newly
created channels and links.
5. Run auto sweep tests to determine the best BER with various combinations of
PMA settings. Check Best Case in the Auto Sweep BER report for the best BER
value. Specify the best PMA settings in Transmitter Channels and Receiver
Channels tabs.
6. Use the control panels to select the channel, PMA settings, and test pattern for
the EyeQ test. Rerun EyeQ sweeps with different settings for best performance.
h For more information about design configuration steps in the Quartus II software,
refer to About Qsys, About Assigning Device I/O Pins, About Compilation, and
Programming Devices in Quartus II Help.
113
Control Panels
You can directly control and monitor transmitters, receivers, and links running on the
board in real time. You can transmit a data pattern across the transceiver link, and
then report the signal quality of the received data in terms of bit error rate or eye
margin with EyeQ. Click Control Transmitter, Control Receiver, or Control Link to
adjust transmitter or receiver settings while the channels are running. The Transceiver
Toolkit can automatically identify the transceiver links in your design or you can
identify them manually.
h For more information, refer to Controlling and Monitoring Transceiver Channels and
Control Channel and Control Link Panels in Quartus II Help.
Transceiver EyeQ
The EyeQ graph allows you to visualize the estimated horizontal eye margin at the
receiver. For Stratix V devices, the EyeQ graph also provides information about the
vertical eye margin. The EyeQ graph displays a bathtub curve or eye diagram
representing eye margin. The run list displays the statistics of each EyeQ test. You can
right-click any of the test runs in the list, and then click Apply Settings to Device to
quickly apply that PMA setting to your device. You can also click Export, Import, or
Create Report.
There is an Auto sweep & EyeQ mode that allows you to create EyesQ graphs for
each PMA setup in a sweep.
h For more information, refer to EyeQ Panel (Receiver/Transceiver) in Quartus II Help.
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For an online demonstration of how to use the Transceiver Toolkit to run a high-speed
link test with one of the design examples, refer to the Transceiver Toolkit Online Demo
on the Altera website.
Custom PHY
Function
Implementation Notes
Disable 8B/10B.
115
Function
Avalon-ST Data
Pattern Checker
Reconfiguration
Controller
(Stratix V and
newer devices)
JTAG to Avalon
Master Bridge
Implementation Notes
Connect reconfig_from_xcvr to
reconfig_to_xcvr.
JTAG-to-Avalon
Master Bridge
XCVR
Reconfiguration
Controller
Custom PHY
IP Core
or
Low-Latency
PHY IP Core
Loopback
on board
Avalon-ST Data
Pattern Generator
Avalon-ST Data
Pattern Checker
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116
Transceiver Toolkit
host computer
JTAG-to-Avalon
Master Bridge
XCVR
Reconfiguration
Controller
Avalon-ST Data
Pattern Generator
Loopback
on board
Avalon-ST Data
Pattern Checker
Avalon-ST Data
Pattern Generator
Avalon-ST Data
Pattern Checker
Avalon-ST Data
Pattern Generator
Avalon-ST Data
Pattern Checker
Avalon-ST Data
Pattern Generator
Avalon-ST Data
Pattern Checker
Custom PHY
IP Core
or
Low-Latency
PHY IP Core
Loopback
on board
Loopback
on board
Loopback
on board
117
Figure 114 shows an expanded single channel example design for the Stratix V GX
device.
Figure 114. Expanded Single Channel Example Design For Stratix V GX Device
You can also communicate with other devices that have the capability to generate and
verify test patterns that Altera supports.
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118
Operational Limitations
The following are the hardware based restrictions for the Serial Bit Comparator.
One BER counter per reconfiguration controller. Only one channel can be
monitored at a time if the reconfiguration controller is shared for multiple
channels.
Reconfiguration controller use is limited while BER is running. For example, you
cannot switch logical channels, run DFE one-time, run AEQ one-time, or
recalibrate because it corrupts the error count.
The bit error counter is not read in real-time because it is read through the memory
mapped interface.
h For more information about the Serial Bit Comparator, refer to EyeQ Panel in
Quartus II Help.
h For more information about using Bypass mode, refer to Auto Sweep Panel and Control
Channel and Control Link Panels in Quartus II Help.
119
Prior to the Transceiver Toolkit version 11.1, you must manually load and
link your design to hardware. In version 11.1 and later, the Transceiver
Toolkit automatically links any device programmed with a project.
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1110
1111
When you run link tests, channel color highlights indicate the test status:
h For more information about channel color highlights, refer to About the Transceiver
Toolkit in Quartus II Help.
You can select the link and click different buttons to control link tests. You can use the
transmitter and receiver channels of the same device and loop them back on the far
side of the board trace to check the signal integrity of your high-speed interface on the
board trace, as shown in Figure 113. You can perform a physical link test without
loopback by connecting one device transmitter channel to another device receiver
channel.
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1112
Using DFE
To use the decision feedback equalization (DFE) flow, follow these steps:
1. Use the Auto Sweep flow to find optimal PMA settings while leaving the DFE
setting OFF.
2. If BER = 0, take the best PMA setting achieved.
3. If BER > 0, then use this PMA setting and set minimum and maximum values
obtained from Transceiver Auto Sweep to match this setting. Set the maximum
DFE range to limits for each of the three DFE settings.
4. Run Create Report in the Auto Sweep panel to determine which DFE setting
results in the best BER. Use these settings in conjunction with the PMA settings for
the best results.
h For more information about DFE, refer to Control Channel and Control Link Panels in
Quartus II Help.
1113
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1114
6. Right-click data pattern generator and click Edit. Specify a value for ST_DATA_W
that matches the FPGA-fabric interface width.
7. Right-click data pattern checker and click Edit. Specify a value for ST_DATA_W
that matches the FPGA-fabric interface width.
8. Right-click transceiver configuration controller and click Edit. Specify 2* number
of lanes for the number of reconfigurations interfaces. Click finish.
9. From the Component Library, instantiate the data pattern generator and the data
pattern checker components. The components are under Debug and Performance
under Peripherals. Add one data pattern generator and data pattern checker for
each transmitter and receiver lane.
10. Create connections for the data pattern generator and data pattern checker
components. Right-click the net name in the System Contents tab and specify the
connections listed in Table 112.
Table 112. Data Pattern Generator/Checker Connections
From
To
Block Name
Net Name
Block Name
Net Name
clk_100
clk
data_pattern_generator
csr_clk
clk_100
clk_reset
data_pattern_generator
csr_clk_reset
master_0
master
data_pattern_generator
csr_slave
xcvr_*_phy_0
tx_clk_out0
data_pattern_generator
pattern_out_clk
xcvr_*_phy_0
tx_parallel_data0
data_pattern_generator
pattern_out
clk_100
clk
data_pattern_checker
csr_clk
clk_100
clk_reset
data_pattern_checker
csr_clk_reset
master_0
master
data_pattern_checker
csr_slave
xcvr_*_phy_0
rx_clk_out0
data_pattern_checker
pattern_in_clk
xcvr_*_phy_0
rx_parallel_data0
data_pattern_checker
pattern_in
1115
14. If you modify the number of lanes in the PHY, you must update the top-level file
accordingly. Example 111 shows Verilog HDL code for a 2 channel design where
input and output ports are declared in the top-level design.
Example 111. I/O Declared in Top-level Two-channel Verilog HDL design
module low_latency_10g_1ch DUT (
input wire GXB_RXL11,
input wire GXB_RXL12,
output wire GXB_TXL11,
output wire GXB_TX12
);
.....
low_latency_10g_1ch DUT (
.....
.xcvr_low_latency_phy_0_tx_serial_data_export({GXB_TXL11,
GXB_TXL12}),
.xcvr_low_latency_phy_0_rx_serial_data_export({GXB_RXL11,
GXB_TXL12}),
.....
);
The example design includes the low latency PHY IP core. If you modify the PHY
parameters, you must modify the top-level design with the correct port names.
Qsys displays an example of the PHY in the design on the HDL example tab.
15. Use the Pin Planner to update pin assignments to match your board, as described
in Updating I/O Pin Assignments.
16. Edit the designs Synopsys Design Constraints (.sdc) to reflect the reference clock
change. Ignore the reset warning messages.
17. Recompile the design.
I/O Standard
Location
GXB_RXL11(input)
1.4-V PCML
PIN_AA36
GXB_TXL11 (output)
1.4-V PCML
PIN_Y34
REFCLK_C70625mhz
LVDS
PIN_U31
SVGX_C100mhz
LVDS
PIN_AV7
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1116
Table 114 shows the pin-assignment edits for the Stratix IV Transceiver Signal
Integrity Development Kit (DK-SI-4SGX230N). You must make these assignments
before you recompile your design.
Table 114. Stratix IV GX Top-Level Pin Assignments (DK-SI-4SGX230N)
Top-Level Signal Name
I/O Standard
Pin Number on
DK-SI-4SGX230N Board
REFCLK_GXB2_156M25 (input)
2.5 V LVTTL/LVCMOS
PIN_G38
S4GX_50M_CLK4P (input)
2.5 V LVTTL/LVCMOS
PIN_AR22
GXB1_RX1 (input)
1.4-V PCML
PIN_R38
GXB1_TX1 (output)
1.4-V PCML
PIN_P36
Table 115 shows pin assignments for the Stratix IV GX development kit
(DK-DEV-4SGX230N). You must make these assignments before you recompile your
design.
Table 115. Stratix IV GX Top-Level Pin Assignments (DK-DEV-4SGX230N)
Top-Level Signal Name
I/O Standard
Pin Number on
DK-DEV-4SGX230N Board
REFCLK_GXB2_156M25 (input)
LVDS
PIN_AA2
S4GX_50M_CLK4P (input)
2.5 V LVTTL/LVCMOS
PIN_AC34
GXB1_RX1 (input)
1.4-V PCML
PIN_AU2
GXB1_TX1 (output)
1.4-V PCML
PIN_AT4
f For more information about other development kits, read the readme.txt file
accompanying the design examples. For more information about the pinouts refer to
the corresponding reference manual on the Development Kits page of the Altera
website.
1117
m_pathname of a variable.
Table 116 through Table 1115 lists the Transceiver Toolkit commands.
Table 116. Transceiver Toolkit Channel_rx Commands (Part 1 of 3)
Command
Arguments
Function
transceiver_channel_rx_get_data
<service-path>
transceiver_channel_rx_get_dcgain
<service-path>
transceiver_channel_rx_get_dfe_tap_value
<service-path>
<tap position>
transceiver_channel_rx_get_eqctrl
<service-path>
transceiver_channel_rx_get_pattern
<service-path>
transceiver_channel_rx_has_dfe
<service-path>
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Arguments
Function
transceiver_channel_rx_has_eyeq
<service-path>
transceiver_channel_rx_is_checking
<service-path>
transceiver_channel_rx_is_dfe_enabled
<service-path>
transceiver_channel_rx_is_locked
<service-path>
transceiver_channel_rx_reset_counters
<service-path>
transceiver_channel_rx_reset
<service-path>
transceiver_channel_rx_set_dcgain
<service-path>
<value>
transceiver_channel_rx_set_dfe_enabled
transceiver_channel_rx_set_dfe_tap_value
<service-path>
<tap position>
<tap value>
transceiver_channel_rx_set_dfe_adaptive
<service-path>
transceiver_channel_rx_set_eqctrl
<service-path>
<value>
transceiver_channel_rx_start_checking
<service-path>
transceiver_channel_rx_stop_checking
<service-path>
transceiver_channel_rx_get_eyeq_phase_step
<service-path>
transceiver_channel_rx_set_pattern
<service-path>
<pattern-name>
transceiver_channel_rx_has_eyeq
<service-path>
transceiver_channel_rx_is_eyeq_enabled
<service-path>
transceiver_channel_rx_set_eyeq_enabled
transceiver_channel_rx_set_eyeq_phase_step
<service-path>
<phase step>
transceiver_channel_rx_set_word_aligner_enabled
<service-path>
Enables or disables the word
<disable(0)/enable(1)> aligner of the specified channel.
1119
Arguments
Function
transceiver_channel_rx_is_word_aligner_enabled
transceiver_channel_rx_is_locked
<service-path>
transceiver_channel_rx_is_rx_locked_to_data
<service-path>
transceiver_channel_rx_is_rx_locked_to_ref
<service-path>
transceiver_channel_rx_has_eyeq_1d
<service-path>
transceiver_channel_rx_set_1deye_mode
<service-path>
Enables or disables 1D-EyeQ
<disable(0)/enable(1)> mode.
transceiver_channel_rx_get_1deye_mode
<service-path>
Arguments
Function
transceiver_channel_tx_disable_preamble
<service-path>
transceiver_channel_tx_enable_preamble
<service-path>
transceiver_channel_tx_get_number_of_preamble_bea
ts
<service-path>
transceiver_channel_tx_get_pattern
<service-path>
transceiver_channel_tx_get_preamble_word
<service-path>
transceiver_channel_tx_get_preemph0t
<service-path>
transceiver_channel_tx_get_preemph1t
<service-path>
transceiver_channel_tx_get_preemph2t
<service-path>
transceiver_channel_tx_get_vodctrl
<service-path>
transceiver_channel_tx_inject_error
<service-path>
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1120
Arguments
Function
transceiver_channel_tx_is_generating
<service-path>
transceiver_channel_tx_is_preamble_enabled
<service-path>
transceiver_channel_tx_set_number_of_preamble_bea
ts
<service-path>
Sets the number of beats to
<number-of-preamblesend out the preamble word.
beats>
transceiver_channel_tx_set_pattern
<service-path>
<pattern-name>
transceiver_channel_tx_set_preamble_word
<service-path>
<preamble-word>
<service-path>
transceiver_channel_tx_set_preemph0t
transceiver_channel_tx_set_preemph1t
transceiver_channel_tx_set_preemph2t
<preemph0t value>
<service-path>
<preemph1t value>
<service-path>
<preemph2t value>
<service-path>
<vodctrl value>
transceiver_channel_tx_start_generation
<service-path>
transceiver_channel_tx_stop_generation
<service-path>
transceiver_channel_tx_set_vodctrl
Arguments
Function
transceiver_debug_link_get_pattern
<service-path>
transceiver_debug_link_is_running
<service-path>
transceiver_debug_link_set_pattern
<service-path>
<data pattern>
transceiver_debug_link_start_running
<service-path>
transceiver_debug_link_stop_running
<service-path>
1121
transceiver_reconfig_analog_get_rx_dcgain
transceiver_reconfig_analog_get_rx_eqctrl
transceiver_reconfig_analog_get_tx_preemph0t
transceiver_reconfig_analog_get_tx_preemph1t
transceiver_reconfig_analog_get_tx_preemph2t
transceiver_reconfig_analog_get_tx_vodctrl
transceiver_reconfig_analog_set_logical_channel_
address
transceiver_reconfig_analog_set_rx_dcgain
transceiver_reconfig_analog_set_rx_eqctrl
transceiver_reconfig_analog_set_tx_preemph0t
transceiver_reconfig_analog_set_tx_preemph1t
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Altera Corporation
Arguments
Function
<service-path>
<service-path>
<service-path>
<service-path>
<service-path>
<service-path>
<service-path>
<service-path>
<logical channel
address>
<service-path>
<dc_gain value>
<service-path>
<eqctrl value>
<service-path>
<preemph0t value>
<service-path>
<preemph1t value>
1122
transceiver_reconfig_analog_set_tx_preemph2t
transceiver_reconfig_analog_set_tx_vodctrl
Arguments
<service-path>
<preemph2t value>
<service-path>
<vodctrl value>
Function
Sets the pre-emphasis second
post-tap value on the
transmitter channel specified
by the current logical channel
address.
Sets the VOD control value on
the transmitter channel
specified by the current logical
channel address.
Arguments
Function
<service-path>
alt_xcvr_reconfig_dfe_is_enabled
<service-path>
alt_xcvr_reconfig_dfe_set_enabled
alt_xcvr_reconfig_dfe_set_logical_channel_address
<service-path>
<logical channel
address>
alt_xcvr_reconfig_dfe_set_tap_value
<service-path>
<tap position>
<tap value>
alt_xcvr_reconfig_dfe_get_logical_channel_address
Arguments
Function
alt_xcvr_custom_set_word_aligner_enabled
alt_xcvr_custom_is_rx_locked_to_data
<service-path>
alt_xcvr_custom_is_rx_locked_to_ref
<service-path>
1123
Arguments
Function
Returns whether the serial
loopback mode of the
previously specified channel is
enabled.
alt_xcvr_custom_is_serial_loopback_enabled
<service-path>
alt_xcvr_custom_set_serial_loopback_enabled
alt_xcvr_custom_is_tx_pll_locked
<service-path>
alt_xcvr_reconfig_eye_viewer_get_logical_channel_
address
<service-path>
alt_xcvr_reconfig_eye_viewer_get_phase_step
<service-path>
alt_xcvr_reconfig_eye_viewer_is_enabled
<service-path>
alt_xcvr_reconfig_eye_viewer_set_enabled
<service-path>
<disable(0)/enable(1)> Setting a value of 2 enables
both EyeQ and the Serial Bit
Comparator.
alt_xcvr_reconfig_eye_viewer_set_logical_channel_
address
<service-path>
<logical channel
address>
alt_xcvr_reconfig_eye_viewer_set_phase_step
<service-path>
<phase step>
alt_xcvr_reconfig_eye_viewer_has_ber_checker
<service-path>
alt_xcvr_reconfig_eye_viewer_ber_checker_is_enabl
ed
<service-path>
alt_xcvr_reconfig_eye_viewer_ber_checker_start
<service-path>
alt_xcvr_reconfig_eye_viewer_ber_checker_stop
<service-path>
alt_xcvr_reconfig_eye_viewer_ber_checker_reset_co
unters
<service-path>
alt_xcvr_reconfig_eye_viewer_ber_checker_is_runni
ng
<service-path>
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1124
Arguments
Function
alt_xcvr_reconfig_eye_viewer_ber_checker_get_data
<service-path>
alt_xcvr_reconfig_eye_viewer_has_1deye
<service-path>
alt_xcvr_reconfig_eye_viewer_set_1deye_mode
alt_xcvr_reconfig_eye_viewer_get_1deye_mode
<service-path>
<disable(0)/enable(1)
<service-path>
Arguments
<service-path>
get_channel_type
<logical-channel-num
>
<service-path>
set_channel_type
<logical-channel-num
>
<channel-type>
Function
Reports the detected type
(GX/GT) of channel
<logical-channel-num> for the
reconfiguration block located at
<service-path>.
Overrides the detected channel
type of channel
<logical-channel-num> for the
reconfiguration block located at
<service-path> to the type
specified (0:GX, 1:GT).
1125
Arguments
Function
Returns the value of a setting
or result on the loopback
channel. Available results
include:
Statusrunning or
stopped.
Bytesnumber of bytes
sent through the loopback
channel.
Errorsnumber of errors
reported by the loopback
channel.
Secondsnumber of
seconds since the loopback
channel was started.
<service-path>
loopback_get
<service-path>
loopback_set
Timernumber of seconds
for the test run.
loopback_start
<service-path>
loopback_stop
<service-path>
Arguments
Function
data_pattern_generator_start
<service-path>
data_pattern_generator_stop
<service-path>
data_pattern_generator_is_generating
<service-path>
data_pattern_generator_inject_error
<service-path>
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1126
Arguments
Function
Sets the output pattern specified by
the <pattern-name>. In all, 6 patterns
are available, 4 are pseudo-random
binary sequences (PRBS), 1 is high
frequency and 1 is low frequency.
data_pattern_generator_set_pattern
<service-path>
<pattern-name>
data_pattern_generator_get_pattern
<service-path>
data_pattern_generator_get_available_patter
ns
<service-path>
data_pattern_generator_enable_preamble
<service-path>
data_pattern_generator_disable_preamble
<service-path>
data_pattern_generator_is_preamble_enabled
<service-path>
data_pattern_generator_set_preamble_word
<service-path>
<preamble-word>
data_pattern_generator_get_preamble_word
<service-path>
data_pattern_generator_set_preamble_beats
<service-path>
<number-of-preamblebeats>
data_pattern_generator_get_preamble_beats
<service-path>
data_pattern_generator_fcnter_start
data_pattern_generator_check_status
data_pattern_generator_fcnter_report
<service-path>
<max-cycles>
<service-path>
<service-path>
<force-stop>
1127
Arguments
Function
data_pattern_checker_start
<service-path>
data_pattern_checker_stop
<service-path>
<service-path>
<service-path>
<service-path>
<pattern-name>
<service-path>
<service-path>
<service-path>
<service-path>
data_pattern_checker_is_checking
data_pattern_checker_is_locked
data_pattern_checker_set_pattern
data_pattern_checker_get_pattern
data_pattern_checker_get_available_patt
erns
data_pattern_checker_get_data
data_pattern_checker_reset_counters
data_pattern_checker_fcnter_start
<service-path>
<max-cycles>
data_pattern_checker_check_status
<service-path>
data_pattern_checker_fcnter_report
<service-path>
<force-stop>
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1128
Version
Changes
May 2013
13.0.0
Added Conduit Mode Support on page 117, Serial Bit Comparator on page 118,
Example 112, Required Files for Running the Transceiver Toolkit on page 114, and
Tcl command tables.
November 2012
12.1.0
Minor editorial updates. Added Tcl help information and removed Tcl command tables.
Added 28-Gbps Transceiver support section. Added Figure 11-4.
August, 2012
12.0.1
June, 2012
12.0.0
November, 2011
11.1.0
May, 2011
11.0.0
December 2010
10.1.0
August 2010
10.0.1
Corrected links
July 2010
10.0.0
Initial release
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
This chapter provides detailed instructions about how to use SignalProbe to quickly
debug your design. The SignalProbe incremental routing feature helps reduce the
hardware verification process and time-to-market for
system-on-a-programmable-chip (SOPC) designs.
Easy access to internal device signals is important in the design or debugging process.
The SignalProbe feature makes design verification more efficient by routing internal
signals to I/O pins quickly without affecting the design. When you start with a fully
routed design, you can select and route signals for debugging to either previously
reserved or currently unused I/O pins.
The SignalProbe feature supports the Arria series, Cyclone series, MAX II, and
Stratix series, device families.
f The Quartus II software provides a portfolio of on-chip debugging tools. For an
overview and comparison of all the tools available in the Quartus II software, refer to
Section IV. System Debugging Tools in volume 3 of the Quartus II Handbook.
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Feedback Subscribe
122
Although you can reserve SignalProbe pins using many features within the Quartus II
software, including the Pin Planner and the Tcl interface, you should use the
SignalProbe Pins dialog box to create and edit your SignalProbe pins.
h For more information, refer to SignalProbe Pins Dialog Box and Add SignalProbe Pins
Dialog Box in Quartus II Help.
Because SignalProbe pins are implemented and routed as ECOs, turning the
SignalProbe enable option on or off is the same as selecting Apply Selected Change
or Restore Selected Change in the Change Manager window. (If the Change Manager
window is not visible at the bottom of your screen, on the View menu, point to Utility
Windows and click Change Manager.)
f For more information about the Change Manager for the Chip Planner and Resource
Property Editor, refer to the Engineering Change Management with the Chip Planner
chapter in volume 2 of the Quartus II Handbook.
123
When you add a register to a SignalProbe pin, the SignalProbe compilation attempts
to place the register to best meet timing requirements. You can place SignalProbe
registers either near the SignalProbe source to meet fMAX requirements, or near the
I/O to meet tCO requirements.
Figure 121. Synchronizing SignalProbe Outputs with a SignalProbe Register
Reg_a_2
Reg_a_1
DFF
DFF
Logic
Logic
Reg_b_1
Reg_b_2
DFF
DFF
Logic
Logic
SignalProbe_Output_1
SignalProbe_Output_2
SignalProbe
Pipeline
Register
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124
f For more information about how to use the Change Manager, refer to the Engineering
Change Management with the Chip Planner chapter in volume 2 of the Quartus II
Handbook.
To view the timing results of each successfully routed SignalProbe pin, on the
Processing menu, point to Start and click Start Timing Analysis.
To run the SignalProbe compilation immediately after a full compilation, on the Tools
menu, click SignalProbe Pins. In the SignalProbe Pins dialog box, click Start Check
& Save All Netlist Changes.
To run a SignalProbe compilation manually after a full compilation, on the Processing
menu, point to Start and click Start SignalProbe Compilation.
1
You must run the Fitter before a SignalProbe compilation. The Fitter generates a list of
all internal nodes that can serve as SignalProbe sources.
Turn the SignalProbe enable option on or off in the SignalProbe Pins dialog box to
enable or disable each SignalProbe pin.
125
Description
Routed
Not Routed
Not enabled
Failed to Route
Need to Compile
Figure 123. SignalProbe Fitting Results Page in the Compilation Report Window
The SignalProbe source to output delays screen in the Timing Analysis section of the
Compilation Report displays the timing results of each successfully routed
SignalProbe pin (Figure 124).
Figure 124. SignalProbe Source to Output Delays Page in the Compilation Report Window
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126
After a SignalProbe compilation, the processing screen of the Messages window also
provides the results for each SignalProbe pin and displays slack information for each
successfully routed SignalProbe pin.
Routing failures can occur if the SignalProbe pins I/O standard conflicts with other
I/O standards in the same I/O bank.
If routing congestion prevents a successful SignalProbe compilation, you can allow
the compiler to modify routing to the specified SignalProbe source. On the Tools
menu, click SignalProbe Pins and turn on Modify latest fitting results during
SignalProbe compilation. This setting allows the Fitter to modify existing routing
channels used by your design.
1
Turning on Modify latest fitting results during SignalProbe compilation can change
the performance of your design.
Scripting Support
You can also run some procedures at a command prompt. For detailed information
about scripting command options, refer to the Quartus II command-line and Tcl API
Help browser. To run the Help browser, type the following command at the command
prompt:
quartus_sh --qhelp r
The Tcl commands in this section are part of the ::quartus::chip_planner Quartus II
Tcl API. Source or include the ::quartus::chip_planner Tcl package in your scripts
to make these commands available.
f For more information about Tcl scripting, refer to the Tcl Scripting chapter in volume 2
of the Quartus II Handbook. For more information about all settings and constraints in
the Quartus II software, refer to the Quartus II Settings File Reference Manual. For more
information about command-line scripting, refer to the Command-Line Scripting
chapter in volume 2 of the Quartus II Handbook.
127
Script Example
Example 121 shows a script that creates a SignalProbe pin called sp1 and connects
the sp1 pin to source node reg1 in a project that was already compiled.
Example 121. Creating a SignalProbe Pin Called sp1
package require ::quartus::chip_planner
project_open project
read_netlist
make_sp -pin_name sp1 -src_name reg1
check_netlist_and_save
project_close
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128
You have the Quartus II Web Edition software, in which the SignalProbe feature is
not enabled by default. You must turn on TalkBack to enable the SignalProbe
feature in the Quartus II Web Edition software.
You have not set the pin reserve type to As Signal Probe Output. To reserve a pin,
on the Assignments menu, in the Assign Pins dialog box, select As SignalProbe
Output.
The pin does not support the SignalProbe feature. Select another pin.
The current device family does not support the SignalProbe feature.
The next command turns on SignalProbe routing. To turn off individual SignalProbe
pins, specify OFF instead of ON with the following command:
set_instance_assignment -name SIGNALPROBE_ENABLE ON -to \
<SignalProbe pin name>
h For more information about adding SignalProbe sources, refer to SignalProbe Pins
Dialog Box and Add SignalProbe Pins Dialog Box in Quartus II Help.
h For a list of valid I/O standards, refer I/O Standards to the in the Quartus II Help.
129
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1210
Version
May 2013
13.0.0
Changes
Changed sequence of flow to clarify that you need to perform a full compilation before
reserving SignalProbe pins. Affected sections are Debugging Using the SignalProbe
Feature on page 121 and Reserving SignalProbe Pins on page 122. Moved
Performing a Full Compilation on page 122 before Reserving SignalProbe Pins on
page 122.
June 2012
12.0.0
November 2011
10.0.2
Template update.
December 2010
10.0.1
July 2010
10.0.0
November 2009
March 2009
9.0.0
November 2008
May 2008
9.1.0
8.1.0
Removed support for SignalProbe pin preservation when recompiling with incremental
compilation turned on.
Style changes.
Added plausible scenarios where SignalProbe connections are not reserved in the
design
Removed the On-Chip Debugging Tool Comparison and replaced with a reference to
the Section V Overview on page 131
8.0.0
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
Altera provides the SignalTap II Logic Analyzer to help with the process of design
debugging. This logic analyzer is a solution that allows you to examine the behavior
of internal signals, without using extra I/O pins, while the design is running at full
speed on an FPGA device.
The SignalTap II Logic Analyzer is scalable, easy to use, and is available as a
stand-alone package or included with the Quartus II software subscription. This
logic analyzer helps debug an FPGA design by probing the state of the internal
signals in the design without the use of external equipment. Defining custom
trigger-condition logic provides greater accuracy and improves the ability to isolate
problems. The SignalTap II Logic Analyzer does not require external probes or
changes to the design files to capture the state of the internal nodes or I/O pins in the
design. All captured signal data is conveniently stored in device memory until you
are ready to read and analyze the data.
The topics in this chapter include:
2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
Feedback Subscribe
132
(1)
FPGA Device
Design Logic
SignalTap II
Instances
JTAG
Hub
Altera
Programming
Hardware
Quartus II
Software
This chapter is intended for any designer who wants to debug an FPGA design
during normal device operation without the need for external lab equipment. Because
the SignalTap II Logic Analyzer is similar to traditional external logic analyzers,
familiarity with external logic analyzer operations is helpful, but not necessary. To
take advantage of faster compile times when making changes to the SignalTap II
Logic Analyzer, knowledge of the Quartus II incremental compilation feature is
helpful.
f For information about using the Quartus II incremental compilation feature, refer to
the Quartus II Incremental Compilation for Hierarchical and Team-Based Design chapter in
volume 1 of the Quartus II Handbook.
133
Download/upload cable
Altera development kit or your design board with JTAG connection to device
under test
1
The Quartus II software Web Edition does not support the SignalTap II
Logic Analyzer with the incremental compilation feature.
The memory blocks of the device store captured data and transfers the data to the
Quartus II software waveform display with a JTAG communication cable, such as
EthernetBlaster or USB-BlasterTM. Table 131 summarizes features and benefits of the
SignalTap II Logic Analyzer.
Table 131. SignalTap II Logic Analyzer Features and Benefits (Part 1 of 2)
Feature
Benefit
Captures data from multiple clock domains in a design at the same time.
Plug-In Support
Easily specifies nodes, triggers, and signal mnemonics for IP, such as the
Nios II processor.
Power-Up Trigger
Captures signal data for triggers that occur after device programming, but
before manually starting the logic analyzer.
Incremental compilation
The buffer acquisition control allows you to precisely control the data that is
written into the acquisition buffer. Both segmented buffers and
non-segmented buffers with storage qualification allow you to discard data
samples that are not relevant to the debugging of your design.
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134
Benefit
Synchronous sampling of data nodes using the same clock tree driving the
logic under test.
No additional cost
You can use the SignalTap II Logic Analyzer in tandem with any JTAG-based
on-chip debugging tool, such as an In-System Memory Content editor,
allowing you to change signal values in real-time while you are running an
analysis with the SignalTap II Logic Analyzer.
135
Verilog
HDL
(.v)
VHDL
(.vhd)
Block
Design File
(.bdf)
AHDL
(.tdf)
EDIF
Netlist
(.edf)
VQM
Netlist
(.vqm)
Fitter
Place-and-Route
Assembler
Timing Analyzer
Configuration
No
Functionality
Satisfied?
Yes
End
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136
Configure
SignalTap II Logic Analyzer
Define Triggers
Yes
Compile Design
Recompilation
Necessary?
No
Program Target
Device or Devices
Adjust Options,
Triggers, or both
Run SignalTap II
Logic Analyzer
Continue Debugging
Functionality
Satisfied or Bug
Fixed?
No
Yes
End
137
The SignalTap II Logic Analyzer supports all current Altera FPGA device families
including Arria, Cyclone, HardCopy, and Stratix devices.
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138
139
Table 132 shows the SignalTap II Logic Analyzer M4K memory block resource usage
for the listed devices per signal width and sample depth.
Table 132. SignalTap II Logic Analyzer M4K Block Utilization (1)
Samples (Depth)
Signals (Width)
256
512
2,048
8,192
<1
16
16
32
32
16
64
64
32
128
256
16
32
128
512
The State-based trigger flow, the state machine debugging feature, and the storage
qualification feature are not supported when using the MegaWizard Plug-In Manager
to create the logic analyzer. These features are described in the following sections:
h For information about creating a SignalTap II instance with the MegaWizard Plug-In
Manager, refer to Setting Up the SignalTap II Logic Analyzer in Quartus II Help.
May 2013
Some settings can only be adjusted when you are viewing Run-Time Trigger
conditions instead of Power-Up Trigger conditions. To learn about Power-Up Triggers
and viewing different trigger conditions, refer to Creating a Power-Up Trigger on
page 1341.
Altera Corporation
1310
Altera recommends that you exercise caution when using a recovered clock from a
transceiver as an acquisition clock for the SignalTap II Logic Analyzer. Incorrect or
unexpected behavior has been noted, particularly when a recovered clock from a
transceiver is used as an acquisition clock with the power-up trigger feature.
If you do not assign an acquisition clock in the SignalTap II Logic Analyzer Editor, the
Quartus II software automatically creates a clock pin called auto_stp_external_clk.
You must make a pin assignment to this pin independently from the design. Ensure
that a clock signal in your design drives the acquisition clock.
f For information about assigning signals to pins, refer to the I/O Management chapter in
volume 2 of the Quartus II Handbook.
If you are not using incremental compilation, add only pre-synthesis signals to the
.stp. Using pre-synthesis helps when you want to add a new node after you change a
design. Source file changes appear in the Node Finder after you perform an Analysis
and Elaboration. On the Processing Menu, point to Start and click Start Analysis &
Elaboration.
1311
The Quartus II software does not limit the number of signals available for monitoring
in the SignalTap II window waveform display. However, the number of channels
available is directly proportional to the number of logic elements (LEs) or adaptive
logic modules (ALMs) in the device. Therefore, there is a physical restriction on the
number of channels that are available for monitoring. Signals shown in blue text are
post-fit node names. Signals shown in black text are pre-synthesis node names.
After successful Analysis and Elaboration, invalid signals are displayed in red. Unless
you are certain that these signals are valid, remove them from the .stp for correct
operation. The SignalTap II Status Indicator also indicates if an invalid node name
exists in the .stp.
You can tap signals if a routing resource (row or column interconnects) exists to route
the connection to the SignalTap II instance. For example, signals that exist in the I/O
element (IOE) cannot be directly tapped because there are no direct routing resources
from the signal in an IOE to a core logic element. For input pins, you can tap the signal
that is driving a logic array block (LAB) from an IOE, or, for output pins, you can tap
the signal from the LAB that is driving an IOE.
When adding pre-synthesis signals, make all connections to the SignalTap II Logic
Analyzer before synthesis. Logic and routing resources are allocated during
recompilation to make the connection as if a change in your design files had been
made. Pre-synthesis signal names for signals driving to and from IOEs coincide with
the signal names assigned to the pin.
In the case of post-fit signals, connections that you make to the SignalTap II Logic
Analyzer are the signal names from the actual atoms in your post-fit netlist. You can
only make a connection if the signals are part of the existing post-fit netlist and
existing routing resources are available from the signal of interest to the SignalTap II
Logic Analyzer. In the case of post-fit output signals, tap the COMBOUT or REGOUT signal
that drives the IOE block. For post-fit input signals, signals driving into the core logic
coincide with the signal name assigned to the pin.
1
Because NOT-gate push back applies to any register that you tap, the signal from the
atom may be inverted. You can check this by locating the signal in either the Resource
Property Editor or the Technology Map Viewer. The Technology Map viewer and the
Resource Property Editor can also be used to help you find post-fit node names.
f For information about cross-probing to source design files and other Quartus II
windows, refer to the Analyzing Designs with Quartus II Netlist Viewers chapter in
volume 1 of the Quartus II Handbook.
For more information about the use of incremental compilation with the SignalTap II
Logic Analyzer, refer to Faster Compilations with Quartus II Incremental
Compilation on page 1344.
Signal Preservation
Many of the RTL signals are optimized during the process of synthesis and
place-and-route. RTL signal names frequently may not appear in the post-fit netlist
after optimizations. For example, the compilation process can add tildes (~) to nets
that fan-out from a node, making it difficult to decipher which signal nets they
actually represent. These process results can cause problems when you use the
incremental compilation flow with the SignalTap II Logic Analyzer. Because you can
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1312
only add post-fitting signals to the SignalTap II Logic Analyzer in partitions of type
post-fit, RTL signals that you want to monitor may not be available, preventing their
use. To avoid this issue, use synthesis attributes to preserve signals during synthesis
and place-and-route. When the Quartus II software encounters these synthesis
attributes, it does not perform any optimization on the specified signals, forcing them
to continue to exist in the post-fit netlist. However, if you do this, you could see an
increase in resource utilization or a decrease in timing performance. The two
attributes you can use are:
f For more information about using these attributes, refer to the Quartus II Integrated
Synthesis chapter in volume 1 of the Quartus II Handbook.
If you are debugging an IP core, such as the Nios II CPU or other encrypted IP, you
might need to preserve nodes from the core to make them available for debugging
with the SignalTap II Logic Analyzer. Preserving nodes is often necessary when a
plug-in is used to add a group of signals for a particular IP.
If you use incremental compilation flow with the SignalTap II Logic Analyzer,
pre-synthesis nodes may not be connected to the SignalTap II Logic Analyzer if the
affected partition is of the post-fit type. A critical warning is issued for all presynthesis node names that are not found in the post-fit netlist.
h For more information about node preservation or how to avoiding these warnings,
refer to Working with Nodes in the SignalTap II Logic Analyzer in Quartus II Help.
1313
Untappable Signals
Not all of the post-fitting signals in your design are available in the SignalTap II :
post-fitting filter in the Node Finder dialog box. The following signal types cannot be
tapped:
Post-fit output pinsYou cannot tap a post-fit output pin directly. To make an
output signal visible, tap the register or buffer that drives the output pin. This
includes pins defined as bidirectional.
Signals that are part of a carry chainYou cannot tap the carry out (cout0 or
cout1) signal of a logic element. Due to architectural restrictions, the carry out
signal can only feed the carry in of another LE.
JTAG SignalsYou cannot tap the JTAG control (TCK, TDI, TDO, and TMS) signals.
DQ, DQS SignalsYou cannot directly tap the DQ or DQS signals in a DDR/DDRII
design.
Nios II Instruction (Setup tab)Capture all the required signals for triggering on
a selected instruction address.
For information about the other features plug-ins provide, refer to Define Triggers
on page 1326 and View, Analyze, and Use Captured Data on page 1354.
To add signals to the .stp using a plug-in, perform the following steps after running
Analysis and Elaboration on your design:
1. Right-click in the node list. On the Add Nodes with Plug-In submenu, choose the
plug-in you want to use, such as the included plug-in named Nios II.
1
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If the IP for the selected plug-in does not exist in your design, a message
informs you that you cannot use the selected plug-in.
1314
2. The Select Hierarchy Level dialog box appears showing the IP hierarchy of your
design. Select the IP that contains the signals you want to monitor with the plug-in
and click OK.
3. If all the signals in the plug-in are available, a dialog box might appear, depending
on the plug-in selected, where you can specify options for the plug-in. With the
Nios II plug-in, you can optionally select an .elf containing program symbols from
your Nios II Integrated Development Environment (IDE) software design. Specify
options for the selected plug-in as desired and click OK.
1
To make sure all the required signals are available, in the Quartus II Analysis &
Synthesis settings, turn on Create debugging nodes for IP cores.
All the signals included in the plug-in are added to the node list.
f For coding guidelines for specifying FSM in Verilog and VHDL, refer to the
Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook.
h For information about adding FSM signals to the configuration file, refer to Setting Up
the SignalTap II Logic Analyzer in Quartus II Help.
1315
If you have added or deleted a signal from the FSM state signal group from within the
setup tab, delete the modified register group and add the FSM signals back again.
For more information about using Mnemonics, refer to Creating Mnemonics for Bit
Patterns on page 1358.
Additional Considerations
The SignalTap II configuration GUI recognizes state machines from your design only
if you use Quartus II Integrated Synthesis (QIS). The state machine debugging feature
is not able to track the FSM signals or state encoding if you use other EDA synthesis
tools.
If you add post-fit FSM signals, the SignalTap II Logic Analyzer FSM debug feature
may not track all optimization changes that are a part of the compilation process. If
the following two specific optimizations are enabled, the SignalTap II FSM debug
feature may not list mnemonic tables for state machines in the design:
If you have physical synthesis turned on, state registers may be resource balanced
(register retiming) to improve fMAX. The FSM debug feature does not list post-fit
FSM state registers if register retiming occurs.
The FSM debugging feature does not list state signals that have been packed into
RAM and DSP blocks during QIS or Fitter optimizations.
You can still use the FSM debugging feature to add pre-synthesis state signals.
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1316
(1), (2)
Center Trigger
Pre-Trigger
Newly
Captured
Data
Oldest Data
Removed
1
All
Trigger Level
Segment
Trigger Level
...
Segment 1
Segment
Trigger Level
...
Segment 2
Segment
Trigger Level
...
Segment 3
...
Segment 4
1317
(1), (2)
For more information about the storage qualification feature, refer to Using the
Storage Qualifier Feature on page 1318.
Non-Segmented Buffer
The non-segmented buffer (also known as a circular buffer) shown in Figure 135 (a)
is the default buffer type used by the SignalTap II Logic Analyzer. While the logic
analyzer is running, data is stored in the buffer until it fills up, at which point new
data replaces the oldest data. This continues until a specified trigger event, consisting
of a set of trigger conditions, occurs. When the trigger event happens, the logic
analyzer continues to capture data after the trigger event until the buffer is full, based
on the trigger position setting in the Signal Configuration pane in the .stp. To capture
the majority of the data before the trigger occurs, select Post trigger position from the
list. To capture the majority of the data after the trigger, select Pre-trigger position. To
center the trigger position in the data, select Center trigger position. Alternatively,
use the custom State-based triggering flow to define a custom trigger position within
the capture buffer.
For more information, refer to Specifying the Trigger Position on page 1341.
Segmented Buffer
A segmented buffer allows you to debug systems that contain relatively infrequent
recurring events. The acquisition memory is split into evenly sized segments, with a
set of trigger conditions defined for each segment. Each segment acts as a nonsegmented buffer. If you want to have separate trigger conditions for each of the
segmented buffers, you must use the state-based trigger flow. Figure 136 shows an
example of a segmented buffer system.
Figure 136. Example System that Generates Recurring Events
Stratix Device
Reference Design Top-Level File
WADDR[17..0]
RADDR[17..0]
WDATA[35..0]
RDATA[35..0]
CMD[1..0]
INCLK
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Altera Corporation
Pipeline
Registers
(Optional)
QDR SRAM
Controller
QDR
SRAM
C, Cn
1318
The SignalTap II Logic Analyzer verifies the functionality of the design shown in
Figure 136 to ensure that the correct data is written to the SRAM controller. Buffer
acquisition in the SignalTap II Logic Analyzer allows you to monitor the RDATA port
when H'0F0F0F0F is sent into the RADDR port. You can monitor multiple read
transactions from the SRAM device without running the SignalTap II Logic Analyzer
again. The buffer acquisition feature allows you to segment the memory so you can
capture the same event multiple times without wasting allocated memory. The
number of cycles that are captured depends on the number of segments specified
under the Data settings.
To enable and configure buffer acquisition, select Segmented in the SignalTap II Logic
Analyzer Editor and select the number of segments to use. In the example in
Figure 136, selecting sixty-four 64-sample segments allows you to capture 64 read
cycles when the RADDR signal is H'0F0F0F0F.
h For more information about buffer acquisition mode, refer to Configuring the Trigger
Flow in the SignalTap II Logic Analyzer in the Quartus II Help.
1319
You can only use the Storage Qualification feature with a non-segmented buffer. The
MegaWizard Plug-In Manager instantiated flow only supports the Input Port mode
for the Storage Qualification feature.
Figure 137. Data Acquisition Using Different Modes of Controlling the Acquisition Buffer
There are six storage qualifier types available under the Storage Qualification feature:
Continuous
Input port
Transitional
Conditional
Start/Stop
State-based
Continuous (the default mode selected) turns the Storage Qualification feature off.
Each selected storage qualifier type is active when an acquisition starts. Upon the start
of an acquisition, the SignalTap II Logic Analyzer examines each clock cycle and
writes the data into the acquisition buffer based upon storage qualifier type and
condition. The acquisition stops when a defined set of trigger conditions occur.
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1320
Figure 139. Data Acquisition of a Recurring Data Pattern Using an Input Signal as a Storage Qualifier
1321
Transitional Mode
In Transitional mode, you choose a set of signals for inspection using the node list
check boxes in the Storage Qualifier column. During acquisition, if any of the signals
marked for inspection have changed since the previous clock cycle, new data is
written to the acquisition buffer. If none of the signals marked have changed since the
previous clock cycle, no data is stored. Figure 1310 shows the transitional storage
qualifier setup. Figure 1311 and Figure 1312 show captures of a data pattern in
continuous capture mode and a data pattern using the Transitional mode for storage
qualification.
Figure 1310. Transitional Storage Qualifier Setup
Node List
Storage Enable
Transitional Enable
Storage Qualifier
Dialog Box
Figure 1311. Data Acquisition of a Recurring Data Pattern in Continuous Capture Mode (to
illustrate Transitional mode)
Figure 1312. Data Acquisition of Recurring Data Pattern Using a Transitional Mode as a Storage
Qualifier
Conditional Mode
In Conditional mode, the SignalTap II Logic Analyzer evaluates a combinational
function of storage qualifier enabled signals within the node list to determine whether
a sample is stored. The SignalTap II Logic Analyzer writes into the buffer during the
clock cycles in which the condition you specify evaluates TRUE.
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You can select either Basic AND, Basic OR, or Advanced storage qualifier conditions.
A Basic AND or Basic OR storage qualifier condition matches each signal to one of
the following:
Dont Care
Low
High
Falling Edge
Rising Edge
Either Edge
If you specify a Basic AND storage qualifier condition for more than one signal, the
SignalTap II Logic Analyzer evaluates the logical AND of the conditions.
Any other combinational or relational operators that you may want to specify with
the enabled signal set for storage qualification can be done with an advanced storage
condition. Figure 1313 details the conditional storage qualifier setup in the .stp.
You can specify storage qualification conditions similar to the manner in which
trigger conditions are specified. For details about basic and advanced trigger
conditions, refer to the sections Creating Basic Trigger Conditions on page 1326
and Creating Advanced Trigger Conditions on page 1327. Figure 1314 and
Figure 1315 show a data capture with continuous sampling, and the same data
pattern using the conditional mode for analysis, respectively.
Figure 1313. Conditional Storage Qualifier Setup
Figure 1314. Data Acquisition of a Recurring Data Pattern in Continuous Capture Mode (to
illustrate Conditional capture)
1323
Figure 1315. Data Acquisition of a Recurring Data Pattern in Conditional Capture Mode
Start/Stop Mode
The Start/Stop mode is similar to the Conditional mode for storage qualification.
However, in this mode there are two sets of conditions, one for start and one for stop.
If the start condition evaluates to TRUE, data begins is stored in the buffer every clock
cycle until the stop condition evaluates to TRUE, which then pauses the data capture.
Additional start signals received after the data capture has started are ignored. If both
start and stop evaluate to TRUE at the same time, a single cycle is captured.
1
You can force a trigger by pressing the Stop button if the buffer fails to fill to
completion due to a stop condition.
Figure 1316 shows the Start/Stop mode storage qualifier setup. Figure 1317 and
Figure 1318 show captures data pattern in continuous capture mode and a data
pattern in using the Start/Stop mode for storage qualification.
Figure 1316. Start/Stop Mode Storage Qualifier Setup
Figure 1317. Data Acquisition of a Recurring Data Pattern in Continuous Mode (to illustrate
Start/Stop mode)
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1324
Figure 1318. Data Acquisition of a Recurring Data Pattern with Start/Stop Storage Qualifier
Enabled
State-Based
The State-based storage qualification mode is used with the State-based triggering
flow. The state based triggering flow evaluates an if-else based language to define
how data is written into the buffer. With the State-based trigger flow, you have
command over boolean and relational operators to guide the execution flow for the
target acquisition buffer. When the storage qualifier feature is enabled for the
State-based flow, two additional commands are available, the start_store and
stop_store commands. These commands operate similarly to the Start/Stop capture
conditions described in the previous section. Upon the start of acquisition, data is not
written into the buffer until a start_store action is performed. The stop_store
command pauses the acquisition. If both start_store and stop_store actions are
performed within the same clock cycle, a single sample is stored into the acquisition
buffer.
For more information about the State-based flow and storage qualification using the
State-based trigger flow, refer to the section State-Based Triggering on page 1330.
1325
Enable
Data Log
The SOF Manager allows you to embed multiple SOFs into one .stp. Embedding an
SOF in an .stp lets you move the .stp to a different location, either on the same
computer or across a network, without the need to include the associated .sof as a
separate. To embed a new SOF in the .stp, right-click in the SOF Manager, and click
Attach SOF File (Figure 1320).
Figure 1320. SOF Manager
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1326
As you switch between configurations in the Data Log, you can extract the SOF that is
compatible with that particular configuration. You can use the programmer in the
SignalTap II Logic Analyzer to download the new SOF to the FPGA, ensuring that the
configuration of your .stp always matches the design programmed into the target
device.
Define Triggers
When you start the SignalTap II Logic Analyzer, it samples activity continuously from
the monitored signals. The SignalTap II Logic Analyzer triggersthat is, the logic
analyzer stops and displays the datawhen a condition or set of conditions that you
specified has been reached. This section describes the various types of trigger
conditions that you can specify using the SignalTap II Logic Analyzer on the Signal
Configuration pane.
Dont Care
Low
High
Falling Edge
Rising Edge
Either Edge
For buses, type a pattern in binary, or right-click and select Insert Value to enter the
pattern in other number formats. Note that you can enter X to specify a set of dont
care values in either your hexadecimal or your binary string. For signals added to the
.stp that have an associated mnemonic table, you can right-click and select an entry
from the table to specify pre-defined conditions for the trigger.
For more information about creating and using mnemonic tables, refer to View,
Analyze, and Use Captured Data on page 1354, and to the Quartus II Help.
For signals added with certain plug-ins, you can create basic triggers easily using
predefined mnemonic table entries. For example, with the Nios II plug-in, if you have
specified an .elf from your Nios II IDE design, you can type the name of a function
from your Nios II code. The logic analyzer triggers when the Nios II instruction
address matches the address of the specified code function name.
Data capture stops and the data is stored in the buffer when the logical AND of all the
signals for a given trigger condition evaluates to TRUE.
1327
(1)
Name of Operator
Type
Less Than
Comparison
Comparison
Equality
Comparison
Inequality
Comparison
Greater Than
Comparison
Comparison
Logical NOT
Logical
Logical AND
Logical
Logical OR
Logical
Logical XOR
Logical
Reduction AND
Reduction
Reduction OR
Reduction
Reduction XOR
Reduction
Left Shift
Shift
Right Shift
Shift
Bitwise Complement
Bitwise
Bitwise AND
Bitwise
Bitwise OR
Bitwise
Bitwise XOR
Bitwise
Signal Detection
Adding many objects to the Advanced Trigger Condition Editor can make the work
space cluttered and difficult to read. To keep objects organized while you build your
advanced trigger condition, use the shortcut menu and select Arrange All Objects.
You can also use the Zoom-Out command to fit more objects into the Advanced
Trigger Condition Editor window.
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1328
Trigger when bus outa is greater than or equal to outb (Figure 1321).
Trigger when bus outa is greater than or equal to bus outb, and when the enable
signal has a rising edge (Figure 1322).
1329
Trigger when bus outa is greater than or equal to bus outb, or when the enable
signal has a rising edge. Or, when a bitwise AND operation has been performed
between bus outc and bus outd, and all bits of the result of that operation are equal
to 1 (Figure 1323).
You can use sequential or state based triggering with either a segmented or a nonsegmented buffer.
Sequential Triggering
Sequential triggering flow allows you to cascade up to 10 levels of triggering
conditions. The SignalTap II Logic Analyzer sequentially evaluates each of the
triggering conditions. When the last triggering condition evaluates to TRUE, the
SignalTap II Logic Analyzer triggers the acquisition buffer. For segmented buffers,
every acquisition segment after the first segment triggers on the last triggering
condition that you have specified. Use the Simple Sequential Triggering feature with
basic triggers, advanced triggers, or a mix of both. Figure 1324 illustrates the simple
sequential triggering flow for non-segmented and segmented buffers.
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1330
The external trigger is considered as trigger level 0. The external trigger must be
evaluated before the main trigger levels are evaluated.
(1), (2)
Non-segmented Buffer
Segmented Buffer
Trigger Condition 1
Trigger Condition 1
Trigger Condition 2
Trigger Condition 2
n - 2 transitions
n - 2 transitions
Trigger Condition n
trigger
Acquisition Segment 1
Acquisition Buffer
Trigger Condition n
trigger
Acquisition Segment 2
m - 2 transitions
Trigger Condition n
trigger
Acquisition Segment m
State-Based Triggering
Custom State-based triggering provides the most control over triggering condition
arrangement. The State-Based Triggering flow allows you to describe the relationship
between triggering conditions precisely, using an intuitive GUI and the SignalTap II
Trigger Flow Description Language, a simple description language based upon
conditional expressions. Tooltips within the custom triggering flow GUI allow you to
describe your desired flow quickly. The custom State-based triggering flow allows for
more efficient use of the space available in the acquisition buffer because only specific
samples of interest are captured.
1331
Figure 1325 illustrates the custom State-based triggering flow. Events that trigger the
acquisition buffer are organized by a state diagram that you define. All actions
performed by the acquisition buffer are captured by the states and all transition
conditions between the states are defined by the conditional expressions that you
specify within each state.
Figure 1325. State-Based Triggering Flow
User-Defined Triggering Flow
(1), (2)
Transition Condition k
Transition Condition i
Transition Condition l
State 1:
State 2:
State 3:
Transition Condition j
segment_trigger
First Acquisition Segment
segment_trigger
Next Acquisition Segment
segment_trigger
Next Acquisition Segment
segment_trigger
Last Acquisition Segment
Each state allows you to define a set of conditional expressions. Each conditional
expression is a Boolean expression dependent on a combination of triggering
conditions (configured within the Setup tab), counters, and status flags. Counters and
status flags are resources provided by the SignalTap II Logic Analyzer custom-based
triggering flow.
Within each conditional expression you define a set of actions. Actions include
triggering the acquisition buffer to stop capture, a modification to either a counter or
status flag, or a state transition.
Trigger actions can apply to either a single segment of a segmented acquisition buffer
or to the entire non-segmented acquisition buffer. Each trigger action provides you
with an optional count that specifies the number of samples captured before stopping
acquisition of the current segment. The count argument allows you to control the
amount of data captured precisely before and after triggering event.
Resource manipulation actions allow you to increment and decrement counters or set
and clear status flags. The counter and status flag resources are used as optional
inputs in conditional expressions. Counters and status flags are useful for counting
the number of occurrences of particular events and for aiding in triggering flow
control.
This SignalTap II custom State-based triggering flow allows you to capture a sequence
of events that may not necessarily be contiguous in time; for example, capturing a
communication transaction between two devices that includes a handshaking
protocol containing a sequence of acknowledgements.
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The State-Based Trigger Flow tab is the control interface for the custom state-based
triggering flow. To enable this tab, select State-based on the Trigger Flow Control list.
(Note that when Trigger Flow Control is specified as Sequential, the State-Based
Trigger Flow tab is hidden.)
The State-Based Trigger Flow tab is partitioned into the following three panes:
Resources Pane
For a full description of the SignalTap II Trigger Flow Description Language, refer to
SignalTap II Trigger Flow Description Language on page 1333.
h You can also refer to SignalTap II Trigger Flow Description Language in Quartus II Help.
The State Machine description text boxes default to show one text box per state. You
can also have the entire flow description shown in a single text field. This option can
be useful when copying and pasting a flow description from a template or an external
text editor. To toggle between one window per state, or all states in one window, select
the appropriate option under State Display mode.
Resources Pane
The Resources pane allows you to declare Status Flags and Counters for use in the
conditional expressions in the Custom Triggering Flow. Actions to decrement and
increment counters or to set and clear status flags are performed within the triggering
flow that you define.
You can specify up to 20 counters and 20 status flags. Counter and status flags values
may be initialized by right-clicking the status flag or counter name after selecting a
number of them from the respective pull-down list, and selecting Set Initial Value. To
specify a counter width, right-click the counter name and select Set Width. Counters
and flag values are updated dynamically after acquisition has started to assist in
debugging your trigger flow specification.
1333
The configurable at runtime options in the Resources pane allows you to configure
the custom-flow control options that can be changed at runtime without requiring a
recompilation. Table 134 contains a description of options for the State-based trigger
flow that can be reconfigured at runtime.
1
For a broader discussion about all options that can be changed without incurring a
recompile refer to Runtime Reconfigurable Options on page 1351.
Description
Comparison values
Allows you to modify comparison values in Boolean expressions at runtime. In addition, you
can modify the segment_trigger and trigger action post-fill count argument at runtime.
Comparison operators
Logical operators
You can restrict changes to your SignalTap configuration to include only the options
that do not require a recompilation by using the menu above the trigger list in the
Setup tab. Allow trigger condition changes only restricts changes to only the
configuration settings that have the configurable at runtime specified. With this
option enabled, to modify Trigger Flow conditions in the Custom Trigger Flow tab,
click the desired parameter in the text box and select a new parameter from the menu
that appears.
1
The runtime configurable settings for the Custom Trigger Flow tab are on by default.
You may get some performance advantages by disabling some of the runtime
configurable options. For details about the effects of turning off the runtime
modifiable options, refer to Performance and Resource Considerations on
page 1347.
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1334
(1)
state <State_label>:
<action_list>
if( <Boolean_expression> )
<action_list>
[else if ( <boolean_expression> )
<action_list>] (1)
[else
<action_list>]
Note to Example 131:
(1) Multiple else if conditions are allowed.
The priority for evaluation of conditional statements is assigned from top to bottom.
The <boolean_expression> in an if statement can contain a single event, or it can
contain multiple event conditions. The action_list within an if or an else if clause
must be delimited by the begin and end tokens when the action list contains multiple
statements. When the boolean expression is evaluated TRUE, the logic analyzer
analyzes all of the commands in the action list concurrently. The possible actions
include:
State Labels
State labels are identifiers that can be used in the action goto.
state <state_label>: begins the description of the actions evaluated when this state is
reached.
The description of a state ends with the beginning of another state or the end of the
whole trigger flow description.
Boolean_expression
Boolean_expression is a collection of logical operators, relational operators, and their
operands that evaluate into a Boolean result. Depending on the operator, the operand
can be a reference to a trigger condition, a counter and a register, or a numeric value.
Within an expression, parentheses can be used to group a set of operands.
1335
Description
Syntax
NOT operator
! expr1
&&
AND operator
||
OR operator
expr1 || expr2
(1) (2)
Operator
Description
>
Greater than
>=
==
Equals
<identifier> == <numerical_value>
!=
<identifier> != <numerical_value>
<=
<
Less than
Action_list
Action_list is a list of actions that can be performed when a state is reached and a
condition is also satisfied. If more than one action is specified, they must be enclosed
by begin and end. The actions can be categorized as resource manipulation actions,
buffer control actions, and state transition actions. Each action is terminated by a
semicolon (;).
Description
increment
increment <counter_identifier>;
decrement
decrement <counter_identifier>;
reset
set
set <register_flag_identifier>;
clear
clear <register_flag_identifier>;
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Altera Corporation
Syntax
reset <counter_identifier>;
1336
segment_trigger
Description
Syntax
trigger <post-fill_count>;
segment_trigger <post-fill_count>;
start_store
stop_store
stop_store
1337
State 1: ST1:
if ( condition1 )
start_store;
else if ( condition2 )
trigger value;
else if ( condition3 )
stop_store;
Figure 1326. Capture Scenario for Storage Qualification with the State-Based Trigger Flow
In this example, the SignalTap II Logic Analyzer does not write into the acquisition
buffer until sample a, when Condition 1 occurs. Once sample b is reached, the
trigger value command is evaluated. The logic analyzer continues to write into the
buffer to finish the acquisition. The trigger flow specifies a stop_store command at
sample c, m samples after the trigger point occurs.
The logic analyzer finishes the acquisition and displays the contents of the waveform
if it can successfully finish the post-fill acquisition samples before Condition 3 occurs.
In this specific case, the capture ends if the post-fill count value is less than m.
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If the post-fill count value specified in Trigger Flow description 1 is greater than m
samples, the buffer pauses acquisition indefinitely, provided there is no recurrence of
Condition 1 to trigger the logic analyzer to start capturing data again. The SignalTap II
Logic Analyzer continues to evaluate the stop_store and start_store commands even
after the trigger command is evaluated. If the acquisition has paused, you can click
Stop Analysis to manually stop and force the acquisition to trigger. You can use
counter values, flags, and the State diagram to help you perform the trigger flow. The
counter values, flags, and the current state are updated in real-time during a data
acquisition.
Figure 1327 and Figure 1328 show a real data acquisition of the scenario.
Figure 1327 illustrates a scenario where the data capture finishes successfully. It uses
a buffer with a sample depth of 64, m = n = 10, and the post-fill count value = 5.
Figure 1328 illustrates a scenario where the logic analyzer pauses indefinitely even
after a trigger condition occurs due to a stop_store condition. This scenario uses a
sample depth of 64, with m = n = 10 and post-fill count = 15.
Figure 1327. Storage Qualification with Post-Fill Count Value Less than m (Acquisition
Successfully Completes)
1339
Figure 1328. Storage Qualification with Post-Fill Count Value Greater than m (Acquisition
Indefinitely Paused)
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State 2: ST2
if (c1 < 3)
increment c1; //skip three clock cycles; c1 initialized to 0
else if (c1 == 3)
begin
start_store; //start_store necessary to enable writing to finish
//acquisition
trigger;
end
Figure 1331. Capture of Data Transaction with Trigger Flow Description Applied
1341
PreSaves signal activity that occurred after the trigger (12% pre-trigger, 88%
post-trigger).
PostSaves signal activity that occurred before the trigger (88% pre-trigger, 12%
post-trigger).
These pre-defined ratios apply to both non-segmented buffers and segmented buffers.
If you use the custom-state based triggering flow, you can specify a custom trigger
position. The segment_trigger and trigger actions accept a post-fill count argument.
The post-fill count specifies the number of samples to capture before stopping data
acquisition for the non-segmented buffer or a data segment when using the trigger
and segment_trigger commands, respectively. When the captured data is displayed
in the SignalTap II data window, the trigger position appears as the number of postcount samples from the end of the acquisition segment or buffer. Refer to
Equation 131:
Equation 131.
Sample Number of Trigger Position = ( N Post-Fill Count )
In this case, N is the sample depth of either the acquisition segment or non-segmented
buffer.
For segmented buffers, the acquisition segments that have a post-count argument
define use of the post-count setting. Segments that do not have a post-count setting
default to the trigger position ratios defined in the Setup tab.
For more details about the custom State-based triggering flow, refer to State-Based
Triggering on page 1330.
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1343
Any change made to the Power-Up Trigger conditions requires that you recompile the
SignalTap II Logic Analyzer instance, even if a similar change to the Runtime Trigger
conditions does not require a recompilation.
While creating or making changes to the trigger conditions for the Run-Time Trigger
or the Power-Up Trigger, you may want to copy these conditions to the other trigger.
This enables you to look for the same trigger during both power-up and runtime. To
do this, right-click the instance name or the Power-Up Trigger name in the Instance
Manager and click Duplicate Trigger, or select the instance name or the Power-Up
Trigger name and on the Edit menu, click Duplicate Trigger.
You can also use In-System Sources and Probes in conjunction with the SignalTap II
Logic Analyzer to force trigger conditions. The In-System Sources and Probes feature
allows you to drive and sample values on to selected nets over the JTAG chain. For
more information, refer to the Design Debugging Using In-System Sources and Probes
chapter in volume 3 of the Quartus II Handbook.
Using the Trigger Out of One Analyzer as the Trigger In of Another Analyzer
An advanced feature of the SignalTap II Logic Analyzer is the ability to use the
Trigger out of one analyzer as the Trigger in to another analyzer. This feature allows
you to synchronize and debug events that occur across multiple clock domains.
To perform this operation, first turn on Trigger out for the source logic analyzer
instance. On the Instance list of the Trigger out trigger, select the targeted logic
analyzer instance. For example, if the instance named auto_signaltap_0 should
trigger auto_signaltap_1, select auto_signaltap_1|trigger_in .
Turning on Trigger out automatically enables the Trigger in of the targeted logic
analyzer instance and fills in the Instance field of the Trigger in trigger with the
Trigger out signal from the source logic analyzer instance. In this example,
auto_signaltap_0 is targeting auto_signaltap_1. The Trigger In Instance field of
auto_signaltap_1 is automatically filled in with auto_signaltap_0|trigger_out.
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1345
To speed compile time, use only post-fit nodes for partitions specified as to
preservation-level post-fit.
Do not mix pre-synthesis and post-fit nodes in any partition. If you must tap
pre-synthesis nodes for a particular partition, make all tapped nodes in that
partition pre-synthesis nodes and change the netlist type to source in the
design partitions window.
Node names may be different between a pre-synthesis netlist and a post-fit netlist. In
general, registers and user input signals share common names between the two
netlists. During compilation, certain optimizations change the names of
combinational signals in your RTL. If the type of node name chosen does not match
the netlist type, the compiler may not be able to find the signal to connect to your
SignalTap II Logic Analyzer instance for analysis. The compiler issues a critical
warning to alert you of this scenario. The signal that is not connected is tied to ground
in the SignalTap II data tab.
If you do use incremental compile flow with the SignalTap II Logic Analyzer and
source file changes are necessary, be aware that you may have to remove
compiler-generated post-fit net names. Source code changes force the affected
partition to go through resynthesis. During synthesis, the compiler cannot find
compiler-generated net names from a previous compilation.
1
Altera recommends using only registered and user-input signals as debugging taps in
your .stp whenever possible.
Both registered and user-supplied input signals share common node names in the
pre-synthesis and post-fit netlist. As a result, using only registered and user-supplied
input signals in your .stp limits the changes you need to make to your SignalTap II
Logic Analyzer configuration.
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1346
You can check the nodes that are connected to each SignalTap II instance using the
In-System Debugging compilation reports. These reports list each node name you
selected to connect to a SignalTap II instance, the netlist type used for the particular
connection, and the actual node name used after compilation. If incremental compile
is turned off, the In-System Debugging reports are located in the Analysis & Synthesis
folder. If incremental compile is turned on, this report is located in the Partition Merge
folder. Figure 1333 shows an example of an In-System Debugging compilation report
for a design using incremental compilation.
Figure 1333. Compilation Report Showing Connectivity to SignalTap II Instance
To verify that your original design was not modified, examine the messages in the
Partition Merge section of the Compilation Report. Figure 1334 shows an example of
the messages displayed.
Figure 1334. Compilation Report Messages
1347
Unless you make changes to your design partitions that require recompilation, only
the SignalTap II design partition is recompiled. If you make subsequent changes to
only the .stp, only the SignalTap II design partition must be recompiled, reducing
your recompilation time.
Minimize the number of combinational signals you add to your .stp and add
registers whenever possible.
f For an example of timing preservation with the SignalTap II Logic Analyzer, refer to
the Area and Timing Optimization chapter in volume 2 of the Quartus II Handbook.
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1348
If SignalTap II logic is part of your critical path, follow these tips to speed up the
performance of the SignalTap II Logic Analyzer:
Minimize the number of signals that have Trigger Enable selectedAll signals
that you add to the .stp have Trigger Enable turned on. Turn off Trigger Enable
for signals that you do not plan to use as triggers.
Turn on Physical Synthesis for register retimingIf you have a large number of
triggering signals enabled (greater than the number of inputs that would fit in a
LAB) that fan-in logic to a gate-based triggering condition, such as a basic trigger
condition or a logical reduction operator in the advanced trigger tab, turn on
Perform register retiming. This can help balance combinational logic across LABs.
If your design is resource constrained, follow these tips to reduce the amount of logic
or memory used by the SignalTap II Logic Analyzer:
Minimize the number of segments in the acquisition bufferYou can reduce the
number of logic resources used for the SignalTap II Logic Analyzer by limiting the
number of segments in your sampling buffer to only those required.
Disable the Data Enable for signals that are used for triggering onlyBy
default, both the data enable and trigger enable options are selected for all
signals. Turning off the data enable option for signals used as trigger inputs only
saves on memory resources used by the SignalTap II Logic Analyzer.
1349
The settings in an .stp must be compatible with the programming .sof used to
program the device. An .stp is considered compatible with an .sof when the settings
for the logic analyzer, such as the size of the capture buffer and the signals selected for
monitoring or triggering, match the way the target device is programmed. If the files
are not compatible, you can still program the device, but you cannot run or control the
logic analyzer from the SignalTap II Logic Analyzer Editor.
1
When the SignalTap II Logic Analyzer detects incompatibility after analysis is started,
a system error message is generated containing two CRC values, the expected value
and the value retrieved from the .stp instance on the device. The CRC values are
calculated based on all SignalTap II settings that affect the compilation.
To ensure programming compatibility, make sure to program your device with the
latest .sof created from the most recent compilation. Checking whether or not a
particular SOF is compatible with the current SignalTap II configuration is achieved
quickly by attaching the SOF to the SOF manager. For more details about using the
SOF manager, refer to Managing Multiple SignalTap II Files and Configurations on
page 1325.
Before starting a debugging session, do not make any changes to the .stp settings that
would requires recompiling the project. You can check the SignalTap II status display
at the top of the Instance Manager pane to verify whether a change you made
requires recompiling the project, producing a new .sof. This gives you the
opportunity to undo the change, so that you do not need to recompile your project. To
prevent any such changes, select Allow trigger condition changes only to lock the
.stp.
Although the Quartus II project is not required when using an .stp, it is
recommended. The project database contains information about the integrity of the
current SignalTap II Logic Analyzer session. Without the project database, there is no
way to verify that the current .stp matches the .sof that is downloaded to the device. If
you have an .stp that does not match the .sof, incorrect data is captured in the
SignalTap II Logic Analyzer.
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1350
Compile Design
Program Device
Possible Missed
Trigger
(Unless Power-Up
Trigger Enabled)
Yes
Changes
Require
Recompile?
Manually Run
SignalTap II
Logic Analyzer
No
Trigger
Occurred?
Make Changes
to Setup
(If Needed)
No
Manually
Stop Analyzer
Yes
Analyze Data:
Power-Up or
Run-Time Trigger
Yes
Data
Downloaded?
No
Yes
Continue
Debugging?
Manually Read
Data from Device
No
End
h For information on running the analyzer from the Instance Manager pane, refer to
Running the SignalTap II Logic Analyzer in Quartus II Help.
f You can also use In-System Sources and Probes in conjunction with the SignalTap II
Logic Analyzer to force trigger conditions. The In-System Sources and Probes feature
allows you to drive and sample values on to selected signals over the JTAG chain. For
more information, refer to the Design Debugging Using In-System Sources and Probes
chapter in volume 3 of the Quartus II Handbook.
1351
Description
Runtime Reconfigurable options can potentially save time during the debugging cycle
by allowing you to cover a wider possible scenario of events without the need to
recompile the design. You may experience a slight impact to the performance and
logic utilization of the SignalTap II IP core. You can turn off Runtime
re-configurability for Advanced Trigger Conditions and the State-based trigger flow
parameters, boosting performance and decreasing area utilization.
You can configure the .stp to prevent changes that normally require recompilation. To
do this, in the Setup tab, select Allow Trigger Condition changes only above the
node list.
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1352
Example 134 illustrates a potential use case for Runtime Reconfigurable features.
This example provides a storage qualified enabled State-based trigger flow
description and shows how you can modify the size of a capture window at runtime
without a recompile. This example gives you equivalent functionality to a segmented
buffer with a single trigger condition where the segment sizes are runtime
reconfigurable.
Example 134. Trigger Flow Description Providing Runtime Reconfigurable Segments
state ST1:
if ( condition1 && (c1 <= m) )
begin
start_store;
increment c1;
goto ST2:
End
else (c1 > m )
the last
begin
start_store
Trigger (n-1)
end
state ST2:
if ( c2 >= n)
begin
reset c2;
stop_store;
goto ST1;
end
else (c2 < n)
begin
increment c2;
goto ST2;
end
Note to Example 134:
(1) m x n must equal the sample depth to efficiently use the space in the sample buffer.
Segment 2
(1)
Segment m
1353
You can add states into the trigger flow description and selectively mask out specific
states and enable other ones at runtime with status flags.
Example 135 shows a modified description of Example 134 with an additional state
inserted. You use this extra state to specify a different trigger condition that does not
use the storage qualifier feature. You insert status flags into the conditional statements
to control the execution of the trigger flow.
Example 135. Modified Trigger Flow Description of Example 16-4 with Status Flags to Selectively Enable States
state ST1 :
if (condition2
&& f1)
begin
start_store;
trigger
end
else if (! f1)
goto ST2;
state ST2:
if ( (condition1 && (c1 <= m)
&& f2)
Set f2
begin
start_store;
increment c1;
goto ST3:
end
else (c1 > m )
start_store
Trigger (n-1)
end
state ST3:
if ( c2 >= n)
begin
reset c2;
stop_store;
goto ST1;
end
else (c2 < n)
begin
increment c2;
goto ST2;
end
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1354
Message Description
Not running
Acquiring (Power-Up)
pre-trigger data (1)
The trigger condition has not been evaluated yet. A full buffer of data is collected
if using the non-segmented buffer acquisition mode and storage qualifier type is
continuous.
Trigger In condition has occurred. The SignalTap II Logic Analyzer is waiting for
the condition of the first trigger condition to occur. This can appear if Trigger In
is specified.
The SignalTap II Logic Analyzer is now waiting for the trigger event to occur.
Acquiring (power-up)
post-trigger data (1)
The entire trigger event has occurred. The SignalTap II Logic Analyzer is
acquiring the post-trigger data. The amount of post-trigger data collected is you
define between 12%, 50%, and 88% when the non-segmented buffer
acquisition mode is selected.
Data is being transmitted to the Quartus II software through the JTAG chain.
Ready to acquire
The SignalTap II Logic Analyzer is waiting for you to initialize the analyzer.
1355
Trigger 2
Pre
Post
1
Trigger 3
Pre
1
Post
1
Trigger 4
Pre
1
Post
1
1
1
0
1
Segment 1 Buffer
1
1
0
1
Segment 2 Buffer
1
1
0
1
Segment 3 Buffer
Pre
1
1
1
0
1
1
1
0
1
Segment 4 Buffer
The SignalTap II Logic Analyzer finishes an acquisition with a segment, and advances
to the next segment to start a new acquisition. Depending on when a trigger condition
occurs, it may affect the way the data capture appears in the waveform viewer.
Figure 1337 illustrates the method in which data is captured. The Trigger markers in
Figure 1337Trigger 1, Trigger 2, Trigger 3 and Trigger 4refer to the evaluation of
the segment_trigger and trigger commands in the Custom State-based trigger flow.
If you use a sequential flow, the Trigger markers refer to trigger conditions specified
within the Setup tab.
If the Segment 1 Buffer is the active segment and Trigger 1 occurs, the SignalTap II
Logic Analyzer starts evaluating Trigger 2 immediately. Data Acquisition for Segment
2 buffer starts when either Segment Buffer 1 finishes its post-fill count, or when
Trigger 2 evaluates as TRUE, whichever condition occurs first. Thus, trigger conditions
associated with the next buffer in the data capture sequence can preempt the post-fill
count of the current active buffer. This allows the SignalTap II Logic Analyzer to
accurately capture all of the trigger conditions that have occurred. Samples that have
not been used appear as a blank space in the waveform viewer.
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1356
Figure 1338 shows an example of a capture using sequential flow control with the
trigger condition for each segment specified as Dont Care. Each segment before the
last captures only one sample, because the next trigger condition immediately
preempts capture of the current buffer. The trigger position for all segments is
specified as pre-trigger (10% of the data is before the trigger condition and 90% of the
data is after the trigger position). Because the last segment starts immediately with the
trigger condition, the segment contains only post-trigger data. The three empty
samples in the last segment are left over from the pre-trigger samples that the
SignalTap II Logic Analyzer allocated to the buffer.
Figure 1338. Segmented Capture with Preemption of Acquisition Segments
(1)
For the sequential trigger flow, the Trigger Position option applies to every segment
in the buffer. For maximum flexibility on how the trigger position is defined, use the
custom state-based trigger flow. By adjusting the trigger position specific to your
debugging requirements, you can help maximize the use of the allocated buffer space.
Non-segmented buffer
Segmented buffer
There are subtle differences in the amount of data captured immediately after running
the SignalTap II Logic Analyzer and before any trigger conditions occur. A nonsegmented buffer, running in continuous mode, completely fills the buffer with
sampled data before evaluating any trigger conditions. Thus, a non-segmented
capture without any storage qualification enabled always shows a waveform with a
full buffer's worth of data captured.
Filling the buffer provides you with as much data as possible within the capture
window. The buffer gets pre-filled with data samples prior to evaluating the trigger
condition. As such, SignalTap requires that the buffer be filled at least once before any
data can be retrieved through the JTAG connection and prevents the buffer from being
dumped during the first acquisition prior to a trigger condition when you perform a
Stop Analysis.
1357
For segmented buffers and non-segmented buffers using any storage qualification
mode, the SignalTap II Logic Analyzer immediately evaluates all trigger conditions
while writing samples into the acquisition memory. The logic analyzer evaluates each
trigger condition before acquiring a full buffer's worth of samples. This evaluation is
especially important when using any storage qualification on the data set. The logic
analyzer may miss a trigger condition if it waits until a full buffer's worth of data is
captured before evaluating any trigger conditions.
If the trigger event occurs on any data sample before the specified amount of pretrigger data has occurred, then the SignalTap II Logic Analyzer triggers and begins
filling memory with post-trigger data, regardless of the amount of pre-trigger data
you specify. For example, if you set the trigger position to 50% and set the logic
analyzer to trigger on a processor reset, start the logic analyzer, and then power on
your target system, the logic analyzer triggers. However, the logic analyzer memory is
filled only with post-trigger data, and not any pre-trigger data, because the trigger
event, which has higher precedence than the capture of pre-trigger data, occurred
before the pre-trigger condition was satisfied.
Figure 1339 and Figure 1340 on page 1358 show the difference between a nonsegmented buffer in continuous mode and a non-segmented buffer using a storage
qualifier. The logic analyzer for the waveforms below is configured with a sample
depth of 64 bits, with a trigger position specified as Post trigger position.
Figure 1339. SignalTap II Logic Analyzer Continuous Data Capture (1)
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1358
Notice in Figure 1339 that Trig1 occurs several times in the data buffer before the
SignalTap II Logic Analyzer actually triggers. A full buffer's worth of data is captured
before the logic analyzer evaluates any trigger conditions. After the trigger condition
occurs, the logic analyzer continues acquisition until it captures eight additional
samples (12% of the buffer, as defined by the "post-trigger" position).
Figure 1340. SignalTap II Logic Analyzer Conditional Data Capture (1)
1359
As an example, the Nios II plug-in helps you to monitor signal activity for your
design as the code is executed. If you set up the logic analyzer to trigger on a function
name in your Nios II code based on data from an .elf, you can see the function name
in the Instance Address signal group at the trigger sample, along with the
corresponding disassembled code in the Disassembly signal group, as shown in
Figure 1341. Captured data samples around the trigger are referenced as offset
addresses from the trigger function name.
Figure 1341. Data Tab when the Nios II Plug-In is Used
Assignment Editor
Pin Planner
Chip Planner
RTL Viewer
Design File
f For more information about using these tools, refer to each of the corresponding
chapters in the Quartus II Handbook.
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To export the captured data from SignalTap II Logic Analyzer, on the File menu, click
Export and specify the File Name, Export Format, and Clock Period.
Other Features
The SignalTap II Logic Analyzer has other features that do not necessarily belong to a
particular task in the task flow.
1361
The SignalTap II MATLAB MEX function is available only in the Windows version of
the Quartus II software. It is compatible with MATLAB Release 14 Original Release
Version 7 and later.
To set up the Quartus II software and the MATLAB environment to perform
SignalTap II acquisitions, perform the following steps:
1. In the Quartus II software, create an .stp file.
2. In the node list in the Data tab of the SignalTap II Logic Analyzer Editor, organize
the signals and groups of signals into the order in which you want them to appear
in the MATLAB matrix. Each column of the imported matrix represents a single
SignalTap II acquisition sample, while each row represents a signal or group of
signals in the order they are organized in the Data tab.
1
3. Save the .stp and compile your design. Program your device and run the
SignalTap II Logic Analyzer to ensure your trigger conditions and signal
acquisition work correctly.
4. In the MATLAB environment, add the Quartus II binary directory to your path
with the following command:
addpath <Quartus install directory>\win r
You can view the help file for the MEX function by entering the following command
in MATLAB without any operators:
alt_signaltap_run r
Use the MATLAB MEX function to open the JTAG connection to the device and run
the SignalTap II Logic Analyzer to acquire data. When you finish acquiring data, close
the JTAG connection.
To open the JTAG connection and begin acquiring captured data directly into a
MATLAB matrix called stp, use the following command:
stp = alt_signaltap_run \
('<stp filename>'[,('signed'|'unsigned')[,'<instance names>'[, \
'<signalset name>'[,'<trigger name>']]]]); r
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When capturing data you must assign a filename, for example, <stp filename> as a
requirement of the MATLAB MEX function. Other MATLAB MEX function options
are described in Table 1311.
Table 1311. SignalTap II MATLAB MEX Function Options
Option
Usage
signed
'signed'
unsigned
'unsigned'
<instance name>
'auto_signaltap_0'
'my_signalset'
<trigger name>
'my_trigger'
Description
The signed option turns signal group data into 32-bit
twos-complement signed integers. The MSB of the group as
defined in the SignalTap II Data tab is the sign bit. The unsigned
option keeps the data as an unsigned integer. The default is signed.
Specify a SignalTap II instance if more than one instance is defined.
The default is the first instance in the .stp, auto_signaltap_0.
Specify the signal set and trigger from the SignalTap II data log if
multiple configurations are present in the .stp. The default is the
active signal set and trigger in the file.
You can enable or disable verbose mode to see the status of the logic analyzer while it
is acquiring data. To enable or disable verbose mode, use the following commands:
alt_signaltap_run('VERBOSE_ON'); r
alt_signaltap_run('VERBOSE_OFF'); r
When you finish acquiring data, close the JTAG connection with the following
command:
alt_signaltap_run('END_CONNECTION'); r
f For more information about the use of MATLAB MEX functions in MATLAB, refer to
the MATLAB Help.
Programming hardware connected to the device on the PCB at the remote location
1363
Equipment Setup
On the PC in the remote location, install the standalone version of the SignalTap II
Logic Analyzer, included in the Quartus II standalone Programmer, or the full version
of the Quartus II software. This remote computer must have Altera programming
hardware connected, such as the EthernetBlaster or USB-Blaster.
On the local PC, install the full version of the Quartus II software. This local PC must
be connected to the remote PC across a LAN with the TCP/IP protocol.
h For information about enabling remote access to a JTAG server, refer to Using the JTAG
Server in Quartus II Help.
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Usage
stp_file
quartus_stp
--stp_file <stp_filename>
Description
Assigns the specified .stp to the
USE_SIGNALTAP_FILE in the .qsf.
enable
quartus_stp --enable
disable
quartus_stp --disable
create_signaltap_hdl_file
quartus_stp
--create_signaltap_hdl_file
Example 136 illustrates how to compile a design with the SignalTap II Logic
Analyzer at the command line.
Example 136.
quartus_stp
quartus_map
quartus_fit
quartus_asm
The quartus_stp --stp_file stp1.stp --enable command creates the QSF variable
and instructs the Quartus II software to compile the stp1.stp file with your design.
The --enable option must be applied for the SignalTap II Logic Analyzer to compile
properly into your design.
1365
Example 137 shows how to create a new .stp after building the SignalTap II Logic
Analyzer instance with the MegaWizard Plug-In Manager.
Example 137.
quartus_stp filtref --create_signaltap_hdl_file --stp_file stp1.stp r
f For information about the other command line executables and options, refer to the
Command-Line Scripting chapter in volume 2 of the Quartus II Handbook.
h For information about Tcl commands that you can use with the SignalTap II Logic
Analyzer Tcl package, refer to ::quartus::stp in Quartus II Help.
Example 138 is an excerpt from a script you can use to continuously capture data.
Once the trigger condition is met, the data is captured and stored in the data log.
Example 138.
#opens signaltap session
open_session -name stp1.stp
#start acquisition of instance auto_signaltap_0 and
#auto_signaltap_1 at the same time
#calling run_multiple_end will start all instances
#run after run_multiple_start call
run_multiple_start
run -instance auto_signaltap_0 -signal_set signal_set_1 -trigger /
trigger_1 -data_log log_1 -timeout 5
run -instance auto_signaltap_1 -signal_set signal_set_1 -trigger /
trigger_1 -data_log log_1 -timeout 5
run_multiple_end
#close signaltap session
close_session
When the script is completed, open the .stp that you used to capture data to examine
the contents of the Data Log.
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f For more information about this example and using the SignalTap II Logic Analyzer
with SOPC builder systems, refer to AN 323: Using SignalTap II Logic Analyzers in
SOPC Builder Systems and AN 446: Debugging Nios II Systems with the SignalTap II Logic
Analyzer.
For additional triggering flow design examples for on-chip debugging, refer to the
On-chip Debugging Design Examples page on the Altera website.
1367
Each segment acts as a non-segmented buffer that continuously updates the memory
contents with the signal values. The last acquisition before stopping the buffer is
displayed on the Data tab as the last sample number in the affected segment. The
trigger position in the affected segment is then defined by N post count fill, where N
is the number of samples per segment. Figure 1342 illustrates the triggering position.
Figure 1342. Specifying a Custom Trigger Position
Trigger
Post Count
1
Sample #1
0
1
1
0
1
1
Last Sample
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This example triggers the acquisition buffer when condition1 occurs after condition3
and occurs ten times prior to condition3. If condition3 occurs prior to ten repetitions
of condition1, the state machine transitions to a permanent wait state.
Example 1310.
state ST1:
if ( condition2
begin
reset c1;
goto ST2;
end
State ST2 :
if ( condition1 )
increment c1;
else if (condition3 && c1 < 10)
goto ST3;
else if ( condition3 && c1 >= 10)
trigger;
ST3:
goto ST3;
f For more information about Tcl scripting, refer to the Tcl Scripting chapter in volume 2
of the Quartus II Handbook
h You can also refer to About Quartus II Tcl Scripting in Quartus II Help.
Conclusion
As the FPGA industry continues to make technological advancements, outdated
methodologies are replaced with new technologies that maximize productivity. The
SignalTap II Logic Analyzer gives you the same benefits as a traditional logic
analyzer, without the many shortcomings of a piece of dedicated test equipment. The
SignalTap II Logic Analyzer provides many new and innovative features that allow
you to capture and analyze internal signals in your FPGA, allowing you to quickly
debug your design.
1369
Version
Changes Made
Added recommendation to use the state-based flow for segmented buffers with separate
trigger conditions, information about Basic OR trigger condition, and hard processor
system (HPS) external triggers.
May 2013
13.0.0
June 2012
12.0.0
November 2011
11.0.1
May 2011
11.0.0
December 2010
10.0.1
July 2010
10.0.0
November 2009
March 2009
9.1.0
Updated Figure 135 on page 1316 and Adding Signals to the SignalTap II File on
page 1310.
Template update.
Minor editorial updates.
Add new acquisition buffer content to the View, Analyze, and Use Captured Data section.
Added script sample for generating hexadecimal CRC values in programmed devices.
No change to content.
9.0.0
8.1.0
Added new section Using the Storage Qualifier Feature on page 1425
May 2008
8.0.0
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
May 2013
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1370
The Quartus II Logic Analyzer Interface (LAI) allows you to use an external logic
analyzer and a minimal number of Altera-supported device I/O pins to examine the
behavior of internal signals while your design is running at full speed on your
Altera- supported device.
The LAI connects a large set of internal device signals to a small number of output
pins. You can connect these output pins to an external logic analyzer for debugging
purposes. In the Quartus II LAI, the internal signals are grouped together, distributed
to a user-configurable multiplexer, and then output to available I/O pins on your
Altera-supported device. Instead of having a one-to-one relationship between internal
signals and output pins, the Quartus II LAI enables you to map many internal signals
to a smaller number of output pins. The exact number of internal signals that you can
map to an output pin varies based on the multiplexer settings in the Quartus II LAI.
This chapter details the following topics:
The term logic analyzer when used in this chapter includes both logic analyzers and
oscilloscopes equipped with digital channels, commonly referred to as mixed signal
analyzers or MSOs.
h Refer to Devices and Adapters in Quartus II Help for a list of Altera-supported devices.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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Registered
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142
Logic
Analyzer
Interface
SignalTap II
Logic
Analyzer
Sample Depth
You have access to a wider sample depth with an external logic analyzer. In the
SignalTap II Logic Analyzer, the maximum sample depth is set to 128 Kb, which is a device
constraint. However, with an external logic analyzer, there are no device constraints,
providing you a wider sample depth.
Debugging Timing Issues
Using an external logic analyzer provides you with access to a timing mode, which
enables you to debug combined streams of data.
Performance
You frequently have limited routing resources available to place and route when you use
the SignalTap II Logic Analyzer with your design. An external logic analyzer adds minimal
logic, which removes resource limits on place-and-route.
Triggering Capability
The SignalTap II Logic Analyzer offers triggering capabilities that are comparable to
external logic analyzers.
Use of Output Pins
Using the SignalTap II Logic Analyzer, no additional output pins are required. Using an
external logic analyzer requires the use of additional output pins.
Acquisition Speed
With the SignalTap II Logic Analyzer, you can acquire data at speeds of over 200 MHz. You
can achieve the same acquisition speeds with an external logic analyzer; however, you
must consider signal integrity issues.
f The Quartus II software offers a portfolio of on-chip debugging tools. For an overview
and comparison of all tools available in the Quartus II software on-chip debugging
tool suite, refer to Section V. In-System Debugging in volume 3 of the Quartus II
Handbook.
Required Components
You must have the following components to perform analysis using the Quartus II
LAI:
143
(2)
FPGA
LAI
Connected to
Unused FPGA Pins
JTAG
Altera Programming
(1)
Hardware
Quartus II Software
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Compile Project
Program Device
Debug Project
145
Description
The Pin Count parameter signifies the number of pins you want dedicated to your LAI. The pins
must be connected to a debug header on your board. Within the Altera-supported device, each pin
is mapped to a user-configurable number of internal signals.
Pin Count
Bank Count
Clock
The Clock parameter is available only when Output/Capture Mode is set to Registered State. You
must specify the sample clock in the Core Parameters view. The sample clock can be any signal in
your design. However, for best results, Altera recommends that you use a clock with an operating
frequency fast enough to sample the data you would like to acquire.
Power-Up State
The Power-Up State parameter specifies the power-up state of the pins you have designated for use
with the LAI. You have the option of selecting tri-stated for all pins, or selecting a particular bank
that you have enabled.
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147
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Conclusion
As the device industry continues to make technological advancements, outdated
debugging methodologies must be replaced with new technologies that maximize
productivity. The LAI feature enables you to connect many internal signals within
your Altera-supported device to an external logic analyzer with the use of a small
number of I/O pins. This new technology in the Quartus II software enables you to
use feature-rich external logic analyzers to debug your Altera-supported device
design, ultimately enabling you to deliver your product in the shortest amount of
time.
Version
June 2012
12.0.0
November 2011
10.1.1
December 2010
10.1.0
August 2010
10.0.1
July 2010
10.0.0
November 2009
9.1.0
March 2009
9.0.0
November 2008
8.1.0
May 2008
8.0.0
Changes
Corrected links
Editorial updates
Editorial updates
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
This chapter explains how to use the QuartusII In-System Memory Content Editor as
part of your FPGA design and verification flow.
The In-System Memory Content Editor allows you to view and update memories and
constants with the JTAG port connection.
The In-System Memory Content Editor allows access to dense and complex FPGA
designs. When you program devices, you have read and write access to the memories
and constants through the JTAG interface. You can then identify, test, and resolve
issues with your design by testing changes to memory contents in the FPGA while
your design is running.
Overview
This chapter contains the following sections:
When you use the In-System Memory Content Editor in conjunction with the
SignalTap II Logic Analyzer, you can more easily view and debug your design in the
hardware lab.
f For more information about the SignalTap II Logic Analyzer, refer to the Design
Debugging Using the SignalTap II Logic Analyzer chapter in volume 3 of the Quartus II
Handbook.
The ability to read data from memories and constants allows you to quickly identify
the source of problems. The write capability allows you to bypass functional issues by
writing expected data. For example, if a parity bit in your memory is incorrect, you
can use the In-System Memory Content Editor to write the correct parity bit values
into your RAM, allowing your system to continue functioning. You can also
intentionally write incorrect parity bit values into your RAM to check the error
handling functionality of your design.
f The Quartus II software offers a variety of on-chip debugging tools. For an overview
and comparison of all tools available in the Quartus II software on-chip debugging
tool suite, refer to Section IV. System Debugging Tools in volume 3 of the Quartus II
Handbook.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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Registered
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152
h For a list of the types of memories and constants currently supported by the
Quartus II software, refer to Megafunctions/LPM in Quartus II Help.
153
If you have more than one device with in-system configurable memories or constants
in a JTAG chain, you can launch multiple In-System Memory Content Editors within
the Quartus II software to access the memories and constants in each of the devices.
Each In-System Memory Content Editor can access the in-system memories and
constants in a single device.
Instance Manager
When you scan the JTAG chain to update the Instance Manager pane, you can view a
list of all run-time modifiable memories and constants in the design. The Instance
Manager pane displays the Index, Instance, Status, Width, Depth, Type, and Mode of
each element in the list.
h You can read and write to in-system memory with the Instance Manager pane. For
more information refer to Instance Manager Pane in Quartus II Help.
1
In addition to the buttons available in the Instance Manager pane, you can read and
write data by selecting commands from the Processing menu, or the right-click menu
in the Instance Manager pane or Hex Editor pane.
The status of each instance is also displayed beside each entry in the Instance
Manager pane. The status indicates if the instance is Not running, Offloading data,
or Updating data. The health monitor provides information about the status of the
editor.
The Quartus II software assigns a different index number to each in-system memory
and constant to distinguish between multiple instances of the same memory or
constant function. View the In-System Memory Content Editor Settings section of
the Compilation Report to match an index number with the corresponding instance
ID.
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Scripting Support
The In-System Memory Content Editor supports reading and writing of memory
contents via a Tcl script or Tcl commands entered at a command prompt. For detailed
information about scripting command options, refer to the Quartus II command-line
and Tcl API Help browser.
To run the Help browser, type the following command at the command prompt:
quartus_sh --qhelp r
f For more information about Tcl scripting, refer to the Tcl Scripting chapter in volume 2
of the Quartus II Handbook and API Functions for Tcl in Quartus II Help. For more
information about command-line scripting, refer to the Command-Line Scripting
chapter in volume 2 of the Quartus II Handbook.
The commonly used commands for the In-System Memory Content Editor are as
follows:
Writing to memory:
write_content_to_memory
h For descriptions of the command options and scripting examples, refer to the Tcl API
Help Browser and the API Functions for Tcl in Quartus II Help.
Example: Using the In-System Memory Content Editor with the SignalTap II
Logic Analyzer
The following scenario describes how you can use the In-System Updating of
Memory and Constants feature with the SignalTap II Logic Analyzer to efficiently
debug your design in-system. You can use the In-System Memory Content Editor and
the SignalTap II Logic Analyzer simultaneously with the JTAG interface.
155
Scenario: After completing your FPGA design, you find that the characteristics of
your FIR filter design are not as expected.
1. To locate the source of the problem, change all your FIR filter coefficients to be
in-system modifiable and instantiate the SignalTap II Logic Analyzer.
2. Using the SignalTap II Logic Analyzer to tap and trigger on internal design nodes,
you find the FIR filter to be functioning outside of the expected cutoff frequency.
3. Using the In-System Memory Content Editor, you check the correctness of the FIR
filter coefficients. Upon reading each coefficient, you discover that one of the
coefficients is incorrect.
4. Because your coefficients are in-system modifiable, you update the coefficients
with the correct data with the In-System Memory Content Editor.
In this scenario, you can quickly locate the source of the problem using both the
In-System Memory Content Editor and the SignalTap II Logic Analyzer. You can also
verify the functionality of your device by changing the coefficient values before
modifying the design source files.
You can also modify the coefficients with the In-System Memory Content Editor to
vary the characteristics of the FIR filter, for example, filter attenuation, transition
bandwidth, cut-off frequency, and windowing function.
Conclusion
The In-System Updating of Memory and Constants feature provides access to a device
for efficient debugging in a hardware lab. You can use the In-System Memory and
Content Editor with the SignalTap II Logic Analyzer to maximize the visibility into an
Altera FPGA. By maximizing visibility and access to internal logic of the device, you
can identify and resolve problems with your design more easily.
Version
Changes
June 2012
12.0.0
November 2011
10.0.3
Template update.
December 2010
10.0.2
August 2010
10.0.1
Corrected links
July 2010
10.0.0
November 2009
9.1.0
Style changes
March 2009
9.0.0
No change to content
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May 2008
8.1.0
8.0.0
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
This chapter provides detailed instructions about how to use the In-System Sources
and Probes Editor and Tcl scripting in the Quartus II software to debug your design.
Traditional debugging techniques often involve using an external pattern generator to
exercise the logic and a logic analyzer to study the output waveforms during run
time. The SignalTap II Logic Analyzer and SignalProbe allow you to read or tap
internal logic signals during run time as a way to debug your logic design. You can
make the debugging cycle more efficient when you can drive any internal signal
manually within your design, which allows you to perform the following actions:
Force the occurrence of trigger conditions set up in the SignalTap II Logic Analyzer
Create simple test vectors to exercise your design without using external test
equipment
Dynamically control run time control signals with the JTAG chain
The In-System Sources and Probes Editor in the Quartus II software extends the
portfolio of verification tools, and allows you to easily control any internal signal and
provides you with a completely dynamic debugging environment. Coupled with
either the SignalTap II Logic Analyzer or SignalProbe, the In-System Sources and
Probes Editor gives you a powerful debugging environment in which to generate
stimuli and solicit responses from your logic design.
f The Virtual JTAG Megafunction and the In-System Memory Content Editor also give
you the capability to drive virtual inputs into your design. The Quartus II software
offers a variety of on-chip debugging tools. For an overview and comparison of all the
tools available in the Quartus II software on-chip debugging tool suite, refer to
Section IV. System Debugging Tools in volume 3 of the Quartus II Handbook.
Overview
This chapter includes the following topics:
Design Flow Using the In-System Sources and Probes Editor on page 164
Tcl interface for the In-System Sources and Probes Editor on page 169
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162
Probes
Sources
altsource_probe
Megafunction
DD
DD
QQ
QQ
DD
DD
QQ
QQ
JTAG
Controller
Altera
Programming
Hardware
Quartus II
Software
163
The In-System Sources and Probes Editor supports Tcl commands that interface with
all your ALTSOURCE_PROBE megafunction instances to increase the level of
automation.
Quartus II software
or
Altera development kit or user design board with a JTAG connection to device
under test
The In-System Sources and Probes Editor supports the following device families:
June 2012
Arria GX
Stratix series
HardCopy II
Cyclone series
MAX series
Altera Corporation
164
Configure
altsource_probe
Megafunction
Program Target
Device(s)
Debug/Modify HDL
Functionality
Satisfied?
No
Yes
End
165
Verify that the currently selected device family matches the device you are
targeting.
b. Select an output file type and enter the name of the ALTSOURCE_PROBE
megafunction. You can choose AHDL (.tdf), VHDL (.vhd), or Verilog HDL (.v)
as the output file type.
5. Click Next.
6. On page 3 of the MegaWizard Plug-In Manager, make the following selections:
a. Under Do you want to specify an Instance Index?, turn on Yes.
b. Specify the Instance ID of this instance.
c. Specify the width of the probe port. The width can be from 0 bit to 256 bits.
d. Specify the width of the source port. The width can be from 0 bit to 256 bits.
7. On page 3 of the MegaWizard Plug-In Manager, you can click Advanced Options
and specify other options, including the following:
June 2012
Write data to the source port synchronously to the source clockAllows you
to synchronize your source port write transactions with the clock domain of
your choice.
Create an enable signal for the registered source portWhen turned on,
creates a clock enable input for the synchronization registers. You can turn on
this option only when the Write data to the source port synchronously to the
source clock option is turned on.
The In-System Sources and Probes Editor does not support simulation. You must
remove the ALTSOURCE_PROBE megafunction instantiation before you create a
simulation netlist.
Altera Corporation
166
Required?
Direction
Comments
probe[]
No
Input
source_clk
No
Input
source_ena
No
Input
source[]
No
Output
167
In-System Sources and Probes EditorLogs all data read from the selected
instance and allows you to modify source data that is written to your device.
When you use the In-System Sources and Probes Editor, you do not need to open a
Quartus II software project. The In-System Sources and Probes Editor retrieves all
instances of the ALTSOURCE_PROBE megafunction by scanning the JTAG chain and
sending a query to the device selected in the JTAG Chain Configuration pane. You
can also use a previously saved configuration to run the In-System Sources and
Probes Editor.
Each In-System Sources and Probes Editor pane can access the
ALTSOURCE_PROBE megafunction instances in a single device. If you have more
than one device containing megafunction instances in a JTAG chain, you can launch
multiple In-System Sources and Probes Editor panes to access the megafunction
instances in each device.
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Instance Manager
The Instance Manager pane provides a list of all ALTSOURCE_PROBE instances in
the design and allows you to configure how data is acquired from or written to those
instances.
The following buttons and sub-panes are provided in the Instance Manager pane:
Read Probe DataSamples the probe data in the selected instance and displays
the probe data in the In-System Sources and Probes Editor pane.
Write Source DataWrites data to all source nodes of the selected instance.
Probe Read IntervalDisplays the sample interval of all the In-System Sources
and Probe instances in your design; you can modify the sample interval by
clicking Manual.
Event LogControls the event log in the In-System Sources and Probes Editor
pane.
The status of each instance is also displayed beside each entry in the Instance
Manager pane. The status indicates if the instance is Not running Offloading data,
Updating data, or if an Unexpected JTAG communication error occurs. This status
indicator provides information about the sources and probes instances in your design.
169
You can access read data with the shortcut menus in the Instance Manager pane.
To adjust the probe read interval, in the Instance Manager pane, turn on the Manual
option in the Probe read interval sub-pane, and specify the sample rate in the text
field next to the Manual option. The maximum sample rate depends on your
computer setup. The actual sample rate is shown in the Current interval box. You can
adjust the event log window buffer size in the Maximum Size box.
Writing Data
To modify the source data you want to write into the ALTSOURCE_PROBE instance,
click the name field of the signal you want to change. For buses of signals, you can
double-click the data field and type the value you want to drive out to the
ALTSOURCE_PROBE instance. The In-System Sources and Probes Editor stores the
modified source data values in a temporary buffer. Modified values that are not
written out to the ALTSOURCE_PROBE instances appear in red. To update the
ALTSOURCE_PROBE instance, highlight the instance in the Instance Manager pane
and click Write source data. The Write source data function is also available via the
shortcut menus in the Instance Manager pane.
The In-System Sources and Probes Editor provides the option to continuously update
each ALTSOURCE_PROBE instance. Continuous updating allows any modifications
you make to the source data buffer to also write immediately to the
ALTSOURCE_PROBE instances. To continuously update the ALTSOURCE_PROBE
instances, change the Write source data field from Manually to Continuously.
Organizing Data
The In-System Sources and Probes Editor pane allows you to group signals into
buses, and also allows you to modify the display options of the data buffer.
To create a group of signals, select the node names you want to group, right-click and
select Group. You can modify the display format in the Bus Display Format and the
Bus Bit order shortcut menus.
The In-System Sources and Probes Editor pane allows you to rename any signal. To
rename a signal, double-click the name of the signal and type the new name.
The event log contains a record of the most recent samples. The buffer size is
adjustable up to 128k samples. The time stamp for each sample is logged and is
displayed above the event log of the active instance as you move your pointer over
the data samples.
You can save the changes that you make and the recorded data to a Sources and
Probes File (.spf). To save changes, on the File menu, click Save. The file contains all
the modifications you made to the signal groups, as well as the current data event log.
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The Tcl interface for the In-System Sources and Probes Editor provides a powerful
platform to help you debug your design. The Tcl interface is especially helpful for
debugging designs that require toggling multiple sets of control inputs. You can
combine multiple commands with a Tcl script to define a custom command set.
f For more information about Tcl scripting, refer to the Tcl Scripting chapter in volume 2
of the Quartus II Handbook. For more information about settings and constraints in the
Quartus II software, refer to the Quartus II Settings File Manual. For more information
about command-line scripting, refer to the Command-Line Scripting chapter in
volume 2 of the Quartus II Handbook.
Table 162 shows the Tcl commands you can use instead of the In-System Sources and
Probes Editor.
Table 162. In-System Sources and Probes Tcl Commands
Command
Argument
start_insystem_source_pro
be
get_insystem_source_
probe_instance_info
read_probe_data
-instance_index
<instance_index>
-value_in_hex (optional)
read_source_data
-instance_index
<instance_index>
-value_in_hex (optional)
write_source_data
-instance_index
<instance_index>
-value <value>
-value_in_hex (optional)
end_interactive_probe
None
Description
Opens a handle to a device with the
specified hardware.
Call this command before starting any
transactions.
Returns a list of all ALTSOURCE_PROBE
instances in your design. Each record
returned is in the following format:
{<instance Index>, <source width>, <probe
width>, <instance name>}
Retrieves the current value of the probe.
A string is returned that specifies the status
of each probe, with the MSB as the
left-most bit.
Retrieves the current value of the sources.
A string is returned that specifies the status
of each source, with the MSB as the
left-most bit.
Sets the value of the sources.
A binary string is sent to the source ports,
with the MSB as the left-most bit.
Releases the JTAG chain.
Issue this command when all transactions
are finished.
Example 161 shows an excerpt from a Tcl script with procedures that control the
ALTSOURCE_PROBE instances of the design as shown in Figure 163. The example
design contains a DCFIFO with ALTSOURCE_PROBE instances to read from and
write to the DCFIFO. A set of control muxes are added to the design to control the
flow of data to the DCFIFO between the input pins and the ALTSOURCE_PROBE
1611
instances. A pulse generator is added to the read request and write request control
lines to guarantee a single sample read or write. The ALTSOURCE_PROBE instances,
when used with the script in Example 161, provide visibility into the contents of the
FIFO by performing single sample write and read operations and reporting the state
of the full and empty status flags.
Use the Tcl script in debugging situations to either empty or preload the FIFO in your
design. For example, you can use this feature to preload the FIFO to match a trigger
condition you have set up within the SignalTap II Logic Analyzer.
Figure 163. A DCFIFO Example Design Controlled by the Tcl Script in Example 161
altsource_probe
(instance 0)
Source_write_sel
S_write_req
Write_clock
S_data[7..0]
Wr_req_in
Write_req
Data[7..0]
Data_in[7..0]
Wr_full
Write_clock
Read_req
Data_out
Q[7..0]
Rd_empty
Read_clock
Rd_req_in
altsource_probe
(instance 1)
S_read_req
Q
Source_read_sel
Read_clock
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Example 161. Tcl Script Procedures for Reading and Writing to the DCFIFO in Figure 163 (Part 1 of 2)
## Setup USB hardware - assumes only USB Blaster is installed and
## an FPGA is the only device in the JTAG chain
set usb [lindex [get_hardware_names] 0]
set device_name [lindex [get_device_names -hardware_name $usb] 0]
## write procedure : argument value is integer
proc write {value} {
global device_name usb
variable full
start_insystem_source_probe -device_name $device_name -hardware_name $usb
#read full flag
set full [read_probe_data -instance_index 0]
if {$full == 1} {end_insystem_source_probe
return "Write Buffer Full"
}
1613
Example 161. Tcl Script Procedures for Reading and Writing to the DCFIFO in Figure 163 (Part 2 of 2)
##toggle select line, drive value onto port, toggle enable
##bits 7:0 of instance 0 is S_data[7:0]; bit 8 = S_write_req;
##bit 9 = Source_write_sel
##int2bits is custom procedure that returns a bitstring from an integer
## argument
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Stratix PLLs allow you to dynamically update PLL coefficients during run time. Each
enhanced PLL within the Stratix device contains a register chain that allows you to
modify the pre-scale counters (m and n values), output divide counters, and delay
counters. In addition, the ALTPLL_RECONFIG megafunction provides an easy
interface to access the register chain counters. The ALTPLL_RECONFIG
megafunction provides a cache that contains all modifiable PLL parameters. After you
update all the PLL parameters in the cache, the ALTPLL_RECONFIG megafunction
drives the PLL register chain to update the PLL with the updated parameters.
Figure 164 shows a Stratix-enhanced PLL with reconfigurable coefficients.
1
Stratix II and Stratix III devices also allow you to dynamically reconfigure PLL
parameters. For more information about these families, refer to the appropriate data
sheet. For more information about dynamic PLL reconfiguration, refer to AN 282:
Implementing PLL Reconfiguration in Stratix & Stratix GX Devices or AN 367:
Implementing PLL Reconfiguration in Stratix II Devices.
fREF
tn
Charge
Pump
PFD
Loop
Filter
g0
VCO
tg0
scandata
scanclk
LSB
MSB
(1)
(2)
scanaclr
LSB
m
LSB
MSB
tm
MSB
g3
tg3
LSB
MSB
e3
te3
MSB
LSB
1615
fref
In-System Sources
and Probes
Tcl Interface
JTAG
Interface
In-System
Sources and Probes
Counter
Parameters
alt_pll_reconfig
Megafunction
PLL_scandata
PLL_scandlk
PLL_scanaclr
E0
Stratix-Enhanced
PLL
C0
C1
Figure 166. Interactive PLL Reconfiguration GUI Created with Tk and In-System Sources and Probes Tcl Package
This design example was created using a Nios II Development Kit, Stratix Edition.
The file sourceprobe_DE_dynamic_pll.zip contains all the necessary files for running
this design example, including the following:
Readme.txtA text file that describes the files contained in the design example
and provides instructions about running the Tk GUI shown in Figure 166.
f Download the In-System Sources and Probes Example from the On-chip Debugging
Design Examples page of the Altera website.
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Conclusion
The In-System Sources and Probes Editor provides stimuli and receives responses
from the target design during run time. With the simple and intuitive interface, you
can add virtual inputs to your design during run time without using external
equipment. When used in conjunction with the SignalTap II Logic Analyzer, you can
use the In-System Sources and Probes Editor to obtain greater control of the signals in
your design, and thus help shorten the verification cycle.
Version
Changes
June 2010
12.0.0
November 2011
10.1.1
Template update.
December 2010
10.1.0
July 2010
10.0.0
Minor corrections.
November 2009
9.1.0
March 2009
9.0.0
No change to content.
November 2008
8.1.0
May 2008
8.0.0
Style changes.
Documented that this feature does not support simulation on page 175
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
The Quartus II software easily interfaces with EDA formal design verification tools
such as the Cadence Encounter Conformal and Synopsys Synplify software. In
addition, the Quartus II software has built-in support for verifying the logical
equivalence between the synthesized netlist from Synopsys Synplify and the post-fit
Verilog Quartus Mapped (.vqm) files using Cadence Encounter Conformal software.
This section discusses formal verification, how to set-up the Quartus II software to
generate the .vqm file and Cadence Encounter Conformal script, and how to compare
designs using Cadence Encounter Conformal software.
This section includes the following chapter:
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
This chapter describes equivalence checking with the Cadence Encounter Conformal
Logic Equivalence Check (LEC) software. The Quartus II software provides formal
verification support for Altera designs through interfaces with the Conformal LEC
software.
Logic equivalence checking uses Boolean arithmetic techniques to compare the logical
equivalence of two versions of the same design. You can use the Conformal LEC
software to verify the functional equivalence of a post-synthesis Verilog Quartus
Mapping (.vqm) netlist from the Synopsys Synplify Pro software, a post-fit Verilog
Output File (.vo) from the Quartus II software, or both. You can also use the
Conformal LEC software to verify the functional equivalence of the register transfer
level (RTL) source code and post-fit .vo with the Quartus II software when using
Quartus II integrated synthesis.
This chapter discusses the following topics:
Generating the Post-Fit Netlist Output File and the Conformal LEC Setup Files
on page 179
Understanding the Formal Verification Scripts for the Conformal LEC Software
on page 1712
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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172
Debug designs
Preserving hierarchy
Enabling retiming
Before you consider using the formal verification flow in your design methodology,
refer to Known Issues and Limitations on page 1716.
The following sections describe the supported design flows for these synthesis tools.
173
Equivalence
Checking
Formal Verification
Library
Conformal
LEC Software
Quartus II
Software
Placement and Routing
Post-Fit
Verilog Output
Synplify Pro
Figure 172 shows the design flow for formal verification with Synplify Pro Synthesis
performing equivalency checking for the post-synthesis netlist from Synplify Pro and
the post-fit netlist generated by Quartus II software.
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f For more information about performing equivalence checking between RTL source
code and post-synthesis netlists generated from the Synplify Pro software, refer to the
Synplify Pro documentation.
Figure 172. Formal Verification Flow Using Synplify Pro and the Conformal LEC Software
RTL
Synplify Pro
Conformal
LEC Software
Synthesized
Netlist
Quartus II
Software
Formal Verification
Library
Conformal
LEC Software
Some of the coding guidelines apply to both Quartus II integrated synthesis and
Synplify Pro flow, as indicated in each of the guidelines in the following sections.
175
synthesis read_comments_as_HDL on
my_rom lpm_rom (.address (address),
.data (data));
synthesis read_comments_as_HDL off
synthesis read_comments_as_HDL on
my_rom : entity lpm_rom
port map (
address => address,
data => data, );
synthesis read_comments_as_HDL off
The Conformal LEC software does not support the read_comments_as_HDL synthesis
directive, and the directive does not affect the Conformal LEC software.
Table 171 lists supported pragmas and trigger keywords for formal verification.
Table 171. Supported Pragmas and Trigger Keywords for Formal Verification
Pragmas
Trigger Keywords
full_case
parallel_case
pragma
synthesis_off
synthesis_on
synthesis
synopsys
translate_off
translate_on
c Do not use Verilog 2001-style pragma declarations. The Quartus II software and the
Conformal LEC software support this style of pragma differently.
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Fixed-Output Registers
Quartus II integrated synthesis and Synplify Pro eliminate registers that have fixed
ouput. Quartus II integrated synthesis issues a warning message and adds an entry to
the corresponding report panel in the formal verification folder of the Analysis &
Synthesis section of the Compilation Report. If the Conformal LEC software does not
find the same optimizations, the result can lead to unmapped points in the golden
netlist. Example 173 shows logic causing register outputs to be fixed at a constant
value.
Example 173. Verilog HDL Example Showing Fixed Register Outputs
module stuck_at_example {clk, a,b,c,d,out};
input a,b,c,d,clk;
output out;
reg e,f,g;
always @(posedge clk) begin
e <= a and g;// e is stuck at 0
g <= c and e;// g is stuck at 0
f <= e | b;
end
assign out = f and d;
endmodule
In this module description, registers e and g are tied to logic 0. In this example, the
Quartus II software generates the following warning message:
Warning: Reduced register "g" with stuck data_in port to stuck value GND
Warning: Reduced register "e" with stuck data_in port to stuck value GND
Example 174 shows that Quartus II integrated synthesis adds a command to the
formal verification scripts to inform the Conformal LEC software that a register is
stuck at a constant value.
Example 174. Conformal LEC Script Showing Commands for Instance Equivalence
//
//
//
//
//
Altera recommends recoding your design to eliminate registers that have fixed
output.
177
RAM Inference
When the Quartus II software infers the ALTSYNCRAM megafunction from the RTL
source code, the Quartus II software generates the following warning message:
Created node "<mem_block_name>" as a RAM by generating altsyncram
megafunction to implement register logic with M512 or M4K memory block
or M-RAM. Expect to get an error or a mismatch for this block in the
formal verification tool.
The Quartus II software generates this warning message because the memory block
(altsyncram) is a new instance in the post-fit netlist. The Quartus II software handles
the ALTSYNCRAM megafunction as a black box by the formal verification tool.
However, no such instance exists in the original RTL design, resulting in mismatch or
error reporting in the formal verification tool.
Latch Inference
A combinational feedback loop implements a latch in Quartus II integrated synthesis.
The Conformal LEC software infers a latch primitive in the Conformal LEC software
library to implement a latch. This results in having a library on the golden side and a
combinational loop with a cut point on the revised side, leading to verification
mismatches. The Quartus II software issues a warning message whenever the
Conformal LEC software infers a latch. The Quartus II software then adds an entry to
the report panel in the Formal Verification folder of the Analysis & Synthesis report.
1
Altera recommends that you avoid latches in your design; however, if latches are
necessary, Altera recommends using the LPM_LATCH megafunction.
f For more information about latches, refer to the Recommended HDL Coding Styles
chapter in volume 1 of the Quartus II Handbook.
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Combinational Loops
If your design consists of an intended combinational loop, you must define an
appropriate cut point for both the RTL and the post-fit .vo netlist. You can find a
warning indicating that a combinational loop exists in your design in the Formal
Verification subfolder of the Quartus II software Analysis & Synthesis report.
For more information about issues with combinational loops, refer to Known Issues
and Limitations on page 1716.
Encrypted IP functions
179
If your golden netlist (.vqm netlist from Synplify Pro or RTL) includes any design
entity not having a corresponding formal verification model, the software treats that
entity as a black box with its boundary interface preserved. Table 172 on page 179
lists three types of black boxes with corresponding required actions.
The Quartus II-generated .vo contains the black box hierarchy when you make an
EDA Formal Verification Hierarchy assignment with the value BLACKBOX.
If you do not make this assignment for a module, the Quartus II software implements
that module in logic cells. When this happens, the .vo netlist no longer contains the
black box hierarchy and does not preserve the port interface, resulting in a mismatch
in the Conformal LEC software.
Table 172. Black Boxes and Required Action
Type of Black Box
Required Action
You can also use the Quartus II GUI to set the black box property on the entities,
which the formal verification tool does not compare.
To preserve the boundary interface of an entity using the GUI, make an EDA Formal
Verification Hierarchy assignment to the entity with the value BLACKBOX.
Generating the Post-Fit Netlist Output File and the Conformal LEC Setup
Files
The following steps describe how to set up the Quartus II software environment to
generate the post-fit .vo netlist and the Conformal LEC script for use in formal
verification. With the exception of step 2, the steps are identical for both of the
synthesis tools:
To create a new Quartus II project or open an existing project, follow these steps:
1. On the Assignments menu, click Settings. The Settings dialog box appears.
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If you do not turn off Perform register retiming, an error occurs during
compilation: Physical Netlist Optimization Register retiming is not
supported by Formal Verification tool Conformal LEC.
7. Under Optimize for fitting (physical synthesis for density), turn off Perform
physical synthesis for combinational logic and Perform logic to memory
mapping to prevent the software from mapping logic to RAMs.
Retiming a design, either during the synthesis step or during the fitting step,
usually results in moving and merging registers along the critical path and is not
supported by the equivalence checking tools. Because equivalence checkers
compare the logic cone terminating at registers, do not use retiming to move the
registers during optimization in the Quartus II software.
f For more information about physical synthesis, refer to the Netlist Optimizations and
Physical Synthesis chapter in volume 2 of the Quartus II Handbook.
8. Perform a full compilation of your design. On the Processing menu, click Start
Compilation, or click the Start Compilation icon on the toolbar.
1711
Name
<proj rev>.ctc
Details
The <proj rev>.ctc references <proj rev>.clg and <proj rev>.clr that read the
library files and black box descriptions. The <proj rev>.ctc also references the
<proj rev>.cmc containing information about the mapped points.
Use the <proj rev>.ctc with the Conformal LEC software.
<proj rev>.cec
<proj rev>.cep
The <proj rev>.cep contains information for black box pin equivalences in your
design.
The <proj rev>.cmp contains information for the black box pin mapping
between the golden and revised sides.
<proj rev>.cmp
<proj rev>.cmc
The Quartus II software calls the <proj rev>.cmp from the <proj rev>.ctc script
file. By default, the line in which this file is called is commented out. This file is
useful only for HardCopy II device family.
The <proj rev>.cmc contains information about the additional points that the
Quartus II software maps in addition to the points that the tool selects.
This <proj rev>_trivial.cmc contains mapping information for all the key points
in your design.
Script file
<proj rev>_trivial.cmc
Sometimes, the Conformal LEC software performs incorrect key point mapping,
resulting in formal verification mismatches. To overcome the verification
mismatches, the Quartus II software writes out the <proj rev>_trivial.cmc that
contains mapping information for all the key points in your design. Reading this
file during the formal verification setup can result in increased run time.
Therefore, the Quartus II software writes out the top-level script file <proj
rev>.ctc with the command to read the <proj rev>_trivial.cmc commented out.
If the formal verification results are not acceptable, you can uncomment the
command and read the <proj rev>_trivial.cmc. The command in the <proj
rev>.ctc is:
//Trivial mappings with same name registers
//read mapped points $PROJECT/fv/conformal/<proj
rev>_trivial.cmc
blackboxes
directory
<proj rev>.clr
The <proj rev>.clr contains information about the macros and libraries for the
revised design.
<proj rev>.clg
The <proj rev>.clg contains information about the macros and libraries for the
golden design.
<project directory>/fv/
conformal/<project rev>_
blackboxes
This directory contains top-level module descriptions for all the user-defined
black box entities and contains modules with definitions other than Verilog HDL
or VHDL, for example, in your design directory
<project directory>/fv/conformal/<project rev>_blackboxes
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The script file contains the setup and constraints information to use with the formal
verification tool. The <entity>.v in the blackboxes directory contains the module
description of entities that you do not define in the formal verification library. The file
also contains entities that you treat as black boxes. For example, if a reference to a
black box for an instance of the ALTDPRAM megafunction in your design is present,
the blackboxes directory does not contain a module description for the ALTDPRAM
megafunction because you define the module description in the altdpram.v of the
formal verification library. When a module does not have an RTL description, or the
description exists only in the formal verification library and you do not want to
compare the module with formal verification, a file containing only the top-level
module description with port declaration is written out to the blackboxes directory
and read into the Conformal LEC software. To learn more about black boxes, refer to
Black Boxes in the Conformal LEC Flow on page 178.
You must update your project location when you move the files from the Windows
environment to the UNIX environment.
The post placement and routing netlist from the Quartus II software might contain net
and instance names that are slightly different from net and instance names of the
golden netlist. With the following command, the Quartus II software defines
temporary substitute string patterns enabling the Conformal LEC software to map
key points automatically when the names are different:
add renaming rule <rule>
1713
The Conformal LEC software employs three name-based methods to map key points
to compare the revised netlist with the golden netlist. Scripts set the correct method to
get the best results.
set mapping method <mapping_rule>
The Quartus II software performs several optimizations, including optimizing the
registers whose input is driven by a constant. Under these circumstances, for the
formal verification software to compare the netlists properly, use the command set
flatten model with the option seq_constant.
set flatten model <flattening_rule>
When you use the report black box command, verify that the software lists the
following modules as black boxes, along with any of the modules that you treat as
black boxes in the golden and revised netlists:
Encrypted IP functions
Use the following command to set the same implementation on multipliers for both
the golden and revised netlists:
set multiplier implementation <implementation_name>
If combinational loops or instances of LPM_LATCH are present, the Quartus II software
cuts the loop at the same point using the following command on both the golden and
revised netlists:
add cut point
The Conformal LEC software does not always automatically map all the key points, or
can incorrectly map some key points. To help the Conformal LEC software
successfully complete the mapping process, the Quartus II software records
optimizations performed on the netlist as a series of add mapped points in the
Conformal LEC <file_name>.cmc script.
add mapped points <key_points>
When the software moves the inverter before the register to after the register, use the
following command:
add mapped points <key_points> -invert
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The following command reads in the mapped point information from the specified
file:
read mapped points <file_name>.cmc
Figure 173. Instance Equivalence
Golden
Revised
U1
DFF
U1
PO
U2
DFF
PO
DFF
During optimization, the Quartus II software might merge two registers into one
(Figure 173). The Quartus II software informs the formal verification tool that the U1
and U2 registers are equivalent to each other using the following command:
add instance equivalence <instance_pathname ..> [-golden]
When register duplication happens, use the following command:
add instance equivalence <instance_pathname ..> [-revised]
When the software moves the inverter beyond the register along with either register
duplication or merging, use the following command:
add instance equivalences <instance_pathname>
[-invert <instance_pathname>]
Sometimes, the software drives the register output to a constant, either logic 0 or
logic 1. The Quartus II software sets the value of the register to a constraint using the
add instance constraint command. For more information about this command,
refer to Fixed-Output Registers on page 176.
add instance constraint <constraint_value>
1715
To get a downloadable design example showing the formal verification flow with
Quartus II software, refer to the Formal Verification Design Example page of the
Altera website.
f For more information about the latest debugging tips and solutions for formal
verification flow between the Conformal LEC software and the Quartus II software,
go to www.altera.com and perform an advanced search with keywords formal
verification.
June 2012
Altera Corporation
1716
When a port on a black box entity drives two or more signals in the black box, the
Quartus II software pushes the connections outside of the black box, and creates
the same number of ports on the black box. This problem occurs only in Stratix II
and HardCopy II designs.
The Quartus II software names the additional ports on the black box as
_unassoc_inputs_[] and _unassoc_outputs_[] (Figure 174). This issue occurs
with reset and enable signals. Figure 174 shows an example in which the reset pin
splits into two ports outside of the black box and the clkctrl block drives the
_unassoc_inputs_[] port. In such situations, the Quartus II-generated .vo netlist
has signals driving these black box ports, but the golden RTL does not contain any
signals to drive the _unassoc_inputs_[] port, which results in a formal
verification mismatch of the black box. The black box module definition that the
Quartus II software generates in the
<Quartus_project>\fv\conformal\*_blackboxes directory contains these
additional _unassoc_inputs_[] and _unassoc_outputs_[] ports. The Quartus II
software reads this black box module on the golden and revised sides of your
design, which results in unconnected ports on the golden side and formal
verification mismatches.
Figure 174 shows the creation of the _unassoc_inputs_[] and
_unassoc_outputs_[] ports for the reset signal.
reset
clkctrl
_unassoc_inputs_[ ]
_unassoc_outputs_[ ]
1717
Signal A
Signal A
_unassoc_inputs_[ ]
Black Box
In designs with combinational feedback loops, the Conformal LEC software can
insert extra cut points in the revised netlist, causing unmapped points and
ultimately verification mismatches.
For Cyclone II designs, the Conformal LEC software might report non-equivalent
flipflops and extra cut points for the revised (post-fit) design under the following
conditions:
When your HDL source code instantiates the lpm_ff primitive with an
asynchronous load signal aload (with or without any other asynchronous
control signals) and;
When you use the asynchronous clear signal aclr and asynchronous set signal
aset together.
To avoid this problem, ensure that a wrapper module or entity is present around
the lpm_ff instantiation, and black box the module or entity that instantiates the
lpm_ff primitive.
June 2012
Altera Corporation
For Stratix III designs, the Conformal LEC software creates cut points for the
combinational loops on the golden side and might fail equivalence checking due
to improper mapping. The combinational loops are due to logic around the
registers emulating multiple sets, resets, or both. The Quartus II software reports
these cut points with warning messages during mapping. You can add Conformal
LEC commands manually to add cut points, which can result in proper mapping
and formal verification.
1718
To perform formal verification, the Quartus II software turns off certain synthesis
optimization options (such as register retiming, optimization through black box
hierarchy boundaries, and disabling the ROM and shift register inference), which
can have an impact on the area resource and performance.
1
When you do not verify RAM and ROM instantiations, inferences, or both using
formal verification.
Formal verification does not support clear box netlists due to unconnected ports
on its WYSIWYG instances.
When a black box contains bidirectional ports, the Quartus II software does not
reconstruct the hierarchy. Therefore, a flat netlist represents the black box, which
results in formal verification mismatches.
You must treat ROMs as black boxes in your design before compilation with
Quartus II integrated synthesis, because the Quartus II software might perform
some optimizations on the ROM, resulting in formal verification mismatches.
Unused logic optimized in and around a black box by the Quartus II software can
result in a black-box interface different from the interface in the synthesized .vqm
netlist.
1719
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1721
Conclusion
Formal verification software enables verification of your design during all stages,
from RTL to placement and routing. Verifying designs requires more time as designs
increase in size. Formal verification helps to reduce the time needed for your design
verification cycle.
Version
June 2012
12.0.0
November 2011
11.1.0
Changes
Updated Black Boxes in the Conformal LEC Flow on page 178 and Known Issues and
Limitations on page 1716.
Removed Figures.
December 2010
10.1.0
July 2010
10.0.0
November 2009
9.1.0
March 2009
9.0.0
November 2008
May 2008
8.1.0
8.0.0
Added support for Cadence Conformal LEC version 7.2 and Synplify Pro version 9.6.2.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
June 2012
Altera Corporation
1722
The Quartus II software offers a complete software solution for system designers
who design with Altera FPGA and CPLD devices, including device programming.
The Quartus II Programmer is part of the Quartus II software package that allows you
to program Altera CPLD and configuration devices, and configure Altera FPGA
devices. This section describes how you can use the Quartus II Programmer to
program or configure your device after you successfully compile your design.
This section includes the following chapter:
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
This chapter describes how to program and configure Altera CPLD, FPGA, and
configuration devices with the Quartus II Programmer.
The Quartus II software offers a complete solution for system designers who design
with Altera FPGA and CPLD devices. After you compile your design, you can use the
Quartus II Programmer to program or configure your device, to test its functionality
on a circuit board.
This chapter contains the following sections:
Programming Flow
h For more information about how to use the Quartus II Programmer GUI to program
and configure your device, refer to Programming Devices in Quartus II Help.
Programming Flow
The following steps describe the general overview of the programming flow:
1. Compile your design, such that the Quartus II Assembler generates the
programming or configuration file.
2. Convert the programming or configuration file to target your configuration device
and, optionally, create secondary programming files.
3. Program and configure the FPGA, CPLD, or configuration device using the
programming or configuration file with the Quartus II Programmer.
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
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182
Table 181 lists the programming and configuration file formats supported by Altera
FPGAs, CPLDs, and configuration devices.
Table 181. Programming and Configuration File Format
FPGA
CPLD
Configuration
Device
Serial
Configuration
Device
File Format
FPGA
.sof
Convert
Programming Files
EPC or
EPCS
.pof
CPLD
.pof
Create Optional
Programming Files
.jam
.jbc
.cdf
Quartus II Programmer
h For more information about Chain Description Files (.cdf), refer to About Programming
in Quartus II Help.
183
Open Quartus II
Programmer
Hardware setup
Select programming/
configuration mode
Specify programming/
configuration file
Need to bypass
another device
in the chain?
No
Yes
Select programming/
configuration options
Start operation
Finish
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184
Hardware Setup
The Quartus II Programmer provides the flexibility to choose a download cable or
programming hardware. Before you can program or configure your device, you must
have the correct hardware setup.
h For hardware settings, refer to Setting Up Programming Hardware in Quartus II Help.
f For more information about programming hardware driver installation, refer to the
Setting up Programming Hardware in Quartus II Software page on the Altera
website.
JTAG Settings
The JTAG server allows the Quartus II Programmer to access the JTAG hardware. You
can also access the JTAG download cable or programming hardware connected to a
remote computer through the JTAG server of that computer. With the JTAG server,
you can control the programming or configuration of devices from a single computer
through other computers at remote locations. The JTAG server uses the TCP/IP
communications protocol.
h For more information about JTAG settings, refer to Using the JTAG Server in Quartus II
Help.
185
Configuration Modes
The Quartus II Programmer supports five configuration modes, including JTAG,
passive serial (PS), active serial (AS), Configuration via Protocol (CvP), and in-socket
modes (ISM).
Table 182 lists the programming and configuration modes supported by Altera
devices.
Table 182. Programming and Configuration Modes
FPGA
CPLD
Configuration Device
Serial Configuration
Device
JTAG
PS
Mode
AS
CvP
In-Socket Programming
v (1)
h For more information about programming and configuration modes, refer to About
Programming in Quartus II Help.
f For more information about CvP configuration mode, refer to the Configuration via
Protocol (CvP) Implementation in Altera FPGAs User Guide.
f For more information about JTAG, PS, and AS configuration modes and in-socket
programming mode, refer to the Configuration Handbook, or the device handbook or
data sheet for the respective FPGA, CPLD, or configuration device.
f For a list of programming adapters available for Altera devices, refer to
www.altera.com.
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186
.sof
.pof
.jam
.jbc
JTAG Indirect
Configuration File (.jic)
In System Configuration
File (.isc)
File Type
187
Table 183. File Types Generated by the Quartus II Software and Supported by the Quartus II
Programmer (Part 2 of 2)
Generated by the Quartus II
Software
Hexadecimal
(Intel-Format) Output
File (.hexout)
File Type
November 2012
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188
When you change settings in the Advanced Options dialog box, the change affects
.pof, .jic, .rpd, and .rbf files. Table 184 lists the Advanced Options settings in more
detail.
Table 184. Advanced Options Settings
Option Setting
Description
Disable AS mode
CONF_DONE error check
Applies to the single- and multi-device AS configuration modes on all FPGA devices.
Applies to single- and multi-device (AS) configuration modes on all FPGA devices.
The CONF_DONE error check is disabled by default for Stratix V, Arria V, and Cyclone V
devices for AS-PS multi device configuration mode.
Specifies the offset you can apply to the computed PLC of the entire bitstream.
Applies to single- and multi-device (AS) configuration modes on all FPGA devices.
Specifies the number of pad bytes appended to the end of an entire bitstream.
Default value is set to 0 if the bitstream of the last device is uncompressed. Set to 2 if the
bitstream of the last device is compressed.
Specifies the number of pad bytes appended to the end of the bitstream of a device.
Specifies the padding value used to prepare bitslice configuration bitstreams, such that all
bitslice configuration chains simultaneously receive their final configuration data bit.
Use only in 2, 4, and 8-bit PS configuration mode, when you use an EPC device with the
decompression feature enabled.
Table 185 lists symptoms you may encounter if a configuration fails, and describes
the advanced options you must use to debug your configuration.
Table 185. Failure Symptoms and Options Settings (Part 1 of 2)
Failure Symptoms
Configuration failure
occurs after a
configuration cycle.
Decompression feature is
enabled.
Disable EPCS
ID Check
Disable AS
Mode
CONF_DONE
Error Check
PLC Settings
Post-Chain
Bitstream
Pad Bytes
Post-Device
Bitstream
Pad Bytes
Bitslice
Padding
Value
189
Failure Symptoms
Disable EPCS
ID Check
Encryption feature is
enabled.
Disable AS
Mode
CONF_DONE
Error Check
PLC Settings
v
v
Post-Chain
Bitstream
Pad Bytes
Post-Device
Bitstream
Pad Bytes
Bitslice
Padding
Value
(Start with
positive
offset to the
PLC settings)
v
(Start with
negative
offset to the
PLC settings)
v
(Use only for
single-device
chain)
v
(Use only for
multi-device
chain)
Configuration failure
occurs at the beginning of
a configuration cycle.
h For more information about the Convert Programming Files dialog box, refer to
Convert Programming Files Dialog Box in Quartus II Help.
November 2012
Altera Corporation
1810
Partial-Masked SRAM Object File (.pmsf) output file generation, with .msf and
.sof as input files.
.rbf for Partial Reconfiguration output file generation, with a.pmsf as the input
file.
1
The .rbf for Partial Reconfiguration file is only for Partial Reconfiguration.
f For more information about Partial Reconfiguration, refer to the Design Planning for
Partial Reconfiguration chapter in volume 1 of the Quartus II Handbook.
Generating .pmsf using a .msf and a .sof
You can generate a .pmsf with a .msf and a .sof. in the Convert Programming Files
dialog box.
To generate the .pmsf in the Convert Programming Files dialog box, follow these
steps:
1. In the Convert Programming Files dialog box, under the Programming file type
field, select Partial-Masked SRAM Object File (.pmsf).
2. In the File name field, specify the necessary output file name.
3. In the Input files to convert field, add necessary input files to convert. You can
add only a .msf and .sof.
4. Click Generate to generate the .pmsf.
1811
Figure 183. Generating .pmsf in the Convert Programming Files Dialog Box
November 2012
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1812
f For more information about these option, refer to the Design Planning for
Partial Reconfiguration chapter in volume 1 of the Quartus II Handbook.
6. Click OK.
7. Click Generate to generate the .rbf for Partial Reconfiguration.
1813
Figure 184. Generating .rbf for Partial Reconfiguration in the Convert Programming Files Dialog Box
November 2012
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1815
Flash Loaders
Parallel and serial configuration devices do not support the JTAG interface. However,
you can use a flash loader to program configuration devices in-system via the JTAG
interface. You can use an FPGA as a bridge between the JTAG interface and the
configuration device. The Quartus II software supports parallel and serial flash
loaders.
h For more information, refer to About Flash Loaders in Quartus II Help.
Scripting Support
In addition to the Quartus II Programmer GUI, you can use the Quartus II
command-line executable quartus_pgm.exe to access programmer functionality from
the command line and from scripts. The programmer accepts .pof, .sof, and .jic
programming or configuration files and Chain Description Files (.cdf).
Example 181 shows a command that programs a device:
Example 181. Programming a Device
quartus_pgm c byteblasterII m jtag o bpv;design.pof r
Where:
The Programmer automatically executes the erase operation before programming the
device.
h For more information about scripting command options, refer to About Quartus II
Scripting in Quartus II Help.
November 2012
The help switch does not reference the -n switch. The jtagconfig -n command
shows each node for each jtag device.
Altera Corporation
1816
You must run this command in the same directory where the files are located.
Conclusion
The Quartus II Programmer offers you a wide variety of options to program and
configure your Altera devices. With the Quartus II Programmer, the Quartus II
software provides you with a complete solution for your FPGA or CPLD design
prototyping, which you can also use in the production environment.
November 2012
June 2012
November 2011
Version
Changes
Updated Table 183 on page 186, and Table 184 on page 188.
12.1.0
12.0.0
11.1.0
1817
11.0.0
December 2010
10.1.0
July 2010
10.0.0
November 2009
9.1.0
March 2009
9.0.0
Updated Hardware Setup on page 214 and JTAG Chain Debugger Tool on
page 214.
Reorganized chapter.
No change to content.
Updated figures.
f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook
Archive.
November 2012
Altera Corporation
1818
Additional Information
This chapter provides additional information about the document and Altera.
Contact Method
Address
Website
www.altera.com/support
Website
www.altera.com/training
Email
Website
custrain@altera.com
www.altera.com/literature
nacomp@altera.com
(software licensing)
authorization@altera.com
Note to Table:
(1) You can also contact your local Altera sales office or sales representative.
May 2013
Altera Corporation
Info2
Additional Information
Typographic Conventions
Typographic Conventions
The following table shows the typographic conventions this document uses.
Visual Cue
Meaning
Indicate command names, dialog box titles, dialog box options, and other GUI
labels. For example, Save As dialog box. For GUI elements, capitalization matches
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bold type
Indicates directory names, project names, disk drive names, file names, file name
extensions, software utility names, and GUI labels. For example, \qdesigns
directory, D: drive, and chiptrip.gdf file.
italic type
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Indicate keyboard keys and menu names. For example, the Delete key and the
Options menu.
Subheading Title
Courier type
Indicates command line commands and anything that must be typed exactly as it
appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.
Also indicates sections of an actual file, such as a Report File, references to parts of
files (for example, the AHDL keyword SUBDESIGN), and logic function names (for
example, TRI).
Numbered steps indicate a list of items when the sequence of the items is important,
such as the steps listed in a procedure.
Bullets indicate a list of items when the sequence of the items is not important.
The question mark directs you to a software help system with related information.
The feet direct you to another document or website with related information.
A warning calls attention to a condition or possible situation that can cause you
injury.
The envelope links to the Email Subscription Management Center page of the Altera
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Methods for collecting feedback vary as appropriate for each document.
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