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ALC655
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ALC655
0. Revision History
Version 0.30: Preliminary version
Version 0.40:
1.Update application circuit for automatic jack sensing function.
2.Add a FRONT-MIC2 for stereo microphone input for front panel application. (Ver.D or later)
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Version 1. 0:
Just change Version from 0.4 to 1.0
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ALC655
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2. General Description
The ALC655 is a 16-bit, full duplex AC'97 2.3 compatible six channels audio CODEC designed for PC multimedia systems,
including host/soft audio and AMR/CNR based designs. The ALC655 incorporates proprietary converter technology to meet
performance requirements on PC99/2001 systems. The ALC655 CODEC provides three pairs of stereo outputs with 5-Bit
volume controls, a mono output, and multiple stereo and mono inputs, along with flexible mixing, gain and mute functions to
provide a complete integrated audio solution for PCs. The digital interface circuitry of the ALC655 CODEC operates from a
3.3V power supply for use in notebook and PC applications. The ALC655 integrates 50mW/20ohm headset audio amplifiers at
Front-Out and Surr-Out, built-in 14.318M 24.576MHz PLL and PCBEEP generator, those can save BOM costs. The ALC655
also supports the S/PDIF input and output function, which can offer easy connection of PCs to consumer electronic products, such
as AC3 decoder/speaker and mini disk devices. ALC655 supports host/soft audio from Intel ICHx chipsets as well as audio
controller based VIA/SIS/ALI/AMD/nVIDIA/ATI chipset. Bundled Windows series drivers (WinXP/ME/2000/98/NT), EAX/
Direct Sound 3D/ I3DL2/ A3D compatible sound effect utilities (supporting Karaoke, 26-kind of environment sound emulation,
10-band equalizer), HRTF 3D positional audio and Sensaura 3D (optional) provide an excellent entertainment package and
game experience for PC users. Besides, ALC655 includes Realteks impedance sensing techniques that makes device load on
outputs and inputs can be detected.
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1. Features
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AUX-IN
CD-IN
mono analog
stereo analog
stereo digital
MX6A.9
MX20.8
* : default setting
SURR-OUT
LINE-IN
Front-MIC
PHONE
MIC1 MX6A.10
CEN-OUT
MIC2
LFE-OUT
PC-BEEP
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MX74.0
+20dB
+20dB
DAC
DAC
DAC
MX16
MX12
MX10
MX0E
MX0C
MX0A
MX18
MX64
MX66
MX6A.0
MX1C
Record
Gain
MX20.9
MX1A
M
U
X
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aux
stereo mix
mono mix
phone
mic-L
mic-R
line
CD
MX6A.4
MX6A.5
ADC
Mono
Volume
MX06
Master
Volume
MX02
Amp
Amp
ALC655
PCM in
FRONT-OUT
SURR-OUT
CEN/LFE-OUT (43,44)
MONO-OUT
RESET#
PCBEEP
Surround
Volume
MX38
Center/LFE
Volume
MX36
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ALC655
3. Block Diagram
Rev1.01
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ALC655
FRONT-OUT-R
FRONT-OUT-L
FRONT-MIC1
NC
FRONT-MIC2
VRDA
AFILT2
AFILT1
VREFOUT
VREF
AVSS1
AVDD1
4. Pin Assignments
ALC655
1 2 3 4 5 6 7 8 9 10 11 12
24
23
22
21
20
19
18
17
16
15
14
13
LINE-IN-R
LINE-IN-L
MIC2
MIC1
CD-R
CD-GND
CD-L
JD1/GPIO1
JD2
AUX-R
AUX-L
PHONE
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36 35 34 33 32 31 30 29 28 27 26 25
37
38
39
40
41
42
43
44
45
46
47
48
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DVDD1
XTL-IN
XTL-OUT
DVSS1
SDATA-OUT
BIT-CLK
DVSS2
SDATA-IN
DVDD2
SYNC
RESET#
PC-BEEP
MONO-OUT
AVDD2
SURR-OUT-L
NC
SURR-OUT-R
AVSS2
CEN-OUT
LFE-OUT
JD0/GPIO0
XTLSEL
SPDIFI/EAPD
SPDIFO
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ALC655
5. Pin Description
5.1 Digital I/O Pins
Name
XTL-IN
XTL-OUT
SDATAOUT
BIT-CLK
Type
I
O
I
Pin No
2
3
5
Description
Crystal input pad (24.576Mhz)
Crystal output pad
Serial TDM AC97 output
Characteristic Definition
Crystal input pad
Crystal output pad
CMOS input
IO
SDATA-IN
SYNC
RESET#
JD1/GPIO1
I
I
I/O
10
11
17
JD2
JD0/GPIO0
I
I/O
16
45
XTLSEL
SPDIFI /
EAPD
SPDIFO
I
I/O
46
47
48
Digital output
TOTAL: 13 Pins
XTLSEL=floating, bypass 14.318MHz 24.576MHz digital PLL. The clock source is 24.576MHz crystal or external clock.
XTLSEL=pull low, select 14.318MHz 24.576MHz digital PLL
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Type
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I
I
Pin No
12
13
14
15
18
19
20
21
22
23
24
34
32
LINE-OUT-L
LINE-OUT-R
MONO-OUT
S-OUT-L
S-OUT-R
CEN-OUT
LFE-OUT
O
O
O
O
O
O
O
35
36
37
39
41
43
44
Description
PC speaker input
Speaker phone input
AUX Left channel
AUX Right channel
CD audio Left channel
CD audio analog GND
CD audio Right channel
First Mic in / CEN-OUT
Secondary Mic in / CEN-OUT
Line-In Left channel / S-OUT-L
Line-In Right channel/ S-OUT-R
Dedicated MIC Input 1
Dedicated MIC Input 1
(Supported by D version or later)
Line-Out Left channel
Line-Out Right channel
Speaker Phone output
Surround Out Left channel
Surround Out Right channel
Center Out channel
Low Frequency Effect Out
channel
Characteristic Definition
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms)
Analog input (1Vrms) / Analog output (1Vrms)
Analog input (1Vrms) / Analog output (1Vrms)
Analog input (1Vrms) / Analog output (1Vrms)
Analog input (1Vrms) / Analog output (1Vrms)
Analog input (1Vrms) for front panel MIC input
Analog input (1Vrms) for front panel MIC input
Analog output (1Vrms)
Analog output (1Vrms)
Analog output (1Vrms)
Analog output (1Vrms)
Analog output (1Vrms)
Analog output (1Vrms)
Analog output (1Vrms)
TOTAL: 20 Pins
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ALC655
5.3 Filter/Reference
Name
VREF
VREFOUT
AFILT1
AFILT2
VRDA
NC
Type
O
O
O
O
O
Pin No
27
28
29
30
31
33,40
Description
Reference voltage
Ref. voltage out with 5mA drive
ADC anti-aliasing filter capacitor
ADC anti-aliasing filter capacitor
Vref for DAC
Not connected
Characteristic Definition
Analog output. +4.7uf and 0.1uf cap to AVSS
Analog output (2.5V/4.0V)
1nf cap to AVSS
1nf cap to AVSS
1uf cap to AVSS
TOTAL: 7 Pins
5.4 Power/Ground
Type
I
Pin No
25
Description
Analog VDD (5.0V)
AVDD2
38
AVSS1
AVSS2
DVDD1
I
I
I
26
42
1
Analog GND
Analog GND
Digital VDD (3.3V)
DVDD2
DVSS1
DVSS2
I
I
4
7
Digital GND
Digital GND
Characteristic Definition
The minimum value is 3.0V
The maximum value is 5.5V
The minimum value is 3.0V
The maximum value is 5.5V
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Name
AVDD1
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TOTAL: 8 Pins
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ALC655
6. Registers
6.1 Mixer Registers
Access to registers with an odd number will return a 0. Reading unimplemented registers will also return a 0.
REG. NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT
(HEX)
06h
0Ah
0Ch
0Eh
10h
12h
16h
18h
1Ah
1Ch
20h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
36h
38h
3Ah
64h
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66h
6Ah
7Ah
7Ch
7Eh
Reset
Master
Volume
Mono-Out
Volume
PC_BEEP
Volume
PHONE
Volume
MIC Volume
Line-In
Volume
CD Volume
Aux Volume
PCM Out
Volume
Record Select
Record Gain
General
Purpose
Audio Int. &
Paging
Power Down
Ctrl/Status
Extended
Audio ID
Extended
Audio Status
PCM front
Sample Rate
PCM Surr.
Sample Rate
PCM LFE.
Sample Rate
PCM Input
Sample Rate
Center/LFE
Volume
Surround
Volume
S/PDIF Ctl
0
Mute
0
X
0
X
Mute
Mute
F7
F6
F5
F4
F3
Mute
Mute
Mute
X
X
X
X
X
NL4
X
NL3
X
NL2
Mute
Mute
Mute
X
X
X
X
X
X
CL4
AL4
PL4
CL3
AL3
PL3
CL2
AL2
PL2
X
Mute
X
X
X
X
X
X
X
X
X
X
I4
I3
I2
I1
I0
EAPD
PR5
PR4
PR3
PR2
PR1
PR0
REV1 REV0
PRK
PRJ
PRI SPCV
Mute
Mute
0
0
0
0
0
0
ML4 ML3 ML2 ML1 ML0 Mute*
*
X
X
X
X
X
X
0
X
0
X
0
0
0
0
0
MR4 MR3 MR2 MR1 MR0
0000h
8000h
8000h
F2
F1
F0
PB3
PB2
PB1
PB0
8000h
PH4
PH3
PH2
PH1
PH0
8008h
X
NL1
X
NL0
X
X
20dB
X
X
X
MI4
NR4
MI3
NR3
MI2
NR2
MI1
NR1
MI0
NR0
8008h
8808h
CL1
AL1
PL1
CL0
AL0
PL0
X
X
X
X
X
X
X
X
X
CR4
AR4
PR4
CR3
AR3
PR3
CR2
AR2
PR2
CR1
AR1
PR1
CR0
AR0
PR0
8808h
8808h
8808h
X
X
X
X
X
X
X
X
X
PG3
PG0
0000h
000Fh
PG1
0000h
8000h
0000h
SPDIF
VRA
09C4h
SPDIF
VRA
0040h
BB80h
BB80h
BB80h
BB80h
8080h
8080h
CC3
CC2
CC1
CC0
2000h
SPSR1 SPSR0
CC6
CC5
CC4
LD4
LD3
LD2
LD1
LD0
CD4
CD3
CD2
CD1
CD0
0808h
0000h
60A2h
1
1
0
0
0
0
0
0
0
1
0
1
1
1
0
0
1
1
0
1
0
0
1
0
1
0
0
0
0
0
414Ch
4760h
0808h
X: reserved bit
*: MX36 is the master volume control of CENTER/LFE output.
MX38 is the master volume control of surround output.
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00h
02h
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ALC655
Default: 8000H
These registers control the volume level of Front-Out. Each step on the left and right channels correspond to 1.5dB in
increase/decrease in volume.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (- dB)
14:13
Reserved
12:8
R/W Master Left Volume (ML[4:0]) in 1.5 dB steps
7:5
Reserved
4:0
R/W Master Right Volume (MR[4:0]) in 1.5 dB steps
For MR/ML, 00h 0 dB
1Fh 46.5 dB attenuation
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Default: 8000H
Register 06H controls the mono volume output. Mono output is the same data sent on all output channels. Each step in bits 0:4
correspond to 1.5dB in increase/decrease in volume, allowing 32 levels of volume from 00000 to 11111.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (- dB)
14:5
Reserved
4:0
R/W Mono Master Volume (MM[4:0]) in 1.5 dB steps
For MM, 00h
0 dB attenuation
1Fh
46.5 dB attenuation
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ALC655
The purpose of this register is to allow the PC Beep signals to pass through the ALC655, eliminating the need for an external system
speaker/buzzer. The PC BEEP pin is directly routed (internally hardwired) to the Front-Out. If the PC speaker/buzzer is eliminated, it is
recommended to connect the external speakers at all times so the POST codes can be heard during reset.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (- dB)
14:13
Reserved
12:5
R/W Internal PCBEEP Frequency, F[7:0]
The internal PCBEEP frequency is the result of dividing the 48KHz clock by 4 times the number
specified in F[7:0].
The lowest tone is 48KHz/(255*4)=47Hz.
The highest tone is 48KHz/(1*4)=12KHz.
A value of 00h in F[7:0] disables internal PCBEEP generator and allows external PCBEEP input.
4:1
R/W PC Beep Volume (PBV[3:0]) in 3 dB steps
0
Reserved
For PB,
00h
0 dB attenuation
0Fh
45 dB attenuation
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Default: 8008H
Register 0EH controls the microphone input volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume,
allowing 32 levels of volume, from 00000 to 11111. Each step in bit 6 corresponds to a magnification of 20dB increase in volume.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (- dB)
14:7
Reserved
6
R/W 20 dB Boost Control 0: Normal 1: 20 dB boost
5
Reserved
4:0
R/W Mic Volume (MV[4:0]) in 1.5 dB steps
For MV,
00h
+12 dB Gain
08h
0dB gain
1Fh
-34.5dB Gain
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Default: 8008H
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ALC655
15
14:13
12:8
7:5
4:0
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Register 16H controls the auxiliary input volume. Each step in bits 4:0 correspond to 1.5dB in increase/decrease in volume for the
right channel, allowing 32 levels of volume, from 00000 to 11111. Each step in bits 12:8 correspond to 1.5dB in increase/decrease in
volume for the left channel, allowing 32 levels of volume, from 00000 to 11111.
Bit
Type
Function
15
R/W Mute Control 0: Normal 1: Mute (- dB)
14:13
Reserved
12:8
R/W AUX Left Volume (AL[4:0]) in 1.5 dB steps
7:5
Reserved
4:0
R/W AUX Right Volume (AR[4:0]) in 1.5 dB steps
For AL/AR,
00h +12 dB Gain
08h 0dB gain
1Fh -34.5dB Gain
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Default: 8808H
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ALC655
For PL/PR,
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Default: 0000H
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ALC655
This register is used to control several functions. Bit 13 enables or disables 3D control. Bit 9 allows selection of mono output.
Bit 8 controls the mic selector. Bit 7 enables loopback of the AD output to the DA input without involving the AC-Link,
allowing for full system performance measurements.
Bit
15:12
11:10
9
8
7
6:0
Type
R
Function
Reserved, Read as 0
DRSS[1:0], Double Rate Slot Select
01: PCM(n+1) data is on Slots 7/8 (Default)
00,10,11: Reserved
R/W Mono Output Select 0: MIX 1: MIC
R/W Mic Select MIC select 0: MIC 1+(Front-MIC)
1: MIC2+ (Front-MIC)
R/W AD to DA Loop-Back Control 0: Disable 1: Enable
Reserved
Bit 7 enables ADC to front DAC loop-back.
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Default: 0000h
Type
14
13
12
R/W
11
R/W
10:4
3:0
NA
R/W
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Function
Interrupt Status, I4
0: Interrupt is clear.
1: Interrupt was generated
Interrupt event and status are clear by writing a 1 to this bit. The status will change regardless of interrupt
enable (I0).
Interrupt Cause, I3
Reserved, read as 0
Interrupt Cause, I2
I2=0: Sense value in page ID-01h MX6A.[12:8] has not changed.
1: Sense cycle completed or new sense value in page ID-01h MX6A.[12:8] is available.
This bit reflects the cause of the first interrupt event generated. Software should read it after interrupt
status (I4) has been confirmed as interrupting. I2 will be zero when I4 is cleared.
Sense Cycle, I1
0: Sense cycle not in progress
1: Sense cycle start
Writing a 1 to this bit causes a sense cycle start. If a sense cycle is in progress, writing a 0 to this bit
will abort the sense cycle.
Whether the data in the sense result register (page ID-01h MX6A) is valid or not is determined by the IV
bit in MX6A, Page ID-1h.
Interrupt Enable, I0
0: Interrupt is masked, interrupt status (I4) will not be shown in bit 0 in Slot 12 in SDATA-IN.
1: Interrupt is un-masked, interrupt status (I4) will be shown in bit 0 in Slot 12 in SDATA-IN.
In ALC655, this bit controls the interrupt of sense cycle.
Reserved, read as 0
Page Selector, PG[3:0]
0000b: Vendor Specific
0001b: Page ID 01 (AC97 2.3 Discovery Descriptor Definition)
Others: Reserved.
This register is used to select a descriptor of 16 word pages between registers MX60 to MX6F. Value of
0 is used to select vendor specific space to maintain compatibility with AC97 2.2 vendor specific
register. Once PG[3:0] is not 0000b and 0001b, ALC655 will return zero data for ACLINK mixer read
command.
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Bit
15
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ALC655
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When the AC-Link CODEC Ready indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the AC-Link and AC97
control and status registers are in a fully operational state. The AC97 controller must further probe this powerdown control
/status register to determine exactly which subsections, if any are ready.
Type
R/W
14
13
R/W
12
11
10
9
8
7:4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R
R
R
R
Function
PR7 External Amplifier Power Down (EAPD)
0: EAPD output low (enable external amplifier)
1: EAPD output high (shut down external amplifier)
Reserved
PR5 0: Normal
1: Disable internal clock usage (BCLK still be output for modem CODEC)
PR4 0: Normal 1: Power down AC-Link
PR3 0: Normal 1: Power down Mixer (Vref off)
PR2 0: Normal 1: Power down Mixer (Vref still on)
PR1 0: Normal 1: Power down PCM DAC (front DAC)
PR0 0: Normal 1: Power down PCM ADC and input MUX
Reserved, Read as 0
Vref Status 1: Vref is up to normal level 0: Not yet
Analog Mixer Status 1: Ready 0: Not yet
DAC Status 1: Ready 0: Not yet
ADC Status 1: Ready 0: Not yet
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Bit
15
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ALC655
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This register contains two active bits for powerdown and status of the surrounding DACs. Bits 1 & 2 are read/write bits which are
used to enable or disable DRA and SPDIF respectively. Bits 4 & 5 are read/write bits used to determine the AC-LINK slot
assignment of the S/PDIF. Bits 6, 7 & 8 are read only bits which tell the controller when the Center, Surround and LFE DACs are
ready to receive data. Bit 10 is a read only bit which tells the controller if the S/PDIF configuration is valid. Bits 11, 12 & 13 are
read/write bits which are used to powerdown the Center, Surround and LFE DACs respectively.
Bit
Type
Function
15
R/W VCFG, Validity Configuration of S/PDIF Output
Combined with MX3A.15 to decide validity control in S/PDIF output signal.
14
Reserved.
13
R/W Power Down LFE DAC. (PRK)
0: Normal
1: Power down LFE DAC
12
R/W Power Down Surround DAC. (PRJ)
0: Normal
1: Power down Surround DAC
11
R/W Power Down Center DAC. (PRI)
0: Normal
1: Power down Center DAC
10
R
SPCV (S/PDIF Configuration Valid)
0: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is not valid
1: Current S/PDIF configuration {SPSA,SPSR,DAC/slot rate} is valid
9
Reserved
8
R
LFE DAC Status (LDAC).
0: Not yet
1: Ready
7
R
Surround DAC Status (SDAC). 0: Not yet
1: Ready
6
R
Center DAC Status (CDAC).
0: Not yet
1: Ready
5:4
R/W SPSA[1:0] (S/PDIF Slot Assignment)
00: S/PDIF source data assigned to AC-LINK slot3/4
01: S/PDIF source data assigned to AC-LINK slot7/8
10: S/PDIF source data assigned to AC-LINK slot6/9
11: S/PDIF source data assigned to AC-LINK slot10/11 (default)
3
Reserved
2
R/W SPDIF Enable. 1: Enable 0: Disable (Hi-Z)
1
R/W DRA Enable. 1: Enable 0: Disable
0
Reserved.
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Default: 05F0H
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ALC655
SPCV is a read only bit that indicates whether the current S/PDIF-Out configuration is
supported or not. If the configuration is supported, SPCV is set as 1 by H/W. So driver can
check this bit to determine the status of the S/PDIF transmitter system. SPCV is always
operating, independent of the SPDIF enable bit (MX2A.2). The S/PDIF output is active if
MX2A.2 is set in spite of SPCV. Once S/PDIF output is enabled but SPCV is invalid
(SPCV=0), channel status is still output, but the output data bits will be all zero. The condition
to allow S/PDIF output is SPDIF(MX2A.2)=1 & SPACV=1, otherwise the S/PDIF
output will be all zero when MX2A.2=1 and SPACV=0 (invalid).
Only front DACs supports 96KHz sample rate when DRA=1. MX2A.1 just selects clock source
for front DACs. Software must mute surround DACs and CEN/LFE DACs.
Type
R
Function
Read as BB80h. (ALC655 supports 48KHz sample rate.)
Function
Read as BB80h. (ALC655 supports 48KHz sample rate.)
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Bit
15:0
Type
R
Function
Read as BB80h. (ALC655 supports 48KHz sample rate.)
Type
R
Function
Read as BB80h. (ALC655 supports 48KHz sample rate.)
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Default: 8080H
Bit
15
14:13
12:8
7
6:5
4:0
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Type
Function
R/W LFE Mute Control 0: Normal 1: Mute (- dB)
Reserved
R/W LFE Master Volume (LFE[4:0]) in 1.5 dB steps
R/W Center Mute Control 0: Normal 1: Mute (- dB)
Reserved
R/W Center Master Volume (CNT[4:0]) in 1.5 dB steps
For LFE/CEN, 00h
0dB
1Fh
46.5dB attenuation
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ALC655
Type
Function
R/W Left Mute Control 0: Normal 1: Mute (- dB)
Reserved
R/W Surround Master Left Volume (LSR[4:0]) in 1.5 dB steps
R/W Right Mute Control 0: Normal 1: Mute (- dB)
Reserved
R/W Surround Master Right Volume (RSR[4:0]) in 1.5 dB steps
For LSR/RSR, 00h 0dB
1Fh -46.5dB attenuation
14
13:12
11
10:4
3
2
1
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Type
R/W
Function
Validity Control (control V bit in Sub-Frame)
0: The V bit (valid flag) in sub-frame depends on whether or not the S/PDIF data is under-run
1: The V bit in sub-frame is always send as 1 to indicate the invalid data is not suitable for receiver
R
DRS (Double Rate S/PDIF)
The ALC655 does not support double rate S/PDIF, this bit is always 0.
R/W SPSR [1:0] (S/PDIF Sample Rate)
10: Sample rate set to 48KHz. Fs[0:3]=0100 (default)
00,01,11: Reserved
R/W LEVEL (Generation Level)
R/W CC [6:0] (Category Code)
R/W PRE (Preemphasis)
0: None
1: Filter preemphasis is 50/15 sec
R/W COPY (Copyright)
0: Asserted
1: Not asserted
R/W /AUDIO (Non-Audio Data type)
0: PCM data
1: AC3 or other digital non-audio data
R
PRO (Professional or Consumer format)
0: Consumer format
1: Professional format
ALC655 supports consumer channel status format, this bit is always 0
To ensure the control and status information started up correctly at the beginning of S/PDIF
transmission, MX3A.[14:0] should only be written to when S/PDIF transmitter is disabled
(MX2A.2=0).
If validity control is set (MX3A.15=1), those data bits (bit 8 ~ bit 27) should be forced to 0 to
get better compatibility with mini disc.
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Bit
15
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ALC655
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Default: 0000h
The data in MX62 are captured from channel status [29:16] of S/PDIF-IN signal.
Bit
Type
Function
15
R
V bit in sub-frame of SPDIFI
0: Data X and Y are valid
1: At least one of data X and Y is invalid
This bit is real-time updated, and it is meaning when S/PDIF-IN is locked
14
R
S/PDIF-IN Input Signal Locked by hardware
0: Unlocked
1: Locked
13:12
R
Ca[1:0] ( Clock Accuracy)
11:8
R
Fs[3:0]. (Sample Frequency in channel status)
0000: 44.1KHz
0010: 48 KHz
0011: 32 KHz
Others: Reserved
7:4
R
Cn[3:0] (Channel Number)
3:0
R
Sn[3:0] (Source Number)
The bits [13:0] are captured from channel status [29:16] of SPDIFI.
The consumer channel status of SPDIFI (bit0~bit31):
0
1
2
3
4
5
6
7
PRO
/AUDIO COPY
PRE0
PRE1
PRE2
Mode0
Mode1
8
9
10
11
12
13
14
15
CC0
CC1
CC2
CC3
CC4
CC5
CC6
LEVEL
16
17
18
19
20
21
22
23
Sn0
Sn1
Sn2
Sn3
Cn0
Cn1
Cn2
Cn3
24
25
26
27
28
29
30
31
Fs0
Fs1
Fs2
Fs3
Ca0
Ca1
0
0
The data from SPDIF input is forced to 0 once the SPDIF input signal is unlocked. Software must check this
LOCK bit before dealing with SPDIF input operations.
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ALC655
Type
Function
R/W Mute Control 0: Normal 1: Mute (- dB)
Reserved
R/W Surround DAC Left Volume (SDL[4:0]) in 1.5 dB steps
Reserved
R/W Surround DAC Right Volume (SDR[4:0]) in 1.5 dB steps
For SDL/SDR,
00h
+12 dB gain
08h
0dB
1Fh
-34.5dB attenuation
The default value is 0808H (unmuted).
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Bit
15
14:13
12:8
7:5
4:0
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Default: 0000h
This register is used to control various parts of the ALC655 multi-channel functions.
Bit
Type
Function
15
RW SPDIF Input Enable
0: Disable (Default) 1: Enable
14
R/W SPDIF-In Monitoring Control
0: Disable, SPDIFI data is not added into PCM data to DAC. (Default)
1: Enable, MSB 16-bit of SPDIFI data will be added into PCM data to DAC if SPDIFI is locked.
13:12
R/W S/PDIF Output Source
00: S/PDIF output data is from ACLINK (default)
01: S/PDIF output data is from ADC
10: Directly bypass S/PDIF-In signal to S/PDIF-Out
11: Reserved.
11
R/W PCM Data to AC-LINK
0: PCM Data are from ADC (default)
1: PCM Data are from SPDIF input.
10
R/W MIC1 & MIC2 / CENTER & LFE Output Control
0: pin-21 is MIC1, pin-22 is MIC2 (default)
1: pin-21 is CENTER-Out, pin-22 is LFE-Out.
9
R/W Line-In / Surround Output Control
0: pin-23 and pin-24 are analog input (Line-In). (default)
1: pin-23 and pin-24 are duplicated output of surround channel (Surround-Out)
8:6
Reserved
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ALC655
5
R/W
R/W
3:1
0
R/W
Function
PCI Sub System Vendor ID
This register can be written once only after power on, and is not affected by AC97 cold reset. System
manufactures BIOS can set its own sub-system ID.
The default value FFFFh means this register is implemented and data is not set by BIOS.
Type
R/W
Function
PCI Vendor ID
This register can be written once only after power on, and is not affected by AC97 cold reset. System
manufactures BIOS can set its own sub-vendor ID.
The default value FFFFh means this register is implemented and data is not set by BIOS.
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Default: 0000h
Bit
15:5
4:1
Type
R/W
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R/W
Function
Reserved
Function Code bits, FC[3:0]
These bits specify the type of audio function described in page ID-01h MX66, MX68 and MX6A.
0h: FRONT OUT
1h: SURROUND OUT
5h: MIC1 In
6h: MIC2 In
7h: LINE In
Others: Not supported
Tip or Ring Selection, T/R
This bit sets which jack conductor the sense value is measured from. It is combined with FC[3:0].
0: Tip (Left channel)
1: Ring (Right channel)
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Bit
15:0
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ALC655
Type
R/W
3:1
0
NA
R
Function
Reserved
Information Valid bit, IV
0: After a sense cycle is completed indicates that no information is provided on the sensing method
1: After a sense cycle is completed indicates that information is provided on the sensing method
Clearing this bit by writing 1, writing 0 to this bit has no effect.
Reserved
Function Information Present, FIP
This bit is set to a 0 indicates that the G[4:0], INV, DL[4:0] and ST[2:0] bits are not supported.
Type
R
7:0
Function
Reserved
Sense bits, S[4:0] (Default value depends on sensed result after Cold Reset)
For output devices:
02h: Not specificed or unknown 05h: Powered speaker
06h: Earphone or passive speaker
Other: Not supported
For input deices:
12h: Not specified or unknown
13h: Mono Microphone 15h: Stereo Line-In
Other: Not supported
This field reports the type of output/input peripheral plugged in the jack after sensing.
Always read as 0.
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Default: 0000h
Bit
15
Type
R/W
14
R/W
13
R/W
12
R/W
11:10
9
NA
R/W
R/W
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Function
GPIO Statue Indication in SDATA_IN
0:The status of GPIO0(JD0)/GPIO1(JD1)/JD2 and its valid tag are not indicated in SDATA_IN.
1: The status of GPIO0(JD0)/GPIO1(JD1)/JD2 and its valid tag are indicated in SDATA_IN
JD2 interrupt Enable
0: Disable
1: Enable.
A low to high transaction will trigger the interrupt in bit0 in SDATA_INs slot-12.
GPIO1(JD1) interrupt Enable (when GPIO1/JD1 is used as input)
0: Disable
1: Enable.
A low to high transaction will trigger the interrupt in bit0 in SDATA_INs slot-12.
GPIO0(JD0) interrupt Enable (when GPIO0/JD0 is used as input)
0: Disable
1: Enable.
A low to high transaction will trigger the interrupt in bit0 in SDATA_INs slot-12.
Reserved
GPIO1Primitiveness Control
0: Set GPIO1(JD1) as input pin.
1: Set GPIO1(JD1) as output pin.
GPIO0 Primitiveness Control
0: Set GPIO0(JD0) as input pin.
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Default: 0000h
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ALC655
3
2
1
0
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Default: 60A2H
This register is used for three types of information. Bit 0 is a read/write bit which enables/disables the S/PDIF input receiver. Bit 1 is
used to switch pin 47, which is duplexed due for pin-count reduction, between EAPD and S/PDIF modes. Bit 2 is used to select the
clock source for the ALC655.
Bit
Type
Function
15
R
Clock Source Selection (XTLSEL)
0: Disable 14.318M 24.576M digital PLL. (Default if XTSEL is floating)
1: Enable 14.318M 24.576M digital PLL. (Default if XTLSEL is pull low)
14:13
Reserved
12
R/W Vrefout Disable
0: Vrefout is driven by the internal reference (Default)
1: Vrefout is in high-Z mode.
Software must set this bit to disable Vrefout output before MX6A.10 is set (MIC1 and MIC2 are shared
as Center and LFE output).
11
R/W Independent Left/Right Mute Control for MX02
0: Disable, only bit15 is a mute bit for left and right channel (Default)
1: Enable, bit15 mute left channel, bit7 mute right channel.
10:4
Reserved
3
R/W JD2 Control Surround-Out, Center-Out and LFE-Out
0: Disable. (Default)
1: Enable, when (MX7A.3=1 & MX78.2=1), Surr-Out and CEN/LFE-Out are muted.
2
R/W JD1 Control Surround-Out, Center-Out and LFE-Out
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ALC655
1
R/W
R/W
0: Disable. (Default)
1: Enable, when (MX7A.2=1 & MX78.1=1 & MX78.9=0), Surr-Out and CEN/LFE-Out are muted.
Pin-47 Function Selection
0: EAPD
1: SPDIF Input (Default)
JD0 Control Surround-Out, Center-Out and LFE-Out
0: Disable. (Default)
1: Enable, when (MX7A.0=1 & MX78.0=1 & MX78.8=0), Surr-Out and CEN/LFE-Out are muted.
(Internal MX36.15, MX36.7, MX38.15 and MX38.7 are all set to 1.)
This function should be implement by digital designer.
Type
R
Function
Vendor ID- AL
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Bit
15:8
7:4
3:0
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Type
R
R
R
Function
Vendor ID- G
Chip ID- 0110b (ALC655)
Version number- 0000b.
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ALC655
7. Electrical Characteristics
7.1.1 Absolute Maximum Ratings
Parameter
Power Supplies
Symbol
Minimum
Typical
Maximum
Units
Digital
Analog
Operating Ambient Temperature
Storage Temperature
ESD (Electrostatic Discharge)
DVDD
AVDD
Ta
Ts
3.0
3.5
0
3.3
5.0
-
3.6
5.5
+70
+125
V
V
o
C
o
C
Susceptibility Voltage
Minimum
-0.30
-
Typical
0.7
Maximum
Dvdd+0.30
0.35Dvdd
Units
V
V
1.0
0.35Dvdd
1.2
0.35Dvdd
0.4DVdd
1.7
0.4DVdd
2.2
0.4DVdd
1.7
0.9DVdd
-10
-10
0.1DVdd
10
10
V
V
A
A
30k
5
50k
100k
mA
Maximum
19.2
Units
KHz
KHz
dB
dB
19.2
KHz
KHz
dB
dB
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Symbol
Passband
Stopband
Stopband Rejection
Passband
Frequency Response
Passband
Stopband
Stopband Rejection
Passband
Frequency Response
Minimum
0
28.8
Typical
-76.0
+- 0.20
0
28.8
-78.5
+- 0.20
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ALC655
Minimum
3.0
-
Typical
3.3
0
Maximum
0.5
Units
V
V
Symbol
Trst_low
Trst2clk
Minimum
1.0
162.8
Typical
-
Maximum
-
Units
s
ns
Symbol
Tsync_high
Tsync2clk
Minimum
1.0
162.8
Typical
-
Maximum
-
Units
s
ns
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ALC655
Minimum
36
Typical
12.288
81.4
40.7
Maximum
750
45
Units
MHz
ns
ps
ns
36
-
40.7
48.0
20.8
1.3
19.5
45
-
ns
KHz
s
s
s
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Units
ns
Parameter
Symbol
Minimum
Typical
Maximum
Input Setup to falling edge of
tsetup
10
BIT_CLK
Input Hold from falling edge of
thold
10
BIT_CLK
Note: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.
Units
ns
Parameter
Symbol
Minimum
Typical
Maximum
BIT_CLK combined rise or fall
7
plus flight time
SDATA combined rise or fall
7
plus flight time
Note: Combined rise or fall plus flight times are provided for worst case scenario modeling purposes.
Units
ns
ns
ns
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ALC655
Typical
-
Maximum
6
6
6
6
6
6
6
6
Units
ns
ns
ns
ns
ns
ns
ns
ns
Maximum
1.0
Units
s
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Parameter
Symbol
BIT_CLK rise time
Triseclk
BIT_CLK fall time
Tfallclk
SYNC rise time
Trisesync
SYNC fall time
Tfallsync
SDATA_IN rise time
Trisedin
SDATA_IN fall time
Tfalldin
SDATA_OUT rise time
Trisedout
SDATA_OUT fall time
Tfalldout
Note 1: 75pF external load (50 pF in AC97 rev2.1)
Note 2: rise is from 10% to 90% of Vdd (Vol to Voh)
Note 3: fall is from 90% to 10% of Vdd (Voh to Vol)
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Parameter
End of slot 2 to BIT_CLK,
SDATA_IN low
Symbol
Ts2_pdown
Minimum
-
Typical
-
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ALC655
Output Pin
BIT_CLK (must support 2
CODECs)
SDATA_IN
1 CODEC
55pF
2 CODEC
62.5pF
3 CODEC
75pF
4 CODEC
85pF
47.5pF
55pF
60pF
62.5pF
Minimum
0
45
Typical
Maximum
10
55
Units
%
%
T(h)
T(l)
90%
50%
10%
T(r)
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Notes:
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T(f)
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ALC655
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29
Units
Vrms
Vrms
Vrms
dB
Hz
dB
dB
Hz
Hz
Hz
dB
dB
ms
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
K
K
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ALC655
Output Impedance
FRONT-OUT / SURROUND-OUT
CEN/LFE-OUT
MONO-OUT
Amplifier Maximum Output Power
@20 load
Power Supply Current
VA=5.0V
VD=3.3V
5
200
500
50
mW
50
15
mA
mA
2.50
5
1000
700
4.0
-
uA
uA
V
mA
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ALC655
9. Design Suggestions
9.1 Clocking
The clock source is decided by XTLSEL latched from pin-46 after power-on reset. The clock source of different
configuration is listed below:
Configuration
Operation & ID0
Pin-46(XTLSEL)
ID0
BIT-CLK Clock source
NC
0 (Primary) Output
Crystal or ext. 24.576MHz is attached
12.288MHz at XTL-IN
Low
0 (Primary) Output
Crystal or ext. 14.318MHz is attached
12.288MHz at XTL-IN
NC
0 (Primary) Input
12.288M input at BIT-CLK
*Low: Pulled low by a 0 ohm resistor. NC: Not connect or pulled high.
*Pin-46is internally pulled high by a weak resistor.
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According to AC97 ver 2.3, the primary mode while RESET# is asserted, if a clock is present at BIT-CLK pin for at least 5
cycles before RESET# is de-asserted, ALC655 is a consumer of BITCLK. ALC655 should use external 12.288MHz
BITCLK as its clock source.
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ALC655
9.2 AC-Link
When the ALC655 receives serial data from the AC97 controller, it samples SDATA_OUT on the falling edge of BIT_CLK.
When the ALC655 sends serial data to the AC97 controller, it starts to drive SDATA_IN on the rising edge of BIT_CLK.
The ALC655 will return any uninstalled bits or registers with 0 for read operations. The ALC655 also stuffs the
unimplemented slot or bit with 0 in SDATA_IN. Note that AC-LINK is MSB-justified.
Refer to Audio CODEC 97 Component Specification Revision 2.3. for details.
0
Slot#
10
11
12
SYNC
SDATA-OUT
SDATA-IN
PCM
R
TAG
PCM
R
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Default ALC655 Slot Arrangement CODEC ID = 00 (ALC655 supports only primary mode)
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ALC655
9.3 Reset
There are 3 types of reset operations: Cold, Warm and Register.
Reset Type
Cold
Register
Warm
Trigger condition
Assert RESET# for a specified period
CODEC response
Reset all hardware logic and all registers to its default
value.
Write register indexed 00h
Reset all registers to its default value.
Driven SYNC high for specified period without Reactivates AC-LINK, no change to register values.
BIT_CLK
The AC97 controller should drive SYNC and SDATA_OUT low during the period of RESET# assertion to guarantee that the
ALC655 has reset successfully.
9.4 CD Input
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ALC655
+5Vstandby
No (0)
Yes (1)
No (0)
-
Operation Mode
Shut Down
Power Off CD
Power Off CD
Digital on, Analog is off
Normal
+5VA
+3.3VCC
+5Vstandby
D1
1N5817M/CYL
1u
VDD
VDD
VREF
VREFOUT
AFILT1
AFILT2
ALC655
PC-BEEP
PHONE
AUX-L
AUX-R
JD2
JD1/GPIO1
CD-L
CD-R
MIC1
MIC2
LINE-L
LINE-R
1u
4
7
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2003/07/31
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1N5817M/CYL
VRDA
VRAD
NC
FRONT-MIC
CEN-OUT
LFE-OUT
JD0/GPIO0
XTLSEL
SPDIFI/EAPD
SPDIFO
SURR-OUT-L
NC
SURR-OUT-R
35
36
37
27
28
29
30
31
32
33
34
43
44
45
46
47
48
39
40
41
AGND
AGND
1u
RESET#
BITCLK
SYNC
SDOUT
SDIN
GND
GND
CD-IN
FRONT-OUT-L
FRONT-OUT-R
MONO-OUT
CD-GND
0
1
2
3
4
12
13
14
15
16
17
18
20
21
22
23
24
0.1u
26
42
11
6
10
5
8
XTL-IN
XTL-OUT
19
2
3
10u
25
38
10u
AVDD
AVDD
1
9
0.1u
D2
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+3.3VCC
No (0)
No (0)
No (0)
Yes (1)
Yes (1)
34
Rev1.01
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ALC655
FRONT-MIC2
C75
+5VAUX
1u@655
+12V
R55
5.6K@ALC655/658
C1
10u
+
C10
42
JD0
CENTER-OUT
C29
1u
43
LFE-OUT
C31
1u
44
45
JD0
R4
0@EXT-14.318M 46
SPDIFI
47
48
25
26
ALC650/655/658
AVSS2
CD-GND
CD-L
CEN-OUT
LFE-OUT
JD1/VIDEO-R
JD0/GPIO0
JD2/VIDEO-L
XTLSEL/ID1#
AUX-R
SPDIFI/EAPD
AUX-L
SPDIFO
DVDD1
Spilt by DGND
SPDIFO
10u
IN
FERB
C8
+10u
10u
PHONE
C21
1u
LINE-IN-R
C22
1u
LINE-IN-L
23
C24
1u
MIC2-IN
22
C25
1u
MIC1-IN
24
21
20
19
18
C27
1u
R1
C28
1u
R2
C30
1u
R3
LINE-IN-R
LINE-IN-L
C67
16
1u@650
C68
15
14
J5
C37
13
1u@655/650
AUX-IN Header
C69
C70
1u
R7
1
2
3
4
VIDEO-IN Header
JD1
ALC-AC97
C41
MIC1-IN
J4
CD-IN Header
4
3
2
1
1u@650
R34 0@655/658 JD1
4
3
2
1
1u@655/650
C39
MIC2-IN
J16
17
+3.3VDD
C43
C11
0.1u
+10u
AVDD1
28
29
30
31
32
33
27
VREF
VREFOUT
AFILT1
AFILT2
VRDA/VRAD
CD-R
SURR-OUT-R/HP-OUT-R
PC-BEEP
41
12
1u
MIC1
NC
SYNC
C26
C15
C7
L3
U8
LINE-IN-R
10
SURR-OUT-R
1u
MIC2
DVDD2
40
JD3
SURR-OUT-L/HP-OUT-L
SDATA-IN
39
DVSS2
1u
C16
10u
LINE-IN-L
BIT-CLK
JD3
C23
AVDD2
FRONT-MIC2/VRDA
SURR-OUT-L
MONO-O
SDATA-OUT
38
VREFOUT2
37
DVSS1
1u
FRONT-MIC1
36
C20
10u
XTL-OUT
C19
FRONT-OUT-R
+5VA
FRONT-OUT-L
34
C14
1000P
35
0@658
XTL-IN
R46
C6
1000P
AVSS1
100u
LM7805CT/200mA
OUT
VREFOUT
+5VA
RESET#
C12
VREFOUT
100u
11
FRONT-OUT-R
C5
FRONT-OUT-L
U1
+5VA
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C13 1u@650
1u@650
1u
GND
C9
C4
D1
1N4148@655/658
0@658
FRONT-MIC1
JD4
JD2
R43
JD4
220u@658
UAJ2-R
0@658
220u@658
UAJ2-L
Audio-From-Modem
C42
0.1u
+ C44
C12A1
0.1u
R12B1 10K
1u
Signal-From-PCSPK
C12B1
R8 0@EXT-14.318M
+3.3VDD
Y1
24.576MHz
C45
C46
22P
22P
R9
22
R10
22
1K
100P
AC97-RESET#
EXT 14.318MHz
R12A1
AC97-SYNC
AC97-SDIN
AC97-BCLK
AC97-SDOUT
C50
22P
Crysatl Saving:
DGND
AGND
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ALC655
ALC658
C67
ALC650
1u
C68
1u
R34
R44
C37
1u
1u
C39
1u
1u
C69
100u
C70
100u
C13
1u
C9
1u
C75
1u
1u
R46
R43
DataSheet 4 U .com
35
Rev1.01
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ALC655
INTEL Front Panel I/O Design Guide V1.0
SURR-OUT-L
SPDIF-IN
SURR-OUT-L
AGND
DGND
SPDIF-IN
DGND
J8
1
3
5
7
9
2
4
6
8
10
SURR-OUT-R
AGND
+3.3VDD
+5VDD
SPDIF-OUT
R27
+5VA
JD1 R61
SURR-OUT-L
FRONT-MIC1
10K
R26
20
FRONT-OUT-L R29
0@Reserve
SURR-OUT-R R39
20
0@658
JD0 R51
SURR-OUT-L
SPDIF-OUT
R40
J11
FRONT-OUT-R R28
20@Reserve
20@Reserve
+5VA
2
4
6
8
10
12
14
16
1
3
5
7
9
11
13
15
AUD-RET-R
AUD-RET-R
KEY
AUD-RET-L
AUD-RET-L
R62
JD2
UAJ2-L
20@655 FRONT-MIC2
UAJ2-R R48
0@658
R47
R48
R26
R61
R62
R51
For ALC650:
R42
JD Block=X
10K
JD0
VREFOUT
VREFOUT
C74
3.3u
R12
R13
4.7K@655/658(Stereo MIC)
MIC2-IN
MIC1-IN
MIC2-IN
MIC1-IN
R15
R17
4.7K/2.2K
0
0
J7
FERB
L8
1
2
3
4
5
FERB
L9
R57
R58
C52
C53
22K
22K
100P
100P
For ALC650:
R45
10K
C73
3.3u
R71
0@658
R72
0@655
JD4
JD Block
JD2
LINE-IN-R
LINE-IN-L
R20
R21
L10
L11
For ALC655:
R71=X R72=0
For ALC658:
R71=0 R72=X
R12=4.7K R13=4.7K
LINE-IN-L
For ALC650:
JD Block=X
R12=X R13=2.2K
LINE-IN-R
JD Block
J10
FERB
1
2
3
4
5
FERB
R22
R23
C55
C56
22K
22K
100P
100P
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For ALC650:
R56
JD Block=X
10K
C72
3.3u
JD Block
R73
0@658
R74
0@655
JD3
For ALC655:
R73=X R74=0
+
JD1
For ALC658:
R73=0 R74=X
AUD-RET-R
AUD-RET-L
AUD-RET-R
AUD-RET-L
L13
FERB
L15
FERB
J13
1
2
3
4
5
R59
R60
C60
C61
22K
22K
100P
100P
2003/07/31
DataSheet 4 U .com
36
Rev1.01
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ALC655
L2
FERB
J1
C2
C3
100P
100P
1
2
3
4
5
TOTX178
5
N.C
CENTER-OUT
FERB
L5
FERB
VCC
J3
C17
C18
100P
100P
1
2
3
4
5
L4
N.C
Surround Out
LFE-OUT
Optical
Transmitter
U3
IN
FERB
GND
SURR-OUT-L
L1
SURR-OUT-R
C32
0.1u
+5VDD
C38
J6
Center/Lfe Out
S/PDIF OUTPUT
SURR-OUT-L
AGND
DGND
SPDIF-IN
DGND
SURR-OUT-R
SPDIF-IN
0.01u
R6
100P
220
2
2
4
6
8
10
1
3
5
7
9
SURR-OUT-R
AGND
+3.3VDD
+5VDD
SPDIF-OUT
100
SPDIF-OUT
C40
(Coaxial)
J2
R5
SURR-OUT-L
SPDIF-OUT
Bracket Connector
+3.3VDD
CASE
Optical
Receiver
C33
10u
C34
C35
0.1u
10u
C36
+
0.1u
OUT
VCC
CASE
DGND
OUT
VCC
TORX178
DGND
CASE
AGND
CASE
U5
TORX176/173
5
Optical
Receiver
U4
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+5VDD
R11
10
SPDIF-IN
L6
47uH
R14
+5VDD
+3.3VDD
L7
2.2K
C48
0.1u
C49
+5VDD
47uH
C47
0.1u
R16
10K
0.01u
J9
C51
0.01u
R18
10
SPDIF-IN
R19
S/PDIF INPUT
C54
100P
10K
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DataSheet 4 U .com
37
Rev1.01
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ALC655
FRONT-JACK2-ON
R24
+5VA
R50 10K@UAJ
+
10K
C57
C71
3.3u@UAJ
UAJ Block
1u@Norm
AUD-MIC
+5VA
R35
R25
10K
L12
FERB
L14
FERB
J12
1
2
3
4
5
C58
C59
100P
100P
R31
UAJ2-IO-R
R53
0@655/658
UAJ2-IO-L
R54
0@655/658
22K@655/658
AUD-MIC
AUD-MIC-BIAS
AUD-OUT-R
FRONT-JACK1-ON
AUD-OUT-L
VREFOUT2-UAJ2
UAJ2-IO-L
FRONT-JACK2-ON
J14
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
+5VA
RET-R
KEY
Front Connector
R52
0@658
VREFOUT2-UAJ2
RET-L
UAJ Block
VREFOUT3-UAJ1
UAJ2-IO-R
1~10 pin connector: INTEL Front Panel I/O Design Guide V1.0
R32
FRONT-JACK1-ON
10K
C64
100u/ 0ohm
RET-R
C66
3.3u
AUD-OUT-R
AUD-OUT-L
R49
L16
FERB
L17
FERB
J15
C62
0@658
C63
100P 100P
R30
VREFOUT3-UAJ1
1
2
3
4
5
UAJ Block
R64
R65
R32
10K
R66
X
3.3u
C65
RET-L
100u/ 0ohm
R30
R31
R24
R57
4.7K
22K
22K
R54
UAJ
Block
R35
R25
R53
1u
ON
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2003/07/31
DataSheet 4 U .com
38
Rev1.01
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22K@655/658
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ALC655
www.DataSHeet4U.com
L
L1
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SYMBOL
A
A1
A2
C
D
D1
D2
E
E1
E2
b
e
TH
L
L1
MILLIMETER
MIN. TYPICAL MAX.
1.60
0.05
0.15
1.35
1.40
1.45
0.09
0.20
9.00 BSC
7.00 BSC
5.50
9.00 BSC
7.00BSC
5.50
0.17
0.20
0.27
0.50 BSC
0o
3.5o
7o
0.45
0.60
0.75
1.00
2003/07/31
DataSheet 4 U .com
INCH
MIN. TYPICAL MAX
0.063
0.002
0.006
0.053 0.055
0.057
0.004
0.008
0.354 BSC
0.276 BSC
0.217
0.354 BSC
0.276 BSC
0.217
0.007 0.008
0.011
0.016 BSC
0o
3.5o
7o
0.018 0.0236 0.030
0.0393
39
Rev1.01
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ALC655
2003/07/31
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