DM74LS90Counters

Decade and Binary

August 1986
Revised March 2000

DM74LS90
Decade and Binary Counters
General DescriptionFeatures

Each of these monolithic counters contains four master-Typical power dissipation 45 mW

slave flip-flops and additional gating to provide a divide-byCount frequency 42 MHz
two counter and a three-stage binary counter for which the
count cycle length is divide-by-five for the DM74LS90.
All of these counters have a gated zero reset and the
DM74LS90 also has gated set-to-nine inputs for use in
BCD nines complement applications.
To use their maximum count length (decade or four bit
output. The
binary), the B input is connected to the Q
A

input count pulses are applied to input A and the outputs

are as described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the
output to the A
DM74LS90 counters by connecting the Q
D

input and applying the input count to the B input which

.
gives a divide-by-ten square wave at output Q
A

Ordering Code:
Order Number Package Number Package Description
DM74LS90M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS90N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram Reset/Count Truth Table

Reset Inputs Output
QQQ
R0(1) R0(2) R9(1) R9(2) Q
DCBA

H H L X LLLL
H H X L LLLL
XXHHHLLH
X L X L COUNT
L X L X COUNT
L X X L COUNT
X L L X COUNT

 2000 Fairchild Semiconductor Corporation DS006381 www.fairchildsemi.com

Function TablesLogic Diagram

BCD Count Sequence (Note 1)

Count Output
DM74LS90
QQQ
Q
DCBA

0 LLLL
1LLLH
2LLHL
3LLHH
4LHLL
5LHLH
6LHHL
7 LHHH
8 HLLL
9HLLH

Bi-Quinary (5-2) (Note 2)

Count Output
QQQ
Q
ADCB

0 LLLL
1LLLH
2LLHL
3LLHH
4LHLL
5 HLLL
6HLLH
7HLHL
8HLHH
9HHLL

H HIGH Level
L LOW Level
X Dont Care

The J and K inputs shown without connection are for reference only and
is connected to input B for BCD count.
Note 1: Output Q
A

are functionally at a high level.

is connected to input A for bi-quinary count.
Note 2: Output Q
D

Note 3: Output Q
is connected to input B.
A

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Absolute Maximum Ratings(Note 4)

Supply Voltage 7V

Note 4: The Absolute Maximum Ratings are those values beyond which

Input Voltage (Reset) 7V

the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical

Input Voltage (A or B) 5.5V

Characteristics table are not guaranteed at the absolute maximum ratings.

The Recommended Operating Conditions table will define the conditions

Operating Free Air Temperature Range 0C to 70C

for actual device operation.

DM74LS90

Storage Temperature Range65C to 150C

Recommended Operating Conditions

Symbol Parameter Min Nom Max Units
Supply Voltage 4.75 5 5.25 V
V

CC

HIGH Level Input Voltage 2 V

V

IH

LOW Level Input Voltage 0.8 V

V

IL

HIGH Level Output Current0.4 mA

I

OH

LOW Level Output Current 8 mA

OL

Clock Frequency (Note 5) A to Q032MHz

CLKA

B to Q

016

Clock Frequency (Note 6) A to Q020MHz

CLKA

B to Q

010

Pulse Width (Note 5) A 15

B30 ns
Reset 15
Pulse Width (Note 6) A 25

B50 ns
Reset 25
Reset Release Time (Note 5) 25 ns

REL

Reset Release Time (Note 6) 35 ns

REL

Free Air Operating Temperature 0 70C

T

A
Note 5: C 15 pF, R 2 k, T 25C and V 5V.
LLACC

Note 6: C
50 pF, R 2 k, T 25C and V 5V.
LLACC

Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol Parameter Conditions MinMax Units
(Note 7)
VInput Clamp Voltage V Min, I 18 mA1.5 V
ICCI

VHIGH Level V Min, I Max

OHCCOH

2.7 3.4 V
Output Voltage V Max, V Min
ILIH

LOW Level V Min, I Max

V
OLCCOL

(Note 8)

Voltage VVOutput
Max, V Min 0.35 0.5
ILIH

4 mA, V Min 0.25 0.4

I
OLCC

IInput Current @ Max V Max, V 7V Reset 0.1

ICCI

Voltage V Max A 0.2mAInput

5.5V B 0.4

CC

IHIGH Level V Max, V 2.7V Reset 20

IHCCI

Current A 40AInput

B80
LOW Level V Max, V 0.4V Reset0.4
I

ILCCI

Current A2.4mAInput
B3.2
Short Circuit Output Current V Max (Note 9)20100 mA

I
OSCC

Supply Current V Max (Note 7) 9 15 mA

CCCC

Note 7: All typicals are at V 5V, T 25C.

CCA

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Electrical Characteristics

(Continued)

Note 8: Q outputs are tested at I Max plus the limit value of I for the B input. This permits driving the B input while maintaining full fan-out capability.
AOLIL

Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second.
is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V and all other inputs grounded.
Note 10: I

CC
DM74LS90

Switching Characteristics
CCA

R 2 k
From (Input)
L

Symbol ParameterC 15 pF C 50 pF Units

To (Output)
LL

Min Max Min Max

fMaximum Clock A to Q32 20

MAXA

MHz
Frequency B to Q
16 10
B

tPropagation Delay Time

PLH

A to Q16 20 ns
A

LOW-to-HIGH Level Output

tPropagation Delay Time

PHL

A to Q18 24 ns
A

HIGH-to-LOW Level Output

tPropagation Delay Time

PLH

A to Q48 52 ns
D

LOW-to-HIGH Level Output

tPropagation Delay Time

PHL

A to Q50 60 ns
D

HIGH-to-LOW Level Output

tPropagation Delay Time

PLH

B to Q16 23 ns

at V 5V and T 25C

LOW-to-HIGH Level Output

tPropagation Delay Time

PHL

21 30 ns
B to Q
B

HIGH-to-LOW Level Output

tPropagation Delay Time

PLH

B to Q32 37 ns
C

LOW-to-HIGH Level Output

tPropagation Delay Time

PHL

B to Q35 44 ns
C

HIGH-to-LOW Level Output

tPropagation Delay Time

PLH

32 36 ns
B to Q
D

LOW-to-HIGH Level Output

tPropagation Delay Time

PHL

B to Q35 44 ns
D

HIGH-to-LOW Level Output

tPropagation Delay Time

PLH

SET-9 to Q, Q30 35 ns
AD

LOW-to-HIGH Level Output

tPropagation Delay Time

PHL

, Q40 48 ns
SET-9 to Q
BC

HIGH-to-LOW Level Output

tPropagation Delay Time

PHL

SET-0 to Any Q 40 52 ns
HIGH-to-LOW Level Output

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Physical Dimensions

DM74LS90
inches (millimeters) unless otherwise noted

14-Lead Small
Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A

5 www.fairchildsemi.com
(Continued)

DM74LS90 DecadeCounters and Binary

Physical Dimensions

inches (millimeters) unless otherwise noted

14-Lead Plastic
Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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