What is a beat and burst in axi??what does that mean??

A 'beat' is an individual data transfer within an AXI burst. An AXI 'burst' is a

transaction in which multiple data items are transferred based upon a single
address, and it is each data item transferred that is referred to as a 'beat'. Since
there is only one address transfer, the addresses of each 'beat' in a burst are
calculated based on the transaction type (INCR, FIXED or WRAP).
The AXI3 protocol allows up to 16 beats in any burst transaction, whereas
the AXI4 protocol allows for up to 256 beats in an INCR type burst transaction.
Difference between lock and exclusive mode
in locked transcation master locked the slave so no another master can it access
upto the unlocked transfer is came.
in exclusive mode if slave is busy with some operation after completing that ,it
gives responce to master i am ready to accept the transcation.in this other master
can access this slave.
Difference between transfer and transaction
Transfer is could be single/mutiple reads or writes
2) Transaction is something where either read or write has done write or read and
got the respective response. Its a complete transfer called transaction
5) Groups of beats is a transfer.
Difference between AXI and AHB.
difference between axi and ahb
"one master is asserting the awvalid signal, 2 slaves are asserting the awready
signal. now, to provide the txn to the right slave, what decoding will be used ? will it
use address provided by the master or the id of the transaction ? "
first AXI is a configurable interconnect, it all depends on how u configure,
Ist case
so all slaves can have seperate buses enrouted from the masters or a single master
can have seperate interfaces such as AWvalid1 , AWvalid2, AWvalid3, ... etc. so now
here in this case if a master's AWvalid (X) is high it looks for only AWready(x) to be
high, it doesn't care even though AWready(x+1) is high.
IInd case

As you said in ur case if u have a single master signal and multiple slaves but a
single interconnect then address decoding can be done. I don't think this will be
feasible bcos AXI is made for high performance and the above scenario is similar to
AHB Bus decoding.

But i don't believe the AXI Interconnect can be done this way, there is AMBA 3
Design Kit available from ARM where the configuration tool automatically develops
the interconnect according to the options given(such as 3 masters 2 slaves .. etc)

Well if u r designing the interconnect with a single bus then there would be no use
of using AXI in that SOC unless there are AXI Master/Slave interface IP's predefined
and bcos of time consumption u develop the AXI interconnect. else AHB is directly
suitable to ur case.

Explain out-of-order transaction support on AXI?

"Out-of-order" is a term usually referring to slaves, not masters. Slaves can return
read data in a different order to that the addresses were received (if the IDs are
different), or they can return BRESP write responses at the end of the write data
transfers, again in a different order to that of the addresses, if the IDs are different.
Masters can interleave write data to the 2 different slaves (where IDs are unique),
but this would be done because the master has that data available, not because it
knows a specific slave can accept that data. If this particular data happens to be for
your slower slave, WREADY will be driven low from that slave to stall the master
until the slave is able to accept that data, and this will stall all data transfers from
that master.
However when designing the interconnect logic linking your master to the 2 slaves,
and if you knew slave #2 was slow, you could implement some sort of write data
buffer on the interconnect output port driving slave #2 so that the buffer fills up
quickly with the master data, and then slowly empties at the slave's data rate, thus
not impacting on the master.
How to ensure data integrity on AXI?

The data in write transactions must be written into the slave correctly..