Icc23 PDF

IC Compiler II
Application Options and Attributes

Version K-2015.06-SP4, December 2015
Copyright Notice and Proprietary Information

2015 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary
information that is the property of Synopsys, Inc. The software and documentation are furnished under a license
agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the
software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic,
mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided
by the license agreement.
Destination Control Statement

All technical data contained in this publication is subject to the export control laws of the United States of America.
Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to
determine the applicable regulations and to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH
REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Trademarks
Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at
http://www.synopsys.com/Company/Pages/Trademarks.aspx.
All other product or company names may be trademarks of their respective owners.
Third-Party Links
Any links to third-party websites included in this document are for your convenience only. Synopsys does not endorse
and is not responsible for such websites and their practices, including privacy practices, availability, and content.
Synopsys, Inc.
690 E. Middlefield Road
Mountain View, CA 94043
www.synopsys.com
IC Compiler II Application Options and Attributes, Version K-2015.06-SP4
ii
Copyright Notice for the Command-Line Editing Feature

1992, 1993 The Regents of the University of California. All rights reserved. This code is derived from software
contributed to Berkeley by Christos Zoulas of Cornell University.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
following conditions are met:
1.Redistributions of source code must retain the above copyright notice, this list of conditions and the following
disclaimer.
2.Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
disclaimer in the documentation and/or other materials provided with the distribution.
3.All advertising materials mentioning features or use of this software must display the following acknowledgement:
This product includes software developed by the University of California, Berkeley and its contributors.
4.Neither the name of the University nor the names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Copyright Notice for the Line-Editing Library

1992 Simmule Turner and Rich Salz. All rights reserved.
This software is not subject to any license of the American Telephone and Telegraph Company or of the Regents of
the University of California.
Permission is granted to anyone to use this software for any purpose on any computer system, and to alter it and
redistribute it freely, subject to the following restrictions:
1.The authors are not responsible for the consequences of use of this software, no matter how awful, even if they arise
from flaws in it.
2.The origin of this software must not be misrepresented, either by explicit claim or by omission. Since few users ever
read sources, credits must appear in the documentation.
3.Altered versions must be plainly marked as such, and must not be misrepresented as being the original software.
Since few users ever read sources, credits must appear in the documentation.
4.This notice may not be removed or altered.
iii
iv
Contents
abstract.allow_fault_in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
abstract.high_fanout_limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
abstract.include_aggressor_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
abstract.latch_levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
block_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
bound_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
bound_shape_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
budget_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
budget_clock_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
budget_path_type_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
budget_pin_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
budget_pin_constraint_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
budget_pin_data_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
budget_segment_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
bundle_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
ccd.ignore_ports_for_boundary_identification . . . . . . . . . . . . . . . . . . . . . . . . . . 41
ccd.optimize_boundary_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
ccd.skip_path_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
cell_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
clock_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
clock_balance_group_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
clock_group_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
clock_group_group_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
Version K-2015.06-SP4
K-2015.06-SP4
clock_opt.congestion.effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
clock_opt.flow.enable_ccd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
clock_opt.flow.enable_ccd_route_clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
clock_opt.flow.enable_ccd_route_clock_eco . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
clock_opt.flow.optimize_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
clock_opt.flow.optimize_layers_critical_range . . . . . . . . . . . . . . . . . . . . . . . . . . 66
clock_opt.flow.optimize_ndr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
clock_opt.flow.pre_place_drc_fix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
clock_opt.flow.skip_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
clock_opt.hold.effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
clock_opt.place.effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
clock_opt.place.legalize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
clock_path_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
constraint_group_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
core_area_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
corner_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
cts.balance_groups.balance_by_source_latency . . . . . . . . . . . . . . . . . . . . . . . 87
cts.balance_groups.honor_source_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
cts.common.auto_exception_macro_balance_point . . . . . . . . . . . . . . . . . . . . . 89
cts.common.directory_for_cts_generated_files . . . . . . . . . . . . . . . . . . . . . . . . . 90
cts.common.enable_auto_exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
cts.common.enable_dirty_design_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
cts.common.max_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
cts.common.max_net_length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
cts.common.user_instance_name_prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
cts.common.verbose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
cts.compile.enable_cell_relocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
cts.compile.enable_global_route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
cts.compile.fix_clock_tree_sinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
cts.compile.primary_corner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
cts.compile.remove_existing_clock_trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
cts.multisource.subtree_merge_cell_name_prefix . . . . . . . . . . . . . . . . . . . . . . 103
cts.multisource.subtree_merge_cell_name_suffix . . . . . . . . . . . . . . . . . . . . . . 105
Contents
vi
IC Compiler II Application Options and Attributes
cts.multisource.subtree_merge_concatenate_length_threshold . . . . . . . . . . . 107
cts.multisource.subtree_routing_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
cts.multisource.subtree_split_cell_name_prefix . . . . . . . . . . . . . . . . . . . . . . . . 111
cts.multisource.subtree_split_cell_name_suffix . . . . . . . . . . . . . . . . . . . . . . . . 112
cts.multisource.subtree_split_net_name_prefix . . . . . . . . . . . . . . . . . . . . . . . . 113
cts.multisource.subtree_split_net_name_suffix . . . . . . . . . . . . . . . . . . . . . . . . 114
cts.multisource.tap_synthesis_route_based_estimation . . . . . . . . . . . . . . . . . 115
cts.multisource.verbose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
cts.placement.cell_spacing_rule_style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
cts.report.transition_histogram_datapoints . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
cts.report.verbose_paths_routing_length_threshold . . . . . . . . . . . . . . . . . . . . 119
cts.routing.fishbone_bias_threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
cts.routing.fishbone_bias_window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
cts.routing.fishbone_horizontal_bias_spacing . . . . . . . . . . . . . . . . . . . . . . . . . 124
cts.routing.fishbone_max_sub_tie_distance . . . . . . . . . . . . . . . . . . . . . . . . . . 126
cts.routing.fishbone_max_tie_distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
cts.routing.fishbone_vertical_bias_spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
design.bus_delimiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
design.edit_read_only_libs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
design.morph_on_save_as . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
design.name_expansion_delimiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
design.preserve_physical_only_pg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
design.sub_blocks_for_read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
design.uniquify_naming_style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
design.verbose_io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
design_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
design_checks_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
drc_error_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
drc_error_data_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
drc_error_type_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
eco.add_buffer_on_route.min_distance_buffer_to_load . . . . . . . . . . . . . . . . . 155
eco.functional.diff_ignore_tie_changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
eco.functional.diff_preprocess_for_verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Chapter 1: Contents
Contents
vii
1-vii
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
edit_group_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
em.net_delta_temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
em.net_duration_condition_for_peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
em.net_global_rms_relaxation_factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
em.net_min_duty_ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
em.net_use_waveform_duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
em.net_violation_rule_types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
ems_check_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
ems_database_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
ems_group_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
ems_message_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
ems_rule_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
exception_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
exception_group_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
extract.connect_open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
extract.enable_coupling_cap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
extract.high_fanout_threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
file.def.non_default_width_wiring_to_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
file.gds.contact_prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
file.gds.create_custom_via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
file.gds.exclude_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
file.gds.port_type_map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
file.gds.rotate_pin_text_by_access_direction . . . . . . . . . . . . . . . . . . . . . . . . . 196
file.gds.text_all_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
file.gds.text_layer_map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
file.gds.trace_unmapped_text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
file.lef.auto_rename_conflict_sites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
file.lef.non_real_cut_obs_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
file.lef.output_non_real_blockages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
file.lib.setup_file_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
file.oasis.contact_prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
file.oasis.create_custom_via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
file.oasis.exclude_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Contents
viii
file.oasis.port_type_map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
file.oasis.rotate_pin_text_by_access_direction . . . . . . . . . . . . . . . . . . . . . . . . 215
file.oasis.text_all_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
file.oasis.text_layer_map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
file.oasis.trace_unmapped_text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
file.verilog.default_user_label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
file.verilog.enable_vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
file.verilog.keep_unconnected_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
file.verilog.keep_unconnected_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
file.verilog.write_non_pg_net_assigns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
file.verilog.write_pg_net_assigns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
fill_cell_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
finfet.ignore_grid.std_cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
flip_chip.route.allow_rotated_via . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
flip_chip.route.connect_edge_center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
flip_chip.route.connect_pad_without_endcap . . . . . . . . . . . . . . . . . . . . . . . . . 234
flip_chip.route.detour_cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
flip_chip.route.layer_bump_spacings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
flip_chip.route.layer_routing_angles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
flip_chip.route.layer_tie_shield_widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
flip_chip.route.route_to_ring_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
flip_chip.route.routing_style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
flip_chip.route.secondary_routing_layer_cost . . . . . . . . . . . . . . . . . . . . . . . . . 241
flip_chip.route.shielding_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
geo_mask_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
grid_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
gui.auto_link_blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
gui.auto_open_layout_windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
gui.command_form_close_dialog_after_run_or_script . . . . . . . . . . . . . . . . . . 249
gui.command_form_show_result_dialog_after_run . . . . . . . . . . . . . . . . . . . . . 250
gui.custom_setup_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
gui.enable_custom_setup_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
gui.graphics_system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Chapter 1: Contents
Contents
ix
1-ix
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
gui.layer_solid_fill_pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
gui.name_based_hier_delimiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
gui_annotation_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
gui_object_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
gui_online_browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
hierarchy_separator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
in_gui_session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
input_delay_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
io_guide_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
io_ring_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
keepout_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
layer_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
lib.logic_model.auto_remove_incompatible_timing_designs . . . . . . . . . . . . . . 280
lib.logic_model.auto_remove_timing_only_designs . . . . . . . . . . . . . . . . . . . . . 281
lib.logic_model.require_same_opt_attrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
lib.logic_model.use_db_rail_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
lib.physical_model.block_all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
lib.physical_model.block_core_margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
lib.physical_model.connect_within_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
lib.physical_model.convert_metal_blockage_to_zero_spacing . . . . . . . . . . . . 288
lib.physical_model.design_rule_via_blockage_layers . . . . . . . . . . . . . . . . . . . 289
lib.physical_model.drc_distances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
lib.physical_model.hierarchical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
lib.physical_model.include_nondefault_via . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
lib.physical_model.include_routing_pg_ports . . . . . . . . . . . . . . . . . . . . . . . . . 293
lib.physical_model.merge_metal_blockage . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
lib.physical_model.pin_must_connect_area_layers . . . . . . . . . . . . . . . . . . . . . 295
lib.physical_model.pin_must_connect_area_thresholds . . . . . . . . . . . . . . . . . 296
lib.physical_model.port_contact_selections . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
lib.physical_model.preserve_metal_blockage . . . . . . . . . . . . . . . . . . . . . . . . . 298
lib.physical_model.source_drain_annotation . . . . . . . . . . . . . . . . . . . . . . . . . . 299
lib.physical_model.trim_metal_blockage_around_pin . . . . . . . . . . . . . . . . . . . 300
lib.workspace.allow_commit_workspace_overwrite . . . . . . . . . . . . . . . . . . . . . 302
Contents
lib.workspace.allow_missing_related_pg_pins . . . . . . . . . . . . . . . . . . . . . . . . 303
lib.workspace.create_workspace_tf_verbose . . . . . . . . . . . . . . . . . . . . . . . . . 304
lib.workspace.enable_secondary_pg_marking . . . . . . . . . . . . . . . . . . . . . . . . 305
lib.workspace.exclude_design_filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
lib.workspace.group_libs_create_slg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
lib.workspace.group_libs_fix_cell_shadowing . . . . . . . . . . . . . . . . . . . . . . . . . 309
lib.workspace.group_libs_macro_grouping_strategy . . . . . . . . . . . . . . . . . . . . 310
lib.workspace.group_libs_naming_strategies . . . . . . . . . . . . . . . . . . . . . . . . . 312
lib.workspace.group_libs_physical_only_name . . . . . . . . . . . . . . . . . . . . . . . . 314
lib.workspace.include_design_filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
lib.workspace.keep_all_physical_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
lib.workspace.remove_frame_bus_properties . . . . . . . . . . . . . . . . . . . . . . . . . 319
lib.workspace.save_layout_views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
lib_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
lib_cell_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
lib_pin_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
lib_timing_arc_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
link.bit_blast_naming_style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
link.prefer_frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
link.reference_limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
link.require_physical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
link.undo_enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
link.user_units_from_first_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
link.verbose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
link_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
matching_type_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
mode_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
module_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
mv.pg.default_ground_supply_net_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
mv.pg.default_ground_supply_port_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
mv.pg.default_power_supply_net_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
mv.pg.default_power_supply_port_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
mv.upf.connect_supply_net_ignore_nonexistent_objects . . . . . . . . . . . . . . . . 354
Chapter 1: Contents
Contents
xi
1-xi
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
mv.upf.enable_pg_pin_reconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
mv.upf.input_enforce_simple_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
mv.upf.load_upf_continue_on_error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
mv.upf.max_supply_count_without_driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
mv.upf.name_map_version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
mv.upf.save_upf_include_supply_exceptions . . . . . . . . . . . . . . . . . . . . . . . . . 360
mv.upf.upf_bias_support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
net_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
opt.area.effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
opt.common.allow_physical_feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
opt.common.buffer_area_effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
opt.common.do_physical_checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
opt.common.enable_target_library_subset_opt . . . . . . . . . . . . . . . . . . . . . . . . 370
opt.common.max_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
opt.common.max_net_length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
opt.common.preserve_pin_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
opt.common.select_inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
opt.common.user_instance_name_prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
opt.dft.clock_aware_scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
opt.dft.optimize_scan_chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
opt.leakage.effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
opt.mcmm.dominant_scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
opt.mcmm.use_synthetic_corners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
opt.port.eliminate_verilog_assign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
opt.power.mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
opt.preroute.physical_synthesis_effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
opt.preroute_synthesis.architecture_booster_transform . . . . . . . . . . . . . . . . . 385
opt.tie_cell.max_fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
opt.timing.effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
outline_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
output_delay_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
parasitic_tech_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
path_group_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Contents
xii
pg_region_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
pin_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
pin_blockage_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
pin_guide_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
place.coarse.congestion_analysis_effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
place.coarse.congestion_driven_max_util . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
place.coarse.detect_detours . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
place.coarse.enable_enhanced_soft_blockages . . . . . . . . . . . . . . . . . . . . . . . 414
place.coarse.enable_spare_cell_placement . . . . . . . . . . . . . . . . . . . . . . . . . . 415
place.coarse.fix_cells_on_soft_blockages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
place.coarse.fix_hard_macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
place.coarse.fix_ios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
place.coarse.fix_soft_macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
place.coarse.icg_auto_bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
place.coarse.icg_auto_bound_fanout_limit . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
place.coarse.low_power_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
place.coarse.max_density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
place.coarse.perturbation_effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
place.coarse.pin_density_aware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
place.coarse.target_routing_density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
place.floorplan.density_aware_hard_movebounds . . . . . . . . . . . . . . . . . . . . . 427
place.floorplan.sliver_size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
place.legalize.enable_prerouted_net_check . . . . . . . . . . . . . . . . . . . . . . . . . . 429
place.rp.allow_non_rp_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
place.rp.allow_non_rp_cells_on_blockages . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
place.rules.vertical_abutment_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
place_opt.congestion.effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
place_opt.final_place.effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
place_opt.final_place.legalize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
place_opt.flow.clock_aware_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
place_opt.flow.do_path_opt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
place_opt.flow.do_spg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
place_opt.flow.optimize_icgs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
Chapter 1: Contents
Contents
xiii
1-xiii
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place_opt.flow.optimize_icgs_critical_range . . . . . . . . . . . . . . . . . . . . . . . . . . 441
place_opt.flow.optimize_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
place_opt.flow.optimize_layers_critical_range . . . . . . . . . . . . . . . . . . . . . . . . . 443
place_opt.flow.optimize_ndr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
place_opt.flow.trial_clock_tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
place_opt.initial_drc.global_route_based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
place_opt.initial_place.effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
place_opt.initial_place.two_pass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
placement_blockage_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
plan.budget.add_missing_feedthrough_clocks . . . . . . . . . . . . . . . . . . . . . . . . 452
plan.budget.all_design_subblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
plan.budget.all_full_budgets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
plan.budget.allow_disconnected_gclocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
plan.budget.allow_top_only_exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
plan.budget.bbt_fixed_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
plan.budget.compute_rise_fall_latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
plan.budget.estimate_timing_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
plan.budget.include_all_clock_inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
plan.budget.include_feedthrough_clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
plan.budget.pessimistic_driving_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
plan.budget.split_latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
plan.budget.time_with_margins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
plan.clock_trunk.estimate_block_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
plan.distributed_run.block_host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
plan.estimate_timing.abstract_add_feedthrough_buffer . . . . . . . . . . . . . . . . . 474
plan.estimate_timing.abstract_feedthrough_buffer_side . . . . . . . . . . . . . . . . . 475
plan.estimate_timing.abstract_feedthrough_logical . . . . . . . . . . . . . . . . . . . . . 476
plan.estimate_timing.abstract_feedthrough_user_buffer . . . . . . . . . . . . . . . . . 477
plan.estimate_timing.optimize_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
plan.estimate_timing.optimize_layers_count . . . . . . . . . . . . . . . . . . . . . . . . . . 479
plan.flow.create_block_abstract_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
plan.flow.overwrite_work_dir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
plan.flow.segment_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
Contents
xiv
plan.flow.target_site_def . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
plan.macro.auto_macro_array_max_height . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
plan.macro.auto_macro_array_max_num_cols . . . . . . . . . . . . . . . . . . . . . . . . 485
plan.macro.auto_macro_array_max_num_rows . . . . . . . . . . . . . . . . . . . . . . . 486
plan.macro.auto_macro_array_max_width . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
plan.macro.auto_macro_array_minimize_channels . . . . . . . . . . . . . . . . . . . . . 488
plan.macro.auto_macro_array_size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
plan.macro.buffer_channel_height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
plan.macro.buffer_channel_width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
plan.macro.congestion_iters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
plan.macro.create_temporary_pg_grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
plan.macro.cross_block_connectivity_planning . . . . . . . . . . . . . . . . . . . . . . . . 495
plan.macro.grid_error_behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
plan.macro.macro_place_only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
plan.macro.max_buffer_stack_height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
plan.macro.max_buffer_stack_width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
plan.macro.pin_shape_track_match_threshold . . . . . . . . . . . . . . . . . . . . . . . . 500
plan.macro.spacing_rule_heights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
plan.macro.spacing_rule_widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
plan.mtcmos.allow_partial_power_strap_overlap . . . . . . . . . . . . . . . . . . . . . . 504
plan.mtcmos.allow_power_switch_outside_core . . . . . . . . . . . . . . . . . . . . . . . 505
plan.mtcmos.snap_to_legal_index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
plan.mtcmos.snap_to_siterow_orient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
plan.mtcmos.treat_keepout_as_blockage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
plan.mtcmos.treat_voltage_area_as_blockage . . . . . . . . . . . . . . . . . . . . . . . . 509
plan.outline.dense_module_depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
plan.outline.glue_cell_count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
plan.outline.keep_port_depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
plan.outline.large_threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
plan.outline.message_limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
plan.outline.partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
plan.outline.target_block_size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
plan.outline.target_cell_count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Chapter 1: Contents
Contents
xv
1-xv
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.path_analysis.enable_timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
plan.pgcheck.check_signal_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
plan.pgcheck.ignore_unfixed_std_cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
plan.pgcheck.use_pin_as_bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
plan.pgroute.auto_connect_pg_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
plan.pgroute.disable_via_creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
plan.pgroute.drc_check_fast_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
plan.pgroute.honor_signal_route_drc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
plan.pgroute.honor_std_cell_drc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
plan.pgroute.max_undo_steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
plan.pgroute.overlap_route_boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
plan.pgroute.snap_stdcell_rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
plan.pgroute.verbose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
plan.pgroute.via_site_threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
plan.pins.exclude_clocks_from_feedthroughs . . . . . . . . . . . . . . . . . . . . . . . . . 532
plan.pins.exclude_inout_nets_from_feedthroughs . . . . . . . . . . . . . . . . . . . . . . 533
plan.pins.incremental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
plan.pins.layer_range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
plan.pins.new_port_name_tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
plan.pins.new_port_name_tag_style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
plan.pins.pin_range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
plan.pins.reserved_channel_threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
plan.pins.retain_bus_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
plan.pins.synthesize_abutted_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
plan.place.auto_generate_blockages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
plan.place.auto_generate_blockages_smooth_rectilinear . . . . . . . . . . . . . . . . 546
plan.place.auto_generate_hard_blockage_channel_width . . . . . . . . . . . . . . . 548
plan.place.auto_generate_soft_blockage_channel_width . . . . . . . . . . . . . . . . 550
plan.place.auto_max_density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
plan.place.congestion_driven_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
plan.place.default_keepout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
plan.place.poly_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
plan.place.trace_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
Contents
xvi
plan.pna.power_switch_resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
plan.shaping.snap_to_boundary_grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
poly_rect_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
port_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
power.clock_network_include_clock_gating_network . . . . . . . . . . . . . . . . . . . 569
power.clock_network_include_clock_sink_pin_power . . . . . . . . . . . . . . . . . . . 570
power.default_static_probability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
power.default_toggle_rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
power.default_toggle_rate_reference_clock . . . . . . . . . . . . . . . . . . . . . . . . . . 573
power.internal_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
power.leakage_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
power.propagation_effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
power.swcap_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
power_domain_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
power_strategy_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
query_objects_format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
refine_opt.congestion.effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
refine_opt.flow.clock_aware_placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
refine_opt.flow.do_path_opt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
refine_opt.flow.exclusive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
refine_opt.flow.optimize_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
refine_opt.flow.optimize_layers_critical_range . . . . . . . . . . . . . . . . . . . . . . . . 587
refine_opt.flow.optimize_ndr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
refine_opt.flow.optimize_rp_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
refine_opt.hold.effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
refine_opt.path_opt.fixed_cell_disturbance . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
refine_opt.place.effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
refine_opt.place.legalize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
route.common.allow_pg_as_shield . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
route.common.check_shield . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
route.common.clock_topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
route.common.color_based_dpt_flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
route.common.comb_distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Chapter 1: Contents
Contents
xvii
1-xvii
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.concurrent_redundant_via_effort_level . . . . . . . . . . . . . . . . . . 600
route.common.concurrent_redundant_via_mode . . . . . . . . . . . . . . . . . . . . . . 601
route.common.connect_floating_shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
route.common.connect_within_pins_by_layer_name . . . . . . . . . . . . . . . . . . . 604
route.common.eco_route_concurrent_redundant_via_effort_level . . . . . . . . . 606
route.common.eco_route_concurrent_redundant_via_mode . . . . . . . . . . . . . 607
route.common.extra_nonpreferred_direction_wire_cost_multiplier_by_layer_nam
e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
route.common.extra_preferred_direction_wire_cost_multiplier_by_layer_name . .
610
route.common.extra_via_cost_multiplier_by_layer_name . . . . . . . . . . . . . . . . 612
route.common.extra_via_off_grid_cost_multiplier_by_layer_name . . . . . . . . . 614
route.common.forbid_new_metal_by_layer_name . . . . . . . . . . . . . . . . . . . . . 616
route.common.freeze_layer_by_layer_name . . . . . . . . . . . . . . . . . . . . . . . . . . 618
route.common.freeze_via_to_frozen_layer_by_layer_name . . . . . . . . . . . . . . 620
route.common.global_max_layer_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
route.common.global_min_layer_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
route.common.high_resistance_flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
route.common.ignore_var_spacing_to_blockage . . . . . . . . . . . . . . . . . . . . . . 627
route.common.ignore_var_spacing_to_pg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
route.common.ignore_var_spacing_to_shield . . . . . . . . . . . . . . . . . . . . . . . . . 629
route.common.mark_clock_nets_minor_change . . . . . . . . . . . . . . . . . . . . . . . 630
route.common.min_edge_offset_for_macro_pin_connection_by_layer_name 631
route.common.min_shield_length_by_layer_name . . . . . . . . . . . . . . . . . . . . . 633
route.common.net_max_layer_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
route.common.net_max_layer_mode_soft_cost . . . . . . . . . . . . . . . . . . . . . . . 637
route.common.net_min_layer_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
route.common.net_min_layer_mode_soft_cost . . . . . . . . . . . . . . . . . . . . . . . . 640
route.common.number_of_secondary_pg_pin_connections . . . . . . . . . . . . . . 641
route.common.number_of_vias_over_global_max_layer . . . . . . . . . . . . . . . . 642
route.common.number_of_vias_over_net_max_layer . . . . . . . . . . . . . . . . . . . 643
route.common.number_of_vias_under_global_min_layer . . . . . . . . . . . . . . . . 644
route.common.number_of_vias_under_net_min_layer . . . . . . . . . . . . . . . . . . 645
route.common.pg_shield_distance_threshold . . . . . . . . . . . . . . . . . . . . . . . . . 646
Contents
xviii
route.common.post_detail_route_fix_soft_violations . . . . . . . . . . . . . . . . . . . . 647
route.common.post_detail_route_redundant_via_insertion . . . . . . . . . . . . . . . 648
route.common.post_eco_route_fix_soft_violations . . . . . . . . . . . . . . . . . . . . . 649
route.common.post_group_route_fix_soft_violations . . . . . . . . . . . . . . . . . . . . 650
route.common.post_incremental_detail_route_fix_soft_violations . . . . . . . . . . 651
route.common.rc_driven_setup_effort_level . . . . . . . . . . . . . . . . . . . . . . . . . . 652
route.common.report_local_double_pattern_odd_cycles . . . . . . . . . . . . . . . . 653
route.common.reroute_clock_shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
route.common.reroute_user_shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
route.common.reshield_modified_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
route.common.rotate_default_vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
route.common.route_soft_rule_effort_level . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
route.common.route_top_boundary_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
route.common.routing_rule_effort_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
route.common.separate_tie_off_from_secondary_pg . . . . . . . . . . . . . . . . . . . 665
route.common.shielding_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
route.common.single_connection_to_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
route.common.soft_rule_weight_to_effort_level_map . . . . . . . . . . . . . . . . . . . 669
route.common.standard_cell_blockage_as_thin . . . . . . . . . . . . . . . . . . . . . . . 671
route.common.threshold_noise_ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
route.common.tie_off_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
route.common.track_auto_fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
route.common.verbose_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
route.common.via_array_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
route.common.via_on_grid_by_layer_name . . . . . . . . . . . . . . . . . . . . . . . . . . 677
route.common.virtual_flat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
route.common.wide_macro_pin_as_fat_wire . . . . . . . . . . . . . . . . . . . . . . . . . . 681
route.common.wire_on_grid_by_layer_name . . . . . . . . . . . . . . . . . . . . . . . . . 682
route.detail.antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
route.detail.antenna_fixing_preference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
route.detail.antenna_on_iteration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
route.detail.antenna_verbose_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
route.detail.check_antenna_on_pg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
Chapter 1: Contents
Contents
xix
1-xix
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.check_patchable_drc_from_fixed_shapes . . . . . . . . . . . . . . . . . . 689
route.detail.check_pin_min_area_min_length . . . . . . . . . . . . . . . . . . . . . . . . . 690
route.detail.check_port_min_area_min_length . . . . . . . . . . . . . . . . . . . . . . . . 691
route.detail.continue_after_large_design_rule_value_error . . . . . . . . . . . . . . . 692
route.detail.default_diode_protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
route.detail.default_gate_size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
route.detail.default_port_external_antenna_area . . . . . . . . . . . . . . . . . . . . . . 695
route.detail.default_port_external_gate_size . . . . . . . . . . . . . . . . . . . . . . . . . . 696
route.detail.detail_route_special_design_rule_fixing_stage . . . . . . . . . . . . . . . 697
route.detail.diagonal_min_width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
route.detail.diode_insertion_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
route.detail.diode_libcell_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
route.detail.diode_preference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
route.detail.drc_convergence_effort_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
route.detail.eco_max_number_of_iterations . . . . . . . . . . . . . . . . . . . . . . . . . . 703
route.detail.eco_route_special_design_rule_fixing_stage . . . . . . . . . . . . . . . . 705
route.detail.eco_route_use_soft_spacing_for_timing_optimization . . . . . . . . . 706
route.detail.elapsed_time_limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
route.detail.force_max_number_iterations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
route.detail.generate_extra_off_grid_pin_tracks . . . . . . . . . . . . . . . . . . . . . . . 709
route.detail.generate_off_grid_feed_through_tracks . . . . . . . . . . . . . . . . . . . . 710
route.detail.group_route_special_design_rule_fixing_stage . . . . . . . . . . . . . . 711
route.detail.hop_layers_to_fix_antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
route.detail.ignore_drc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
route.detail.incremental_detail_route_special_design_rule_fixing_stage . . . . 715
route.detail.insert_diodes_during_routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
route.detail.macro_pin_antenna_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
route.detail.max_antenna_pin_count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
route.detail.merge_gates_for_antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
route.detail.optimize_tie_off_effort_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
route.detail.optimize_wire_via_effort_level . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
route.detail.pin_taper_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
route.detail.port_antenna_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Contents
xx
route.detail.post_process_special_design_rule_fixing_stage . . . . . . . . . . . . . 725
route.detail.repair_shorts_over_macros_effort_level . . . . . . . . . . . . . . . . . . . . 726
route.detail.report_ignore_drc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
route.detail.reuse_filler_locations_for_diodes . . . . . . . . . . . . . . . . . . . . . . . . . 730
route.detail.save_after_iterations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
route.detail.save_cell_prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
route.detail.skip_antenna_fixing_for_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
route.detail.timing_driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
route.detail.top_layer_antenna_fix_threshold . . . . . . . . . . . . . . . . . . . . . . . . . 735
route.detail.use_default_width_for_min_area_min_len_stub . . . . . . . . . . . . . . 736
route.detail.use_lower_hierarchy_for_port_diodes . . . . . . . . . . . . . . . . . . . . . 737
route.detail.use_wide_wire_effort_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
route.detail.use_wide_wire_to_input_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
route.detail.use_wide_wire_to_macro_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
route.detail.use_wide_wire_to_output_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
route.detail.use_wide_wire_to_pad_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
route.detail.use_wide_wire_to_port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
route.detail.user_defined_partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
route.detail.var_spacing_to_same_net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
route.global.coarse_grid_refinement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
route.global.connect_pins_outside_routing_corridor . . . . . . . . . . . . . . . . . . . . 748
route.global.crosstalk_driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
route.global.deterministic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
route.global.double_pattern_utilization_by_layer_name . . . . . . . . . . . . . . . . . 751
route.global.effort_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
route.global.exclude_blocked_gcells_from_congestion_report . . . . . . . . . . . . 755
route.global.extra_blocked_layer_utilization_reduction . . . . . . . . . . . . . . . . . . 756
route.global.force_full_effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
route.global.macro_boundary_track_utilization . . . . . . . . . . . . . . . . . . . . . . . . 758
route.global.macro_boundary_width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
route.global.macro_corner_track_utilization . . . . . . . . . . . . . . . . . . . . . . . . . . 760
route.global.timing_driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
route.global.timing_driven_effort_level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
Chapter 1: Contents
Contents
xxi
1-xxi
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.global.voltage_area_corner_track_utilization . . . . . . . . . . . . . . . . . . . . . 763
route.track.crosstalk_driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
route.track.timing_driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
route_opt.eco_route.mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
route_opt.flow.enable_ccd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
route_opt.flow.enable_cto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
route_opt.flow.enable_power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
route_opt.flow.xtalk_reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
routing_blockage_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
routing_corridor_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
routing_corridor_shape_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
routing_guide_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
routing_rule_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
rp_blockage_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
rp_group_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
scenario_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
search_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
sh_allow_tcl_with_set_app_var . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
sh_allow_tcl_with_set_app_var_no_message_list . . . . . . . . . . . . . . . . . . . . . 800
sh_arch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
sh_command_abbrev_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
sh_command_abbrev_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
sh_command_log_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
sh_continue_on_error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
sh_deprecated_is_error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
sh_dev_null . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
sh_enable_page_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
sh_enable_stdout_redirect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
sh_help_shows_group_overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
sh_obsolete_is_error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
sh_output_log_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
sh_product_version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
sh_script_stop_severity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
Contents
xxii
sh_source_emits_line_numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
sh_source_logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
sh_source_uses_search_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
sh_tcllib_app_dirname . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
sh_user_man_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
shape_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
shaping_blockage_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
shell.common.collection_result_display_limit . . . . . . . . . . . . . . . . . . . . . . . . . . 829
shell.common.copyright_year . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
shell.common.enable_line_editing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
shell.common.line_editing_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
shell.common.product_abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
shell.common.product_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
shell.common.product_version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
shell.common.report_default_significant_digits . . . . . . . . . . . . . . . . . . . . . . . . 837
shell.common.shell_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
shell.common.single_line_messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
shell.common.tmp_dir_path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
signoff.antenna.contact_layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
signoff.antenna.contact_layers_between_m0_diffusion . . . . . . . . . . . . . . . . . 843
signoff.antenna.custom_runset_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
signoff.antenna.diffusion_layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
signoff.antenna.enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
signoff.antenna.extract_via_antenna_property . . . . . . . . . . . . . . . . . . . . . . . . 848
signoff.antenna.gate_class1_layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
signoff.antenna.hierarchical_gate_class_include_file . . . . . . . . . . . . . . . . . . . 852
signoff.antenna.m0_layers_for_diffusion_connection . . . . . . . . . . . . . . . . . . . 854
signoff.antenna.m0_layers_for_poly_connection . . . . . . . . . . . . . . . . . . . . . . . 855
signoff.antenna.max_gate_class_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
signoff.antenna.poly_layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858
signoff.antenna.report_diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
Chapter 1: Contents
Contents
xxiii
1-xxiii
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.antenna.top_cell_pin_only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
signoff.antenna.treat_source_drain_as_diodes . . . . . . . . . . . . . . . . . . . . . . . . 863
signoff.antenna.user_defined_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
signoff.antenna.v0_layers_between_m1_m0 . . . . . . . . . . . . . . . . . . . . . . . . . . 865
signoff.calculate_hier_antenna_property.extract_via_antenna_prop . . . . . . . . 866
signoff.calculate_hier_antenna_property.user_defined_options . . . . . . . . . . . 867
signoff.check_design.generate_runset_only . . . . . . . . . . . . . . . . . . . . . . . . . . 868
signoff.check_design.max_errors_per_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
signoff.check_design.run_dir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
signoff.check_design.runset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
signoff.check_design.user_defined_options . . . . . . . . . . . . . . . . . . . . . . . . . . 872
signoff.check_drc.always_read_fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
signoff.check_drc.auto_eco_threshold_value . . . . . . . . . . . . . . . . . . . . . . . . . 874
signoff.check_drc.excluded_cell_types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
signoff.check_drc.ignore_blockages_in_cells . . . . . . . . . . . . . . . . . . . . . . . . . 877
signoff.check_drc.ignore_child_cell_errors . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
signoff.check_drc.max_errors_per_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
signoff.check_drc.merge_base_error_name . . . . . . . . . . . . . . . . . . . . . . . . . . 881
signoff.check_drc.merge_incremental_error_data . . . . . . . . . . . . . . . . . . . . . . 883
signoff.check_drc.read_design_view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
signoff.check_drc.read_design_views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
signoff.check_drc.run_dir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
signoff.check_drc.runset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
signoff.check_drc.user_defined_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
signoff.color_macro.enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
signoff.color_macro.input_gds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
signoff.color_macro.layer_map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
signoff.color_macro.macro_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894
signoff.color_macro.output_gds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895
signoff.color_macro.preferred_routing_direction . . . . . . . . . . . . . . . . . . . . . . . 896
signoff.color_macro.rule_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
signoff.color_macro.run_dir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898
signoff.color_macro.technology_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 899
Contents
xxiv
signoff.color_macro.track_color_preference . . . . . . . . . . . . . . . . . . . . . . . . . . 900
signoff.color_macro.track_offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901
signoff.create_metal_fill.apply_nondefault_rules . . . . . . . . . . . . . . . . . . . . . . . 902
signoff.create_metal_fill.auto_eco_threshold_value . . . . . . . . . . . . . . . . . . . . 903
signoff.create_metal_fill.fill_over_net_on_adjacent_layer . . . . . . . . . . . . . . . . 904
signoff.create_metal_fill.fix_density_errors . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
signoff.create_metal_fill.flat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
signoff.create_metal_fill.max_density_threshold . . . . . . . . . . . . . . . . . . . . . . . 908
signoff.create_metal_fill.run_dir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
signoff.create_metal_fill.runset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910
signoff.create_metal_fill.space_to_clock_nets . . . . . . . . . . . . . . . . . . . . . . . . . 911
signoff.create_metal_fill.space_to_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
signoff.create_metal_fill.space_to_nets_on_adjacent_layer . . . . . . . . . . . . . . 914
signoff.create_metal_fill.tcd_fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
signoff.create_metal_fill.user_defined_options . . . . . . . . . . . . . . . . . . . . . . . . 917
signoff.fix_drc.advanced_guidance_for_rules . . . . . . . . . . . . . . . . . . . . . . . . . 918
signoff.fix_drc.check_drc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
signoff.fix_drc.config_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
signoff.fix_drc.custom_guidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
signoff.fix_drc.fix_detail_route_drc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
signoff.fix_drc.init_drc_error_db . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
signoff.fix_drc.last_run_full_chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
signoff.fix_drc.max_detail_route_iterations . . . . . . . . . . . . . . . . . . . . . . . . . . . 925
signoff.fix_drc.max_errors_per_rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
signoff.fix_drc.read_frame_view_only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
signoff.fix_drc.run_dir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
signoff.fix_drc.target_clock_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
signoff.fix_drc.user_defined_options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
signoff.fix_isolated_via.avoid_net_types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
signoff.fix_isolated_via.isolated_via_max_range . . . . . . . . . . . . . . . . . . . . . . . 934
signoff.fix_isolated_via.run_dir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
signoff.fix_isolated_via.user_defined_options . . . . . . . . . . . . . . . . . . . . . . . . . 936
signoff.physical.layer_map_file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Chapter 1: Contents
Contents
xxv
1-xxv
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.physical.merge_stream_files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
site_array_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
site_def_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
site_row_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
skew_group_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
supernet_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952
supply_net_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
supply_port_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
supply_set_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
synopsys_program_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960
synopsys_root . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
tech_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
tech_purpose_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
terminal_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
time.all_clocks_propagated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
time.aocvm_analysis_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
time.aocvm_enable_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
time.aocvm_enable_clock_network_only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
time.aocvm_enable_single_path_metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
time.case_analysis_propagate_through_icg . . . . . . . . . . . . . . . . . . . . . . . . . . 977
time.case_analysis_sequential_propagation . . . . . . . . . . . . . . . . . . . . . . . . . . 978
time.clock_gating_propagate_enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
time.clock_gating_user_setting_only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
time.clock_reconvergence_pessimism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
time.convert_constraint_from_bc_wc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
time.create_clock_no_input_delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
time.crpr_remove_clock_to_data_crp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
time.delay_calculation_style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
time.disable_case_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989
time.disable_case_analysis_ti_hi_lo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990
time.disable_clock_gating_checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
time.disable_cond_default_arcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
time.disable_internal_inout_net_arcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994
Contents
xxvi
time.disable_recovery_removal_checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
time.early_launch_at_latch_loop_breaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
time.edge_specific_source_latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
time.enable_clock_propagation_through_preset_clear . . . . . . . . . . . . . . . . . . 999
time.enable_clock_propagation_through_three_state_enable_pins . . . . . . . 1000
time.enable_clock_to_data_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
time.enable_io_path_groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002
time.enable_non_sequential_checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
time.enable_preset_clear_arcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
time.gclock_source_network_num_master_registers . . . . . . . . . . . . . . . . . . 1006
time.high_fanout_net_pin_capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
time.high_fanout_net_threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
time.ideal_clock_zero_default_transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
time.ocvm_enable_distance_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
time.ocvm_precedence_compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
time.pocvm_corner_sigma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
time.pocvm_enable_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
time.port_input_threshold_fall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
time.port_input_threshold_rise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019
time.port_output_threshold_fall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
time.port_output_threshold_rise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
time.port_slew_derate_from_library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
time.port_slew_lower_threshold_fall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
time.port_slew_lower_threshold_rise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
time.port_slew_upper_threshold_fall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
time.port_slew_upper_threshold_rise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
time.remove_clock_reconvergence_pessimism . . . . . . . . . . . . . . . . . . . . . . 1035
time.report_with_clock_path_edrc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
time.scenario_auto_name_separator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
time.si_enable_analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040
time.use_lib_cell_generated_clock_name . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
time.use_pin_capacitance_ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042
timing_arc_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043
Chapter 1: Contents
Contents
xxvii
1-xxvii
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
timing_exception_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
timing_path_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
timing_point_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
topological_constraint_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
topology_edge_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
topology_node_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
track_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
utilization_config_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
via_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
via_def_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
voltage_area_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
voltage_area_shape_attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
wildcards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089
Contents
xxviii
abstract.allow_fault_in
To support automatic missing pin additions to abstract boundary.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This app-option is used to support automatic missing pin additions to abstract boundary
when necessary. User must set this as true to enable the support. User need to set this
app-option before opening top level design.
SEE ALSO
get_app_option_value(2)
set_app_options(2)
Chapter 1:
abstract.allow_fault_in
1
1-1
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
abstract.high_fanout_limit
Set threshold for high fanout when generating "full" timing abstracts.
TYPE
integer
DEFAULT
600
DESCRIPTION
The -timing_level option of the create_abstract command may be used to create a "full"
abstract. Full abstracts contain nearly all of the boundary (donut) logic that can be found in
the original design. But some of the boundary logic is filtered out in order to keep the
abstract size reasonable. In particular, logic connected only to high-fanout networks is
filtered. Usually, the filtered logic includes clock networks, scan enable, and reset. For these
signals, only the essential part of the logic is kept, instead of all of the logic.
The abstract.high_fanout_limit option allows you to control how much logic is filtered. If you
set the value to 1000, then only high fanout networks with more than 1000 fanouts will be
filtered. If you set the value to 5000, then only high fanout networks with more than 5000
fanouts will be filtered.
You can set the value to 0 if you want to turn off filtering completely. Usually this will cause
every register in your design to be included in the abstract.
If you set the value very low, you will get an abstract which is very similar to a "compact"
abstract.
SEE ALSO
report_app_options(2)
set_app_options(2)
create_abstract(2)
abstract.high_fanout_limit
abstract.include_aggressor_nets
To include aggressors in the block-abstract netlist.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This app-option is used to support Signal Integrity(SI) flow with block-abstracts. User must
set this as true to include the aggressors of the nets belonging to the block-abstract in the
block-abstract netlist. This will help improve timing correlation with SI. User need to set this
app-option before create_abstract command.
SEE ALSO
set_app_options(2)
Chapter 1:
abstract.include_aggressor_nets
3
1-3
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
abstract.latch_levels
Controls the number of latch levels included in the timing abstract
TYPE
Integer
DEFAULT
3
DESCRIPTION
This app-option is used to control the number of latch levels that will be included in the timing
abstract. Using a higher value can increase the accuracy of timing operations at the
top-level, at the expense of additional run-time.
SEE ALSO
set_app_options(2)
abstract.latch_levels
block_attributes
Description of the predefined attributes for blocks.
DESCRIPTION
Attributes are properties assigned to objects such as pins, cells and nets. Definitions for
block attributes are provided in the subsections that follow.
Attributes are read-only unless marked as settable. Read-only attributes are informational,
and you cannot set its value. A settable attribute can be modified with the set_attribute
command.
To determine the value of an attribute, use the get_attribute command. To see a list of all
attributes available for a class of objects use the list_attributes -application command.
Block Attributes
bbox
A rectangle attribute for the bounding-box of a design. The format of a rectangle
specification is {{llx lly} {urx ury}}, which specifies the lower-left and upper-right corners of
the rectangle.
boundary
A coordinate_list attribute for the boundary of a design. The format of a coordinate_list
specification is {{x1 y1} {x2 y2}...}. This attribute is settable. If you want to clear an existing
boundary, use the remove_attribute(2) command.
boundary_bbox
the rectangle.
clock_path_target_library_subset
A collection attribute containing the lib objects in the target library subset assigned to this
block to constrain the clock paths. This attribute contains only the libraries which were
Chapter 1:
block_attributes
5
1-5
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
explicitly specified in the target library subset assigned to this block. It does not contain
libraries which are inferred from the reference library list.
clock_path_target_lib_cell_subset
A collection attribute containing the lib_cell objects in the target library subset's only-here list
assigned to this block to constrain the clock paths.
clock_path_target_lib_cell_exclusions
A collection attribute containing the lib_cell objects in the target library subset's dont-use list
assigned to this block to constrain the clock paths.
core_area_area
A double attribute for the area of the core_area.
core_area_bbox
A rectangle attribute for the bounding-box of the core_area. The format of a rectangle
the rectangle.
core_area_boundary
A coordinate_list attribute for the coordinates of the core_area. The format of a
coordinate_list specification is {{x1 y1} {x2 y2}...}.
data_path_target_library_subset
block to constrain the data paths. This attribute contains only the libraries which were
explicitly specified in the target library subset assigned to this block. It does not contain
libraries which are inferred from the reference library list.
data_path_target_lib_cell_subset
assigned to this block to constrain the data paths.
data_path_target_lib_cell_exclusions
assigned to this block to constrain the data paths.
block_attributes
design
A collection attribute of design of this block.
design_name
A string attribute for the name of this block as a design.
extended_name
A string attribute representing the full path to the library plus the design name, separated by
a ':' character, an optional label name, separated by a '/' character, and a view name,
separated by a '.'. For example, "/disks/user1/work/top_lib:top_design/my_label.design".
full_name
A string attribute for the full name of a block, including the library name plus the block name,
separated by a ':' character, an optional label name, separated by a '/' character, and a view
name, separated by a '.' character. For example, "top_lib:top_design/my_label.design"
inner_keepout_margin
A margin_list attribute
inner_keepout_type
A string attribute representing the inner keepout type of the design. This attribute is settable.
Valid values are "hard" and "soft".
is_current
A Boolean attribute. The value will be "true" if this design is the current_design for the
session, "false" otherwise.
is_hierarchical
A Boolean attribute. The value is always true.
is_mask_shiftable
A Boolean attribute. If the value is "true" then this block enables multi-patterning mask
shifting of cells. If "false", the mask_shift of any cell which references this block will be
ignored.
Chapter 1:
block_attributes
7
1-7
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
is_modified
A Boolean attribute. The value will be "true" if this design has modified and un-saved data,
false otherwise. This attribute is settable.
is_open
A Boolean attribute. The value will be "true" if this design is already loaded into memory,
false otherwise.
last_modified
A string attribute representing the date and time this design was last modified.
last_saved
A string attribute representing the date and time this design was last saved.
lib
A collection attribute of library of this design.
lib_name
A string attribute for the name of library of this design.
logic_only
A Boolean attribute. The value will be "true" if this design is marked for the logic-only design
flow. The attribute can only be set to "true" before the design is linked with link_design.
Logic-only designs are used for Design Planning budgeting timing. They can not have
physical design information, so they use less memory.
use_frame_blockage
A Boolean attribute. This option enables the user to choose to not use blockages in certain
frames. The default value is "true", which results in usage of the blockages in the frame.
object_class
A string attribute with the value of "block".
block_attributes
open_count
An integer attribute representing the number of times this design has been opened.
subset_name
A String attribute indicating the block subset name for LEQ. This attribute is valid only for
blocks which are library cells. All library cells with no subset name also form a subset, which
is used by the technology mapping function. Named subsets are used for special library
cells (e.g., clock buffers that are specifically designed to match the delay of certain clock
gates).
switch_list
A string attribute representing the effective view switch list of this design. The effective view
switch list is the precedence-ordered list of design views that is applied when attempting to
bind this design.
top_module
A collection attribute of the top module of this design.
top_module_name
A string attribute for the name of the top module of this design. This attribute is settable, and
will change the name of the top module in the design. This is useful when managing multiple
versions of modules, allowing use of the different versions by giving them different
top-module names.
view_name
A string attribute for the view name of this design. The valid value is ine of, abstract, design,
frame, layout, outline or timing.
SEE ALSO
current_block(2)
get_blocks(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
block_attributes
9
1-9
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
bound_attributes
Description of the predefined attributes for bounds.
DESCRIPTION
bound attributes are provided in the subsections that follow.
command.
Bound Attributes
allowed_design_type
A string attribute that specifies the type of cells that are allowed to be associated with the
bound. The possible value are abstract, analog, black_box, corner, cover, diode, end_cap,
fill, filler, flip_chip_driver, flip_chip_pad, lib_cell, macro, module, pad, pad_spacer,
physical_only and well_tap.
bbox
A rectangle attribute for the bounding-box of a bound. The format of a rectangle specification
is {{llx lly} {urx ury}}, which specifies the lower-left and upper-right corners of the rectangle.
bound_type
A string attribute telling if the bound is a group bound or a move bound.
cells
A collection attribute of the cells associated with this bound.
bound_attributes
10
dimensions
A coordinate attribute representing the width of bound as x-coordinate and height as
y-coordinate. This is a settable attribute and is applicable for group bounds only.
effort
A string attribute representing the effort of bringing cells closer inside a group bound. This is
a settable attribute and is applicable for group bounds only. The values it can take are
restricted to high, low, medium and ultra.
full_name
A string attribute for the name of the bound.
in_edit_group
A Boolean attribute to specify whether a bound belongs to an edit_group.
is_exclusive
A Boolean attribute to specify whether a move bound should be treated as an exclusive area
with respect to cells not associated with this bound. This is a settable attribute and is
applicable for move bounds only.
is_shadow
A Boolean attribute to specify whether a bound is pushed down from above.
name
A string attribute for the name of the bound. This is a settable attribute.
object_class
A string attribute with the value of "bound".
ports
A collection attribute of the ports associated with this bound.
Chapter 1:
bound_attributes
11
1-11
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
shadow_status
A string attribute to represent the shadow status of a bound. Valid values are copied_down,
copied_up, normal, pulled_up, and pushed_down. This is a settable attribute.
shape_count
An integer attribute representing number of bound_shape objects in the bound. This is
applicable for move bounds only.
shapes
A collection attribute with the bound_shape objects in the bound. This is applicable for move
bounds only.
type
A string attribute representing the type of bound as hard or soft. This is a settable attribute
and the values are restricted to hard and soft.
utilization
A float attribute representing the utilization of a move bound as ratio of area of associated
instances to the area of the bound.
parent_block
A collection attribute with the owner block object for this bound.
parent_cell
A collection attribute with the owner cell object for this bound.
parent_block_cell
A collection attribute with the parent block cell object for this bound.
top_block
A collection attribute with the top block object for this bound.
bound_attributes
12
SEE ALSO
create_bound(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
bound_attributes
13
1-13
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
bound_shape_attributes
Description of the predefined attributes for bound_shapes.
DESCRIPTION
bound_shape attributes are provided in the subsections that follow.
command.
Bound Shape Attributes
bbox
A rectangle attribute for the bounding-box of a bound_shape. The format of a rectangle
the rectangle.
bound
A collection attribute representing the owning bound of this bound_shape.
boundary
A polygon attribute for the boundary of this bound_shape. The format of a boundary
specification is {{{llx1 lly1} {urx1 ury1}} {{llx2 lly2} {urx2 ury2} ...} ...}. This is a settable
attribute.
full_name
A string attribute for the name of the bound_shape.
name
A string attribute for the name of the bound_shape.
14
object_class
A string attribute with the value of "bound_shape".
SEE ALSO
create_bound_shape(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
15
1-15
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
budget_attributes
Summary of attributes available on tcl objects returned by get_budgets
Attributes of budget clock object

object_class
Returns the string "budget_clock"
full_name
Returns the name of the clock as seen in the output of the report_budget command.
name
Same as full_name
source
Pin or port where budget clock is defined. If this is a portion of a clock tree that crosses into
a budgeted block, then the source is the hierarchical pin on the block where the clock
entered. Will be undefined for top-level virtual clocks.
block
Budget block (a cell) when the clock is defined. Will be undefined for top-level clocks.
clock
Object corresponding to the clock defined by your SDC.
Attributes of budget path type object

object_class
Returns the string "budget_path_type"
full_name
Returns the name of the path_type as seen in the output of the report_budget command.
name
Same as full_name
path_type_id
budget_attributes
16
Returns an integer which is a unique identifier for this path type. You can use this identifier
to check that two objects refer to the same data. This identifier is also used as an anchor in
the output of "report_budget -html".
launch_clock
Returns a budget_clock object corresponding to the start of this type of path. Will be
undefined if the path is not clocked.
capture_clock
Returns a budget_clock object corresponding to the end of this type of path. Will be
exception_type
Returns a short string corresponding to an exception applying to this path. For example, a
"multicycle 2" path will have exception type "mcp2". Will be an empty string if there is no
exception.
exception
Returns a long string corresponding to an excpetion applying to this path. The string will
have SDC format. For example "set_multicycle_path 2". Will be an empty string if there is no
exception.
level_sensitive_capture
Will return the string "true" if the path ends in a level sensitive latch and "false" otherwise.
total_path_delay
Returns a float which is the total delay of the path based on the launch clock, the capture
clock, and the exception.
budget_path_delay
Returns a float which is the portion of the total path delay used for budgeting. Margins and
clock unceratinty are removed. clock, the capture clock, and the exception.
launch_uncertainty
Returns a float which represents the clock uncertainty applied to the the budgeted portion of
the path at the launching end.
capture_uncertainty
the path at the capturing end.
Chapter 1:
budget_attributes
17
1-17
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
Attributes of budget pin object

Budget_segment objects are returned by the -budget_pin and -all_budget_pins options of
the get_budgets command. You can use the get_attribute command to query the following
attributes of this object:
object_class
Returns the string "budget_pin".
full_name
Returns the string "pin%d"
name
Same as full_name
pin_id
Returns an integer which is a unique identifier for this object. You can use this identifier to
check that two objects refer to the same data. This identifier is also used as an anchor in the
output of "report_budget -html".
pin
Returns the pin object that this data refers to.
direction
Returns a string which is "input" for input pins and "output" for output pins. This attribute will
return the appropriate direction of the associated path for inout pins.
internal_frozen
Return the string "true" if the value of internal constraints have been frozen for this pin, and
"false" otherwise.
feedthrough_frozen
Return the string "true" if the value of feedthrough constraints have been frozen for this pin,
and "false" otherwise.
constraints
Return a collection of budget pin constraints that have been set for this pin. If no constraints
are set, then this attribute will not be defined.
pin_data
Return a collection of budget pin data objects for paths that pass through this pin. If no paths
pass through this pin, then this attribute will not be defined.
budget_attributes
18
Attributes of budget pin data object

object_class
Returns the string "budget_pin_data".
full_name
Returns the string "pd%d"
name
Same as full_name
pin_id
path_type_id
Returns an integer which is a unique identifier for the path type of this object. You can use
this identifier to check that two objects refer to the same data. This identifier is also used as
an anchor in the output of "report_budget -html".
pin
budget_pin
Returns the budget_pin object that this data refers to.
path_type
Returns the budget_path_type object that applies to the timing path for this data.
direction
constraint
Returns the budget_pin_constraint object used to derive the budget for this path. Will be
undefined in the pin is unconstrained.
is_feedthrough
Returns true if the pin_data is for a path that feeds through the pin's block.
launch_budget
Chapter 1:
budget_attributes
19
1-19
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
Returns a float which is the budgeted portion of the path on the launching side of this pin.
Will be undefined if there is no budget.
launch_delay
Returns an estimate of the longest actual delay of the portion of the path on the launching
side of this pin.
launch_slack
Returns a float which is launch_budget minus launch_delay. Will be undefined if there is no
budget.
capture_budget
Returns a float which is the budgeted portion of the path on the capturing side of this pin. Will
be undefined if there is no budget.
capture_delay
Returns an estimate of the longest actual delay of the portion of the path on the capturing
side of this pin.
capture_slack
Returns a float which is capture_budget minus capture_delay. Will be undefined if there is
no budget.
Attributes of budget pin constraint object

object_class
Returns the string "budget_pin_constraint".
full_name
Returns the string "cons%d"
name
Same as full_name
constraint_id
Returns an integer which is a unique identifier for this pin constraint. You can use this
identifier to check that two objects refer to the same data.
pin
Returns the pin object being constrainted.
budget_attributes
20
direction
constraint_type
Returns a string which is one of "internal_percent", "internal_delay", "from_percent",
"from_delay", "to_percent", "to_delay", or "none".
constraint_value
Returns a float value corresponding to the constraint type.
path_type
Return "feedthrough" for a constraint on a feedthrough path, "internal" for a constraint on an
path start or end, and "" if the constraint applies to both.
from_clock
Return the name of the clock object specified to the set_budget_pin_options command.
Return "" if none.
from_clock_edge
Return the string "rise", "fall" or "" depending on the options passed to the
set_budget_pin_options command.
to_clock
Return "" if none.
to_clock_edge
frozen
Return the string "true" if the value of the constraint has been frozen, and "false" otherwise.
Attributes of budget segment object

object_class
Returns the string "budget_segment".
full_name
Chapter 1:
budget_attributes
21
1-21
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
Returns the string "seg%d"

name
Same as full_name
from_pin_id
Returns an integer which is a unique identifier for the budget_pin_data object that fans into
this segment. You can use this identifier to check that two objects refer to the same data.
This identifier is also used as an anchor in the output of "report_budget. Will be undefined if
this segment does not have a budget pin at its input.
to_pin_id
Returns an integer which is a unique identifier for the budget_pin_data object that fans out
of this segment. You can use this identifier to check that two objects refer to the same data.
this segment does not have a budget pin at its output.
path_type_id
Returns an integer which is a unique identifier for the budget_path_type object that for the
path that this segment is part of. You can use this identifier to check that two objects refer to
the same data. This identifier is also used as an anchor in the output of "report_budget.
segment_id
Returns an integer which is a unique identifier for this budget_segment object. You can use
an anchor in the output of "report_budget.
path_type
Returns the budget_path_type object that for the path that this segment is part of.
from_block
Returns the name of the block where the segment starts. If the segment starts on a block
boundary, the block on the other side of the boundary will be returned. For the top level, ""
is returned.
through_block
Returns the name of the block where the segment passes through. For the top level, "" is
returned.
to_block
Returns the name of the block where the segment ends. If the segment ends on a block
is returned.
budget_attributes
22
from_pin
Return the pin object for the pin that is at the input of this segment. Will be undefined if this
segment does not have a budget pin at its input.
to_pin
Return the pin object for the pin that is at out the output of this segment. Will be undefined if
from_pin_data
Returns the budget_pin_data object that fans into this segment. Will be undefined if this
to_pin_data
Returns the budget_pin_data object that fans of of this segment. Will be undefined if this
segment does not have a budget pin at its output.
budget
Returns the delay that has been budgeted to this segment. Will be undefined if this segment
does not have a budget constraint.
delay
Returns an estimate of the longest actual delay for timing represented by this budget
segment.
fixed_delay
Returns the portion of delay that is "fixed". This includes delay through macros, clock skew
and ocv, and flop setup and hold times.
slack
Returns budget minus delay.
fixed_slack
Returns budget minus fixed_delay.
constraint
If a delay constraint has been set for this segment using the -busplans option of the
compute_budget_constraints command or by the set_segment_budget_constraints
command, the applied value is returned. Otherwise, the attribute is undefined.
rule_name
If a busplan rule has been used to constrain this segment, the name of that rule is returned.
Otherwise, the attribute is undefined.
Chapter 1:
budget_attributes
23
1-23
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_budgets(2)
budget_pin_attributes(3)
budget_pin_constraint_attributes(3)
budget_clock_attributes(3)
budget_pin_data_attributes(3)
budget_path_type_attributes(3)
budget_segment_attributes(3)
budget_attributes(3)
collections(3)
get_attribute(2)
report_attributes(2)
list_attributes(2)
report_budget(2)
set_budget_options(2)
set_pin_budget_constraints(2)
compute_budget_constraints(2)
write_budgets(2)
budget_attributes
24
budget_clock_attributes
Attributes of budget clock object

The budget_clock object is returned by the -clock option of the get_budgets command.
They can also be accessed as an attribute of budget_path_type objects. You can use the
get_attribute command to query the following attributes of this object:
object_class
Returns the string "budget_clock"
full_name
Returns the name of the clock as seen in the output of the report_budget command.
name
Same as full_name
source
Pin or port where budget clock is defined. If this is a portion of a clock tree that crosses into
a budgeted block, then the source is the hierarchical pin on the block where the clock
entered. Will be undefined for top-level virtual clocks.
block
Budget block (a cell) when the clock is defined. Will be undefined for top-level clocks.
clock
Object corresponding to the clock defined by your SDC.
SEE ALSO
get_budgets
budget_attributes
collections
get_attribute
report_attributes
report_budget
set_budget_options
set_pin_budget_constraints
compute_budget_constraints
write_budgets
Chapter 1:
25
1-25
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
26
budget_path_type_attributes
Attributes of budget path type object

Budget_path_type objects are returned by the -path_types option of get_budgets. They can
also be accessed as attributes of budget_pin_data and budget_segment objects. You can
use the get_attribute command to query the following attributes of this object:
object_class
Returns the string "budget_path_type"
full_name
Returns the name of the path_type as seen in the output of the report_budget command.
name
Same as full_name
path_type_id
Returns an integer which is a unique identifier for this path type. You can use this identifier
to check that two objects refer to the same data. This identifier is also used as an anchor in
the output of "report_budget -html".
launch_clock
Returns a budget_clock object corresponding to the start of this type of path. Will be
capture_clock
Returns a budget_clock object corresponding to the end of this type of path. Will be
exception_type
Returns a short string corresponding to an exception applying to this path. For example, a
"multicycle 2" path will have exception type "mcp2". Will be an empty string if there is no
exception.
exception
Returns a long string corresponding to an excpetion applying to this path. The string will
have SDC format. For example "set_multicycle_path 2". Will be an empty string if there is no
exception.
Chapter 1:
27
1-27
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
level_sensitive_capture
Will return the string "true" if the path ends in a level sensitive latch and "false" otherwise.
total_path_delay
Returns a float which is the total delay of the path based on the launch clock, the capture
clock, and the exception.
budget_path_delay
Returns a float which is the portion of the total path delay used for budgeting. Margins and
clock unceratinty are removed. clock, the capture clock, and the exception.
launch_uncertainty
the path at the launching end.
capture_uncertainty
the path at the capturing end.
SEE ALSO
get_budgets
budget_attributes
collections
get_attribute
report_attributes
report_budget
set_budget_options
write_budgets
28
budget_pin_attributes
Attributes of budget pin object

Budget_pin objects are returned by the -budget_pin and -all_budget_pins options of the
get_budgets command. You can use the get_attribute command to query the following
object_class
Returns the string "budget_pin".
full_name
Returns the string "pin%d"
name
Same as full_name
pin_id
pin
direction
internal_frozen
Return the string "true" if the value of internal constraints have been frozen for this pin, and
"false" otherwise.
feedthrough_frozen
Return the string "true" if the value of feedthrough constraints have been frozen for this pin,
and "false" otherwise.
constraints
Chapter 1:
29
1-29
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
Return a collection of budget pin constraints that have been set for this pin. If no constraints
are set, then this attribute will not be defined.
pin_data
Return a collection of budget pin data objects for paths that pass through this pin. If no paths
pass through this pin, then this attribute will not be defined.
SEE ALSO
get_budgets
budget_attributes
collections
get_attribute
report_attributes
report_budget
set_budget_options
write_budgets
30
budget_pin_constraint_attributes
Attributes of budget pin constraint object

Budget_pin_constraint objects are returned by the -pin_constraints or -all_pin_constraints
options of the get_budgets command. You can use the get_attribute command to query the
following attributes of this object:
object_class
Returns the string "budget_pin_constraint".
full_name
Returns the string "cons%d"
name
Same as full_name
constraint_id
Returns an integer which is a unique identifier for this pin constraint. You can use this
identifier to check that two objects refer to the same data.
pin
Returns the pin object being constrainted.
direction
constraint_type
Returns a string which is one of "internal_percent", "internal_delay", "from_percent",
"from_delay", "to_percent", "to_delay", or "none".
constraint_value
Returns a float value corresponding to the constraint type.
path_type
Return "feedthrough" for a constraint on a feedthrough path, "internal" for a constraint on an
path start or end, and "" if the constraint applies to both.
Chapter 1:
31
1-31
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
from_clock
Return "" if none.
from_clock_edge
to_clock
Return "" if none.
to_clock_edge
frozen
Return the string "true" if the value of the constraint has been frozen, and "false" otherwise.
SEE ALSO
get_budgets
budget_attributes
collections
get_attribute
report_attributes
report_budget
set_budget_options
write_budgets
32
budget_pin_data_attributes
Attributes of budget pin data object

Budget_pin_data objects are returned by the -pin_data and -all_pin_data options of the
get_budgets command. You can use the get_attribute command to query the following
object_class
Returns the string "budget_pin_data".
full_name
Returns the string "budget_pin_data"
name
Same as full_name
pin_id
path_type_id
Returns an integer which is a unique identifier for the path type of this object. You can use
an anchor in the output of "report_budget -html".
pin
budget_pin
Returns the budget_pin object that this data refers to.
path_type
Returns the budget_path_type object that applies to the timing path for this data.
direction
Chapter 1:
33
1-33
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
constraint
Returns the budget_pin_constraint object used to derive the budget for this path. Will be
undefined in the pin is unconstrained.
is_feedthrough
Returns true if the pin_data is for a path that feeds through the pin's block.
launch_budget
Returns a float which is the budgeted portion of the path on the launching side of this pin.
Will be undefined if there is no budget.
launch_delay
Returns an estimate of the longest actual delay of the portion of the path on the launching
side of this pin.
launch_slack
Returns a float which is launch_budget minus launch_delay. Will be undefined if there is no
budget.
capture_budget
Returns a float which is the budgeted portion of the path on the capturing side of this pin. Will
be undefined if there is no budget.
capture_delay
Returns an estimate of the longest actual delay of the portion of the path on the capturing
side of this pin.
capture_slack
Returns a float which is capture_budget minus capture_delay. Will be undefined if there is
no budget.
SEE ALSO
get_budgets
budget_attributes
collections
get_attribute
report_attributes
report_budget
set_budget_options
write_budgets
34
Chapter 1:
35
1-35
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
budget_segment_attributes
Attributes of budget segment object

Budget_segment objects are returned by the -all_segments, -fanin_segments and
-fanout_segments option of the get_budgets command. You can use the get_attribute
command to query the following attributes of this object:
object_class
Returns the string "budget_segment".
full_name
Returns the string "seg%d"
name
Same as full_name
from_pin_id
Returns an integer which is a unique identifier for the budget_pin_data object that fans into
this segment. You can use this identifier to check that two objects refer to the same data.
this segment does not have a budget pin at its input.
to_pin_id
Returns an integer which is a unique identifier for the budget_pin_data object that fans out
of this segment. You can use this identifier to check that two objects refer to the same data.
path_type_id
Returns an integer which is a unique identifier for the budget_path_type object that for the
path that this segment is part of. You can use this identifier to check that two objects refer to
the same data. This identifier is also used as an anchor in the output of "report_budget.
segment_id
Returns an integer which is a unique identifier for this budget_segment object. You can use
an anchor in the output of "report_budget.
path_type
36
Returns the budget_path_type object that for the path that this segment is part of.
from_block
Returns the name of the block where the segment starts. If the segment starts on a block
is returned.
through_block
Returns the name of the block where the segment passes through. For the top level, "" is
returned.
to_block
Returns the name of the block where the segment ends. If the segment ends on a block
is returned.
from_pin
Return the pin object for the pin that is at the input of this segment. Will be undefined if this
to_pin
Return the pin object for the pin that is at out the output of this segment. Will be undefined if
from_pin_data
Returns the budget_pin_data object that fans into this segment. Will be undefined if this
to_pin_data
Returns the budget_pin_data object that fans of of this segment. Will be undefined if this
segment does not have a budget pin at its output.
budget
Returns the delay that has been budgeted to this segment. Will be undefined if this segment
does not have a budget constraint.
delay
Returns an estimate of the longest actual delay for timing represented by this budget
segment.
fixed_delay
Chapter 1:
37
1-37
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
Returns the portion of delay that is "fixed". This includes delay through macros, clock skew
and ocv, and flop setup and hold times.
slack
Returns budget minus delay.
fixed_slack
Returns budget minus fixed_delay.
constraint
If a delay constraint has been set for this segment using the -busplans option of the
compute_budget_constraints command or by the set_segment_budget_constraints
command, the applied value is returned. Otherwise, the attribute is undefined.
rule_name
If a busplan rule has been used to constrain this segment, the name of that rule is returned.
Otherwise, the attribute is undefined.
SEE ALSO
get_budgets(2)
budget_attributes(3)
collections(3)
get_attribute(2)
report_budget(2)
set_budget_options(2)
set_pin_budget_constraints(2)
write_budgets(2)
38
bundle_attributes
Description of the predefined attributes for bundles.
DESCRIPTION
bundle attributes are provided in the subsections that follow.
command.
Bundle Attributes
bundle_type
A string attribute representing the type of objects associated with this bundle.
expanded_objects
A collection attribute representing all the objects associated with this bundle but flattened
out.
name
A string attribute for the name of the bundle.
object_class
A string attribute with the value of "bundle".
object_count
An integer attribute representing number of objects associated with this bundle.
Chapter 1:
bundle_attributes
39
1-39
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
objects
A collection attribute representing all the objects associated with this bundle.
SEE ALSO
create_bundle(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
bundle_attributes
40
ccd.ignore_ports_for_boundary_identification
When ccd.optimize_boundary_timing is set to false, this option can be used to exclude IO
ports for boundary identification.
TYPE
string
DEFAULT
empty string
DESCRIPTION
When ccd.optimize_boundary_timing is set to false, this option can be used to exclude IO
ports for boundary identification. It often includes ports like reset and scan.
SEE ALSO
ccd.optimize_boundary_timing(3)
set_app_options(2)
Chapter 1:
ccd.ignore_ports_for_boundary_identification
41
1-41
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
ccd.optimize_boundary_timing
Specify if concurrent clock and data (CCD) optimizes on boundary timing path.
TYPE
boolean
DEFAULT
true
DESCRIPTION
This option specifies if CCD will perform optimization on boundary timing path. By default, it
is true. It is often used to set it to false to disable optimization on IO paths. Latencies of the
boundary registers will not be adjusted for improving register to register timing as well with
this app option set is set to false.
SEE ALSO
ccd.ignore_ports_for_boundary_identification(3)
set_app_options(2)
ccd.optimize_boundary_timing
42
ccd.skip_path_groups
Skip the path groups for concurrent clock and data (CCD) optimization.
TYPE
string
DEFAULT
empty string
DESCRIPTION
This option provides a list of path groups and CCD will skip these path groups during critical
endpoint selection for optimization. This app option does not skip optimization on data path
on the specified path groups. This app option affects post-CTS concurrent clock and data
optimization (for example in clock_opt and route_opt).
SEE ALSO
set_app_options(2)
Chapter 1:
ccd.skip_path_groups
43
1-43
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cell_attributes
Description of the predefined attributes for cells.
DESCRIPTION
Attributes are properties assigned to objects such as pins, cells and nets. Definitions for cell
attributes are provided in the subsections that follow.
command.
Cell Attributes
area
A float attribute for the area of a cell.
base_name
A string attribute for the name of a cell. This name does not include the instance path prefix.
bounds
A collection attribute representing the group and move bounds to which the cell belongs.
clock_path_target_library_subset
cell to constrain the clock paths. This attribute contains only the libraries which were
explicitly specified in the target library subset assigned to this cell. It does not contain
libraries which are inferred from the reference library list or inherited from target library
subsets assigned to higher levels of hierarchy.
cell_attributes
44
clock_path_target_lib_cell_subset
assigned to this cell to constrain the clock paths. This attribute contains only the library cells
which were specified in the target library subset assigned to this cell. It does not contain
library cells which are inherited from target library subsets assigned to higher levels of
hierarchy.
clock_path_target_lib_cell_exclusions
assigned to this cell to constrain the clock paths. This attribute contains only the library cell
exclusions which were specified in the target library subset assigned to this cell. It does not
contain library cell exclusions which are inherited from target library subsets assigned to
higher levels of hierarchy.
data_path_target_library_subset
cell to constrain the data paths. This attribute contains only the libraries which were explicitly
specified in the target library subset assigned to this cell. It does not contain libraries which
are inferred from the reference library list or inherited from target library subsets assigned to
data_path_target_lib_cell_subset
assigned to this cell to constrain the data paths. This attribute contains only the library cells
which were specified in the target library subset assigned to this cell. It does not contain
library cells which are inherited from target library subsets assigned to higher levels of
hierarchy.
data_path_target_lib_cell_exclusions
assigned to this cell to constrain the data paths. This attribute contains only the library cell
exclusions which were specified in the target library subset assigned to this cell. It does not
contain library cell exclusions which are inherited from target library subsets assigned to
full_name
A string attribute for the name of a cell. This name includes a prefix for the instance path to
this cell.
Chapter 1:
cell_attributes
45
1-45
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
hold_uncertainty
A float attribute representing the user-specified clock uncertainty for hold. This attribute will
exist only if set_clock_uncertainty was specified on this object.
io_guide
A collection attribute representing the IO guide the cell is associated with.
is_black_box
A Boolean attribute. The value will be "true" if this cell is unresolved or if it refers to a lib_cell
with no logic function.
is_combinational
A Boolean attribute that is true if the cell is not sequential.
is_fall_edge_triggered
A Boolean attribute that is true if the cell has timing behavior relative to the falling edge of a
clock signal.
is_fs_eco_add
A Boolean attribute. The value will be "true" if this cell has been created in freeze_silicon
mode, "false" otherwise.
is_hierarchical
A Boolean attribute. The value will be "true" if this cell is hierarchical, "false" otherwise.
is_integrated_clock_gating_cell
A Boolean attribute that is true if the cell refers to a lib_cell that is defined in the library as an
integrated clock gating cell.
is_memory_cell
A Boolean attribute that is true if the cell refers to a lib_cell that is defined in the library as a
memory cell.
cell_attributes
46
is_isolation
A Boolean attribute that is true if the cell is a isolation cell.
is_level_shifter
A Boolean attribute that is true if the cell is a level shifter cell.
is_enable_level_shifter
A Boolean attribute that is true if the cell is a enable level shifter cell.
is_retention
A Boolean attribute that is true if the cell is a retention cell.
is_power_switch
A Boolean attribute that is true if the cell is a power switch cell.
is_mux
A Boolean attribute that is true i the cell is a mux.
is_negative_level_sensitive
A Boolean attribute that is true if the cell has negative level-sensitive timing behavior, as in
a negative D-latch.
is_pad_cell
A Boolean attribute that is true if the cell refers to a lib_cell that is defined in the library as a
pad cell.
is_positive_level_sensitive
A Boolean attribute that is true if the cell has positive level-sensitive timing behavior, as in a
positive D-latch.
is_rise_edge_triggered
A Boolean attribute that is true if the cell has timing behavior relative to the rising edge of a
clock signal.
Chapter 1:
cell_attributes
47
1-47
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
is_sequential
A Boolean attribute that is true if the cell has sequential logic function.
is_three_state
A Boolean attribute that is true if the cell has one or more three_state outputs.
mask_shift
A list of layer mask shifts, formatted { { layer_name shift } ... }, in which layer_name is the
layer and shift indicates the amount to shift the mask. Valid shift values are 0 and 1.
number_of_pins
An integer attribute representing the number of pins on this cell.
object_class
A string attribute with the value of "cell". Each object class has a different object class value.
The possible object classes are: block, cell, pin, port, net, lib, lib_cell, lib_pin, clock, mode,
corner, input_delay, output_delay, timing_exception, timing_arc, lib_timing_arc,
timing_path, clock_timing_path, timing_point.
pad_offset
A coord attribute used to specify the offset location for the IO Pad Cell which is not already
associated with any IO Guide. This is a settable attribute.
parent_block
A collection attribute with the owner block object for this cell.
parent_block_cell
A collection attribute with the parent block cell object for this cell.
parent_cell
A collection attribute representing the owning instance the cell belongs to. For a cell at top
level this attribute will not exist.
cell_attributes
48
is_fs_eco_add
A Boolean attribute that is true if the cell was a programmable spare cell (psc) filler and is
used now.
physical_status
A string attribute representing the physical placement status of the cell. Valid values are
unplaced, placed, legalize_only, application_fixed, fixed, and locked. If status is unplaced,
the cell has not been placed. If status is placed, the cell has been placed and may be moved.
If status is legalize_only, the cell may be moved for legalization only. If status is
application_fixed, the cell is fixed by the application for automatic changes (the application
may change this status). If status is fixed, the cell is fixed by the user for automatic changes.
If status is locked, the cell is fixed for automatic and manual changes. This is a settable
attribute.
power_domain
A string attribute. The value is the power domain name of the given cell instance.
ref_module_name
A string attribute. The value is the name of the module, or the name of the top module of the
block or lib_cell to which this cell instance refers.
ref_name
A string attribute. The value is the base name of the block or lib_cell to which this cell
instance refers.
ref_label_name
A string attribute. The value is the label name of the block or lib_cell to which this cell
instance refers.
ref_view_name
A string attribute. The value is the view name of the block or lib_cell to which this cell
instance refers.
ref_full_name
A string attribute. The value is the full_name of the block or lib_cell to which this cell instance
refers. It consists of the reference lib_name and block_name, separated by a ':' character,
Chapter 1:
cell_attributes
49
1-49
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
and an optional layer_name, separated by a '/' character, and a view name, separated by a
'.' character. For example, "bot_lib:bot/my_label.design".
ref_block
A collection attribute returning the block referenced by the cell.
ref_phys_block
A collection attribute returning the block referenced by the cell. Same as ref_block, except
for lib_cells where ref_block typically returns the timing view and ref_phys_block typically
returns the frame view if both views are present for the lib_cell.
retention_cell_style
A String attribute which returns the retention-cell-type of lib_cell to which this cell instance
refers.
rp_column
An integer attribute that specifies the column position of the cell in rp_group.
rp_num_columns
An integer attribute that specifies the number of columns occupied by the cell in rp_group.
rp_num_rows
An integer attribute that specifies the number of rows occupied by the cell in rp_group.
rp_orientations
A string attribute for the user given orientations for cell of rp_group.
rp_parent_group
A string attribute that specifies the parent rp_group name of the cell.
rp_pin_name
A string attribute for the name of pin on which cell will be aligned in a rp_group column.
cell_attributes
50
rp_override_alignment
A string attribute that specifies the alignment to be used to override the alignment of the
relative placement cell in the column of its parent rp_group.
rp_row
An integer attribute that specifies the row position of the cell in rp_group.
rp_top_group
A string attribute that specifies the top rp_group name of cell.
setup_uncertainty
A float attribute representing the user-specified clock uncertainty for setup. This attribute will
supernet_disabled
A Boolean attribute representing the supernet disabled status for this cell instance. For a
non-repeater cell this is always false and for repeater it is true if the repeater has been
explicitly disable for supernet transparency using the set_supernet_exceptions
-disabled_cell command.
supernet_transparent
A Boolean attribute representing the supernet transparent status for this cell instance.
supernet_transparent_pins
A collection attribute representing the supernet transparent pins for this cell instance.
top_block
A collection attribute with the top block object for this cell.
view_name
A string attribute. The value is the view name selected by change_view for this cell
reference. A cell with the default view name of "" uses the view switch list to select the
reference block view.
Chapter 1:
cell_attributes
51
1-51
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
voltage_area
A collection attribute with a single voltage_area object for this cell object.
voltage_area_shape
A collection attribute with a single voltage_area_shape object for this cell object.
SEE ALSO
get_attribute(2)
list_attributes(2)
set_clock_uncertainty(2)
cell_attributes
52
clock_attributes
Description of the predefined attributes for clocks.
DESCRIPTION
clock attributes are provided in the subsections that follow.
command.
Clock Attributes
clock_latency_fall_max
A float attribute representing the user-specified clock network latency for max fall. The value
defaults to 0.0.
clock_latency_fall_min
A float attribute representing the user-specified clock network latency for min fall. The value
defaults to 0.0.
clock_latency_rise_max
A float attribute representing the user-specified clock network latency for max rise. The
value defaults to 0.0.
clock_latency_rise_min
A float attribute representing the user-specified clock network latency for min rise. The value
defaults to 0.0.
clock_network_pins
An collection attribute. The value is a collection of pins in the network of this clock.
Chapter 1:
clock_attributes
53
1-53
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
clock_source_latency_early_fall_max
A float attribute representing the user-specified clock network latency for early max fall.
clock_source_latency_early_fall_min
A float attribute representing the user-specified clock network latency for early min fall.
clock_source_latency_early_rise_max
A float attribute representing the user-specified clock network latency for early max rise.
clock_source_latency_early_rise_min
A float attribute representing the user-specified clock network latency for early min rise.
clock_source_latency_late_fall_max
A float attribute representing the user-specified clock network latency for late max fall.
clock_source_latency_late_fall_min
A float attribute representing the user-specified clock network latency for late min fall.
clock_source_latency_late_rise_max
A float attribute representing the user-specified clock network latency for late max rise.
clock_source_latency_late_rise_min
A float attribute representing the user-specified clock network latency for late min rise.
clock_source_latency_pins
An collection attribute. The value is a collection of pins in the source latency network of this
clock.
command_text
A string attribute. The value is the equivalent command(s) that can re-create the object.
clock_attributes
54
file_line_info
A string attribute. If it exists, the value contains one or more Tcl or SDC source file name and
line number pairs of the commands which were used to create this object.
full_name
A string attribute for the name of a clock.
hold_uncertainty
A float attribute representing the user-specified clock uncertainty for hold.
is_active
A Boolean attribute. The value will be "true" if this clock is active, "false" if the clock was
excluded by set_active_clocks.
is_generated
A Boolean attribute. The value will be "true" if this clock is a generated clock, "false"
otherwise.
master_clock
An collection attribute. If it exists, the value is a collection containing the master clock for this
generated clock.
period
A float attribute representing the period of the clock.
propagated_clock
A Boolean attribute. The value will be "true" if this clock has propagated clock latency, "false"
if it has ideal latency.
object_class
A string attribute with the value of "clock". Each object class has a different object class
value. The possible object classes are: design, cell, pin, port, net, lib, lib_cell, lib_pin, clock,
mode, corner, input_delay, output_delay, timing_exception, timing_arc, lib_timing_arc,
Chapter 1:
clock_attributes
55
1-55
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
setup_uncertainty
A float attribute representing the user-specified clock uncertainty for setup.
sources
An collection attribute. The value is a collection of source objects for the clock.
waveform
A string attribute. The value represents the clock waveform as a list of edges.
SEE ALSO
get_attribute(2)
list_attributes(2)
set_active_clocks(2)
clock_attributes
56
clock_balance_group_attributes
Description of the predefined attributes for clock_balance_group.
DESCRIPTION
clock_balance_group attributes are provided in the subsections that follow.
command.
clock_balance_group Attributes
name
A string attribute for the name of an clock_balance_group.
object_class
A string attribute with the value of "clock_balance_group". Each object class has a different
object class value.
SEE ALSO
create_clock_balance_group(2)
get_attribute(2)
list_attributes(2)
Chapter 1:
clock_balance_group_attributes
57
1-57
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
clock_group_attributes
Lists the predefined attributes for clock_group objects.
DESCRIPTION
Attributes are properties assigned to objects. Definitions for clock_group attributes are
provided in the subsections that follow.
Attributes are informational, or "read-only." You cannot set the value of attributes designed
by the application.
Clock Group Attributes
clock_group_type
A string attribute indicating the type of exception. Valid values are "logically exclusive",
"asynchronous", and "physically exclusive".
file_line_info
A string attribute. If it exists, the value contains the Tcl or SDC source file name and line
number pair of the command which was used to create this object.
full_name
A string attribute returning a unique name for the clock_group. This is the user given name
or a tool generated one if user doesnt specify any.
group_count
An int attribute giving the number of individual groups given in the set_clock_group
command.
is_allow_path
A bool attribute which is true if the -allow_paths option is used in the set_clock_group
command for an asynchronous clock group setting.
58
object_class
A string attribute, with the value "clock_group".
SEE ALSO
get_clock_groups(2)
get_attribute(2)
list_attributes(2)
report_clocks(2)
set_clock_groups(2)
Chapter 1:
59
1-59
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
clock_group_group_attributes
Lists the predefined attributes for clock_group_group objects.
DESCRIPTION
Attributes are properties assigned to objects. Definitions for clock_group_group attributes
are provided in the subsections that follow.
by the application.
Clock Group Group Attributes
object_class
A string attribute, with the value "clock_group_group".
objects
A collection attribute. The value is a collection of clocks contained in this group of the
clock_group.
SEE ALSO
get_clock_groups(2)
get_clock_group_groups(2)
get_attribute(2)
list_attributes(2)
report_clocks(2)
set_clock_groups(2)
clock_group_group_attributes
60
clock_opt.congestion.effort
TYPE
string
DEFAULT
medium
DESCRIPTION
Specifies the effort level for the congestion alleviation in clock_opt. Allowed values are
none, medium, or high. Expect a significant increase in runtime for high effort. If set to none,
clock_opt will not run in a congestion mode.
SEE ALSO
clock_opt(2)
create_placement(2)
place_opt.congestion.effort(3)
refine_opt.congestion.effort(3)
place.coarse.congestion_analysis_effort(3)
Chapter 1:
clock_opt.congestion.effort
61
1-61
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
clock_opt.flow.enable_ccd
Enable concurrent clock and data optimization (CCD) during clock_opt.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this option is set to true, concurrent clock and data optimization (CCD) will be enabled
during clock_opt. By default, it is set to false.
SEE ALSO
set_app_options(2)
clock_opt(2)
clock_opt.flow.enable_ccd
62
clock_opt.flow.enable_ccd_route_clock
Enable clock routing in the clock_opt flow when clock_opt concurrent clock and data
optimization (CCD) is enabled. To enable CCD, please use the app option
clock_opt.flow.enable_ccd.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this option is set to true, and when the app option clock_opt.flow.enable_ccd is also
set to true, clock routing step will be performed during clock_opt. By default, it is set to
false. When only the app option clock_opt.flow.enable_ccd is set to true, clock_opt will
skip the clock routing step.
SEE ALSO
set_app_options(2)
clock_opt(2)
clock_opt.flow.enable_ccd(3)
clock_opt.flow.enable_ccd_route_clock_eco(3)
Chapter 1:
clock_opt.flow.enable_ccd_route_clock
63
1-63
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
clock_opt.flow.enable_ccd_route_clock_eco
Enable incremental clock routing during concurrent clock and data optimization (CCD) in the
clock_opt flow when CCD is enabled. To enable CCD, please use the app option
clock_opt.flow.enable_ccd.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this option is set to true, and when the app option clock_opt.flow.enable_ccd is also
set to true, incremental clock routing will be performed during clock_opt. By default, it is set
to false. To ensure consistent detailed routing for clock in CCD enabled clock_opt, please
set this option as well as clock_opt.flow.enable_ccd and
clock_opt.flow.enable_ccd_route_clock to true.
SEE ALSO
set_app_options(2)
clock_opt(2)
clock_opt.flow.enable_ccd(3)
clock_opt.flow.enable_ccd_route_clock(3)
clock_opt.flow.enable_ccd_route_clock_eco
64
clock_opt.flow.optimize_layers
Enable layer optimization in clock_opt
TYPE
String
DEFAULT
auto
DESCRIPTION
It has three modes: {auto, true, false}. In auto mode, layer optimization will be automatically
activated if the design has fast metal layers. When layer optimization is activated, the
clock_opt flow assigns long timing critical nets to upper metal layers to improve timing.
SEE ALSO
set_app_options(2)
Chapter 1:
clock_opt.flow.optimize_layers
65
1-65
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
clock_opt.flow.optimize_layers_critical_range
Set critical range for layer optimization when clock_opt.flow.optimize_layers is set to true.
TYPE
Float
DEFAULT
0.9
DESCRIPTION
It accepts values from {0 ~ 1.0}. For a given value y, it optimizes nets that have slacks
between {y*WNS, WNS}, where WNS is the worst negative slack. Set it to a lower value to
fix paths that are in less critical range. It may cause a lot more nets to be promoted and use
much more routing resource. So, lower the critical range only if necessary.
SEE ALSO
set_app_options(2)
clock_opt.flow.optimize_layers(3)
clock_opt.flow.optimize_layers_critical_range
66
clock_opt.flow.optimize_ndr
Enable NDR optimization in clock_opt
TYPE
Boolean
DEFAULT
false
DESCRIPTION
clock_opt flows will run automatic non-default-routing rule optimization that assigns long
timing critical nets to NDR to improve timing.
SEE ALSO
set_app_options(2)
Chapter 1:
clock_opt.flow.optimize_ndr
67
1-67
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
clock_opt.flow.pre_place_drc_fix
TYPE
Boolean
DEFAULT
true
DESCRIPTION
If set to true, clock_opt will run a drc fixing step before it enters post-CTS timing and
congestion driven placement stage. This pre-placement step will clean up the drc violations
potentially caused by clock tree synthesis, giving a better input netlist for placement and
subsequent optimizations.
SEE ALSO
clock_opt(2)
clock_opt.place.legalize(3)
clock_opt.flow.pre_place_drc_fix
68
clock_opt.flow.skip_placement
Run the clock_opt flow without redoing the netlist placement.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
clock_opt will run and omit the initial timing-driven placement of the clocked netlist.
SEE ALSO
set_app_options(2)
Chapter 1:
clock_opt.flow.skip_placement
69
1-69
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
clock_opt.hold.effort
Control the optimization effort for hold fixing.
TYPE
String
DEFAULT
medium
DESCRIPTION
Enable higher effort hold fixing in clock_opt flows.
The hold fixing effort can be: none, low, medium, or high. Setting to none disables hold
fixing.
The high effort option may result in slight degradation in setup TNS.
SEE ALSO
clock_opt(2)
set_app_options(2)
clock_opt.hold.effort
70
clock_opt.place.effort
TYPE
string
DEFAULT
medium
DESCRIPTION
Specifies the CPU effort level for coarse placements invoked in clock_opt. Allowed values
are medium or high.
SEE ALSO
clock_opt(2)
create_placement(2)
place_opt.initial_place.effort(3)
place_opt.final_place.effort(3)
refine_opt.place.effort(3)
Chapter 1:
clock_opt.place.effort
71
1-71
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
clock_opt.place.legalize
TYPE
Boolean
DEFAULT
true
DESCRIPTION
If set to true, the placement stage in clock_opt will include cell legalizations immediately
after the timing driven placement.
SEE ALSO
clock_opt(2)
place_opt.final_place.legalize(3)
refine_opt.place.legalize(3)
clock_opt.place.legalize
72
clock_path_attributes
Description of the predefined attributes for clock_paths.
DESCRIPTION
clock_path attributes are provided in the subsections that follow.
command.
All clock_path attributes are read-only.
All time-valued attributes will be based on the user output units in effect when the attribute
value is gotten, not when the clock path was originally created.
The object-valued attributes (such as clock, mode, corner, etc.) are not guaranteed to have
valid values if the design has been modified since the clock_path was created. However, the
corresponding "name" attributes (for example, clock_name) will always be valid, even if the
object itself no longer exists.
Clock_path Attributes
clock
A collection attribute representing the clock_path's clock.
clock_name
A string attribute representing the name of the clock_path's launch clock.
clock_edge_type
A string attribute representing the clock_path's relevant edge, as measured at the clock
source. The value will be either "rise" or "fall".
Chapter 1:
73
1-73
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
clock_edge_value
A float attribute representing the time of the clock_path's relevant clock edge, measured at
the clock source.
corner
A collection attribute representing the clock_path's corner.
corner_name
A string attribute representing the name of clock_path's corner.
design_name
A string attribute representing the name of the clock_path's design.
driving_cell_adjustment
A float attribute representing the clock_path's driving_cell adjustment time, for paths starting
at input ports.
endpoint
A collection attribute representing the clock_path's endpoint.
endpoint_name
A string attribute representing the name of the clock_path's endpoint.
full_name
A string attribute representing the clock_path's name, which is synthesized from some of its
other attributes. The name is not guaranteed to be unique.
lib_name
A string attribute representing the name if the library containig the clock_path's design.
mode
A collection attribute representing the clock_path's mode
74
mode_name
A string attribute representing the name of clock_path's mode.
name
A string attribute representing the clock_path's name, which is synthesized from some of its
object_class
A string attribute with the value "clock_path".
path_type
A string attribute representing the clock_path's delay type, either "min" or "max".
points
A collection attribute representing the clock_path's points.
propagation_type
Equivalent to the path_type attribute, with a value of "min" or "max".
scenario
A collection attribute representing the clock_path's scenario.
scenario_name
A string attribute representing the name of the clock_path's scenario.
source_clock
A float attribute representing the clock's source clock, if the clock is generated.
source_clock_arrival_open_edge_type
A string attribute representing the clock_path's launch clock edge, as measured at the clock
source. The value will be either "rise" or "fall".
Chapter 1:
75
1-75
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
source_clock_name
A string attribute representing the name of the clock's source clock, if the clock is generated.
source_clock_edge_type
A string attribute representing the clock_path's applicable clock edge, as measured at the
clock source. The value will be either "rise" or "fall".
source_clock_edge_value
A float attribute representing the time of the applicable clock edge, measured at the clock
source.
source_latency
A float attribute representing the clock_path's source latency.
startpoint
A collection attribute representing the clock_path's startpoint.
startpoint_name
A string attribute representing the name of the clock_path's startpoint.
SEE ALSO
get_attribute(2)
list_attributes(2)
get_timing_paths(2)
report_timing(2)
set_user_units(2)
report_user_units(2)
76
constraint_group_attributes
Description of the predefined attributes for constraint_groups.
DESCRIPTION
constraint_group attributes are provided in the subsections that follow.
command.
Constraint Group Attributes
attraction_type
A string attribute applicable only for river style of bus routing type of analog constraints
defining the attraction force. This is for river style bus routing constraint group and is a
settable attribute.
corner_type
A string attribute applicable only for bus style of bus routing type of analog constraints
defining the corner type. This is for bus style bus routing constraint group and is a settable
attribute.
default_gap
A distance attribute applicable for differential group/pair, net shielding and bus routing type
of analog constraints defining the gap between outermost shape of the group with other
shapes in the design. This is for differential, shielding and both bus routing constraint groups
and is a settable attribute.
default_width
A distance attribute applicable only for net shielding type of analog constraints defining the
width of shield material. This is for shielding constraint group and is a settable attribute.
Chapter 1:
77
1-77
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
disabled_layers
A collection attribute applicable only for net shielding type of analog constraints defining the
disallowed layers. This is for shielding constraint group and is a settable attribute.
enclose_pins
A string attribute applicable only for net shielding type of analog constraints defining if pins
are enclosed by the shield. This is for shielding constraint group and is a settable attribute.
enclose_vias
A string attribute applicable only for net shielding type of analog constraints defining if vias
are enclosed by the shield. This is for shielding constraint group and is a settable attribute.
is_relative
A boolean attribute applicable for wire matching, resistance limit and wire length limit type of
analog constraints specifying whether the tolerance value is in absolute (when false) or
percentage. This is for wire matching constraint group and is a settable attribute.
jog_length
A distance attribute applicable only for river style bus routing type of analog constraints
defining the minimum length of jogs. This is for river style bus routing constraint group and
is a settable attribute.
layer_gap
layer specific gap between route objects and shield. This is a subscripted attribute based on
layer names. This is for shielding constraint group and is a settable attribute.
layer_max_gap
layer specific max gap between route objects and shield. This is a subscripted attribute
based on layer names. This is for shielding constraint group and is a settable attribute.
layer_spacing
A distance attribute applicable for differential group/pair and bus routing type of analog
constraints defining the layer specific minimum spacing for trunk. This is a subscripted
78
attribute based on layer names. Only one layer name is applicable for river style bus routing
type. This is for differential and both bus routing constraint group and is a settable attribute.
layer_width
A distance attribute applicable for differential group/pair, net shielding and bus routing type
of analog constraints defining the layer specific minimum width for trunk. This is a
subscripted attribute based on layer names. Only one layer name is applicable for river style
bus routing type. This is for differential, shielding and both bus routing constraint group and
matching_style
A string attribute applicable for wire matching, resistance limit and wire length limit type of
analog constraints specifying the parameter used for matching the nets. This is for wire
matching, resistance limit and wire length limit constraint group and is a settable attribute for
wire matching.
max_gap
max gap between route objects and shield. This is for shielding constraint group and is a
settable attribute.
max_layer
A collection attribute applicable for differential group/pair and bus style bus routing type of
analog constraints defining the maximum metal layer out of the specified layers. This is for
differential and bus style bus routing constraint group.
min_layer
A collection attribute applicable for differential group/pair and bus style bus routing type of
analog constraints defining the minimum metal layer out of the specified layers. This is for
differential and bus style bus routing constraint group.
min_segment
minimum segment length to be shielded. This is for shielding constraint group and is a
settable attribute.
Chapter 1:
79
1-79
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
min_value
A float attribute applicable for resistance limit and wire length limit type of analog constraints
defining the minimum value to be achieved for each of the constituents of the constraint
group. This is for resistance limit and wire length limit constraint group and is a settable
attribute.
name
A string attribute for the name of the constraint group. This is a settable attribute.
object_class
A string attribute with the value of "constraint_group".
objects
A collection attribute for the members of the constraint group.
priority
An integer attribute applicable only for net priority type of analog constraints defining the
priority of its constituents. This is for net priority constraint group and is a settable attribute.
reference_net
A collection attribute applicable only for river style bus routing type of analog constraints that
dictates the topology of the bus routing. This is for river style bus routing constraint group
river_layer
A collection attribute applicable only for river style bus routing type of analog constraints
specifying the layer for river trunk. This is for river style bus routing constraint group and is
a settable attribute.
sharing
A string attribute applicable only for net shielding type of analog constraints specifying if a
shield can be shared between constituents of the group. This is for shielding constraint
group and is a settable attribute.
80
shield_net
A collection attribute applicable only for net shielding type of analog constraints specifying
the net to connect to shield material. This is for shielding constraint group and is a settable
attribute.
shield_net_2
A collection attribute applicable only for net shielding type of analog constraints specifying a
second net to connect to shield material. This is for shielding constraint group and is a
settable attribute.
shield_placement
A string attribute applicable for differential group/pair and bus routing type of analog
constraints defining how main bus trunk will be shielded when one or more constituent nets
of the group are shielded. This is for differential and both bus routing constraint group and is
shielding_style
A string attribute applicable only for net shielding type of analog constraints specifying a
collective set of shielding style, tandem layers, tandem offset and coaxial type. Below table
captures the set. This is for shielding constraint group and is a settable attribute.
name shield tandem tandem coaxial style layers offset type
------------------------------------------------------------------ parallel parallel N/A N/A N/A tandem
tandem both 1 N/A coaxial coaxial both 1 solid split_coaxial coaxial both 1 split
center_coaxial coaxial both 1 centerOnly below tandem below 1 N/A above tandem above
1 N/A offset_below tandem below 2 N/A pffset_above tandem above 2 N/A offset_tandem
tandem both 2 N/A offset_coaxial coaxial both 2 solid below_split_coaxial coaxial below 1
split above_split_coaxial coaxial above 1 split below_center_coaxial coaxial below 1
centerOnly above_center_coaxial coaxial above 1 centerOnly above_solid_coaxial coaxial
above 1 solid below_solid_coaxial coaxial below 1 solid offset_above_solid_coaxial coaxial
above 2 solid offset_below_solid_coaxial coaxial below 2 solid offset_split_coaxial coaxial
both 2 split offset_above_split_coaxial coaxial above 2 split offset_below_split_coaxial
coaxial below 2 split offset_center_coaxial coaxial both 2 centerOnly
offset_above_center_coaxial coaxial above 2 centerOnly offset_below_center_coaxial
coaxial below 2 centerOnly
tolerance
A float attribute applicable only for wire matching type of analog constraints defines the
tolerance, either as absolute or percentage (goverened by is_relative), of the specified
Chapter 1:
81
1-81
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
parameter across all constituents of the group. This is for wire matching constraint group
twist_interval
A distance attribute applicable only for differential group/pair type of analog constraints
defining the interval for twisting and is applicable only when twist style is not none. This is
for differential constraint group and is a settable attribute.
twist_offset
A distance attribute applicable only for differential group/pair type of analog constraints
defining the offset for twisting and is applicable only when twist style is not none. This is for
differential constraint group and is a settable attribute.
twist_style
A string attribute applicable only for differential group/pair type of analog constraints defining
how the nets in the group will be twisted. This is for differential constraint group and is a
settable attribute.
type
A string attribute for the type of the constraint group.
via_defs
A collection attribute applicable only for net shielding type of analog constraints specifying
the via definitions to be used. This is for shielding constraint group and is a settable attribute.
SEE ALSO
create_wire_matching(2)
create_resistance_limit(2)
create_length_limit(2)
create_differential_group(2)
create_net_shielding(2)
create_net_priority(2)
create_bus_routing_style(2)
create_river_routing_style(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
82
core_area_attributes
Description of the predefined attributes for core_areas.
DESCRIPTION
core_area attributes are provided in the subsections that follow.
command.
Core Area Attributes
area
An area attribute representing the area of the core area of a block.
bbox
A rectangle attribute for the bounding-box of a core_area. The format of a rectangle
the rectangle.
boundary
A coordinate list attribute for the boundary of a core_area. The format of a boundary
attribute.
full_name
A string attribute for the name of the core_area.
name
A string attribute for the name of the core_area.
Chapter 1:
83
1-83
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
object_class
A string attribute with the value of "core_area".
SEE ALSO
get_core_area(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
84
corner_attributes
Description of the predefined attributes for corners.
DESCRIPTION
corner attributes are provided in the subsections that follow.
command.
Corner Attributes
file_line_info
full_name
A string attribute for the name of a corner.
is_current
A Boolean attribute. The value will be "true" if this corner is the current corner, "false"
otherwise.
is_default
A Boolean attribute. The value will be "true" if this corner is the default corner, "false"
otherwise.
object_class
A string attribute with the value of "corner". Each object class has a different object class
value.
Chapter 1:
corner_attributes
85
1-85
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
create_corner(2)
get_attribute(2)
list_attributes(2)
corner_attributes
86
cts.balance_groups.balance_by_source_latency
This option controls whether or not the balance_clock_groups program will achieve the
purpose by adjusting source latency of clocks.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When true, the balance_clock_groups command will not insert buffers or inverters.
Instead, it will set source latency of clocks to achieve the balance.
When this variable is false, it will insert buffers or inverters to meet the delay for balancing.
SEE ALSO
balance_clock_groups(2)
Chapter 1:
cts.balance_groups.balance_by_source_latency
87
1-87
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.balance_groups.honor_source_latency
This option controls whether or not the balance_clock_groups program will honor source
latency of clocks.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When true, the balance_clock_groups command will honor the source latency of clocks.
Therefore, a clock delay will include its source latency and network latency.
When this variable is false, the balance_clock_groups command will only consider
network latency.
SEE ALSO
balance_clock_groups(2)
cts.balance_groups.balance_by_source_latency(3)
cts.balance_groups.honor_source_latency
88
cts.common.auto_exception_macro_balance_point
Controls whether the synthesize_clock_trees -auto_exceptions command sets clock tree
balance points for macros with large internal skew.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
Controls whether the synthesize_clock_trees -auto_exceptions command sets balance
points for macros with large internal skew. This balance point is created with an offset equal
to the largest latency inside the macro.
SEE ALSO
synthesize_clock_trees(2)
set_clock_tree_balance_point(2)
Chapter 1:
cts.common.auto_exception_macro_balance_point
89
1-89
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.common.directory_for_cts_generated_files
Set a directory for new files created by clock tree synthesis tools.
TYPE
String
DEFAULT
""
DESCRIPTION
This app option sets a directory for new files created by clock tree synthesis tools. The CTS
programs will automatically create this directory if it does not exist. By default CTS program
uses the current directory to store new files.
SEE ALSO
cts.common.directory_for_cts_generated_files
90
cts.common.enable_auto_exceptions
Controls whether the auto_exceptions feature is enabled for the clock tree synthesis tools.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This option controls whether the auto_exceptions feature is enabled for the clock synthesis
tools. The auto_exceptions feature will derive exceptions such as ignore point based on
analysis covering scenarios, such as structually impossible-to-balance, and internal pins in
macro cells.
SEE ALSO
Chapter 1:
cts.common.enable_auto_exceptions
91
1-91
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.common.enable_dirty_design_mode
Controls whether the dirty_design_mode feature is enabled for the clock tree synthesis
tools.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This option controls whether the dirty_design_mode feature is enabled for the clock
synthesis tools. When the dirty_design_mode is enabled, the CTS could override the user
settings, such as max transitions, max capacitances, cell spacing rules, and clock routing
rules.
Once set to true, the following constraint may be ignored or set:
1. Removes max_netlength constraint if it is too tight (less than 50um).
2. Ignores clock cell spacing rules if the spacing requirement setting is too high (x spacing is
more than 3 times of site height, y spacing is more than 20 times of site height).
3. Ignores NDR if width and spacing requirement settings are too high (width + space
requirement is more than 10 times of default width + default spacing).
4. Ignores max_transitions or max_capacitance if they are too small (compared against
internally calibrated values).
5. Treat dont_touch flag on nets as soft constraint if there is a large transition or net delay
violation on the nets.
6. Treat dont_touch_network as soft constraint if it is causing large skew.
7. Set auto_exceptions on ETM internal sinks as ignore to prevent impossible-to-fix large
skew.
92
SEE ALSO
Chapter 1:
93
1-93
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.common.max_fanout
Fanout constraint for clock tree synthesis
TYPE
int
DEFAULT
999
DESCRIPTION
This option sets a fanout constraint for clock tree synthesis in the synthesize_clock_trees
command. Clock tree synthesis will ensure that clock tree cells do not drive more than
max_fanout cells.
SEE ALSO
set_app_options(2)
cts.common.max_fanout
94
cts.common.max_net_length
Sets the maximum net length constraint for the clock tree synthesis tools.
TYPE
Float
DEFAULT
1.0e+30
DESCRIPTION
This option sets the maximum net length constraint for the clock synthesis tools. Here the
net length is measured from the net driver pin to its farthest load pin.
SEE ALSO
Chapter 1:
cts.common.max_net_length
95
1-95
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.common.user_instance_name_prefix
Set a prefix for new cell names created by clock tree synthesis tools.
TYPE
String
DEFAULT
""
DESCRIPTION
This app option sets a prefix for new cell names created by clock tree synthesis tools. The
default value of the prefix is a NULL string.
SEE ALSO
cts.common.user_instance_name_prefix
96
cts.common.verbose
Controls the verbosity level of clock tree synthesis tools.
TYPE
Integer
DEFAULT
1
DESCRIPTION
This option sets the verbosity level for the clock synthesis log file. The verbosity level can be
set to 0 or 1, where 0 is no debugging information and 1 is more debugging information.
SEE ALSO
Chapter 1:
cts.common.verbose
97
1-97
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.compile.enable_cell_relocation
Specifies the mechanism for relocating the existing cells in the clock tree prior to clock tree
synthesis.
TYPE
Enum
DEFAULT
"leaf_only"
DESCRIPTION
This option controls how existing clock tree cells are relocated before clock tree synthesis.
Possible values are leaf_only, all and none. leaf_only is the default.
The default value, leaf_only, relocates clock tree cells, for which relocation is allowed, to the
center of the bounding box of its fanout, only if none of the sinks in the fanout has
downstream phase delay. The all argument relocates all of the cells in the clock tree in such
manner. The none argument keeps incoming clock tree intact and prevents any relocation
of the existing clock tree cells.
Application options are set using the set_app_options command, and specified globally.
SEE ALSO
set_app_options(2)
cts.compile.enable_cell_relocation
98
cts.compile.enable_global_route
Specifies the mechanism for using global router in the initial stage of
synthesize_clock_trees command.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this option is true, global router will be used during the initial stage of the
synthesize_clock_trees command. By default this option is false and virtual router is used
during initial synthesis.
SEE ALSO
set_app_options(2)
Chapter 1:
cts.compile.enable_global_route
99
1-99
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.compile.fix_clock_tree_sinks
This application option controls whether clock tree sinks will be marked as fixed after
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this options is true, clock tree sinks will be marked as fixed after
SEE ALSO
cts.compile.fix_clock_tree_sinks
100
cts.compile.primary_corner
This application option specifies the primary corner used in the synthesize_clock_trees
command.
TYPE
String
DEFAULT
""
DESCRIPTION
The synthesize_clock_trees command will pick a primary corner in the compile stage. It
inserts buffers to balance clock delays in all modes on this corner. By default the primary
corner is selected with the worst delay corner. This option will force the tool to use the
specified corner as primary corner.
SEE ALSO
Chapter 1:
cts.compile.primary_corner
101
1-101
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.compile.remove_existing_clock_trees
Controls the synthesize_clock_trees command to remove existing buffers or inverters in the
clock trees.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
When this option is true, the synthesize_clock_trees command will remove existing
buffers and inverters in the clock trees before synthesis. Usually this will result in better clock
latencies and skews.
SEE ALSO
cts.compile.remove_existing_clock_trees
102
cts.multisource.subtree_merge_cell_name_prefix
TYPE
string
DEFAULT
""
DESCRIPTION
When merging of clock logic occurs during subtree synthesis, the new cell name created by
merging is called <mergedName>, where the convention for <mergedName> is controlled
by the cts.multisource.subtree_merge_concatenate_length_threshold app option.
If this subtree_merge_cell_name_prefix app option is used, then the merged cell name
will be called <prefix>_<mergedName> instead, where <prefix> is defined by this app
option.
If this app option is not specified, the default behavior is that the merged cell name has no
user defined prefix.
See also the cts.multisource.subtree_merge_cell_name_suffix app option for defining a
merged cell name suffix. If a prefix and suffix are both defined, then the merged cell name
convention is <prefix>_<mergedName>_<suffix>.
The cts.multisource.subtree_split_* app options also exist for controlling naming
conventions of cells that are split during multisource subtree synthesis.
This app option affects only the behavior of the synthesize_multisource_clock_subtrees
command.
SEE ALSO
synthesize_multisource_clock_subtrees(2)
cts.multisource.subtree_merge_cell_name_suffix(3)
cts.multisource.subtree_merge_concatenate_length_threshold(3)
cts.multisource.subtree_split_cell_name_prefix(3)
cts.multisource.subtree_split_cell_name_suffix(3)
Chapter 1:
103
1-103
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.multisource.subtree_split_net_name_prefix(3)
cts.multisource.subtree_split_net_name_suffix(3)
104
cts.multisource.subtree_merge_cell_name_suffix
TYPE
string
DEFAULT
""
DESCRIPTION
by the cts.multisource.subtree_merge_concatenate_length_threshold app option.
If this subtree_merge_cell_name_suffix app option is used, then the merged cell name
will be called <mergedName>_<suffix> instead, where <suffix> is defined by this app option.
If this app option is not specified, the default behavior is that the merged cell name has no
user defined suffix.
See also the cts.multisource.subtree_merge_cell_name_prefix app option for defining a
merged cell name prefix. If a prefix and suffix are both defined, then the merged cell name
convention is <prefix>_<mergedName>_<suffix>.
command.
SEE ALSO
cts.multisource.subtree_merge_cell_name_prefix(3)
Chapter 1:
105
1-105
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
106
cts.multisource.subtree_merge_concatenate_length_threshold
TYPE
Integer
DEFAULT
0
DESCRIPTION
by this app option.
By default, the merged cell name is arbitrarily inherited from the name of one of the
non-merged cells. For example, if cell1, cell2, and cell3 are merged during multisource
subtree synthesis, then the merged cell name might be cell2.
Setting this app option to a positive integral value enables name concatenation, where the
merged cell name is derived by concatenating the names of the unmerged cells. There is
some identification of common parts of the cell names avoid duplicating the common part
during the name concatenation.
For example, the original cells may have been named cell_123 and cell_456. The
concatenated name for the merged cell could be cell_123_456, or cell_456_123.
Name concatenation only occurs if the total length of the cell name does not exceed the
value set by this app option. If the name length does exceed the concatenation threshold,
then the default behavior is used of just choosing one of the original cell's names for the
merged cell name.
Consider the same example again where the concatenated name is cell_123_456, which is
12 characters long. If this app option is set to 12 or greater, then the merged cell name of
cell_123_456 will be used. But if this app option is set to a value less than 12, then the
merged cell name will be either cell_123 or cell_456.
See also the cts.multisource.subtree_merge_cell_name_prefix app option for defining a
merged cell name prefix. If a prefix is defined, then the merged cell name convention is
<prefix>_<mergedName>.
Chapter 1:
107
1-107
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
See also the cts.multisource.subtree_merge_cell_name_suffix app option for defining a

merged cell name suffix. If a suffix is defined, then the merged cell name convention is
<mergedName>_<suffix>.
If both a prefix and suffix are set with those app options, then the merged cell name is
<prefix>_<mergedName>_<suffix>.
Note that this app option only considers <mergedName> when checking if the name
exceeds the concatenation length threshold, not the <prefix> and/or <suffix> parts of the
name.
command.
SEE ALSO
108
cts.multisource.subtree_routing_mode
TYPE
global | fishbone | none
DEFAULT
none
DESCRIPTION
When multisource CTS subtree synthesis runs, the clock nets can be routed using one of
three methods, as configured by this app option.
The default routing mode is global, which uses global routing on clock nets. This app option
can also be set to fishbone, which enables fishbone routing on all clock nets for the
subtrees. The other available setting for this app option is none, which uses virtual routing
for all clock nets on the subtrees.
When fishbone routing is used, the clock nets will be a mix of detailed routes and global
routes. A fishbone routing structure involves a central fishbone trunk off of the net driver,
which extends the full length of the cluster of net loads. Fishbone routing will only be used
on a net if the fishbone trunk is at least 5 gcells in length. Off of this trunk, several fishbone
fingers may extend. The trunk and fingers are routed on the two highest allowed routing
layers. The trunk and the fingers are protected detailed route shapes with shape_use of
stripe.
The net loads are connected to the fishbone fingers by short comb routes, which are global
routed. The comb routes can use all allowed routing layers for the net.
When fishbone routing is used, there are several app options available to control the
fishbone routing behavior for CTS commands. See the cts.routing.fishbone_* app options
for more details.
command.
Chapter 1:
109
1-109
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
cts.routing.fishbone_max_tie_distance(3)
cts.routing.fishbone_max_sub_tie_distance(3)
cts.routing.fishbone_bias_threshold(3)
cts.routing.fishbone_bias_window(3)
cts.routing.fishbone_horizontal_bias_spacing(3)
cts.routing.fishbone_vertical_bias_spacing(3)
110
cts.multisource.subtree_split_cell_name_prefix
TYPE
string
DEFAULT
""
DESCRIPTION
During multisource subtree synthesis, clock cells may be split in order to meet optimization
goals. This app option configures a prefix for the names of cells created by splitting.
When splitting, the naming convention for newly created cells is
<originalCellName>_<index>, where <index> is incremented for each newly created cell. By
default, no prefix is attached to this cell name.
This app option defines a prefix for the split cell names. When this app option is set to a
non-null value, the newly created cells are named <prefix>_<originalCellName>_<index>,
where <prefix> is defined by this app option.
command.
SEE ALSO
Chapter 1:
cts.multisource.subtree_split_cell_name_prefix
111
1-111
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.multisource.subtree_split_cell_name_suffix
TYPE
string
DEFAULT
""
DESCRIPTION
goals. This app option configures a suffix for the names of cells created by splitting.
When splitting, the naming convention for newly created cells is
<originalCellName>_<index>, where <index> is incremented for each newly created cell. By
default, no suffix is attached to this cell name.
This app option defines a suffix for the split cell names. When this app option is set to a
non-null value, the newly created cells are named <originalCellName>_<index>_<suffix>,
where <suffix> is defined by this app option.
command.
SEE ALSO
cts.multisource.subtree_split_cell_name_suffix
112
cts.multisource.subtree_split_net_name_prefix
TYPE
string
DEFAULT
""
DESCRIPTION
goals. Every time a cell is split, a new net must be created which is driven by that split cell.
This app option configures a prefix for the names of the new nets created by splitting.
When splitting, the naming convention for newly created nets is
<originalNetName>_<index>, where <index> is incremented for each newly created cell/
net. By default, no prefix is attached to this net name.
This app option defines a prefix for the split net names. When this app option is set to a
non-null value, the newly created nets are named <prefix>_<originalNetName>_<index>,
where <prefix> is defined by this app option.
command.
SEE ALSO
Chapter 1:
cts.multisource.subtree_split_net_name_prefix
113
1-113
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.multisource.subtree_split_net_name_suffix
TYPE
string
DEFAULT
""
DESCRIPTION
goals. Every time a cell is split, a new net must be created which is driven by that split cell.
This app option configures a suffix for the names of the new nets created by splitting.
When splitting, the naming convention for newly created nets is
<originalNetName>_<index>, where <index> is incremented for each newly created cell/
net. By default, no suffix is attached to this net name.
This app option defines a suffix for the split net names. When this app option is set to a
non-null value, the newly created nets are named <originalNetName>_<index>_<suffix>,
where <suffix> is defined by this app option.
command.
SEE ALSO
cts.multisource.subtree_split_net_name_suffix
114
cts.multisource.tap_synthesis_route_based_estimation
By default tap assignment considers the placeable standard cell area when computing the
path length between a tap cell and a clock sink. Setting this option to true let's tap
assignment perform buffer-aware global routing based distance computation.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This option controls how multisource tap assignment performs the estimation of distance
between tap cells and clock tree sinks. Possible values are true and false (the default). Sinks
are assigned to tap cells based on the closest of such distance.
When this option is set to its default value of false tap assignment computes the distance
between a clock sink and a tap cell by estimating a path in the placeable standard cell area,
i.e. placement blockages or macros might introduce detouring. Setting this option to true will
enable a buffer-aware global routing based estimation. Small placement blockages or
macros won't trigger detouring in case tap assignment determines that CTS can route over
those blockages honoring clock DRC constraints. NDRs and min or max layer constraints
on clock nets are considered while performing the routing based estimation.
This application option is set using the set_app_options command, and specified per
design.
SEE ALSO
set_app_options(2)
synthesize_multisource_clock_taps(2)
Chapter 1:
cts.multisource.tap_synthesis_route_based_estimation
115
1-115
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.multisource.verbose
TYPE
Integer
DEFAULT
0
DESCRIPTION
All multisource CTS synthesis commands generate some logfile output. By default, this
logfile output is limited, giving some information about progress and results of the command,
as well as information about any problems encountered during synthesis.
The verbosity of this logfile output can be increased by setting this app option to 1. This will
give more detailed logfile output that may be helpful in debugging a more complex problem
with multisource CTS synthesis. For most users, the default setting of 0 should be sufficient.
This app option controls verbosity of logfile messages for all multisource synthesis
commands.
SEE ALSO
cts.multisource.verbose
116
cts.placement.cell_spacing_rule_style
This application option implies the style of the spacing rules used / honored between the
cells in the clock tree for which such rules are defined.
TYPE
Enum
DEFAULT
maximum
DESCRIPTION
Possible values are cumulative and maximum.
When cumulative is specified and spacing rules are present valid distance between 2 cells
affected by the rules changes from default - (maximum) between x1 and x2 and (maximum)
between y1 and y2 to the sum of x1 and x2 and sum of y1 and y2.
SEE ALSO
report_clock_cell_spacing(2)
set_clock_cell_spacing(2)
Chapter 1:
cts.placement.cell_spacing_rule_style
117
1-117
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.report.transition_histogram_datapoints
This option gives user control over how the transition histograms are populated for
-histogram_type transition of report_clock_qor command.
TYPE
Enum
DEFAULT
"loads"
DESCRIPTION
When loads, only net loads are populated in the histograms. When drivers, only net drivers
are populated. When all, all clock pins/ports are considered as datapoints for the transition
histograms.
SEE ALSO
report_clock_qor(2)
cts.report.transition_histogram_datapoints
118
cts.report.verbose_paths_routing_length_threshold
This option gives user control to filter the output of the routing layer field to only show the
layers which have length over a certain threshold in -show_verbose_path report of
report_clock_qor command.
TYPE
Double
DEFAULT
100000.00
DESCRIPTION
This option controls for the routing layer information in show_verbose_pathsreports. The
default value is 10um. If a certain routing layer has length below the threshold, it wouldn't be
printed. So for example with threshold of 0 we may see {M1 2.0} {M2 15.4} {M3 300.8} and
with threshold of 20um we would instead just see {M3 300.8}.
SEE ALSO
report_clock_qor(2)
Chapter 1:
cts.report.verbose_paths_routing_length_threshold
119
1-119
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.routing.fishbone_bias_threshold
TYPE
Double
DEFAULT
0
DESCRIPTION
This app option controls fishbone routing behavior for all CTS synthesis commands that
have fishbone routing enabled. It has no effect if fishbone routing is not used during CTS.
Fishbone routing topologies can be biased towards power or ground nets so that those nets
act as shields, to improve signal integrity on the fishbone route. Biasing, if enabled, is
performed on the fishbone trunks only, not the fishbone fingers nor the comb routes
connecting the net loads to the fingers.
This app option specifies a minimum trunk length on a fishbone route before biasing of the
trunk placement is attempted. It has no effect unless fishbone trunk biasing is enabled
through either or both of the fishbone_horizontal_bias_spacing and
fishbone_vertical_bias_spacing app options.
The default value of 0 means that biasing will be attempted on all fishbone trunks. By setting
this app option to a positive value, it prevents biasing attempts on trunks shorter than the
specified length threshold. The threshold should be specified in length units as configured
by the set_user_units -type length -input command, which is micrometers (um) by
default.
See also the fishbone_vertical_bias_spacing app option to enable biasing on vertical
fishbone trunks.
See also the fishbone_horizontal_bias_spacing app option to enable biasing on
horizontal fishbone trunks.
See also the fishbone_bias_window app option to specify a maximum displacement of a
trunk from its preferred location in order to achieve biasing.
120
SEE ALSO
cts.multisource.subtree_routing_mode(3)
Chapter 1:
121
1-121
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.routing.fishbone_bias_window
TYPE
Double
DEFAULT
0
DESCRIPTION
connecting the net loads to the fingers.
This app option specifies a maximum displacement from the preferred location of the
fishbone trunk, in order to achieve biasing against a power or ground net. It has no effect
unless fishbone trunk biasing is enabled through either or both of the
fishbone_horizontal_bias_spacing and fishbone_vertical_bias_spacing app options.
Each fishbone trunk has a preferred location, based on the locations of the net driver and
the net loads. Typically the fishbone trunk must be shifted away from its preferred location
in order to achieve biasing against the nearest power or ground net. The default value of 0
on this app option means that there is no limit to how far the fishbone trunk may be displaced
to achieve biasing. Setting this app option to a positive value places a maximum
displacement limit on the fishbone trunks to achieve biasing. If the required displacement
exceeds this threshold for a given fishbone trunk, then it will not be biased. The threshold
should be specified in length units as configured by the set_user_units -type length -input
command, which is micrometers (um) by default.
fishbone trunks.
122
See also the fishbone_bias_threshold app option to specify a minimum trunk length
before attempting biasing.
SEE ALSO
Chapter 1:
123
1-123
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.routing.fishbone_horizontal_bias_spacing
TYPE
Double
DEFAULT
0
DESCRIPTION
connecting the net loads to the fingers. This app option controls biasing for horizontal
fishbone trunks.
The default value for this app option is 0, meaning that no attempt is made to bias the
placement of horizontal fishbone trunks towards power or ground nets. If this app option is
set to a positive value, then biasing of the horizontal fishbone trunks is enabled, and this app
option indicates the desired spacing between the fishbone trunk and the power or ground
net. The spacing should be specified in length units as configured by the set_user_units
-type length -input command, which is micrometers (um) by default.
fishbone trunks.
SEE ALSO
124
Chapter 1:
125
1-125
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.routing.fishbone_max_sub_tie_distance
TYPE
Double
DEFAULT
0
DESCRIPTION
A fishbone routing structure involves a central fishbone trunk off of the net driver, which
extends the full length of the cluster of net loads. Off of this trunk, several fishbone fingers
may extend. The net loads are connected to the fishbone fingers by short comb routes.
Comb routes are not shared: each comb routes connects only one net load to its fishbone
finger.
Optionally, another level of fishbone routing can be introduced, called sub-fingers. These
connect to the fingers, and then the comb routes can instead connect the net loads to the
sub-fingers. This can reduce wirelength, especially in the case that a large
fishbone_max_tie_distance is used. Multiple comb routes can connect to a single
sub-finger, though each comb route still connects to only one net load.
The fishbone trunk and fingers are routed on the two highest layers configured for the net. If
sub-fingers are used, they are routed on the layer directly below the finger.
By default, sub-fingers are not created. But by setting this app option to a value greater than
0, sub-fingers are created. This app option controls the maximum distance from a fishbone
sub-finger to all of its connected net loads. In other words, it defines a window around the
sub-finger (orthogonal to the routing direction of the sub-finger) in which net loads can be
connected to that sub-finger. For example, if the max sub-tie distance is configured to 20um
on a vertical sub-finger, then the farthest away net loads might be 13um to the west and 7um
to the east of the sub-finger.
This behavior is identical to that of the fishbone_max_tie_distance app option, but in this
case the connection window is defined for sub-fingers rather than fishbone fingers.
126
The max sub-tie distance should be specified in length units as configured by the
set_user_units -type length -input command, which is micrometers (um) by default.
SEE ALSO
Chapter 1:
127
1-127
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.routing.fishbone_max_tie_distance
TYPE
Double
DEFAULT
0
DESCRIPTION
A fishbone routing structure involves a central fishbone trunk off of the net driver, which
extends the full length of the cluster of net loads. Off of this trunk, several fishbone fingers
may extend. The net loads are connected to the fishbone fingers by short comb routes.
This app option controls the maximum distance from a fishbone finger to all of its connected
net loads. In other words, it defines a window around the finger (orthogonal to the routing
direction of the finger) in which net loads can be connected to that finger. For example, if the
max tie distance is configured to 20um on a vertical finger, then the farthest away net loads
might be 13um to the west and 7um to the east of the finger.
In a sense, this app option controls the frequency with which fishbone fingers are created
along the fishbone trunk. The smaller the max tie distance, the greater the number of
fishbone fingers that will be created to connect to the net loads.
The default value of this app option is 0. With this default, a max tie distance equal to 20
gcells distance is automatically derived. When specifying a non-default value for this app
option, the max tie distance should be specified in length units as configured by the
set_user_units -type length -input command, which is micrometers (um) by default.
SEE ALSO
128
Chapter 1:
129
1-129
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
cts.routing.fishbone_vertical_bias_spacing
TYPE
Double
DEFAULT
0
DESCRIPTION
connecting the net loads to the fingers. This app option controls biasing for vertical fishbone
trunks.
The default value for this app option is 0, meaning that no attempt is made to bias the
placement of vertical fishbone trunks towards power or ground nets. If this app option is set
to a positive value, then biasing of the vertical fishbone trunks is enabled, and this app
option indicates the desired spacing between the fishbone trunk and the power or ground
net. The spacing should be specified in length units as configured by the set_user_units
-type length -input command, which is micrometers (um) by default.
SEE ALSO
130
Chapter 1:
131
1-131
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
design.bus_delimiters
Specifies the bus delimiters to be used in port, pin, and net names.
TYPE
String
DEFAULT
"[]"
DESCRIPTION
This app_option specifies the bus delimiters to be used in port, pin, and net names to denote
bus subscripts. Valid values are "[]", "{}", "()", and "<>". However the bus delimiters may not
be the same as the name expansion delimiters.
These delimiters may be used in the get_ports, get_pins, and get_nets commands, as
well as any commands that creates a collection from port, pin, or net names.
All bus port, pin, and net names are displayed with these delimiters.
SEE ALSO
design.name_expansion_delimiters(3)
get_ports(2)
get_pins(2)
get_nets(2)
set_app_options(2)
design.bus_delimiters
132
design.edit_read_only_libs
Controls whether the open_block command changes a read-only library to edit mode when
you open a block in the library in edit mode.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This option controls how the open_block command treats a read-only library when opening
a block in the library.
By default (true), the open_block command changes a read-only library to edit mode when
you open a block in the library in edit mode.
When this option is set to false, the behavior depends on whether you explicitly open the
block in edit mode by using the -edit option with the open_block command.
If you specify the -edit option, the open_block command fails with a DES-029 error.
If you do not specify the -edit option, the open_block command opens the block in
read-only mode.
SEE ALSO
open_block(2)
reopen_block(2)
get_app_options(2)
set_app_options(2)
Chapter 1:
design.edit_read_only_libs
133
1-133
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
design.morph_on_save_as
Controls whether the save_block command renames the block before saving it when you
use the -as option.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
By default (false), the save_block -as command does not rename the block before saving
it.
When this option is set to true, the command first renames the block and then saves it.
SEE ALSO
save_block(2)
get_app_options(2)
set_app_options(2)
design.morph_on_save_as
134
design.name_expansion_delimiters
Specifies the name expansion delimiters to be used in port, pin, and net names.
TYPE
String
DEFAULT
"()"
DESCRIPTION
This app_option specifies the name expansion delimiters to be used in port, pin, and net
names to denote name expansion subscripts. Valid values are "[]", "{}", "()", and "<>".
However the name expansion delimiters may not be the same as the bus delimiters.
These delimiters may be used in the get_ports, get_pins, and get_nets commands, as
well as any commands that creates a collection from port, pin, or net names.
SEE ALSO
design.bus_delimiters(3)
get_ports(2)
get_pins(2)
get_nets(2)
set_app_options(2)
Chapter 1:
design.name_expansion_delimiters
135
1-135
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
design.preserve_physical_only_pg
Controls whether resolve_pg_nets and connect_pg_net preserve PG connections to
physical only cells.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
By default (false), resolve_pg_nets and connect_pg_net do not preserve PG connections to
physical only cells.
When this option is true, resolve_pg_nets and connect_pg_net preserve PG connections to
physical only cells. No PG connection to any physical only cell will be changed.
SEE ALSO
resolve_pg_nets(2)
connect_pg_net(2)
design.preserve_physical_only_pg
136
design.sub_blocks_for_read
Controls whether the open_block and link_block command opens the sub-blocks in
read-only mode.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
By default (false), the open_block and link_block command opens the sub-blocks in the
same open-mode as its library.
When this option is set to true, the sub-blocks are always open in read-only mode even
when the library is in edit mode or with the open_block -ref_libs_for_edit option.
SEE ALSO
open_block(2)
link_block(2)
lib_attributes(3)
get_app_options(2)
set_app_options(2)
Chapter 1:
design.sub_blocks_for_read
137
1-137
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
design.uniquify_naming_style
Specifies the naming style string to be used by "uniquify" and "uniquify_block" commands
while naming new reference copy created during uniquification process. It is a block scoped
app option.
TYPE
String
DEFAULT
"%s_%d"
DESCRIPTION
This app option provides naming style string for commands "uniquify" and "uniquify_block"
for naming new reference copy during uniquification process. Default value for app option is
"%s_%d", where "%s" denotes name of existing reference and "%d" denotes incrementally
generated integer. Value provided for this app option must contain single instance of
substrings "%s" and "%d", and these two substrings should be present in that order. To
include "%" in actual string use "%%".
EXAMPLES
Following is an example of valid input value: prompt> set_app_options
{design.uniquify_naming_style pre_%s_mid_%d_suf} -global prompt> set_app_options
{design.uniquify_naming_style %s_%d_%%s} -global
Following are few examples of invalid input values: prompt> set_app_options
{design.uniquify_naming_style pre_%d} -global prompt> set_app_options
{design.uniquify_naming_style %s_suf} -global prompt> set_app_options
{design.uniquify_naming_style %d_%s} -global prompt> set_app_options
{design.uniquify_naming_style %s_%d_%s} -global
SEE ALSO
uniquify(2)
uniquify_block(2)
138
set_app_options(2)
Chapter 1:
139
1-139
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
design.verbose_io
Controls whether each design I/O operation issues an information message.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
By default (false), design I/O operations do not issue an information message.
When this option is true, the following design I/O operations issue an information message:
reading a design from a library, saving a design to a library, closing a design, and changing
the open mode of a design.
For example,
Information: Opening design myLib:myDesign.design, mode edit. (NDM-065)
SEE ALSO
close_blocks(2)
open_block(2)
remove_blocks(2)
reopen_block(2)
get_app_options(2)
set_app_options(2)
design.verbose_io
140
design_attributes
Description of the predefined attributes for designs.
DESCRIPTION
design attributes are provided in the subsections that follow.
command.
Design Attributes
bbox
the rectangle.
block
A collection attribute of block of this design.
block_name
A string attribute for the name this design as a block.
boundary
A coordinate_list attribute for the boundary of a design. The format of a coordinate_list
specification is {{x1 y1} {x2 y2}...}.
Chapter 1:
design_attributes
141
1-141
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
boundary_bbox
the rectangle.
core_area_area
A double attribute for the area of the core_area.
core_area_bbox
A rectangle attribute for the bounding-box of the core_area. The format of a rectangle
the rectangle.
core_area_boundary
A coordinate_list attribute for the coordinates of the core_area. The format of a
coordinate_list specification is {{x1 y1} {x2 y2}...}.
extended_name
A string attribute representing the full path to the library plus the design name, separated by
a ':' character, an optional label name, separated by a '/' character, and a view name,
separated by a '.'. For example, "/disks/user1/work/top_lib:top_design/my_label.design".
full_name
A string attribute for the full name of a design, including the library name plus the design
name, separated by a ':' character, an optional label name, separated by a '/' character, and
a view name, separated by a '.' character. For example, "top_lib:top_design/
my_label.design"
inner_keepout_margin
A margin_list attribute
inner_keepout_type
A string attribute representing the inner keepout type of the design. This attribute is settable.
Valid values are "hard" and "soft".
design_attributes
142
is_current
A Boolean attribute. The value will be "true" if this design is the current_design for the
session, "false" otherwise.
is_hierarchical
A Boolean attribute. The value is always true.
is_modified
A Boolean attribute. The value will be "true" if this design has modified and un-saved data,
false otherwise. This attribute is settable.
is_open
A Boolean attribute. The value will be "true" if this design is already loaded into memory,
false otherwise.
last_modified
A string attribute representing the date and time this design was last modified.
last_saved
A string attribute representing the date and time this design was last saved.
lib
A collection attribute of library of this design.
lib_name
A string attribute for the name of library of this design.
logic_only
A Boolean attribute. The value will be "true" if this design is marked for the logic-only design
flow. The attribute can only be set to "true" before the design is linked with link_design.
Logic-only designs are used for Design Planning budgeting timing. They can not have
physical design information, so they use less memory.
Chapter 1:
design_attributes
143
1-143
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
use_frame_blockage
A Boolean attribute. This option enables the user to choose to not use blockages in certain
frames. The default value is "true", which results in usage of the blockages in the frame.
object_class
A string attribute with the value of "design".
open_count
switch_list
A string attribute representing the effective view switch list of this design. The effective view
switch list is the precedence-ordered list of design views that is applied when attempting to
bind this design.
top_module
A collection attribute of the top module of this design.
top_module_name
A string attribute for the name of the top module of this design.
view_name
A string attribute for the view name of this design. The valid value is ine of, abstract, design,
frame, layout, outline or timing.
SEE ALSO
current_design(2)
get_designs(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
design_attributes
144
design_checks_attributes
Description of the predefined attributes for design_checks attributes.
DESCRIPTION
design_checks attributes are provided in the subsections that follow.
command.
attributes available for a class of objects use the list_attributes -application -class
ems_check command.
design_checks Attributes:
current_definition
A string attribute representing the current check - or a group of checks performed by using
the design_check.
default_definition
A string attribute representing the default setting of check/s performed by using the
design_check. Be aware that user defined checks don't have default_definitions.
enabled
A Boolean attribute representing the curent enable status of the check. This is a settable
attribute.
full_name
A string attribute for the full name of the design_check. This attribute is assensial for
get_object_name command.
Chapter 1:
145
1-145
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
group_members_count
A string (number) attribute describes the number of members in the group. If the design
check is defined as a check, this number is 0. If the design check is defined as a group, this
number is higher then 0.
group_name
A string attribute describes the group name. If the design check is defined as a check, this
attribute is empty. If the design check is defined as a group, this attribute gives the group
name.
help_info
A string attribute describes what is the check doing.
is_default
A Boolean attribute representing the current status of the command. If the default settings of
the design check remains, it returns true. If the default settings Overridden by user settings
it returns false.
is_group_member
A Boolean attribute describes a check membership in a group of checks. If the design check
is not a member in a group of checks, it returns false. If the design check is a member in a
group of checks, it returns true.
is_group_name
A Boolean attribute describes if a design check is defined as group. If the design check is
defined as a check, it returns false. If the design check is defined as a group, it returns true.
name
A string attribute for the name of the design_check.
object_class
A string attribute discribes the check design class which is "ems_check".
146
SEE ALSO
get_design_checks(2)
get_attribute(2)
list_attributes(2)
get_object_name(2)
set_attribute(2)
Chapter 1:
147
1-147
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
drc_error_attributes
Description of the predefined attributes for drc_error.
DESCRIPTION
Definitions for drc_error attributes are provided in the subsections that follow.
command.
DRC Error Attributes
name
A string attribute for the name of a drc_error.
full_name
A string attribute for the full name of a drc_error. This is equivalent to the name.
object_class
A string attribute with the value of "drc_error".
error_class
The category of errors in which the drc_error belongs, e.g. short or spacing. The basic
category includes all errors that do not belong in others.
error_data
A string attribute for the name of the drc_error_data in which the drc_error was created.
error_type
A string attribute for the name of the drc_error_type in which the drc_error belongs.
148
error_id
An integer attribute for identfier for the drc_error.
brief_info
A string attribute with a brief information about the drc_error.
verbose_info
A string attribute with verbose information about the drc_error.
error_info
A string attribute with additional information specific to the drc_error. This is a settable
attribute.
status
A string attribute indicating the current status of the drc_error: error, fixed, ignored, or
waived. This is a settable attribute.
must_fix
A Boolean attribute indicating whether this drc_error was marked as a must_fix error. This is
bbox
A rectangle attribute with the bounding box about all shapes that describe this drc_error.
shape
A list of polyrects or polygons which describe the drc_error.
points
A list of points which describe the drc_error.
layers
A string attribute with the layer name(s) on which the drc_error was detected.
Chapter 1:
149
1-149
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
shape_uses
A list of shape_uses associated with the layers on which the drc_error was detected.
objects
A collection attribute with the design objects associated with the drc_error.
required_spacing
A distance attribute indicating the required spacing which was violated in the drc_error.
actual_spacing
A distance attribute indicating the actual spacing which violated the required spacing in the
drc_error.
direction
A string attribute with the direction of the violation, for example in a spacing violation.
pin_edge
A integer attribute with the pin edge involved in the violation.
required_width
A distance attribute indicating the required width of an object which was violated in the
drc_error.
required_height
A distance attribute indicating the required height of an object which was violated in the
drc_error.
SEE ALSO
get_drc_error(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
150
drc_error_data_attributes
Description of the predefined attributes for drc_error_data.
DESCRIPTION
Definitions for drc_error_data attributes are provided in the subsections that follow.
command.
DRC Error Data Attributes
name
A string attribute for the name of a drc_error_data.
full_name
A string attribute for the full name of a drc_error_data. This is equivalent to the name.
object_class
A string attribute with the value of "drc_error_data".
checker_name
A string attribute for the name of the checker which produced this error data.
checker_version
A string attribute for the version of the checker which produced this error data.
creation_date
A string attribute for the date on which this error error was created.
Chapter 1:
151
1-151
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
modification_date
A string attribute for the date on which this error error was last modified.
schema_version
A string attribute for the schema version for this error data.
information
A string attribute with additional information about this error data.
open_mode
A string attribute with the mode in which the error data was opened, read_only or read_write.
modified
A Boolean attribute for whether the error data contains uncommitted changes.
num_errors
An integer attribute for the number of reported drc_error instances in this drc_error_data.
num_types
An integer attribute for the number of drc_error_type instances in this drc_error_data.
SEE ALSO
get_drc_error_data(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
152
drc_error_type_attributes
Description of the predefined attributes for drc_error_type.
DESCRIPTION
Definitions for drc_error_type attributes are provided in the subsections that follow.
command.
DRC Error Type Attributes
name
A string attribute for the name of a drc_error_type.
full_name
A string attribute for the full name of a drc_error_type. This is equivalent to the name.
object_class
A string attribute with the value of "drc_error_type".
error_class
The category of errors in which the drc_error_type belongs, e.g. short or spacing. The basic
category includes all error types that do not belong in others.
error_data
A string attribute for the name of the drc_error_data in which the drc_error_type was
created.
Chapter 1:
153
1-153
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
num_errors
An integer attribute for the number of reported drc_error instances in this drc_error_type.
num_detected_errors
An integer attribute for the number of detected drc_error instances in this drc_error_type.
Some checkers allow the user to set a limit on the number of reported error instances per
type. The checker may detect more and may record the actual number detected in this
attribute.
severity
A string attribute for the serverity level of the error type: error, warning, recommendation,
information, or unknown.
brief_info
A string attribute with a brief information about the error type.
brief_format
A string attribute used internally to interpret the brief information string.
verbose_info
A string attribute with verbose information about the error type.
verbose_format
A string attribute used internally to interpret the verbose information string.
bbox
A rectangle attribute with the bounding box about all drc_error instance shapes and points.
SEE ALSO
get_drc_error_type(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
154
eco.add_buffer_on_route.min_distance_buffer_to_load
Option for the add_buffer_on_route command. Specifies the minimum distance from the
last buffer to a load.
TYPE
float
DEFAULT
Automatically setting as 1% of -repeater_distance of add_buffer_on_route
DESCRIPTION
When add_buffer_on_route tries to add a buffer whose route distance (path travelled by
the net) to load pin is less than the value specified by this variable, the buffer will not be
inserted. It is an absolute value and its unit is micron. If the buffer to add is an inverter, it still
will be added no matter how close to load. This is to make sure inverter is always paired.
EXAMPLES
The following example specifies the min_distance_buffer_to_load for the
add_buffer_on_route command.
prompt> set_app_options -name
eco.add_buffer_on_route.min_distance_buffer_to_load -value 1
SEE ALSO
get_app_options(2)
set_app_options(2)
add_buffer_on_route(2)
Chapter 1:
eco.add_buffer_on_route.min_distance_buffer_to_load
155
1-155
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
eco.functional.diff_ignore_tie_changes
Option for the eco_netlist command. Ignore the unexpected netlist difference related to tie
nets.
TYPE
bool
DEFAULT
false
DESCRIPTION
read_verilog will generate unexpected tie net changes caused by tie net assignment, this
option provides a control to ignore these unexpected difference.
EXAMPLES
The following example specifies the diff_ignore_tie_changes for the eco_netlist
command.
prompt> set_app_options -name eco.functional.diff_ignore_tie_changes
-value true
SEE ALSO
get_app_options(2)
set_app_options(2)
eco_netlist(2)
eco.functional.diff_ignore_tie_changes
156
eco.functional.diff_preprocess_for_verilog
Option for the eco_netlist command. Ignore the unexpected netlist difference caused by
verilog syntax.
TYPE
bool
DEFAULT
false
DESCRIPTION
Due to the verilog syntax, write_verilog will generate some netlist difference from the
original design. eco_netlist will detect these difference when using the outputted verilog file
as golden. Since these difference are not user intention, this option provides a control to
ignore these unexpected difference.
EXAMPLES
The following example specifies the diff_preprocess_for_verilog for the eco_netlist
command.
prompt> set_app_options -name eco.functional.diff_preprocess_for_verilog
-value true
SEE ALSO
get_app_options(2)
set_app_options(2)
eco_netlist(2)
Chapter 1:
eco.functional.diff_preprocess_for_verilog
157
1-157
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
edit_group_attributes
Description of the predefined attributes for edit_groups.
DESCRIPTION
edit_group attributes are provided in the subsections that follow.
command.
Edit Group Attributes
bbox
A rectangle attribute for the bounding-box of an edit_group. The format of a rectangle
the rectangle.
bump_array_bbox
A rectangle attribute for the bounding-box of an edit_group used for bump array. The format
of a rectangle specification is {{llx lly} {urx ury}}, which specifies the lower-left and
upper-right corners of the rectangle.
delta
A coordinate attribute representing the distance between members of an edit_group used
for bump array. The x-coordinate is the distance in x direction and y-coordinate is the
distance in y direction.
full_name
A string attribute for the name of the edit_group.
158
group_use
A string attribute representing what the edit_group is used for. This is a settable attribute and
values are restricted to bump_array, io_group, macro_array and user.
isBumpArray
A Boolean attribute representing if the edit_group is used for bump array.
is_placement_constraint
A Boolean attribute indicating if the edit_group is used as a placement constraint. This is a
settable attribute.
is_shadow
A Boolean attribute to specify whether an edit_group is pushed down from above.
is_transformable
A Boolean attribute to determine whether the edit_group can be transformed based on the
current group status and the presence of unsupported member types.
lib_cell
A string attribute representing the design name of the first member of the edit_group.
name
A string attribute for the name of the edit_group.
object_class
A string attribute with the value of "edit_group".
objects
A collection attribute representing the objects associated with the edit_group.
orientation
A string attribute representing the orientation of edit_group used for bump array as N, S, W,
E, FN, FS, FW or FE.
Chapter 1:
159
1-159
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
origin
A coordinate attribute representing origin across all members of edit_group used for bump
array with respect to top level bounding box origin.
parent_edit_group
A collection attribute representing the owner edit_group in which current edit_group
belongs.
pattern
A string attribute to specify if the edit_group pattern is inline or of staggered types.
physical_status
A string attribute representing the physical modification status of the edit_group. Valid
values are unrestricted and locked. If status is unrestricted, the edit_group may be freely
modified. If status is locked, the edit_group is fixed for automatic and manual changes. This
repeat
A coordinate attribute where x-coordinate specifies number of members in edit_group used
for bump array having unique bounding box upper right x-coordinate and similarly for
y-coordinate.
shadow_status
A string attribute to represent the shadow status of an edit_group. Valid values are
copied_down, copied_up, normal, pulled_up, and pushed_down. This is a settable attribute.
ungroup_on_remove
A string attribute to specify when an edit_group should self delete. This is a settable attribute
and values are restricted to first, last, never and second-to-last.
parent_block
A collection attribute with the owner block object for this edit_group.
parent_cell
A collection attribute with the owner cell object for this edit_group.
160
parent_block_cell
A collection attribute with the parent block cell object for this edit_group.
top_block
A collection attribute with the top block object for this edit_group.
SEE ALSO
create_edit_group(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
161
1-161
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
em.net_delta_temperature
Define the delta temperature used in signal EM RMS limit lookup.
TYPE
float
DEFAULT
5.0
DESCRIPTION
This application option define delta temperature used in signal EM RMS limit lookup. If the
signal EM RMS constraints are defined on delta temperature, the setting value is used in the
limit lookup. Higher delta temperature allows higher RMS current. By default, the value is
5.0.
Application options are set using the set_app_options command, and they may be
specified globally or with respect to a design.
Use get_app_option_value -design $design -name em.net_delta_temperature to get
the current value of this application option on a specific design.
Use get_app_option_value -name em.net_delta_temperature to retrieve the current
value. Use set_app_options -as_user_default {em.net_delta_temperature value} to set
the new value. Use report_app_options to show the value of multiple application options.
SEE ALSO
set_app_options(2)
em.net_delta_temperature
162
em.net_duration_condition_for_peak
Define the duration value for signal EM PEAK current checking.
TYPE
float
DEFAULT
0.0
DESCRIPTION
This application option define the duration value for signal EM PEAK current checking. The
PEAK current is defined as the maximum current value of current waveform. The PEAK_DC
current is defined as PEAK current multiplied by square root of duty ratio. By default,
PEAK_DC current is used to check against with limit. When the option is set, PEAK current
is used if the computed duration is not less than the condition, otherwise PEAK_DC current
is used.
Use get_app_option_value -design $design -name
em.net_duration_condition_for_peak to get the current value of this application option on
a specific design.
Use get_app_option_value -name em.net_duration_condition_for_peak to retrieve the
current value. Use set_app_options -as_user_default
{em.net_duration_condition_for_peak value} to set the new value. Use
report_app_options to show the value of multiple application options.
SEE ALSO
set_app_options(2)
Chapter 1:
em.net_duration_condition_for_peak
163
1-163
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
em.net_global_rms_relaxation_factor
Define the global relaxation factor on signal EM RMS limit.
TYPE
float
DEFAULT
1.0
DESCRIPTION
This application option define the global relaxation factor on signal EM RMS limit. The RMS
current limit from constraints file is multiplied by the relaxation factor as the real limit. By
default, there is no relaxation.
em.net_global_rms_relaxation_factor to get the current value of this application option on
a specific design.
Use get_app_option_value -name em.net_global_rms_relaxation_factor to retrieve the
{em.net_global_rms_relaxation_factor value} to set the new value. Use
SEE ALSO
set_app_options(2)
em.net_global_rms_relaxation_factor
164
em.net_min_duty_ratio
Define the minimum duty ratio value used in signal EM PEAK_DC current calculation.
TYPE
float
DEFAULT
0.0
DESCRIPTION
This application option define the minimum duty ratio value used in signal EM PEAK_DC
current calculation. Duty ratio is defined as duration divided by period. If the computed duty
ratio value is not less than the minimum value, the computed value is used. If the computed
duty ratio value is smaller than the minimum value, the minimum value is used. By default,
the computed duty ratio is used.
Use get_app_option_value -design $design -name em.net_min_duty_ratio to get the
current value of this application option on a specific design.
Use get_app_option_value -name em.net_min_duty_ratio to retrieve the current value.
Use set_app_options -as_user_default {em.net_min_duty_ratio value} to set the new
value. Use report_app_options to show the value of multiple application options.
SEE ALSO
set_app_options(2)
Chapter 1:
em.net_min_duty_ratio
165
1-165
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
em.net_use_waveform_duration
Define the duration used in signal EM PEAK_DC current calculation.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option controls which duration is used in signal EM PEAK_DC current
calculation. There are two duration definition, current integral based or current waveform
based. By default, the current integral based duration is used and it is defined as the integral
of current in one period divided by the current peak value. When set to "true", the current
waveform based duration is used and it is defined as the time range of half peak points on
the current waveform.
Use get_app_option_value -design $design -name em.net_use_waveform_duration to
get the current value of this application option on a specific design.
Use get_app_option_value -name em.net_use_waveform_duration to retrieve the
{em.net_use_waveform_duration true|false} to set the new value. Use
SEE ALSO
set_app_options(2)
em.net_use_waveform_duration
166
em.net_violation_rule_types
Specify the types of signal EM rules used in signal EM analysis violation checking.
TYPE
string
DEFAULT
auto
DESCRIPTION
This application option specifies the types of signal EM rules used in signal EM analysis
violation checking. There are three types of rules supported in signal EM analysis, avg/rms/
peak. Any combination of rule types could be specified. If it's set as auto, signal EM analysis
checks the current for which constraints are given. Auto is the default behavior. Application
options are set using the set_app_options command, and they may be specified globally
or with respect to a design.
Use get_app_option_value -design $design -name em.net_violation_rule_types to get
the current value of this application option on a specific design.
Use get_app_option_value -name em.net_violation_rule_types to retrieve the current
value. Use set_app_options -as_user_default {em.net_violation_rule_types value} to
set the new value. Use report_app_options to show the value of multiple application
options.
SEE ALSO
set_app_options(2)
Chapter 1:
em.net_violation_rule_types
167
1-167
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
ems_check_attributes
Description of the predefined attributes for ems_check attributes.
DESCRIPTION
ems_check attributes are provided in the subsections that follow.
command.
ems_check command.
ems_check Attributes:
current_definition
A string attribute representing the current check - or a group of checks performed by using
the ems_check.
default_definition
A string attribute representing the default setting of check/s performed by using the
ems_check. Be aware that user defined checks don't have default_definitions.
enabled
A boolean attribute representing the curent enable status of the check. This is a settable
attribute.
full_name
A string attribute for the full name of the ems_check. This attribute is assensial for
get_object_name command.
168
group_members_count
A string (number) attribute describes the number of members in the group. If the design
check is defined as a check, this number is 0. If the design check is defined as a group, this
number is higher then 0.
group_name
A string attribute describes the group name. If the design check is defined as a check, this
attribute is empty. If the design check is defined as a group, this attribute gives the group
name.
help_info
A string attribute describes what is the check doing.
is_default
A boolean attribute representing the current status of the command. If the default settings of
the design check remains, it returns true. If the default settings Overridden by user settings
it returns false.
is_group_member
A boolean attribute describes a check membership in a group of checks. If the design check
is not a member in a group of checks, it returns false. If the design check is a member in a
group of checks, it returns true.
is_group_name
A boolean attribute describes if a design check is defined as group. If the design check is
defined as a check, it returns false. If the design check is defined as a group, it returns true.
name
A string attribute for the name of the ems_check.
object_class
A string attribute discribes the check design class which is "ems_check".
Chapter 1:
169
1-169
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_design_checks(2)
get_attribute(2)
list_attributes(2)
get_object_name(2)
set_attribute(2)
170
ems_database_attributes
Description of the predefined attributes for ems_database.
DESCRIPTION
Attributes are properties assigned to objects such as ems rules, messages, groups,and
database. Definitions for ems_database attributes are provided in the subsections that
follow.
command.
ems_database command.
ems_database Attributes:
filename
A string attribute to represent the location the EMS database is stored.
full_name
A string attribute to represent the full path of the EMS database name.
msg_count
A string attribute to represent the total number of message the database stores.
name
A string attribute to represent the name of the EMS database.
object_class
A string attribute with the value of "ems_database".
Chapter 1:
171
1-171
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
ems_rule_attributes(2)
ems_message_attributes(2)
ems_group_attributes(2)
get_attribute(2)
list_attributes(2)
get_object_name(2)
set_attribute(2)
172
ems_group_attributes
Description of the predefined attributes for ems_group.
DESCRIPTION
Attributes are properties assigned to objects such as ems rule, message, group and
database. Definitions for ems_group attributes are provided in the subsections that follow.
command.
ems_group command.
ems_group Attributes:
full_name
A string attribute to represent full name of the group.
grouping
A string attribute to identify the parameters to have "grouping" function. "grouping" is an
EMS display feature. User can identify the parameter that messages be arranged and
displayed by it.
messages
A collection attribute to represent sequences of the messages under the group .
name
A string attribute to represent the name of the group.
object_class
A string attribute with the value of "ems_group".
Chapter 1:
173
1-173
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
parameters
A string attribute to represent the parameters defined on the group. These parameters are
the common parameters among those rules which belong to this group.
rules
A collection attribute to represent the rules belong to the group.
visible
A string attribute to identify the parameters to have "visible" function. "visible" is an EMS
display feature. User can identify parameters that their value be displayed in separate
columns and be able to sort if needed.
SEE ALSO
ems_database_attribute(2)
ems_message_attribute(2)
ems_rule_attribute(2)
get_attribute(2)
list_attributes(2)
get_object_name(2)
set_attribute(2)
174
ems_message_attributes
Description of the predefined attributes for ems_message.
DESCRIPTION
Attributes are properties assigned to objects such as ems rule, group, message and
database. Definitions for ems_message attributes are provided in the subsections that
follow.
command.
ems_message command.
ems_message Attributes:
detail
A string attribute to represent the detail(html) information of the message.
full_name
A string attribute to represent the full path name of the message.
name
A string attribute to represent the name of the message. sequence number is used to
represent the name of the message.
object_class
A string attribute with the value of "ems_message".
rule
A collection attribute to represent all rules through those the message generated.
Chapter 1:
175
1-175
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
rule_name
A string attribute to represent the rule name the message generated.
solution
A string attribute to represent the solution to fix the problem the message identified.
status
A string attribute to specify the message status. The status can be active, waive or fixed.
This is a settable attribute.
summary
A string attribute to represent the summary, message type and content, of the message.
values
A string attribute to represent all parameters and their values of the message.
SEE ALSO
ems_rule_attribute(2)
ems_group_attribute(2)
get_attribute(2)
list_attributes(2)
get_object_name(2)
set_attribute(2)
176
ems_rule_attributes
Description of the predefined attributes for ems_rule.
DESCRIPTION
Attributes are properties assigned to objects such as ems rules, database, groups and
messages. Definitions for ems_rule attributes are provided in the subsections that follow.
command.
ems_rule command.
ems_rule Attributes:
enabled
A boolean attribute to specify the rule status. If "False" - "disabled", messages of the rule
wont be created. This is a settable attribute.
full_name
A string attribute returns the full name of a rule.
group
A collection attribute to represent the name of the group which the rule belongs to.
group_name
A string attribute to repesent the name of the group which the rule belongs to.
max_count
A string attribute to specify the maximum count, the number of rule message to be
displayed. This is a settable attribute. If nothing has been set, the value is "-1".
Chapter 1:
ems_rule_attributes
177
1-177
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
message_count
A string attribute to represent the total number of messages the rule generated.
messages
A collection attribute to represent sequences of all messages generated under the rule.
name
A string attribute to represent the name of the rule.
object_class
A string attribute with the value of "ems_rule".
parameters
A string attribute to specify the parameters defined on the rule.
type
A string attribute to specify the rule type. The type can be information, warning or error.
verbose
A boolean attribute to specify how message info like to be displayed. This is a settable
attribute. If verbose set to "true" message will be displayed on both GUI and log file.
Otherwise the message only be displayed on GUI.
SEE ALSO
ems_message_attribute(2)
ems_group_attribute(2)
get_attribute(2)
list_attributes(2)
get_object_name(2)
set_attribute(2)
ems_rule_attributes
178
exception_attributes
Lists the predefined attributes for exception objects.
DESCRIPTION
Attributes are properties assigned to objects. Definitions for exception attributes are
by the application.
Exception Attributes
command_text
exception_type
A string attribute indicating the type of exception. Valid values are "false_path",
"multicycle_path", and "max_min_delay".
file_line_info
full_name
A string attribute returning a unique name for the exception.
group_count
An int attribute specifying the number of groups in the exception.
Chapter 1:
179
1-179
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
has_from
A boolean attribute; true if the exception has a -from group.
has_through
A boolean attribute; true if the exception has a -through group.
has_to
A boolean attribute; true if the exception has a -to group.
hold_fall_end
A boolean attribute; true if the exception is multicycle and the hold fall multiplier is relative to
the end clock.
hold_fall_multiplier
An int attribute for multicycle_path exceptions, specifying the multiplier value for hold fall.
hold_rise_end
A boolean attribute; true if the exception is multicycle and the hold rise multiplier is relative
to the end clock.
hold_rise_multiplier
An int attribute for multicycle_path exceptions, specifying the multiplier value for hold rise.
is_hold_fall_false
A boolean attribute; true if the exception is false_path, and the hold fall timing is set to be
false.
is_hold_rise_false
A boolean attribute; true if the exception is false_path, and the hold rise timing is set to be
false.
is_setup_fall_false
A boolean attribute; true if the exception is false_path, and the setup fall timing is set to be
false.
180
is_setup_rise_false
A boolean attribute; true if the exception is false_path, and the setup rise timing is set to be
false.
max_fall_delay
A float attribute for max_min_delay exceptions. Specifies the delay value for max_fall.
max_rise_delay
A float attribute for max_min_delay exceptions. Specifies the delay value for max_rise.
min_fall_delay
A float attribute for max_min_delay exceptions. Specifies the delay value for min_fall.
min_rise_delay
A float attribute for max_min_delay exceptions. Specifies the delay value for min_rise.
object_class
A string attribute, with the value "exception".
setup_fall_multiplier
An int attribute for multicycle_path exceptions, specifying the multiplier value for setup fall.
setup_fall_start
A boolean attribute; true if the exception is multicycle and the setup fall multiplier is relative
to the start clock.
setup_rise_multiplier
An int attribute for multicycle_path exceptions, specifying the multiplier value for setup rise.
setup_rise_start
A boolean attribute; true if the exception is multicycle and the setup rise multiplier is relative
to the start clock.
Chapter 1:
181
1-181
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
through_group_count
An int attribute specifying the number of -through, -rise_through, and/or -fall_through
options that were specified with the exception command. For example, if the exception was
specified as "-through {a1 a2 a3} -rise_through {b1 b2 b3}", the through_group_count
attribute value will be 2.
SEE ALSO
get_exceptions(2)
get_attribute(2)
list_attributes(2)
report_exceptions(2)
set_false_path(2)
set_max_delay(2)
set_min_delay(2)
set_multicycle_path(2)
182
exception_group_attributes
Lists the predefined attributes for exception_group objects.
DESCRIPTION
Attributes are properties assigned to objects. Definitions for exception_group attributes are
by the application.
Exception Group Attributes
edge
A string attribute, gives the edge type of the from/through/to group. It can be one of "rise",
"fall", or "both.
exception_object
A collection type attribute containing exactly one exception. This exception is the one which
contains this exception_object.
full_name
A string attribute returning the type of from/through/to group. It can return one of "from",
"rise_from", "fall_from", ... "rise_to" or "fall_to".
has_clock
A boolean attribute, which is true if the this from/through/to group contains a clock.
object_class
A string attribute, with the value "exception_group".
Chapter 1:
183
1-183
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
objects
A collection attribute containing heterogenous objects of the type pins, ports and/or clocks.
This returns all the objects which are in this exception_group object.
type
A string attribute returning the type of group. It can return one of "from", "to" or "through".
SEE ALSO
get_exceptions(2)
get_exception_groups(2)
get_attribute(2)
list_attributes(2)
184
extract.connect_open
To force resistance-network builder to do dummy connecting when it is open.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this option is set to its default of false, the open resistance-network will keep open.
When you set this option to true, resistance-network builder will create dummy resistances
among separate graphs of open network and make it fully connected.
This option works for CTO/GR/DR extraction when it uses real geometry to build
resistance-network. And it expects the original open resistance-network to have internal
nodes for dummy connection, otherwise it will keep open.
SEE ALSO
write_parasitics(2)
Chapter 1:
extract.connect_open
185
1-185
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
extract.enable_coupling_cap
Enable coupling capacitance calculation in detail-route extraction.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this option is set to its default of false, coupling capacitance extraction is not
performed.
When you set this option to true, coupling capacitance will be extracted in detail route
extraction.
GR/CTO/VR extraction will not handle with coupling capacitance even this option is on.
SEE ALSO
write_parasitics(2)
extract.enable_coupling_cap
186
extract.high_fanout_threshold
Threshold for high fanout net extraction.
TYPE
int
DEFAULT
1000
DESCRIPTION
When a net's number of pin is bigger than this threshod, its extraction will be skipped.
when it's less than this threshold, extractraction will be performed on it.
SEE ALSO
write_parasitics(2)
Chapter 1:
extract.high_fanout_threshold
187
1-187
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
file.def.non_default_width_wiring_to_net
Controls whether the write_def command writes nets with nondefault width to the DEF
NETS section or SPECIALNETS section.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
Controls whether the write_def command writes nets with nondefault width to the DEF
NETS section or SPECIALNETS section.
By default (false), the write_def command writes nets with nondefault width to the
SPECIALNETS section.
If you set the variable to true, the write_def command creates a nondefault routing rule
named SNPS_DefGenNDR_<n> for each nondefault width, and then writes the nets with
nondefault width to the DEF NETS section with a NONDEFAULTRULE statement for single
nondefault width and TAPERRULE statements for multiple nondefault widths, which makes
the output DEF file less dependent on the user-specified nondefault routing rules.
The read_def command creates a nondefault routing rule in the design cell if it finds a
definition in the NONDEFAULTRULES section, unless its prefix is SNPS_DefGenNDR_<n>.
SEE ALSO
read_def(2)
write_def(2)
create_routing_rule(2)
file.def.non_default_width_wiring_to_net
188
file.gds.contact_prefix
Used by "write_gds" command to prefix the contact via names to be written as Structures
into the GDSII file.
TYPE
string
DEFAULT
$$
DESCRIPTION
This option set the prefix to be used in the name when the contact via name is to be written
as Structures into the GDSII file. The default value for the prefix to be used is $$.
EXAMPLES
The following example defines the contact prefix to be used for naming the contact via
Structures in the output GDSII file.
prompt> set_app_options -name "file.gds.contact_prefix" -value "PREFIX_"
SEE ALSO
write_gds(2)
set_app_options(2)
Chapter 1:
file.gds.contact_prefix
189
1-189
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
file.gds.create_custom_via
Used by "read_gds" and "trace_connectivity" commands in icc2_lm_shell to enable or
disable creation of custom vias from the cut shapes read from the input GDSII file.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This option enables or disables creating custom vias from cut geometries by the read_gds
and trace_connectivity commands. The default behavior is to retain the cut geometries in
the input GDSIII file as cut shapes. This option can be used to retain the input cut
geomertries as cut shapes only or generate custom vias. This option will not be required to
be enabled in most general cases, so this option should be set only in most rare cases.
The default value is false and hence generates cut shapes from cut layer geometries. You
must set this option before running the read_gds or trace_connectivity commands.
EXAMPLES
The following example enables the creation of custom via from the cut shapes during GDSII
import and the connectivity tracing and convert them to custom via.
prompt> set_app_options -name "file.gds.create_custom_via true" -value
true
SEE ALSO
read_gds(2)
trace_connectivity(2)
190
set_app_options(2)
Chapter 1:
191
1-191
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
file.gds.exclude_layers
Specifies the rules for mapping between the input layers and the layers which are to be used
for excluding geometries from the specified input layers.
TYPE
list
DEFAULT
null
DESCRIPTION
This option specifies the mapping between input layers and other layers which are to be
used for exclusion. The geometries in the other layers are subtracted from same colored
geometries of the input layer during the read_gds and trace_connectivity commands.
The tool uses the geometries in a specfic color of the mapped layers to subtract same
colored geometries from the input layers. Multiple mapping between the same input layer
and exclude layers can be specified. The exclusions works by subtracting geometries of the
same color using relationship specified in the mapping.
You must set this option before running the read_gds or trace_connectivity commands.
You can specify the mapping for one or more input layers and excluded layers and color.
The syntax used to specify each mapping is
{ {metal_layer1:ppurpose1 exclude_layer1[:exclude_purpose1][:mask_name]}
{metal_layer2:purpose2
exclude_layer2[:exclude_purpose2][:mask_name]}... }
.in -0.25in
You specify the layer names and purpose to be excluded from input layer names and
purpose by using the information in the technology file.
EXAMPLES
The following example defines the exclude layers mapping for the M1 and M2 metal layers.
192
In the example below, mask_one of M1 will be subtracted by the mask_one geometries of

EM1. And if layer M2 has two mask, mask_one geometries of layer M2 will be subtracted by
the mask_one geometries of EM2. mask_two of EM2 will remove geomtries occupied by the
mask_two of M2. Layers EM1 and EM2 will not be modified. Only input layers M1 and M2
will change.
prompt> set_app_options -name "file.gds.exclude_layers" -value {
EM1:mask_one} {M2 EM2} }
{M1
SEE ALSO
read_gds(2)
set_app_options(2)
Chapter 1:
193
1-193
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
file.gds.port_type_map
Used by the "read_gds" and "trace_connectivity" commands in icc2_lm_shell to identify
port types correctly
TYPE
list_of_pairs
DEFAULT
null
DESCRIPTION
This option is used to specify the mapping between port type and port name.This map is
used in commands like read_gds and trace_connectivity to correctly identify the port type.
This option shall be set before calling read_gds or trace_connectivity commands. The first
element in the value pair is the port type and the second element in the pair is the name of
the port name to be matched. One port type can be used with multiple port names.
The following are the port types supported now.
power
ground
pwell
nwell
EXAMPLES
The following example shows how the application option is to be set
prompt> set_app_options {file.gds.port_type_map {{power VDD} {ground
VSS}}}
194
SEE ALSO
read_gds(2)
set_app_options(2)
Chapter 1:
195
1-195
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
file.gds.rotate_pin_text_by_access_direction
Used by "write_gds" command to enable or disable controlling of the rotation of the TEXT
object when the pin object is written into the GDSII file.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This option enables or disables controlling of the value of the ANGLE token in the TEXT
object of a pin during the write_gds flow. If this app-option is enabled, then the value of the
ANGLE token will be dependent on the access-direction flags on the pin object. If the
access-direction flags has left or right direction set then a value of R0 will be used as the
TEXT object's orientation. In other cases a value of R90 will be used as the TEXT object's
orientation.
By default this option is disabled and the TEXT objects are always written with an orientation
value of R0.
EXAMPLES
The following example defines that the rotation of the TEXT object of the pin should be
controlled by the access direction flags set on the pin.
prompt> set_app_options {file.gds.rotate_pin_text_by_access_direction
true}
SEE ALSO
write_gds(2)
set_app_options(2)
196
Chapter 1:
197
1-197
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
file.gds.text_all_pins
Used by "write_gds" command to write the text for all pins of the port into the GDSII file.
TYPE
bool
DEFAULT
false
DESCRIPTION
This option set the value such that text for each pins of the port are written into the GDSII
file. The default behavior is to write a single text for all pins of the port.
EXAMPLES
The following example specifies that the text for each pins of the port are to be written into
the output GDSII file.
prompt> set_app_options -name "file.gds.text_all_pins" -value true
SEE ALSO
write_gds(2)
set_app_options(2)
file.gds.text_all_pins
198
file.gds.text_layer_map
Specifies the mapping between metal layers and text layers that is used for tracing ports.
TYPE
list
DEFAULT
null
DESCRIPTION
This option specifies the mapping between metal layers and text layers that is used for
tracing ports by the read_gds and trace_connectivity commands.
The tool uses the text labels in a GDSII file to associate metal shapes with a net or pin and
then traces the connectivity of the labeled metal shapes to identify additional metal shapes
associated with that net or pin. If the text for a port is not on the same layer as the metal
shape, you must set this option to specify the layer mapping so the tool can correctly identify
the ports. You must set this option before running the read_gds or trace_connectivity
commands.
You can specify the mapping for one or more metal layers. The syntax used to specify each
mapping is
{metal_layer {text_layer1[:data_type1] text_layer2[:data_type2] ...}}
You specify the layer names and data type numbers by using the information in the
technology file.
EXAMPLES
The following example defines the text layer mapping for the M1 and M2 metal layers.
prompt> set_app_options { file.gds.text_layer_map { {M1 M1PIN} {M2 M2PIN}
}
Chapter 1:
199
1-199
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
read_gds(2)
set_app_options(2)
200
file.gds.trace_unmapped_text
Used by "read_gds" and "trace_connectivity" command in icc2_lm_shell to enable or
disable tracing on all routing layers for the texts not mapped to any routing layers.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This option enables or disables tracing on all routing layers for text labels not mapped to a
routing layer by the read_gds and trace_connectivity commands. The default behavior is
to ignore use of such text labels for identification of pins. This option will be required to be
enabled in most rare cases, so this option should be disabled in most cases.
The tool uses the text labels in a GDSII file to associate metal shapes with a net or pin and
shape, you must set the option file.gds.text_layer_map to specify the layer mapping so the
tool can correctly identify the ports. In some rare cases only, you may need to set this option
to make the tool identify pin geomtries on all routing layers for such unmapped text labels.
So normally this option should be used to disable the setting to trace for unmapped texts.
You must set this option before running the read_gds or trace_connectivity commands.
EXAMPLES
The following example defines that tracing should be enabled for all texts not mapped to the
routing layers.
prompt> set_app_options { file.gds.trace_unmapped_text true}
SEE ALSO
Chapter 1:
201
1-201
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
read_gds(2)
file.gds.text_layer_map(3)
set_app_options(2)
202
file.lef.auto_rename_conflict_sites
Specifies whether to automatically rename a conflict site definition.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
A conflict site definition means a same name site definition exists with different size. The
conflict site definition is usually an error condition (LEFR-018) and will cause read_lef to fail.
However, if file.lef.auto_rename_conflict_sites is set to true, an attempt to rename the
site definition will be tried. The renamed site definition will have a name like
<lefFileName>.<siteName>. Here, <lefFileName> is the base name of the LEF file that is
reading; <siteName> is the conflict site definition name. If <lefFileName>.<siteName> also
exists, then <lefFileName>.<siteName>_0, <lefFileName>.<siteName>_1, ... will be tried.
When a proper site definition name is found, the conflict site definition will be created using
this new name and LEFR-026 will be reported.
After reading all data in the LEF file, if the renamed site definition has never been refered by
any macros, then the site definition will be removed, and message LEFR-038 will be
reported.
Since there is possible that renamed site definition will be removed eventually, LEFR-039
will be reported when file.lef.auto_rename_conflict_sites is set to true.
SEE ALSO
LEFR-018(n)
LEFR-026(n)
LEFR-038(n)
LEFR-039(n)
read_lef(2)
Chapter 1:
203
1-203
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
set_app_options(2)
204
file.lef.non_real_cut_obs_mode
Specifies whether to distinguish non-real cut routing blockages from regular cut routing
blockages of lef cut obstructions.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
When this app option is true, the read_lef command will set a lef cut obstruction as
zero-spacing if it does not have SPACING and DESIGNRULEWIDTH syntax and meets any
of the following conditions:
is not rectangular
the width and height attributes does not match any of the following values
the minimum width of the layer
the default width of the layer
the values in cutHeightTbl and cutWidthTbl of the layer
the values of cut size of any simple via definitions of the layer
SEE ALSO
read_lef(2)
set_app_options(2)
Chapter 1:
file.lef.non_real_cut_obs_mode
205
1-205
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
file.lef.output_non_real_blockages
Specifies whether to output non-real blockages from write_lef.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This app option, if set to true, indicates that the write_lef command will output non-real
blockages. Following types of blockages are non-real blockages:
the is_zero_spacing attribute is true
converted from IC Compiler no-signal route guides or system layer blockages
This app option, if set to false (default), indicates that the write_lef command will not
output non-real blockages.
SEE ALSO
write_lef(2)
set_app_options(2)
file.lef.output_non_real_blockages
206
file.lib.setup_file_name
Specifies the name of a setup file which read_lib uses to control Library Compiler.
TYPE
String
DEFAULT
Empty
DESCRIPTION
This application option specifies the name of a setup file which will be used by Library
Compiler when read_lib calls it. The content of this setup file is very restricted. It can contain
set commands, blank lines, or comment lines. The file is used to enable or disable specific
features in Library Compiler.
EXAMPLE
If you wanted deprecated Liberty features to signal an error from read_lib you could create
a file, called read_lib.setup, with this content:
# Make sure we don't use any deprecated features
set sh_deprecated_is_error true
Then, in the library manager, set our app option to point at the setup file:
# Make sure we don't use any deprecated features
set_app_options -name file.lib.setup_file_name -value /path/
read_lib.setup
SEE ALSO
read_lib(2)
set_app_options(2)
Chapter 1:
file.lib.setup_file_name
207
1-207
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
file.oasis.contact_prefix
Used by "write_oasis" command to prefix the contact via names to be written as Structures
into the OASIS file.
TYPE
string
DEFAULT
$$
DESCRIPTION
This option set the prefix to be used in the name when the contact via name is to be written
as Structures into the OASIS file. The default value for the prefix to be used is $$.
EXAMPLES
The following example defines the contact prefix to be used for naming the contact via
Structures in the output OASIS file.
prompt> set_app_options -name "file.oasis.contact_prefix" -value
"PREFIX_"
SEE ALSO
write_oasis(2)
set_app_options(2)
file.oasis.contact_prefix
208
file.oasis.create_custom_via
Used by "read_oasis" commands in icc2_lm_shell to enable or disable creation of custom
vias from the cut shapes read from the input OASIS file.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This option enables or disables creating custom vias from cut geometries by the read_oasis
command. The default behavior is to retain the cut geometries in the input OASIS file as cut
shapes. This option can be used to retain the input cut geomertries as cut shapes only or
generate custom vias. This option will not be required to be enabled in most general cases,
so this option should be set only in most rare cases.
The default value is false and hence generates cut shapes from cut layer geometries. You
must set this option before running the read_oasis command.
EXAMPLES
The following example enables the creation of custom via from the cut shapes during OASIS
import and the connectivity tracing and convert them to custom via.
prompt> set_app_options -name "file.oasis.create_custom_via true" -value
true
SEE ALSO
read_oasis(2)
set_app_options(2)
Chapter 1:
209
1-209
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
210
file.oasis.exclude_layers
Specifies the rules for mapping between the input layers and the layers which are to be used
for excluding geometries from the specified input layers.
TYPE
list
DEFAULT
null
DESCRIPTION
This option specifies the mapping between input layers and other layers which are to be
used for exclusion. The geometries in the other layers are subtracted from same colored
geometries of the input layer during the read_oasis command.
The tool uses the geometries in a specfic color of the mapped layers to subtract same
colored geometries from the input layers. Multiple mapping between the same input layer
and exclude layers can be specified. The exclusions works by subtracting geometries of the
same color using relationship specified in the mapping.
You must set this option before running the read_oasis command.
You can specify the mapping for one or more input layers and excluded layers and color.
The syntax used to specify each mapping is
{ {metal_layer1:ppurpose1 exclude_layer1[:exclude_purpose1][:mask_name]}
{metal_layer2:purpose2
exclude_layer2[:exclude_purpose2][:mask_name]}... }
.in -0.25in
You specify the layer names and purpose to be excluded from input layer names and
purpose by using the information in the technology file.
EXAMPLES
The following example defines the exclude layers mapping for the M1 and M2 metal layers.
Chapter 1:
211
1-211
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
In the example below, mask_one of M1 will be subtracted by the mask_one geometries of

EM1. And if layer M2 has two mask, mask_one geometries of layer M2 will be subtracted by
the mask_one geometries of EM2. mask_two of EM2 will remove geomtries occupied by the
mask_two of M2. Layers EM1 and EM2 will not be modified. Only input layers M1 and M2
will change.
prompt> set_app_options -name "file.oasis.exclude_layers" -value {
EM1:mask_one} {M2 EM2} }
{M1
SEE ALSO
read_oasis(2)
set_app_options(2)
212
file.oasis.port_type_map
Used by the "read_oasis" command in icc2_lm_shell to identify port types correctly
TYPE
list_of_pairs
DEFAULT
null
DESCRIPTION
This option is used to specify the mapping between port type and port name.This map is
used in command read_oasis to correctly identify the port type. This option shall be set
before calling read_oasis command. The first element in the value pair is the port type and
the second element in the pair is the name of the port name to be matched. One port type
can be used with multiple port names.
The following are the port types supported now.
power
ground
pwell
nwell
EXAMPLES
The following example shows how the application option is to be set
prompt> set_app_options {file.oasis.port_type_map {{power VDD} {ground
VSS}}}
Chapter 1:
213
1-213
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
read_oasis(2)
set_app_options(2)
214
file.oasis.rotate_pin_text_by_access_direction
Used by "write_oasis" command to enable or disable controlling of the rotation of the TEXT
object when the pin object is written into the OASIS file.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This option enables or disables controlling of the value of the ANGLE token in the TEXT
object of a pin during the write_oasis flow. If this app-option is enabled, then the value of
the ANGLE token will be dependent on the access-direction flags on the pin object. If the
access-direction flags has left or right direction set then a value of R0 will be used as the
TEXT object's orientation. In other cases a value of R90 will be used as the TEXT object's
orientation.
By default this option is disabled and the TEXT objects are always written with an orientation
value of R0.
EXAMPLES
The following example defines that the rotation of the TEXT object of the pin should be
controlled by the access direction flags set on the pin.
prompt> set_app_options {file.oasis.rotate_pin_text_by_access_direction
true}
SEE ALSO
write_oasis(2)
set_app_options(2)
Chapter 1:
215
1-215
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
216
file.oasis.text_all_pins
Used by "write_oasis" command to write the text for all pins of the port into the OASIS file.
TYPE
bool
DEFAULT
false
DESCRIPTION
This option set the value such that text for each pins of the port are written into the OASIS
file. The default behavior is to write a single text for all pins of the port.
EXAMPLES
The following example specifies that the text for each pins of the port are to be written into
the output OASIS file.
prompt> set_app_options -name "file.oasis.text_all_pins" -value true
SEE ALSO
write_oasis(2)
set_app_options(2)
Chapter 1:
file.oasis.text_all_pins
217
1-217
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
file.oasis.text_layer_map
Specifies the mapping between metal layers and text layers that is used for tracing ports.
TYPE
list
DEFAULT
null
DESCRIPTION
This option specifies the mapping between metal layers and text layers that is used for
tracing ports by the read_oasis command.
The tool uses the text labels in a OASIS file to associate metal shapes with a net or pin and
shape, you must set this option to specify the layer mapping so the tool can correctly identify
the ports. You must set this option before running the read_oasis command.
You can specify the mapping for one or more metal layers. The syntax used to specify each
mapping is
{metal_layer {text_layer1[:data_type1] text_layer2[:data_type2] ...}}
You specify the layer names and data type numbers by using the information in the
technology file.
EXAMPLES
The following example defines the text layer mapping for the M1 and M2 metal layers.
prompt> set_app_options { file.oasis.text_layer_map { {M1 M1PIN} {M2
M2PIN} }
218
SEE ALSO
read_oasis(2)
set_app_options(2)
Chapter 1:
219
1-219
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
file.oasis.trace_unmapped_text
Used by "read_oasis" command in icc2_lm_shell to enable or disable tracing on all
routing layers for the texts not mapped to any routing layers.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This option enables or disables tracing on all routing layers for text labels not mapped to a
routing layer by the read_oasis and command. The default behavior is to ignore use of such
text labels for identification of pins. This option will be required to be enabled in most rare
cases, so this option should be disabled in most cases.
The tool uses the text labels in a OASIS file to associate metal shapes with a net or pin and
shape, you must set the option file.oasis.text_layer_map to specify the layer mapping so
the tool can correctly identify the ports. In some rare cases only, you may need to set this
option to make the tool identify pin geomtries on all routing layers for such unmapped text
labels. So normally this option should be used to disable the setting to trace for unmapped
texts. You must set this option before running the read_oasis command.
EXAMPLES
The following example defines that tracing should be enabled for all texts not mapped to the
routing layers.
prompt> set_app_options { file.oasis.trace_unmapped_text true}
SEE ALSO
220
read_oasis(2)
file.oasis.text_layer_map(3)
set_app_options(2)
Chapter 1:
221
1-221
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
file.verilog.default_user_label
Specifies the user label in which to create the block.
TYPE
string
DEFAULT
""
DESCRIPTION
This application option specifies the user label in which to create the block.
When this option is set to a non-empty string, the Verilog reader creates the block in the
specified user label. When set to an empty string, the Verilog reader creates the block in the
default, unnamed label.
To determine the current value of this application option, use the get_app_option_value
-name file.verilog.default_user_label command. For a list of all verilog application options
and their current values, use the report_app_options file.verilog.* command.
SEE ALSO
get_app_options(2)
set_app_option(2)
read_verilog_outline(2)
read_verilog(2)
file.verilog.default_user_label
222
file.verilog.enable_vpp
Enables or disables preprocessing of Verilog files by the Verilog preprocessor.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option enables or disables preprocessing of Verilog files by the Verilog
preprocessor. It is used only by the native Verilog reader.
When true, before the Verilog reader reads a Verilog file, the Verilog preprocessor scans for
and expands the Verilog preprocessor directives `define, ùndef, ìnclude, ìfdef, èlse, and
èndif. Intermediate files from the preprocessor are created in the directory specified by the
icc2_tmp_dir variable. Also, the ìnclude directive uses the search_path to find files.
Very few structural Verilog files use preprocessor directives. Set this variable to true only if
your Verilog file contains directives that require the preprocessor. Without the preprocessor,
the native Verilog reader does not recognize these directives.
-name file.verilog.enable_vpp command. For a list of all verilog application options and
their current values, use the report_app_options file.verilog.* command.
SEE ALSO
get_app_options(2)
set_app_option(2)
read_verilog(2)
Chapter 1:
file.verilog.enable_vpp
223
1-223
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
file.verilog.keep_unconnected_cells
Controls whether the Verilog reader keeps unconnected cells in the netlist.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option controls whether the Verilog reader keeps unconnected cells in the
netlist. It is used only by the native Verilog reader.
When false, if no instances of a certain reference have connections, those cell instances are
discarded. This saves memory by not representing cells that have no impact on the timing
of the design, such as metal fill cells. When true, such cells are preserved.
-name file.verilog.keep_unconnected_cells command. For a list of all verilog application
options and their current values, use the report_app_options file.verilog.* command.
SEE ALSO
get_app_options(2)
set_app_option(2)
read_verilog(2)
file.verilog.keep_unconnected_cells
224
file.verilog.keep_unconnected_nets
Controls whether the Verilog reader keeps unconnected nets in the netlist.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option controls whether the Verilog reader keeps unconnected nets in the
netlist. It is used only by the native Verilog reader.
When true (the default), unconnected nets are preserved. When false, unconnected nets
are discarded.
-name file.verilog.keep_unconnected_nets command. For a list of all verilog application
SEE ALSO
get_app_options(2)
set_app_option(2)
read_verilog(2)
Chapter 1:
file.verilog.keep_unconnected_nets
225
1-225
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
file.verilog.write_non_pg_net_assigns
Controls whether the Verilog writer outputs extra assign statements for renamed signal, tie,
and clock nets, so that their original names are retained in the Verilog output.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option, if set to true, causes the Verilog writer to output extra assign
statements for renamed signal, tie, and clock nets, so that their original names are retained
in the Verilog output. If set to false, the extra assign statements are omitted and the original
net names are not retained in the Verilog netlist.
This application option affects each net that is named differently from its port. In the Verilog
language, the port and pins of a net are connected together by an implicit net. This net is
implicitly named to match one of its ports. So when writing Verilog, a net name is implicitly
renamed to its connected port's name, and thus the original net name is not retained in the
Verilog output. The netlist is valid. However to retain the original net name, an assign
statement is necessary to assign the original net name to the actual net name in the Verilog
output.
-name file.verilog.write_non_pg_net_assigns command. For a list of all verilog
application options and their current values, use the report_app_options file.verilog.*
command.
SEE ALSO
file.verilog.write_pg_net_assigns
get_app_options(2)
set_app_option(2)
read_verilog(2)
226
Chapter 1:
227
1-227
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
Controls whether the Verilog writer outputs extra assign statements for renamed power and
ground nets, so that their original names are retained in the Verilog output.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option, if set to true, causes the Verilog writer to output extra assign
statements for renamed power and ground nets, so that their original names are retained in
the Verilog output. If set to false, the extra assign statements are omitted and the original net
names are not retained in the Verilog netlist.
This application option affects each net that is named differently from its port. In the Verilog
language, the port and pins of a net are connected together by an implicit net. This net is
implicitly named to match one of its ports. So when writing Verilog, a net name is implicitly
renamed to its connected port's name, and thus the original net name is not retained in the
Verilog output. The netlist is valid. However to retain the original net name, an assign
statement is necessary to assign the original net name to the actual net name in the Verilog
output.
-name file.verilog.write_pg_net_assigns command. For a list of all verilog application
SEE ALSO
get_app_options(2)
set_app_option(2)
read_verilog(2)
228
fill_cell_attributes
Description of the predefined attributes for fill_cells.
DESCRIPTION
fill_cell attributes are provided in the subsections that follow.
command.
Fill_Cell Attributes
object_class
A string attribute with the value of "fill_cell". Each object class has a different object class
value.
is_arrayed
A boolean attribute specifying if the fill_cell is an array
origin
Origin of the fill_cell.
bbox
Bounding box of the fill_cell.
columns
An integer attribute that specifies the number of columns if fill_cell is an array.
Chapter 1:
229
1-229
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
rows
An integer attribute that specifies the number of rows if fill_cell is an array.
x_pitch
Horizontal pitch for array elements if fill_cell is an array.
y_pitch
Veritcal pitch for array elements if fill_cell is an array.
x_stagger
Horizontal stagger for array elements if fill_cell is an array.
y_stagger
Veritcal stagger for array elements if fill_cell is an array.
SEE ALSO
get_attribute(2)
list_attributes(2)
230
finfet.ignore_grid.std_cell
Used by various UI commands in icc2_shell to ignore or honor the FinFET grid by std cell,
site def, site row, site array and core area in the whole design or certain steps of the flow.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, the TCL UI commands like create_site_array, create_site_row,
initialize_floorplan etc. will ignore the FinFET grid for std cell, site def, site row, site array
and core area even if the FinFET grid is defined in the tech file. The default value is false.
The value will be set to true, when the user want to ignore the FinFET grid for std cell, site
def, site row, site array and core area in the whole design or certain steps of the flow.
SEE ALSO
check_finfet_grid(2)
initialize_floorplan(2)
create_site_row(2)
create_site_array(2)
set_app_options(2)
Chapter 1:
finfet.ignore_grid.std_cell
231
1-231
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
flip_chip.route.allow_rotated_via
Option for the RDL router commands. Specifies how to create NDR vias.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
When this option is true, the RDL router can create rotated NDR vias. When this option is
false, RDL router create the specified NDR vis only.
SEE ALSO
route_rdl_flip_chip(2)
set_app_options(2)
flip_chip.route.allow_rotated_via
232
flip_chip.route.connect_edge_center
Option for the RDL router commands. Specifies how to connect to Through-Silicon Vias
(TSVs) or bump cells.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this option is false, the RDL router might not connect to TSVs or bumps at the center
of an edge. When this option is true, RDL router is forced to connect to TSVs or bumps at
the center of edge.
SEE ALSO
set_app_options(2)
Chapter 1:
flip_chip.route.connect_edge_center
233
1-233
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
flip_chip.route.connect_pad_without_endcap
Option for the RDL router commands. Specifies how to connect to pads or vias.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this option is true, the RDL router uses a wire with squre_ends endcap to connect to
pads or vias. When this option is false, RDL router uses wires with
squre_ends_by_half_width / octagon_ends_by_half_width to connect to pads or vias
depending on the layer routing angle.
SEE ALSO
set_app_options(2)
flip_chip.route.connect_pad_without_endcap
234
flip_chip.route.detour_cost
Specifies the detour cost level for the auto via insertion flow.
TYPE
String (low | high)
DEFAULT
low
DESCRIPTION
Specifies the detour cost level for the auto via insertion flow. If the detour cost is low, the
RDL router avoids congestion by implementing detours on the same layer rather than
changing layers. If the detour cost is high, the RDL router uses different layers instead of
implementing detours.
SEE ALSO
set_app_options(2)
Chapter 1:
flip_chip.route.detour_cost
235
1-235
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
flip_chip.route.layer_bump_spacings
Option for the RDL router commands. Specifies the bump-to-route spacing rules for each
given metal layer.
TYPE
list
DEFAULT
null
DESCRIPTION
This option specifies the bump-to-route spacing rules for each given metal layer. You can
specify spacing values that are larger than the net nondefault routing rule (NDR) spacing.
The list format is:
{layer_name1 spacing1
layer_name2 spacing2
layer_name3 spacing3 ...}
You must specify the layer name by using the layer name from technology file. The units are
in microns.
By default, the RDL router uses the minimum spacing specified in the technology file.
SEE ALSO
set_app_options(2)
flip_chip.route.layer_bump_spacings
236
flip_chip.route.layer_routing_angles
Option for the RDL router commands. Specifies the routing angle for each given metal layer.
TYPE
list
DEFAULT
null
DESCRIPTION
Specifies the routing angle for each given metal layer. The list format is:
{layer_name1 routing_angle1
layer_name2 routing_angle2 ...}
You must specify the layer name by using the layer name from technology file. The
supported routing angle settings are:
45_degree
90_degree
By default, the RDL router uses 45_degree for routing.
SEE ALSO
set_app_options(2)
Chapter 1:
flip_chip.route.layer_routing_angles
237
1-237
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
flip_chip.route.layer_tie_shield_widths
Specifies the width of shields to tie for each given metal layer. Option for the RDL router
commands.
TYPE
list
DEFAULT
null
DESCRIPTION
Specifies the width of shields to tie for each given metal layer. The list format is:
{layer_name1 width1
layer_name2 width2 ...}
You must specify the layer name by using the layer name from technology file.
By default, the RDL router uses NDR width of shielding net.
SEE ALSO
create_rdl_shields(2)
set_app_options(2)
flip_chip.route.layer_tie_shield_widths
238
flip_chip.route.route_to_ring_nets
Option for the RDL router commands. Specifies the ring nets for RDL routing.
TYPE
List
DEFAULT
null
DESCRIPTION
For each ring net, the RDL router connects its floating bumps to the specified ring net. The
list format is:
{net_name1 net_name2 ...}
SEE ALSO
set_app_options(2)
Chapter 1:
flip_chip.route.route_to_ring_nets
239
1-239
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
flip_chip.route.routing_style
Specifies how to connect RDL nets from driver pads to bumps.
TYPE
String (star | spanning_tree)
DEFAULT
star
DESCRIPTION
Specifies how to connect RDL nets from driver pads to bumps. The star option directs the
RDL router to create a separate connection between each driver pad and bump. The
spanning_tree option directs the RDL router to connect all routing targets (drivers and
bump cells) on the same net into a spanning tree.
SEE ALSO
set_app_options(2)
flip_chip.route.routing_style
240
flip_chip.route.secondary_routing_layer_cost
Option for the RDL router commands. Specifies the secondary layer cost for the auto via
insertion flow.
TYPE
String (low | medium | high)
DEFAULT
medium
DESCRIPTION
Specifies the secondary layer cost for the auto via insertion flow. You can use this option to
trade off between via number and secondary layer utilization rate. Use the high cost level to
implement a low utilization rate for the secondary layer; use the low cost level to implement
a low number of vias. By default, the secondary routing layer cost is medium.
SEE ALSO
set_app_options(2)
Chapter 1:
flip_chip.route.secondary_routing_layer_cost
241
1-241
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
flip_chip.route.shielding_net
Specifies the shielding net for RDL routing. This option is used by the RDL router
commands.
TYPE
String
DEFAULT
""
DESCRIPTION
Specifies the shielding net for RDL routing. Since the RDL router uses only one shielding net
for each run, only one shielding net is allowed in this option. If this option is not set, RDL
router uses the ground net with maximum number of ports as the shielding net.
SEE ALSO
create_rdl_shields(2)
set_app_options(2)
flip_chip.route.shielding_net
242
geo_mask_attributes
Description of the predefined attributes for geo_masks.
DESCRIPTION
geo_mask attributes are provided in the subsections that follow.
command.
GeoMask Attributes
is_empty
A boolean attribute for whether the geo_mask contains any poly-rectangular regions.
object_class
A string attribute with the value of "geo_mask".
poly_rects
A collection attribute representing the poly-rectangular regions contained in the geo_mask.
shape_count
An integer attribute representing the number of poly-rectangular regions contained in the
geo_mask.
SEE ALSO
create_geo_mask(2)
get_attribute(2)
list_attributes(2)
Chapter 1:
geo_mask_attributes
243
1-243
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
set_attribute(2)
geo_mask_attributes
244
grid_attributes
Description of the predefined attributes for grid.
DESCRIPTION
Attributes are properties assigned to objects such as pins, cells and nets. Definitions for grid
command.
grid Attributes
allowed_orientations
List of orientations that cells associated with the grid is allowed to be placed. This attribute
is only available for grid of type block, and is only settable for manual defined block grid.
full_name
A string attribute for the full name of a grid.
is_auto_derived
A boolean attribute stating if the grid is a block grid that is derived from site rows and/or PG
strategies.
name
A string attribute for the name of a grid.
object_class
A string attribute with the value of "grid".
Chapter 1:
grid_attributes
245
1-245
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
type
A string attribute indicating the type of the grid.
x_offset
A distance attribute for the grid point's offset to the block's origin on the X-axis. This attribute
is not settable for auto derived block grid.
x_step
A distance attribute for the grid's pitch along the X-axis. This attribute is not settable for auto
derived block grid.
y_offset
A distance attribute for the grid point's offset to the block's origin on the Y-axis. This attribute
is not settable for auto derived block grid.
y_step
A distance attribute for the grid's pitch along the Y-axis. This attribute is not settable for auto
derived block grid.
SEE ALSO
create_grid(2)
set_grid(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
grid_attributes
246
gui.auto_link_blocks
Controls whether the tool automatically links the current block.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option controls whether the tool automatically links the current block.
When set to true (the default) and the GUI is active, the tool automatically links the current
block when the current block changes. The link occurs when the application is idle (for
example, when the current command or script finishes).
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
gui.auto_link_blocks
247
1-247
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
gui.auto_open_layout_windows
Controls whether the GUI automatically opens a new layout window when you change the
current block.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
By default (true), the GUI automatically opens a new layout window when you change the
current block.
To prevent the GUI from opening a new layout window when you change the current block,
set this option to false.
SEE ALSO
current_block(2)
get_app_options(2)
set_app_options(2)
gui.auto_open_layout_windows
248
gui.command_form_close_dialog_after_run_or_script
Controls whether a shell command form invoked from command search closes itself after
the command is successfully executed or scripted.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When you invoke the command search from the menu bar search icon and select a shell
command during the search, the GUI creates a form for entering the command parameters.
This option controls whether the command form automatically closes after the command is
successfully executed or added to the script editor.
By default (false), the command form remains open so that you can execute the same
command multiple times, possibly after changing some of the parameters.
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
gui.command_form_close_dialog_after_run_or_script
249
1-249
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
gui.command_form_show_result_dialog_after_run
Controls whether a shell command form invoked from command search displays the results
from the command execution in a message dialog.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When you invoke the command search from the menu bar search icon and select a shell
command during the search, the GUI creates a form for entering the command parameters.
This option controls whether the tool displays the results of a successfully executed
command in a message dialog.
Command results can often be uninteresting, such as the name of a resulting collection, so
having the results displayed in a dialog which must be dismissed is unnecessary. By default
(false), the tool outputs the command results to the terminal but does not display them in a
message dialog. If you set this option to true, the tool displays the results in a message
dialog.
SEE ALSO
get_app_options(2)
set_app_options(2)
gui.command_form_show_result_dialog_after_run
250
gui.custom_setup_files
Specifies a list of Tcl files to source when the GUI starts.
TYPE
list
DEFAULT
""
DESCRIPTION
This option specifies a list of Tcl files to source when the GUI starts.
If the file name is fully qualified (starts with ./ or /), the tool loads it from the specified
directory. If the file name is not fully qualified, the tool searches the following directories for
the file:
1. <root>/admin/setup, where <root> is the installation root of the executable
2. ~/.synopsys_icc2_gui
3. .
4. The tool does not issue a warning or error message if the file is not found in any of the
search directories.
5. Note that the custom setup files are loaded only if the gui.enable_custom_setup_files
application option is true, which is the default.
SEE ALSO
gui_start(2)
get_app_options(2)
set_app_options(2)
gui.enable_custom_setup_files(3)
Chapter 1:
251
1-251
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_app_options(2)
set_app_option(2)
252
gui.enable_custom_setup_files
Controls whether custom setup files are loaded.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
By default (true), if you have specified custom GUI setup files with the
gui.custom_setup_files application option, the tool loads these files when it opens the
GUI.
If you set this option to false, the tool does not load the custom setup files.
SEE ALSO
gui_start(2)
get_app_options(2)
set_app_options(2)
gui.custom_setup_files(3)
Chapter 1:
gui.enable_custom_setup_files
253
1-253
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
gui.graphics_system
Controls the graphics system used by the GUI.
TYPE
String
DEFAULT
native
DESCRIPTION
This application option controls how the GUI draws to the display. Valid values are "raster"
or "native". Changing this application option after the GUI has started has no effect.
The default value of "native" preserves pre-existing rendering mode.
The value of "raster" guarantees an optimal visual result, by ensuring that anti-aliasing and
transparency support will be available without a dependency on the capabilities of the X
server used. There can be performance differences between the graphics systems,
depending on the specific compute and network environment for the application, X server,
and viewer used. So the native graphics system may be slightly faster in some
environments.
This is a global app_option, so you can add the setting of this app_option to your application
setup file to override the default setting.
SEE ALSO
get_app_options(2)
set_app_option(2)
gui.graphics_system
254
gui.layer_solid_fill_pattern
Controls the default display of solid-filled layers.
TYPE
string
DEFAULT
Dense4Pattern
DESCRIPTION
The technology defines the appearance of layers in the GUI. Some technology files define
layers with a solid fill pattern. Using a solid fill pattern causes some usability issues because
valuable information is not visible in the layout window. For example, you cannot see net
names for shapes on solid-filled layers.
This application option controls how these solid fill patterns are mapped. By default, the GUI
maps the solid pattern to a pattern that appears more transparent. This allows net names to
be visible for example. Set this option to SolidPattern to disable this mapping.
To see the set of available fill patterns, use the get_app_option_value -details -name
gui.layer_solid_fill_pattern command.
SEE ALSO
gui_start(2)
get_app_options(2)
set_app_options(2)
Chapter 1:
gui.layer_solid_fill_pattern
255
1-255
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
gui.name_based_hier_delimiter
Specifies the hierarchy delimiter used by the Name Based Hierarchy Browser.
TYPE
String
DEFAULT
/
DESCRIPTION
This application option specifies the hierarchy delimiter used by the Name Based Hierarchy
Browser when processing a logically flat design. You can change this value and use a
different delimiter to extract the hierarchy from a design. Only one character is allowed. The
effective scope is block. The default value is "/".
SEE ALSO
set_app_options(2)
gui.name_based_hier_delimiter
256
gui_annotation_attributes
Description of the predefined attributes for gui_annotation.
DESCRIPTION
Objects of type gui_annotation are created by the gui_add_annotation command. See the
manpage for that command for more details.
To determine the value of an attribute use the get_attribute command.
GUI Annotation Attributes
client_data
A string attribute that can be used by client code to store arbitrary information
color
The color used to draw the annotation.
fill_pattern
The fill pattern used to fill the annotationshape
group
The group of the annotation.
info_tip
The tip text (or command) displayed when a user hovers over the annotation in the layout.
line_style
The line style to use when drawing the annotaiton
line_width
The width of the line in pixels.
Chapter 1:
257
1-257
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
object_class
The string attribute with the value "gui_annotation"
points
The points for the annotation
query_command
The command to use when the annotation is queried in the layout.
query_text
The text to display when the annotation is queried in the layout.
shape_type
The type of shape for this annotation. For example, rect, line, etc.
text
If the shape_type is text this attribute has the text to display
window
When set this annotation will only be drawn on the specified window.
SEE ALSO
gui_create_annotation(2)
gui_get_annotations(2)
gui_remove_all_annotations(2)
gui_remove_annotation(2)
258
gui_object_attributes
Description of the predefined attributes for gui_object.
DESCRIPTION
Objects of type gui_object are created by the gui_create_vm_objects command. See the
manpage for that command for more details.
All attributes are read-only. To determine the value of an attribute use the get_attribute
command.
GUI Object Attributes
name
A string attribute for the name of the object
full_name
The same as name
object_class
A string attribute with the value of "gui_object"
layout_info_tip
The info-tip to use in the layout when the user hovers over this object.
query_text
The query text to display if the user queries this object in the layout.
core_object
A collection containing the actual object wrapped by this gui_object.
Chapter 1:
259
1-259
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
gui_create_vm_objects(2)
gui_create_vm(2)
gui_create_vm_bucket(2)
gui_update_vm_annotations(2)
260
gui_online_browser
Specifies the name of the browser used to invoke the online help system from the help menu
of the product.
TYPE
string
DEFAULT
netscape
GROUP
gui
DESCRIPTION
This string variable holds the value of the default browser which is used to invoke online help
system from Help menu of the application. The value the variable should be either
netscape, mozilla or firefox.
If you specify a browser other than those listed above, the application defaults to the
netscape browser.
Use the following command to determine the current value of the variable:
prompt> printvar gui_online_browser
SEE ALSO
gui_custom_setup_files(3)
Chapter 1:
gui_online_browser
261
1-261
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
hierarchy_separator
hierarchy_separator
TYPE
string
DEFAULT
/ (forward slash)
DESCRIPTION
Determines how hierarchical elements of the netlist are delimited in reports, and searched
for in selections and other commands. By default, the value is the slash, "/". The choice of a
separator is limited to these characters: bar "|", caret "^", at "@", dot ".", and slash "/".
Normally, you should accept the default slash. However, in some cases where the hierarchy
character is embedded in some names, the search engine might produce results that are not
intended; the hierarchy_separator is a convenient method for dealing with this situation.
For example, consider a design that contains a hierarchical cell A, which contains
hierarchical cells B and B/C; B/C contains D; B contains C. Searching for "A/B/C/D" is
ambiguous and might not match what you intended. However, if you set the
hierarchy_separator to the vertical bar "|", searching for "A | B/C | D" is very explicit, as is
"A | B | C | D".
SEE ALSO
selection(2)
hierarchy_separator
262
in_gui_session
This read-only variable is "true" when the GUI is active and "false" when the GUI is not
active.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This variable can be used in writing Tcl code that depends on the presence the graphical
user interface (GUI). The read-only variable has the value "true" if gui_start has been
invoked and the GUI is active. Otherwise, the variable has the value "false" (default).
SEE ALSO
printvar(2)
gui_start(2)
gui_stop(2)
Chapter 1:
in_gui_session
263
1-263
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
input_delay_attributes
Description of the predefined attributes for input delay objects.
DESCRIPTION
input_delay attributes are provided in the subsections that follow.
command.
Input_Delay Attributes
clock_name
A string attribute representing the name of the relative clock.
file_line_info
full_name
A string attribute representing a unique name for the input delay object.
is_clock_fall
A Boolean attribute. The value will be "true" if this input_delay is relative to the falling edge
of the clock, "false" otherwise.
is_level_sensitive
A Boolean attribute. The value will be "true" if this input_delay represents a level-sensitive
startpoint, "false" otherwise.
264
is_network_latency_included
A Boolean attribute. The value will be "true" if this input_delay includes clock network
latency, "false" otherwise.
is_source_latency_included
A Boolean attribute. The value will be "true" if this input_delay includes clock source latency,
"false" otherwise.
max_fall
A float attribute representing the maximum fall delay value.
max_rise
A float attribute representing the maximum rise delay value.
min_fall
A float attribute representing the minimum fall delay value.
min_rise
A float attribute representing the minimum rise delay value.
mode
A collection attribute returning the mode that contains the input_delay.
object_class
A string attribute with the value of "input_delay". Each object class has a different object
class value.
SEE ALSO
set_input_delay(2)
get_attribute(2)
list_attributes(2)
Chapter 1:
265
1-265
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
io_guide_attributes
Description of the predefined attributes for io_guides.
DESCRIPTION
io_guide attributes are provided in the subsections that follow.
command.
IO Guide Attributes
bbox
A rectangle attribute for the bounding-box of an io_guide. The format of a rectangle
the rectangle.
cells
A collection attribute representing the instances associated with the IO guide.
end_offset
A distance attribute representing the end offset of IO guide. This is a settable attribute.
full_name
A string attribute for the name of the io_guide.
in_edit_group
A Boolean attribute stating if the IO guide belongs to an edit group.
io_guide_attributes
266
io_ring
A collection attribute representing the IO ring associated with the IO guide.
is_shadow
A Boolean attribute to specify whether an IO guide is pushed down from above.
length
A distance attribute to specify the length of the IO guide.
line
A coordinate list attribute representing the first and last points of the IO guide. This is a
settable attribute.
name
A string attribute for the name of the io_guide. This is a settable attribute.
object_class
A string attribute with the value of "io_guide".
origin
A coordinate attribute representing the first point of the IO guide. This is a settable attribute.
over_constrained
A Boolean attribute to specify if the IO guide is over constrained.
shadow_status
A string attribute to represent the shadow status of an io_guide. Valid values are
side
A string attribute to specify the access direction of the IO guide. This is a settable attribute.
Chapter 1:
io_guide_attributes
267
1-267
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
start_offset
A distance attribute representing the start offset of IO guide. This is a settable attribute.
parent_block
A collection attribute with the owner block object for this IO guide.
parent_cell
A collection attribute with the owner cell object for this IO guide.
parent_block_cell
A collection attribute with the parent block cell object for this IO guide.
top_block
A collection attribute with the top block object for this IO guide.
is_placed
A boolean attribute to indicate that the "io_guide" is placed.
physical_status
A string attribute representing the physical modification status of the ioguide . Valid values
are unrestricted, application_fixed, fixed, and locked. If status is unrestricted, the ioguide
may be freely modified. If the status is application_fixed, the ioguide is fixed by the
application for automatic changes (the application may change this status). If status is fixed,
the ioguide is fixed by the user for automatic changes. If status is locked, the ioguide is fixed
for automatic and manual changes. This is a settable attribute.
signal_constraint_order
A string attribute to indicate that the relative order of IO driver cells within the IO Guide.
signal_constraint_location
A string attribute to specify location of each individual IO driver cell within the IO Guide.
io_guide_attributes
268
signal_constraint_fixed
A string attribute to specify location of each individual IO driver cell which are fixed with
respect to the IO Guide.
signal_constraint_other
A string attribute to specify if other IO Pad Cells can be inserted before the first or the last IO
Pad cell.
signal_constraint_insert
A string attribute to specify the array of locations where other IO Pad Cells can be inserted
in spaces between other IO Pad cells if allowed.
power_constraint_cell
A collection attribute to specify the list of Power/Ground IO pad cells in the IO Guide. This is
power_constraint_space
A string attribute to specify the list of distances which signifies the maximal distance
between two consecutive power driver cells. This is a settable attribute.
power_constraint_share
A string attribute to specify the list of the number of IO driver cells that can share a single
bump. This is a settable attribute.
power_constraint_ratio
A string attribute to specify the list of the number of signal IO driver cells allowed between
consecutive power driver cells of the same power supply or ground. This is a settable
attribute.
power_constraint_offset
A string attribute to specify the list of the maximal distances permitted between starting edge
of IO Guide and closest edge of the first IO power driver cell. This is a settable attribute.
Chapter 1:
io_guide_attributes
269
1-269
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
create_io_guide(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
SEE ALSO
create_io_guide(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
io_guide_attributes
270
io_ring_attributes
Description of the predefined attributes for io_rings.
DESCRIPTION
io_ring attributes are provided in the subsections that follow.
command.
IO Ring Attributes
bbox
A rectangle attribute for the bounding-box of an io_ring. The format of a rectangle
the rectangle. This is a settable attribute.
cells
A collection attribute representing the instances associated with the IO ring.
corner_height
A distance attribute representing corner height of IO ring. This is a settable attribute.
full_name
A string attribute for the name of the io_ring.
in_edit_group
A Boolean attribute stating if the IO ring belongs to an edit group.
Chapter 1:
io_ring_attributes
271
1-271
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
io_guides
A collection attribute representing the IO guides associated with the IO ring.
name
A string attribute for the name of the io_ring. This is a settable attribute.
object_class
A string attribute with the value of "io_ring".
offset
A distance attribute to specify the offset of IO ring from block boundary or outer ring. This is
outer_ring
A collection attribute to specify the outer ring, if any, relative to the IO ring. This is a settable
attribute.
over_constrained
A Boolean attribute to specify if the IO ring is over constrained.
parent_block
A collection attribute with the owner block object for this IO Ring.
parent_cell
A collection attribute with the owner cell object for this IO Ring.
parent_block_cell
A collection attribute with the parent block cell object for this IO Ring.
top_block
A collection attribute with the top block object for this IO Ring.
io_ring_attributes
272
SEE ALSO
create_io_ring(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
io_ring_attributes
273
1-273
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
keepout_attributes
Description of the predefined attributes for keepout.
DESCRIPTION
keepout attributes are provided in the subsections that follow.
command.
keepout Attributes
boundary
A coordinate_list attribute for the boundary of the owner the current keepout belongs to. The
boundary value has the current keepout margin applied. The format of a coordinate_list
specification is {{x1 y1} {x2 y2}...}.
full_name
A string attribute for the full name of a keepout. The string value has the full-name of the
owner and the name of the keepout.
layers
A collection attribute consisting of layers for the route_blockage type keepout. This attribute
is applicable only for the route_blockage type keepout. This attribute is settable.
margin
A margin_list attribute consisting of the keepout margin values in the following order : left,
bottom, right and top. The format of a margin_list specification is {l b r t}. This attribute is
settable.
keepout_attributes
274
name
A string attribute for the name of the keepout.
object_class
A string attribute with the value of "keepout".
owner
A collection attribute representing the design or the cell object the keepout margin belongs
to.
scope
A string attribute with one of the following values : inner, outer.
type
A string attribute with one of the following values : hard, soft, hard_macro, route_blockage.
SEE ALSO
create_keepout_margin(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
keepout_attributes
275
1-275
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
layer_attributes
Description of the predefined attributes for layer.
DESCRIPTION
layer attributes are provided in the subsections that follow.
Attributes are read-only unless marked as settable. Read-only attributes are informational
and you cannot set their values. A settable attribute can be modified with the set_attribute
command.
To determine the value of an attribute, use the get_attributecommand. To see a list of all
the attributes of a class of objects, use the list_attributes -application\P command.
Layer Attributes
adjacent_cut_range
A float attribute. The value is adjacent cut range of layer.
capacitance_multiplier
A float attribute. The value is capacitance multiplier of layer.
check_manhattan_spacing
A Boolean attribute. The value is true if manhattan spacing is set on the layer.
default_width
A float attribute. The value is default width of layer.
end_of_line_corner_keepout_width
A float attribute. The value is end of line corner keepout width of layer.
end_of_line_side_keepout_length
A float attribute. The value is end of line side keepout length of layer.
layer_attributes
276
end_of_line1_neighbor_corner_keepout_width
A float attribute. The value is end of line1 neighbor corner keepout width of layer.
end_of_line1_neighbor_threshold
A float attribute. The value is end of line1 neighbor threshold of layer.
end_of_line1_neighbor_wire_min_threshold
A float attribute. The value is end of line1 neighbor wire min threshold of layer.
end_of_line1_neighbor_min_spacing
A float attribute. The value is end of line1 neighbor min spacing of layer.
end_of_line1_neighbor_min_length
A float attribute. The value is end of line1 neighbor min length of layer.
fat_table_dimension
A int attribute. The value is fat_table_dimension of layer.
fat_table_parallel_length_dimension
A int attribute. The value is fat_table_parallel_length_dimension of layer.
full_name
A string attribute representing the name.
layer_number
A string attribute. The value is layer number of layer.
layer_type
A string attribute. The value is the type of the layer. Valid types include: INTERCONNECT,
LOCAL_INTERCONNECT, VIA_CUT, LOCAL_VIA_CUT, DIFFUSION, NWELL, PWELL,
N_IMPLANT, P_IMPLANT, IMPLANT, MIM_INTERCONNECT, MIM_VIA_CUT, and
SADP_TRIM
Chapter 1:
layer_attributes
277
1-277
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
mask_name
A string attribute representing the mask name.
max_num_adjacent_cut
An integer attribute. The value is max number of adjacent cuts of layer.
min_area
A float attribute. The value is min area of layer.
min_spacing
A float attribute. The value is min spacing of layer.
min_width
A float attribute. The value is min width of layer.
name
object_class
A string attribute with the value of "layer".
pitch
A float attribute. The value is pitch of layer.
purpose_name
A string attribute. The value is the purpose name of the layer.
purpose_number
An integer attribute. The value is the purpose number of the layer.
routing_direction
A string attribute. The value is the routing direction of the layer.
layer_attributes
278
special_min_area
A float attribute. The value is special min area of layer.
stub_spacing
A float attribute. The value is stub spacing of layer.
stub_threshold
A float attribute. The value is stub threshold of layer.
track_offset
A float attribute. The value is the track offset value of the layer.
SEE ALSO
get_layers(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
layer_attributes
279
1-279
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.logic_model.auto_remove_incompatible_timing_designs
Specifies whether to automatically remove timing designs which fail to compare to the same
design in the base (first) logical library.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, if check_workspace encounters a timing design that does not compare
to the same design in the base (first) logical library for any reason (missing port, different
port direction, different logic function, etc.), the offending design will be automatically
removed, and no timing for that design for that library will be present in the workspace.
Incompatible designs are a sign of out of sync libraries. This is an option to avoid.
SEE ALSO
LM-032(n)
set_app_options(2)
lib.logic_model.auto_remove_incompatible_timing_designs
280
lib.logic_model.auto_remove_timing_only_designs
Specifies whether to automatically remove designs which exist in logical (DB, Liberty)
libraries which do not exist in physical libraries.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, designs that exist in logical libraries that do not exist in physical libraries
will be removed from the workspace automatically by check_workspace
SEE ALSO
LM-035(n)
LM-092(n)
set_app_options(2)
Chapter 1:
lib.logic_model.auto_remove_timing_only_designs
281
1-281
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.logic_model.require_same_opt_attrs
Specifies whether optimization attributes have to match between the base logical (DB)
library and other DB libraries in the library manager.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, a difference in the dont_touch, dont_use, or use_for_size_only design
attributes between the base DB library and other DB libraries becomes an error which you
must correct with set_attribute. In all cases, you are warned when there is a difference.
SEE ALSO
LM-080(n)
LM-081(n)
set_app_options(2)
lib.logic_model.require_same_opt_attrs
282
lib.logic_model.use_db_rail_names
Specifies whether voltage rail names are take from the logical library source files (DB, .lib)
or if they are automatically generated.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
In Liberty, the voltage_map construct defines the voltage rails. The voltage rail name is
essentially a constant which is replaced with a voltage value. For this application, there can
be only one name for a rail in the committed NDM library. So, when you combine a set of DB
or .lib source libraries with this application, the voltage rail names must match across these
DB libraries. You can avoid most rail naming problems by not encoding a voltage value into
the name; for example use VDD, not VDD_1.0 for the 1.0 volt rail. You can also use a
template approach, where you put the same voltage_map entries in all of your .lib files,
whether you need them or not.
When the rails don't match, you have some choices:
You can use the rename_rail command to rename the rails in one or more of the
libraries which came from DB. See the man page for the rename_rail command for good
examples.
You can let the application choose voltage rail names for you by setting the application
option lib.logic_model.use_db_rail_names to false. There are cases when it is very
difficult to find a combination of rename_rail commands that will get you do a consistent
set of rail names. The application can do this by spreading the voltage values out across
all of the library cell pins for all libraries, then collecting unique combinations and
considering each as a voltage rail. The rail names are very simple: power_1, power_2,
ground_1, and so on. Note that this may result in a reduction in the number of rails from
DB if there are duplicate values. Currently, during check_workspace, this will result in a
number of errors followed by a message that rail mismatches have been fixed.
Note that this option is a last-resort fix for rail problems. It is intended only for cases when
there is a loop in the rail naming scheme. This should not be used to get around combining
Chapter 1:
283
1-283
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
unrelated libraries. If you are not sure which DB or .lib files go together, consider using the
exploration flow to group the related libraries.
SEE ALSO
rename_rail(2)
set_app_options(2)
284
lib.physical_model.block_all
icc2_lm_shell Option to block all area excepts pins on the metal layer
TYPE
Enum
DEFAULT
false
DESCRIPTION
Blocks all area excepts pins on the metal layer. The tool cuts the blockage around pins. The
detail shapes inside drc distance are preserved in the frame and covered by blockage.
There are four choices for this option: true, false, used_layers, and auto. If set to true, block
all routing layers. If set to used_layers, block only used routing layers and leave out empty
ones. If set to auto, the tool decides which mode is applied according to design type: true for
analog, black_box, and module; used_layers for macro; false, otherwise. Default is false.
lib.physical_model.block_core_margin has priority over lib.physical_model.block_all
by layer.
SEE ALSO
set_app_options(2)
lib.physical_model.block_core_margin(3)
lib.physical_model.include_nondefault_via(3)
lib.physical_model.drc_distances(3)
lib.physical_model.preserve_metal_blockage(3)
Chapter 1:
lib.physical_model.block_all
285
1-285
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.physical_model.block_core_margin
icc2_lm_shell Option to block the core area with given margin by layer.
TYPE
list_of_pairs
DEFAULT
null
DESCRIPTION
Creates a core blockage on a specified layer. However, unlike the block all option, there is a
margin (open area) between the core blockage and the macro cell boundary. You can enter
0, or a positive number in margin. When the margin value is a positive number, the margin
is equal to the value between the macro boundary and the blockage created.
This option has priority over lib.physical_model.block_all by layer.
SEE ALSO
set_app_options(2)
lib.physical_model.block_all(3)
lib.physical_model.block_core_margin
286
lib.physical_model.connect_within_pin
icc2_lm_shell Option to generate connect within pin via region.
TYPE
bool
DEFAULT
"true"
DESCRIPTION
Connect within pin via region means via enclosure will not be outside pin shape while
dropping via on the via region. When the option is false, via enclosure could be outside pin
shape while dropping via on the via reigon.
SEE ALSO
set_app_options(2)
Chapter 1:
lib.physical_model.connect_within_pin
287
1-287
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.physical_model.convert_metal_blockage_to_zero_spacing
Library Shell Option to convert regular routing blockages in design view to zero-spacing
blockages with a bloating distance in frame view.
TYPE
list_of_pairs
DEFAULT
null
DESCRIPTION
Specifies the layer name and distance pair to convert regular routing blockages in design
view to zero-spacing blockages with a bloating distance in frame view. The layer name
should be a metal or poly layer. The distance value should be no less than zero.
SEE ALSO
set_app_options(2)
lib.physical_model.convert_metal_blockage_to_zero_spacing
288
lib.physical_model.design_rule_via_blockage_layers
icc2_lm_shell option to convert zero spacing routing blockage in cut layer of frame view to
design rule routing blockage.
TYPE
list
DEFAULT
""
DESCRIPTION
Convert zero spacing routing blockage in cut layer of frame view to design rule routing
blockage. The option accepts a list of cut layers and only works for zero spacing routing
blockage on those cut layers.
Design rule routing blockage is the routing blockage whose is_design_rule_blockage
attribute is true. The purpose of design rule routing blockage is to honor spacing between
viaBlockage and via in DesignRule section of tech file.
e.g.
DesignRule { layer1 = "via1Blockage" layer2 = "V1" minSpacing = 0.084 }
SEE ALSO
set_app_options(2)
Chapter 1:
lib.physical_model.design_rule_via_blockage_layers
289
1-289
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.physical_model.drc_distances
Library Shell Option to preserve detail shapes from the boundary of blockage generated by
-block_all or -block_core_margin.
TYPE
list_of_pairs
DEFAULT
null
DESCRIPTION
Specifies the layer name and distance pair to preserve detail shapes from the boundary of
blockage generated by -block_all or -block_core_margin. By default, tool use the maximum
spacing value from technology file as the drc distance.
SEE ALSO
set_app_options(2)
lib.physical_model.drc_distances
290
lib.physical_model.hierarchical
icc2_lm_shell Option to perform hierarchical extraction.
TYPE
bool
DEFAULT
true
DESCRIPTION
Performs hierarchical extraction, when true. If false, the tool does not extract pins, vias and
blockages hierarchically while creating the frame view.
SEE ALSO
set_app_options(2)
Chapter 1:
lib.physical_model.hierarchical
291
1-291
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.physical_model.include_nondefault_via
icc2_lm_shell Option to add additional via definitions for via region extraction.
TYPE
string
DEFAULT
""
DESCRIPTION
Specifies the via definition names of any additional vias that are to be considered during
calculation of via regions. By default, the extraction process considers the use of the default
via only.
SEE ALSO
set_app_options(2)
lib.physical_model.include_nondefault_via
292
lib.physical_model.include_routing_pg_ports
icc2_lm_shell Option to include routing PG ports when generating via regions and access
edges.
TYPE
list
DEFAULT
""
DESCRIPTION
Specifies the PG ports names that requires via regions and access edges in frame views.
Usually, these ports are the secondary PG ports and bias PG ports, which are going to be
routed by the signal router. By default, PG ports are skipped when generating via regions
and access edges.
SEE ALSO
Chapter 1:
lib.physical_model.include_routing_pg_ports
293
1-293
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.physical_model.merge_metal_blockage
icc2_lm_shell Option to merge metal layer blockages.
TYPE
bool
DEFAULT
false
DESCRIPTION
Merge metal blockage based on minimum width and minimum spacing. If two metal
blockages are too close, the space between the two shapes will be filled, thereby creating a
single larger shape for the blockage in the frame view.
SEE ALSO
set_app_options(2)
lib.physical_model.merge_metal_blockage
294
lib.physical_model.pin_must_connect_area_layers
Library Shell Option to specify for each connection layer the associated spare layer being
used to designate the required via connection area within the pin geometry.
TYPE
list_of_pairs
DEFAULT
null
DESCRIPTION
Specifies for each connection layer the associated spare layer being used to designate the
required via connection area within the pin geometry. By default, the router can connect a
wire to any part of a large pin. To restrict the connection to a subarea of a large pin, specify
the subarea polygon on a spare layer and specify the spare area associated with each
connection layer using this option. List the connection layers and associated spare layers as
in the following example:
{{M1 S1} {M2 S2} ...}
SEE ALSO
set_app_options(2)
lib.physical_model.pin_must_connect_area_thresholds(3)
Chapter 1:
lib.physical_model.pin_must_connect_area_layers
295
1-295
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.physical_model.pin_must_connect_area_thresholds
Library Shell Option to specify the width threshold for automatic determination of the
required via connection arera within the pin geometry.
TYPE
list_of_pairs
DEFAULT
null
DESCRIPTION
Specifies the width threshold (in the unit size defined in the technology file) for automatic
determination of the required via connection area within the pin geometry. By default, the
router can connect a wire to any part of a large pin. To automatically restrict the connection
to a subarea of a pin with an irregular shape, use this option and specify each layer and its
associated width threshold. For example,
{{M1 0.56} {M2 0.63} ...}
Areas within a pin having a width smaller than the threshold are excluded from allowing a via
connection to be made. For a fat pin, the first-dimension fat contact threshold is used to
calculate the allowed connection area, so that the router does not drop a fat contact on the
thin part of a fat pin.
SEE ALSO
set_app_options(2)
lib.physical_model.pin_must_connect_area_layers(3)
lib.physical_model.pin_must_connect_area_thresholds
296
lib.physical_model.port_contact_selections
icc2_lm_shell Option to specify custom contactCodes for specific port in via region
generation.
TYPE
string
DEFAULT
""
DESCRIPTION
Specify custom contactCodes for specific port in via region generation. The port will only
have via regions with custom contactCodes. If user does not specify any contactCode for
the port, via regions of default contactCodes will be generated.
EXAMPLES
The following option setting will generate via regions of contactCode VIA12HH and
VIA12HV in terminal A and via region of contactCode VIA12 in terminal B.
prompt> set_app_options -as_user_default -list
{lib.physical_model.port_contact_selections {{A {VIA12HH VIA12HV}} {B
{VIA12}}} }
SEE ALSO
set_app_options(2)
Chapter 1:
lib.physical_model.port_contact_selections
297
1-297
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.physical_model.preserve_metal_blockage
icc2_lm_shell Option to preserve metal layer blockages without trimming for frame view lib
cell.
TYPE
Enum
DEFAULT
auto
DESCRIPTION
Preserve all metal blockages as they exist in the design view.
If false, metal blockages touching pins are trimmed as needed to prevent design rule
violations.
If true, all metal blockages are retained exactly, so be sure that the preserved metal
blockages do not violate the design rules.
The default value is auto. The tool automatically determines the value by design_type: true
for lib_cell, diode, end_cap, fill, filler, physical_only, well_tap; false, otherwise.
lib.physical_model.trim_metal_blockage_around_pin has priority over
lib.physical_model.preserve_metal_blockage by layer.
SEE ALSO
set_app_options(2)
lib.physical_model.trim_metal_blockage_around_pin(3)
lib.physical_model.preserve_metal_blockage
298
lib.physical_model.source_drain_annotation
Library Shell Option to specify the name of the input file containing the source-drain
annotation information for the cells in the specified library.
TYPE
string
DEFAULT
""
DESCRIPTION
Specifies the name of the input file containing the source-drain annotation information for
the cells in the specified library. The file identifies the type of transistor geometry (SOURCE,
DRAIN, or NONE) abutting each side (left or right) and subrow (upper or lower half of the tile
height) of each cell. The command reads this source-drain information from the file and
annotates it in the frame view. Extraction of this property requires the site def information.
SEE ALSO
set_app_options(2)
Chapter 1:
lib.physical_model.source_drain_annotation
299
1-299
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.physical_model.trim_metal_blockage_around_pin
Specifies how to trim metal blockages around pins for each layer.
TYPE
list_of_pairs
DEFAULT
null
DESCRIPTION
This application option specifies how the tool trims metal blockages around pins during
frame view creation. The supported methods are
touch
Trims only the metal blockages that touch a pin.
all
Trims all metal blockages around pins.
none
Does not trim metal blockages.
You specify the method used for each layer by using the following format:
{{layer_name touch | all | none} ...}
Specify the layer name by using the layer name from the technology file. If you do not
specify a method for a layer, the tool uses the setting of
lib.physical_model.preserve_metal_blockage for that layer.
If the method specified for a layer conflicts with the setting of the
lib.physical_model.preserve_metal_blockage application option for that layer, the
lib.physical_model.trim_metal_blockage_around_pin setting has priority.
SEE ALSO
300
set_app_options(2)
check_workspace(2)
Chapter 1:
301
1-301
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.workspace.allow_commit_workspace_overwrite
Specifies whether allow the command commit_workspace to overwrite existing file.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to false, commit_workspace will error out if there is a file has the same name
with your specified name or default name. When set to true, commit_workspace will
overwrite the existing file. commit_workspace will overwrite the existing file when option
-force is specified, even though this application option value is false.
SEE ALSO
commit_workspace(2)
set_app_options(2)
lib.workspace.allow_commit_workspace_overwrite
302
lib.workspace.allow_missing_related_pg_pins
Specifies whether signal pins are allowed to have no related power and ground pins.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to false, a signal pin is not allowed to have no related power or ground pin except
that if the containing cell has no power and ground pins at all or if the signal pin is an internal
pin. If a signal pin is found to have no related power or ground pin, error messages will be
displayed and the check_workspace command will fail. When set to true, if the related pg
pin information of a signal pin is missing, information of the signal pin and its containing lib
cell will be displayed but the missing of related pg pins will not cause check_workspace to
fail.
SEE ALSO
LM-088(n)
set_app_options(2)
Chapter 1:
lib.workspace.allow_missing_related_pg_pins
303
1-303
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.workspace.create_workspace_tf_verbose
In the Library Manager, customize the detail in output from create_workspace when used
with option -technology.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option is used to customize the messages output by
create_workspacewith option -technology. It can be set to true or false. Detail
messages like unsupported sytax, will be reported when this application option value
is true.
SEE ALSO
create_workspace(2)
set_app_options(2)
lib.workspace.create_workspace_tf_verbose
304
lib.workspace.enable_secondary_pg_marking
This app option specifies whether secondary power and ground pins should be marked.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
When set to true, secondary pg pins will be marked by the library manager. By default the
option is set to true. It cen be set to false with the set_app_options command.
SEE ALSO
set_app_options(2)
Chapter 1:
lib.workspace.enable_secondary_pg_marking
305
1-305
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.workspace.exclude_design_filters
Specifies one or more patterns to match designs to exclude from the library workspace
when reading library source files in icc2_lm_shell.
TYPE
list
DEFAULT
empty
DESCRIPTION
This application option is used with the lib.workspace.include_design_filters application
option to determine which designs are loaded into the library workspace when you run
commands such as read_db, read_lib, read_lef, read_gds, and read_ndm.
By default, all designs in a source library file are loaded into the library workspace by the
read commands and none are excluded.
The comparisons are done in two steps:
If a design name matches any exclude filter, the design is not loaded into the library
workspace.
If a design name matches any include filter (or if there are no include filters), the design
is loaded into the library workspace. Note that if you specify an include filter, any design
that does not match the filter is not loaded into the library workspace.
These options are useful for splitting your libraries into more or finer groups. You can
accomplish the same effect by reading all the source libraries, building collections of designs
to remove by using the get_lib_cells command and manipulating those collections, and
then using the remove_lib_cells command. Both methods work, but using the read filters is
more efficient.
If you specify any filters, the tool issues a one-line notation for each included design. For
example, if you set the include filter to AN2 and used read_db, you might see this:
... including AN2
306
If you read an NDM file which might contain several views of the same design, you might see
this:
... including AN2/frame
... including AN2/design
SEE ALSO
read_db(2)
read_lib(2)
read_lef(2)
read_gds(2)
read_ndm(2)
get_lib_cells(2)
remove_lib_cells(2)
set_app_options(2)
lib.workspace.include_design_filters(3)
Chapter 1:
307
1-307
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.workspace.group_libs_create_slg
Specifies whether allow the command group_libs to create scaling group.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to false, group_libs will not create scaling group, however if identified any
potential valid scaling group, will issue message LM-027 to remind user. When set to true,
group_libs will create valid scaling group if feasible.
SEE ALSO
group_libs(2)
set_app_options(2)
lib.workspace.group_libs_create_slg
308
lib.workspace.group_libs_fix_cell_shadowing
Specifies whether allow the command group_libs to fix potential cell shadowing.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
When set to false, group_libs will perform grouping based on cell name signatures only,
which means logical libraries with exact same set of lib cells are grouped together. However,
if there are cell misaligned among set of libraries, some cells may be created in multiple
reference ndm libraries, each library only contains partial of pvt panes, this will cause cell
shadowing during link designs.
When set to true which is default, group_libs will fix potential cell shadowing if detects any.
The cell shadowing fix will break down some logical libraries into pieces, each contains
subset of lib cells of original library. Refer EXAMPLE of LM-121 for more details.
SEE ALSO
group_libs(2)
LM-121(n)
set_app_options(2)
Chapter 1:
lib.workspace.group_libs_fix_cell_shadowing
309
1-309
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.workspace.group_libs_macro_grouping_strategy
Specifies the strategy for grouping macro cells in group_libs command during the
exploration flow.
TYPE
I Enum
DEFAULT
minimize_libs
DESCRIPTION
This application option specifies the strategy used for grouping macro cells in group_libs
command during the exploration flow.
Usually each input DB or LIB file contains a single macro cell, it is helpful to organize the
macro cells efficiently if there are a large number of macro cells. Currently two strategies are
supported.
By default, the tool uses the minimize_libs strategy. This strategy will try to get as many
macros as possible into a single library -all of them if possible. Macros with the same set of
characterization points can be grouped into one lib. With this strategy, the number of
reference libraries could be greatly reduced.
Another supported strategy is single_cell_per_lib. This strategy will generate 1 ndm
reference library for each macro cell, each library includes only one macro cell and with all
PVTs. With this strategy, you could end up with a large number of reference libraries.
For example, if you have 100 macros with 4 PVTs (so 400 DB files), in the default case, we
will try to create one NDM library. In the single_cell_per_lib case, we will create 100 NDM
libraries.
EXAMPLES
To apply single_cell_per_lib strategy:
lib.workspace.group_libs_macro_grouping_strategy\
-value single_cell_per_lib
310
SEE ALSO
group_libs(2)
set_app_options(2)
Chapter 1:
311
1-311
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.workspace.group_libs_naming_strategies
Specifies the naming strategy for the library groups created by the group_libs command
during the exploration flow.
TYPE
list
DEFAULT
common_prefix_and_common_suffix
DESCRIPTION
This application option specifies the naming strategy used for library groups created by the
group_libs command during the exploration flow.
This name is used as the name of the subworkspace for the library group, as well as its
committed reference library.
By default, the tool uses the common_prefix_and_common_suffix strategy. This strategy
names the library groups by using a unique combination of logic library prefix and suffix
characters, except the physical-only library group, which is named
<root_workspace_name>_physical_only where <root_workspace_name> is the name of
the root workspace, which was specified with the create_workspace command.
To change the naming strategy, specify an ordered list of one or more of the following
values:
common_prefix
This strategy names the library groups by using a common prefix of the logic libraries in
the library group.
common_suffix
This strategy names the library groups by using a common suffix of the logic libraries in
the library group.
common_prefix_and_common_suffix
This strategy names the library groups by using both the common prefix and common
suffix of the logic libraries in the library group. If the tool can find only a common prefix or
a common suffix, it uses that as the library group name.
312
first_logical_lib_name
This naming strategy names the library groups by using the name of the first logic library
name in the library group.
If you specify multiple values, the tool uses the first naming strategy that generates a valid
name.
EXAMPLES
To apply common prefix first followed by common suffix strategy:
prompt> set_app_options -name lib.workspace.group_libs_naming_strategies
\
-value common_prefix common_suffix
SEE ALSO
group_libs(2)
set_app_options(2)
Chapter 1:
313
1-313
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.workspace.group_libs_physical_only_name
Specifies the name of the physical_only library group created by the group_libs command
in the exploration flow.
TYPE
string
DEFAULT
"" (an empty string)
DESCRIPTION
This application option specifies the name of the physical_only library group created by the
group_libs command in the exploration flow. The name of a library group is used as the
name of the subworkspace for the library group as well as its committed reference library.
The default value of this application option is "", i.e. an empty string. If the value of this option
is "", the physical_only library group created by the group_libs command is named
<root_workspace_name>_physical_only, where <root_workspace_name> is the name of
the root_workspace which was specified with the create_workspace command.
You can change the naming of the physical_only group by setting the
lib.workspace.group_libs_physical_only_name application option to the name you want
before running the group_libs command. To change the naming back to using
<root_workspace_name>_physical_only, set the option to "" or simply reset it with the
reset_app_options command.
EXAMPLES
To name the physical library group "physical_only":
prompt> set_app_options -name lib.workspace.group_libs_physical_only_name
\
-value physical_only
To set the option back to its default value:
314

\
-value ""
To name the physical library group "ABC":

\
-value ABC
To reset the option to its default value:

prompt> reset_app_options lib.workspace.group_libs_physical_only_name
SEE ALSO
group_libs(2)
set_app_options(2)
reset_app_option(2)
lib.workspace.group_libs_naming_strategies(3)
Chapter 1:
315
1-315
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.workspace.include_design_filters
Specifies one or more patterns to match designs to load into the library workspace when
reading library source files in icc2_lm_shell.
TYPE
list
DEFAULT
empty
DESCRIPTION
This application option is used with the lib.workspace.exclude_design_filters application
option to determine which designs are loaded into the library workspace when you run
commands such as read_db, read_lib, read_lef, read_gds, and read_ndm.
By default, all designs in a source library file are loaded into the library workspace by the
read commands and none are excluded.
The comparisons are done in two steps:
If a design name matches any exclude filter, the design is not loaded into the library
workspace.
If a design name matches any include filter (or if there are no include filters), the design
is loaded into the library workspace. Note that if you specify an include filter, any design
that does not match the filter is not loaded into the library workspace.
These options are useful for splitting your libraries into more or finer groups. You can
accomplish the same effect by reading all the source libraries, building collections of designs
to remove by using the get_lib_cells command and manipulating those collections, and
then using the remove_lib_cells command. Both methods work, but using the read filters is
more efficient.
If you specify any filters, the tool issues a one-line notation for each included design. For
example, if you set the include filter to AN2 and used read_db, you might see this:
... including AN2
316
If you read an NDM file which might contain several views of the same design, you might see
this:
... including AN2/frame
... including AN2/design
SEE ALSO
read_db(2)
read_lib(2)
read_lef(2)
read_gds(2)
read_ndm(2)
get_lib_cells(2)
remove_lib_cells(2)
set_app_options(2)
lib.workspace.exclude_design_filters(3)
Chapter 1:
317
1-317
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.workspace.keep_all_physical_cells
Specifies whether the generated reference library includes cells from physical sources
which don't have any contribution from a logical source.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to false, The generated reference library contains the cells that exist in both the
logic and physical library files. If the physical library files contain additional cells that are not
in the logic library files, they are not included in the generated reference library. When set to
true, the additional cells that are not in the logic library files, they will be built into the
generated reference library, but no timing view.
SEE ALSO
set_app_options(2)
lib.workspace.keep_all_physical_cells
318
lib.workspace.remove_frame_bus_properties
Specifies whether remove bus properties which exist in frame view but not in timing view.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, bus properties which exist in frame views but not in timing views will be
removed automatically by command check_workspace
SEE ALSO
LM-095(n)
LM-096(n)
set_app_options(2)
Chapter 1:
lib.workspace.remove_frame_bus_properties
319
1-319
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib.workspace.save_layout_views
Specifies whether layout views from GDS input will be saved.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, read_gds and check_workspace will keep layout views in the result
library.
SEE ALSO
read_gds(2)
check_workspace(2)
set_app_options(2)
lib.workspace.save_layout_views
320
lib_attributes
Lists the predefined attributes for library objects.
DESCRIPTION
Attributes are properties assigned to objects such as pins, cells and nets. Definitions for lib
command.
Library Attributes
capacitance_unit
A string attribute representing the capacitance unit for this library.
characterization_points
A string attribute representing the characterization points of this library.
current_unit
A string attribute representing the current unit for this library.
extended_name
A string attribute representing the full path to the library directory of this library plus the
library name, separated by a ':' character. For example, "/disks/user1/work/
tech_lib:tech_lib".
full_name
A string attribute for the name of a library.
Chapter 1:
lib_attributes
321
1-321
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
is_current
A Boolean attribute. The value will be "true" if this library is the current_lib for the session,
"false" otherwise.
is_hidden
A Boolean attribute. The value will be "true" if this library is implicitly opened as reference
library, "false" otherwise.
is_lib_cell_lib
A Boolean attribute. The value will be "true" if this library is a lib-cell library created from
icc2_lm shell.
is_mask_shiftable
A Boolean attribute. If the value is "true" then this library enables multi-patterning mask
shifting of cells. If "false", the mask_shift of any cell which references a lib_cell or block in
this library will be ignored.
is_modified
A Boolean attribute. The value will be "true" if this library has modified and un-saved data,
false otherwise.
name
A string attribute for the name of a library.
object_class
A string attribute with the value of "lib". Each object class has a different object class value.
open_count
open_mode
A string attribute representing the open-mode of the library. Valid values are "read" and
"append".
lib_attributes
322
read_from_schema_version
A string attribute representing the schema version of the library file,in
(major_version.minor_version) format.
ref_libs
A string attribute representing the list of reference libraries.
resistance_unit
A string attribute representing the resistance unit for this library.
save_mode
A string attribute representing the save mode of this library. Valid values are "file" and
"directory".
scale_factor
Length precision used in this library. This attribute is read only.
source_file_name
A string attribute representing the full path to the source file of this library.
switch_list
A string attribute representing the effective view switch list of this library. The view switch list
of a design is the precedence-ordered list of design views that is applied when attempting to
bind it. If a design in this library does not have a view switch list explicitly set, then the
effective view switch list of this library (this attribute value) is applied to the design.
tech
A collection attribute of technology of this library.
tech_lib
A collection attribute of technology library of this library.
tech_name
A string attribute for the name of technology of this library.
Chapter 1:
lib_attributes
323
1-323
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
temperature_unit
A string attribute representing the temperature unit for this library.
voltage_unit
A string attribute representing the voltage unit for this library.
SEE ALSO
find(2)
get_attribute(2)
list_attributes(2)
lib_attributes
324
lib_cell_attributes
Lists the predefined attributes for lib_cells.
DESCRIPTION
lib_cell attributes are provided in the subsections that follow.
command.
Library Cell Attributes
area
A float attribute for the area of a lib_cell.
base_name
A String attribute for the name of a lib_cell. This name does not include a library prefix.
disable_timing
A Boolean attribute that is true if the lib_cell is marked as disable_timing in the library. This
attribute can be set in icc2_lm_shell.
dont_touch
A Boolean attribute that is true if the lib_cell is marked as dont_touch to prevent optimization
from changing any instances of this lib_cell. This is a settable attribute.
dont_use
A Boolean attribute that is true if the lib_cell is marked as dont_use to prevent optimization
from inserting instances of this lib_cell. This is a settable attribute.
Chapter 1:
lib_cell_attributes
325
1-325
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
extended_name
A String attribute representing the full path to the source .db file of the library containing this
lib_cell plus the full name of the lib_cell, separated by a ':' character. For example, "/disks/
user1/work/tech_lib.db:tech_lib/AN2".
full_name
A String attribute for the name of a lib_cell. This name includes a prefix for the library of the
lib_cell.
function_id
A String attribute representing the logic function of the lib_cell.
is_black_box
A Boolean attribute. The value will be "true" if this lib_cell has no logic function.
is_combinational
A Boolean attribute that is true if the lib_cell is not sequential.
is_fall_edge_triggered
A Boolean attribute that is true if the lib_cell has timing behavior relative to the falling edge
of a clock signal. This attribute can be set in icc2_lm_shell.
is_integrated_clock_gating_cell
A Boolean attribute that is true if the lib_cell is defined in the library as an integrated clock
gating cell. This attribute can be set in icc2_lm_shell.
is_memory_cell
A Boolean attribute that is true if the lib_cell is defined in the library as a memory cell. This
is_mux
A Boolean attribute that is true if the lib_cell is a mux.
lib_cell_attributes
326
is_negative_level_sensitive
A Boolean attribute that is true if the lib_cell has negative level-sensitive timing behavior, as
in a negative D-latch. This attribute can be set in icc2_lm_shell.
is_pad_cell
A Boolean attribute that is true if the lib_cell is defined in the library as a pad cell.
is_positive_level_sensitive
A Boolean attribute that is true if the lib_cell has positive level-sensitive timing behavior, as
in a positive D-latch. This attribute can be set in icc2_lm_shell.
is_rise_edge_triggered
A Boolean attribute that is true if the lib_cell has timing behavior relative to the rising edge
of a clock signal. This attribute can be set in icc2_lm_shell.
is_sequential
A Boolean attribute that is true if the lib_cell has sequential logic function.
is_three_state
A Boolean attribute that is true if the lib_cell has one or more three_state outputs. This
is_isolation
A Boolean attribute that is true if the lib_cell is a isolation cell.
is_level_shifter
A Boolean attribute that is true if the lib_cell is a level shifter cell.
is_enable_level_shifter
A Boolean attribute that is true if the lib_cell is a enable level shifter cell.
is_retention
A Boolean attribute that is true if the lib_cell is a retention cell.
Chapter 1:
lib_cell_attributes
327
1-327
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
is_power_switch
A String attribute that is true if the lib_cell is a power switch cell.
level_shifter_type
A String attribute with the value "HL" if the level shifter is of type "high-to-low", "LH" if the
level shifter is of type "low-to-high" and "HL_LH" if the level shifter is of type "high-to-low
low-to-high". Empty string is returned in case input library cell is not a level-shifter.
number_of_pins
An integer attribute representing the number of pins on this lib_cell.
object_class
A String attribute with the value of "lib_cell". Each object class has a different object class
value.
power_switch_type
A String attribute with the value "header" if the power switch is a header cell and " footer" if
the power switch is a footer cell. Empty string is returned in case input library cell is not a
power-switch.
retention_cell_style
A String attribute which returns the retention-cell-type of the lib-cell.
subset_name
A String attribute indicating the lib_cell subset name for LEQ. All lib_cells with no subset
name also form a subset, which is used by the technology mapping function. Named
subsets are used for special lib_cells (e.g., clock buffers that are specifically designed to
match the delay of certain clock gates).
SEE ALSO
find(2)
get_attribute(2)
list_attributes(2)
lib_cell_attributes
328
lib_pin_attributes
Lists the predefined attributes for lib_pins.
DESCRIPTION
lib_pin attributes are provided in the subsections that follow.
command.
Library Pin Attributes
base_name
A string attribute for the name of a lib_pin. This name does not include a library, lib_cell
prefix.
clock
A Boolean attribute that is true if the lib_pin is defined as a clock in the library.
direction
A string attribute for the direction of a pin. Possible values are in, out, inout, or unknown.
disable_timing
A Boolean attribute that is true if the lib_pin is marked as disable_timing in the library.
extended_name
A string attribute representing the full path to the source .db file of the library containing this
lib_pin plus the full name of the lib_pin, separated by a ':' character. For example, "/disks/
user1/work/tech_lib.db:tech_lib/AN2/Z".
Chapter 1:
lib_pin_attributes
329
1-329
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
full_name
A string attribute for the name of a lib_pin. This name includes a prefix for the library and
lib_cell of the lib_pin.
function
A string attribute on output or inout lib_pins for the logic function. The logic function is
defined in the library.
is_async_pin
A Boolean attribute that is true if this lib_pin is a preset or clear pin.
is_clear_pin
A Boolean attribute that is true if this lib_pin is a clear (reset) pin.
is_clock_pin
A Boolean attribute that is true for clock pins of registers. A clock pin is any pin that has a
timing check from it to a data pin.
is_data_pin
A Boolean attribute that is true for data pins of registers. A data pin is any pin that has a
timing check to it.
is_fall_edge_triggered_clock_pin
A Boolean attribute that is true for clock pins of registers with falling edge-triggered behavior.
is_fall_edge_triggered_data_pin
A Boolean attribute that is true for data pins of registers with falling edge-triggered behavior.
is_negative_level_sensitive_clock_pin
A Boolean attribute that is true for clock pins of latches with negative level-sensitive
behavior.
is_negative_level_sensitive_data_pin
A Boolean attribute that is true for data pins of latches with negative level-sensitive behavior.
lib_pin_attributes
330
is_positive_level_sensitive_clock_pin
A Boolean attribute that is true for clock pins of latches with positive level-sensitive behavior.
is_positive_level_sensitive_data_pin
A Boolean attribute that is true for data pins of latches with positive level-sensitive behavior.
is_preset_pin
A Boolean attribute that is true if this lib_pin is an asynchronous preset pin.
is_rise_edge_triggered_clock_pin
A Boolean attribute that is true for clock pins of registers with rising edge-triggered behavior.
is_rise_edge_triggered_data_pin
A Boolean attribute that is true for data pins of registers with rising edge-triggered behavior.
is_secondary_pg
A Boolean attribute that is true if this is a secondary PG pin.
is_three_state
A Boolean attribute. Possible values are "true" and "false". A library pin is a three-state pin
if there are three-state enable and or three-state disable arcs from or to that pin.
is_three_state_enable_pin
A Boolean attribute. Possible values are "true" and "false". A library pin is a three-state
enable pin if there are three-state enable and or three-state disable arcs from that pin.
is_three_state_output_pin
A Boolean attribute. Possible values are "true" and "false". A library pin is a three-state
output pin if there are three-state enable and or three-state disable arcs to that pin.
object_class
A string attribute with the value of "lib_pin". Each object class has a different object class
value.
Chapter 1:
lib_pin_attributes
331
1-331
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
pg_type
Specifies the PG type of the pin. Possible values are primary, backup and internal.
physical_status
A string attribute representing the physical placement status of the lib_pin. Valid values are
unplaced, placed, fixed, and locked. If status is unplaced, the lib_pin has not been placed. If
status is placed, the lib_pin has been placed and may be moved. If status is fixed, the lib_pin
is fixed for automatic changes. If status is locked, the lib_pin is fixed for automatic and
manual changes. This is a settable attribute.
pin_capacitance
A float attribute representing the capacitance of this lib_pin.
pin_direction
This is the same as "direction". This variable is supported for compatibility with other tools.
The "direction" attribute is supported for both ports and pins and therefore easier to use for
heterogeneous collections of pins and ports.
three_state_function
A string attribute on output or inout lib_pins for the three_state logic function. The
three_state logic function is defined in the library. If the three_state logic function evaluates
to zero, then the lib_pin is enabled.
SEE ALSO
find(2)
get_attribute(2)
list_attributes(2)
lib_pin_attributes
332
lib_timing_arc_attributes
man page to document the available lib_timing_arc attributes.
DESCRIPTION
lib_timing_arc attributes are provided in the subsections that follow.
command.
Library Timing Arc Attributes
from_lib_pin
A collection attribute returning the from library pin for a lib_timing_arc. If this lib_timing_arc
is for a timing check such as setup or hold, the from pin is the clock pin of the check.
is_disabled
A Boolean attribute for whether this library timing arc is disabled. Library timing arcs may be
disable either because the user has disabled it with the command set_disable_timing or
because of mode settings.
is_user_disabled
A Boolean attribute for whether this library timing arc is disabled because of a
set_disable_timing command.
mode
A string attribute with the name of the mode this lib timing arc is active for. The attribute will
is only defined for moded arcs.
Chapter 1:
333
1-333
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
object_class
The possible object classes are: design, cell, pin, port, net, lib, lib_cell, lib_pin, clock, mode,
sense
A string attribute for the sense of a lib_timing_arc. Possible values are
rising_edgerising_to_rise falling_to_rise
falling_edge rising_to_fall falling_to_fall
rise_to_rise fall_to_rise rise_to_fall
fall_to_fall positive_unate negative_unate
non_unate clear_high clear_low
clear_both preset_high preset_low
preset_both disable_high disable_low
disable_both disable_high_rise
disable_low_rise disable_both_rise
disable_high_fall disable_low_fall
disable_both_fall
enable_high enable_low enable_both
enable_high_rise enable_low_rise enable_both_rise
enable_high_fall enable_low_fall enable_both_fall
retain_rising_edge retain_rise_to_rise
retain_fall_to_rise retain_falling_edge
retain_rise_to_fall retain_fall_to_fall
retain_positive_unate retain_negative_unate
retain
max_clock_tree_positive_unate max_clock_tree_rise_to_rise
max_clock_tree_fall_to_fall max_clock_tree_negative_unate
max_clock_tree_rise_to_fall max_clock_tree_fall_to_rise
max_clock_tree_non_unate min_clock_tree_positive_unate
min_clock_tree_rise_to_rise min_clock_tree_fall_to_fall
min_clock_tree_negative_unate min_clock_tree_rise_to_fall
min_clock_tree_fall_to_rise min_clock_tree_non_unate
nonseq_setup_clk_rise nonseq_setup_rise_clk_rise
nonseq_setup_fall_clk_rise nonseq_setup_clk_fall
nonseq_setup_rise_clk_fall nonseq_setup_fall_clk_fall
nonseq_hold_clk_rise nonseq_hold_rise_clk_rise
nonseq_hold_fall_clk_rise nonseq_hold_clk_fall
nonseq_hold_rise_clk_fall nonseq_hold_fall_clk_fall
clock_gating_setup_clk_rise clock_gating_setup_rise_clk_rise
clock_gating_setup_fall_clk_rise clock_gating_setup_clk_fall
clock_gating_setup_rise_clk_fall clock_gating_setup_fall_clk_fall
clock_gating_hold_clk_rise clock_gating_hold_rise_clk_rise
to_lib_pin
A collection attribute returning the to library pin for a lib_timing_arc. If this lib_timing_arc is
for a timing check such as setup or hold, the from pin is the data pin of the check.
334
when
A string attribute returning the when value for the lib_timing_arc.
SEE ALSO
get_attribute(2)
list_attributes(2)
Chapter 1:
335
1-335
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
link.bit_blast_naming_style
Specifies the naming format for blasted bus bits which will be used during linking to resolve
differences of bus bit naming styles between instance and its reference.
TYPE
list_of_string
DEFAULT
%s(%d) %s_%d_
DESCRIPTION
The linker will not bind any verilog instance to its reference when blasted bus ports across
the two don't match which may be due to different naming styles of bit blasted ports. In order
to enable linker to understand compatible bit blasted bus ports having different naming
styles this app option is used.
This app option is a list of string where each value must contain one occurrence each of %s
and %d and it must start with %s followed by the %d. Later when multi dimension bus will
be supported, this format will be enhanced.
EXAMPLES
Following example will allow verilog instance with port A[0] and A[1] to match the reference
with ports A_0 and A_1.
prompt> set_app_options -name link.bit_blast_naming_style -value %s_%d
link.bit_blast_naming_style %s_%d
Following example is for different references having different naming styles.

prompt> set_app_options -name link.bit_blast_naming_style -value {%s_%d
%s(%d)}
link.bit_blast_naming_style {%s_%d %s(%d)}
link.bit_blast_naming_style
336
link.prefer_frame
Controls whether the tool uses the frame view, if it exists, or the Verilog module stubs when
linking a newly read Verilog netlist.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
By default (true), if a block has a frame view, the tool uses the frame view when linking a
newly read Verilog netlist.
To use the Verilog module stubs instead of the frame view, set this application option to
false.
SEE ALSO
link_block(2)
read_verilog(2)
get_app_options(2)
set_app_options(2)
Chapter 1:
link.prefer_frame
337
1-337
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
link.reference_limit
Specifies the maximum number of detailed unresolved reference errors to display for each
block when linking the design.
TYPE
integer
DEFAULT
12
DESCRIPTION
In many cases, many link errors have the same root cause, such as a missing leaf cell
library. Subsequent error messages do not provide additional information to resolve the
issue. This option allows you to control the maximum number of errors displayed for each
block before the tool moves to the next design in the physical design hierarchy. After the
specified limit has been reached, the tool outputs a summary of the number of unresolved
references.
By default, the tool displays a maximum of 12 detailed unresolved reference errors.
To display all unresolved reference error messages, set this option to -1.
SEE ALSO
link_block(2)
get_app_options(2)
set_app_options(2)
link.reference_limit
338
link.require_physical
Controls whether subblocks must have physical information.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
To create the physical hierarchy for a block, the tool requires that all subblocks have
physical information.
By default (true), the tool verifies that all subblocks have physical information when it links
a block.
An improperly prepared library cell library might contain some library cells that do not have
a physical description. You can link a block with subblocks that are missing physical
information by setting this option to false. However, subsequent commands might give
unexpected results with these designs.
SEE ALSO
link_block(2)
get_app_options(2)
set_app_options(2)
Chapter 1:
link.require_physical
339
1-339
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
link.undo_enabled
Controls whether to keep undo information so the link_block command can be undone with
the undo command.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
The link_block command makes considerable changes when first linking a design read
from Verilog. By default (false), these changes cannot be undone by the undo command.
You can enable the changes made by the link_block command to be undone by setting this
option to true. However, this can cause the undo cache to grow very large. If there are
problems when linking the design, you typically reread the design from Verilog, so there is
less value in allowing the link_block command to be undone.
For more information, see the undo man page.
SEE ALSO
link_block(2)
redo(2)
undo(2)
get_app_options(2)
set_app_options(2)
link.undo_enabled
340
link.user_units_from_first_library
Controls whether the tool uses the units from the first library cell library in the reference
library list or from the values set by the set_user_units command.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
By default (true), the tool uses the units from the first library cell library in the reference
library list. This makes the tool consistent with other tools, such as Design Compiler and IC
Compiler.
When this option is set to false, the tool uses the units that you specify with the
set_user_units command, which is the recommended method.
SEE ALSO
link_block(2)
get_app_options(2)
set_app_options(2)
Chapter 1:
link.user_units_from_first_library
341
1-341
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
link.verbose
Controls whether the tool outputs verbose messages when linking a block.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
Verbose messages can help you debug link issues, but for most design flows they are
unnecessary.
By default, the tool does not issue verbose message when linking a block.
To enable verbose messages during linking, set this option to true.
SEE ALSO
link_block(2)
get_app_options(2)
set_app_options(2)
link.verbose
342
link_path
link_path Obsolete list of libraries, design files, and library files once used during linking.
TYPE
list
DESCRIPTION
The link_path variable is is obsolete. It is no longer used by the link_design command to
resolve design references. You may set and use this variable in your scripts, but it will not
affect linking.
Use the set_ref_libs command to tell the linker which libraries to use to locate designs to
resolve references and bind sub-designs.
The default value of link_path is "". To determine the current value of this variable, type
printvar link_path or echo $link_path.
SEE ALSO
link_design(2)
printvar(2)
set_ref_libs(2)
search_path(3)
Chapter 1:
link_path
343
1-343
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
matching_type_attributes
Lists the predefined attributes for matching_types.
DESCRIPTION
matching_type attributes are provided in the subsections that follow.
command.
Matching Type Attributes
full_name
A string attribute for the name of the matching_type.
name
A string attribute for the name of the matching_type. This attribute is settable.
object_class
A string attribute with the value of "matching_type".
objects
A collection attribute with the cells, pins, and terminals in the matching_type.
uniquify_number
An integer attribute for the uniquify number of the matching_type. Valid values are in the
range [-4, 8]. If the value is > 0, the value indicates the number of pad pins that may be
assigned to a single bump cell, and no two bump cells may be assigned to the same pad pin.
If the value is < 0, the absolute value indicates the number of bump cells that must be
344
assigned to each pad pin, and no two pad pins may be associated to the same bump cell. If
the value = 0, only 1 bump cell is assigned to all pad pins. This attribute is settable.
SEE ALSO
get_attribute(2)
list_attributes(2)
Chapter 1:
345
1-345
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
mode_attributes
Description of the predefined attributes for modes.
DESCRIPTION
mode attributes are provided in the subsections that follow.
command.
Mode Attributes
file_line_info
full_name
A string attribute for the name of a mode.
is_current
A Boolean attribute. The value will be "true" if this mode is the current mode, "false"
otherwise.
is_default
A Boolean attribute. The value will be "true" if this mode is the default mode, "false"
otherwise.
object_class
A string attribute with the value of "mode". Each object class has a different object class
value.
mode_attributes
346
SEE ALSO
create_mode(2)
get_attribute(2)
list_attributes(2)
Chapter 1:
mode_attributes
347
1-347
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
module_attributes
Description of the predefined attributes for modules.
DESCRIPTION
module attributes are provided in the subsections that follow.
command.
Module Attributes
full_name
A string attribute for the full name of a module.
is_outline
A Boolean attribute. The value will be "true" if this module is an outline module. That is, the
design owning it an outline view.
object_class
A string attribute with the value of "module".
outline_def_file_name
A string attribute representing the outline def file for this module
outline_def_file_size
A string attribute representing the size of the outline def file.
module_attributes
348
outline_def_file_timestamp
A string attribute representing the timestamp of the outline def file.
outline_file_line_end
An integer attribute representing the end line of outline file
outline_file_line_start
An integer attribute representing the start line of outline file
outline_file_name
A string attribute representing the outline file for this module, usually the source verilog file.
outline_file_size
An integer attribute representing the size of the outline file.
outline_file_timestamp
A string attribute representing the timestamp of the outline file.
outline_port_count
An integer attribute representing the ports on the module.
outline_ref_count
A string attribute representing the ref count of the module.
SEE ALSO
get_modules(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
module_attributes
349
1-349
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
mv.pg.default_ground_supply_net_name
Specifies default ground supply net name.
TYPE
String
DEFAULT
VSS
DESCRIPTION
This variable specifies the default ground supply net name for default power domain flow.
SEE ALSO
mv.pg.default_ground_supply_net_name
350
mv.pg.default_ground_supply_port_name
Specifies default ground supply port name.
TYPE
String
DEFAULT
VSS
DESCRIPTION
This variable specifies the default ground supply port name for default power domain flow.
SEE ALSO
Chapter 1:
mv.pg.default_ground_supply_port_name
351
1-351
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
mv.pg.default_power_supply_net_name
Specifies default power supply net name.
TYPE
String
DEFAULT
VDD
DESCRIPTION
This variable specifies the default power supply net name for default power domain flow.
SEE ALSO
mv.pg.default_power_supply_net_name
352
mv.pg.default_power_supply_port_name
Specifies default power supply port name.
TYPE
String
DEFAULT
VDD
DESCRIPTION
This variable specifies the default power supply port name for default power domain flow.
SEE ALSO
Chapter 1:
mv.pg.default_power_supply_port_name
353
1-353
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
mv.upf.connect_supply_net_ignore_nonexistent_objects
Allows connect_supply_net command to ignore nonexistent objects.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This option controls whether connect_supply_net command ignores nonexistent objects. By
default, the connect_supply_net command errors out when a nonexistent object is specified.
SEE ALSO
connect_supply_net(2)
mv.upf.connect_supply_net_ignore_nonexistent_objects
354
mv.upf.enable_pg_pin_reconnection
Allows connect_supply_net to reconnect power and ground pins.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This option controls whether or not to allow reconnection to power and ground pins. By
default, the connect_supply_net command errors out when connecting a supply net to a PG
pin that has an existing explicit supply net connection.
By setting this option to true, the connect_supply_net command reconnects the new supply
net to the PG pin and the previous connection is discarded.
SEE ALSO
Chapter 1:
mv.upf.enable_pg_pin_reconnection
355
1-355
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
mv.upf.input_enforce_simple_names
Enforces the use of simple names for restricted commands as per the IEEE 1801 (UPF)
standard.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This option controls the use of hierarchical names for the arguments of certain restricted
commands that require simple names as per the IEEE 1801 (UPF) standard.
The default value of this option is false. So, by default, the tool accepts hierarchical names,
even though the IEEE 1801 (UPF) standard requires them to be simple.
When you set this option to true, the tool errors out when you use hierarchical names for the
arguments of certain restricted commands.
SEE ALSO
load_upf(2)
mv.upf.input_enforce_simple_names
356
mv.upf.load_upf_continue_on_error
load_upf does not stop on errors.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This option controls whether load_upf command stops reading the UPF file on errors.
Similar to setting the shell variable sh_continue_on_error to true, but only applies to this
particular load_upf command.
SEE ALSO
load_upf(2)
Chapter 1:
mv.upf.load_upf_continue_on_error
357
1-357
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
mv.upf.max_supply_count_without_driver
Maximum limit of supply nets without legal driver in the design
TYPE
Integer
DEFAULT
7
DESCRIPTION
When a UPF supply net does not have a valid driver object, commit_upf issues a UPF-176
warning, indicating that there may be problems with the UPF constraints since all supplies
should have a valid driver. By default, once seven of these warnings are issued, the tool then
issues a UPF-177 error, indicating that too many supply nets without drivers have been
detected.
This app option controls the threshold for issuing the UPF-177 error. If a large number of
UPF-176 warnings are expected with the current UPF constraints, this app option can be
used to increase the UPF-177 threshold and avoid the error. Regardless of whether the
UPF-177 error message is issued or not, any supply nets which missing drivers should
eventually be cleaned up to ensure proper and complete power intent.
WHAT NEXT
UPF-176 warning messages indicates which supplies do not have valid drivers. See the
UPF-176 manpage for additional information.
SEE ALSO
commit_upf(2)
UPF-176(2)
UPF-177(2)
mv.upf.max_supply_count_without_driver
358
mv.upf.name_map_version
This option specifies the default version of name mapping to be used for applying UPF to the
design.
TYPE
enum
DEFAULT
none
DESCRIPTION
This option specifies the default version of name mapping to be used for applying UPF to the
design. The default value of this option is none, and it means that name mapping will not be
applied to UPF constraints. "v1.0" is the only supported option value.
SEE ALSO
load_upf(2)
Chapter 1:
mv.upf.name_map_version
359
1-359
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
mv.upf.save_upf_include_supply_exceptions
Specifies whether save_upf should include explicit supply net connections in the
supplemental UPF section.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
Specifies whether the supplemental UPF section in the output UPF should include explicit
supply net connections.
SEE ALSO
save_upf(2)
mv.upf.save_upf_include_supply_exceptions
360
mv.upf.upf_bias_support
Enables the UPF bias support functionality.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This option enables the UPF bias support. Please note this app option needs to be set to
TRUE, in order to access the full bias functionality. You still need to use the following
command to control the bias functionality for each individual block. set_design_attributes
-element {.} -attribute enable_bias TRUE
If this app option is FALSE, the library cells with or without bias pins will be treated as
equivalent for the optimization purposes, irrespective of the enable_bias attribute.
If this app option is TRUE, for the blocks with enable_bias design attribute TRUE, tool will
use library cells with the bias pins. And for the blocks with enable_bias design attribute
FALSE, tool will use library cells without the bias pins.
SEE ALSO
set_design_attributes(2)
Chapter 1:
mv.upf.upf_bias_support
361
1-361
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
net_attributes
Description of the predefined attributes for nets.
DESCRIPTION
Attributes are properties assigned to objects such as pins, cells and nets. Definitions for net
command.
Net Attributes
antenna_rule_name
A string attribute representing the antenna rule that is associated with the net.
base_name
A string attribute for the name of a net. This name does not include a the instance path
prefix.
full_name
A string attribute for the name of a net. This name includes a prefix for the instance path to
this net.
is_global
A Boolean attribute. Possible values are "true" and "false". Global nets are those tied to logic
0 and logic 1.
max_layer
A collection attribute with the maximum routing layer that is active on this net.
net_attributes
362
max_layer_mode
A string attribute representing the maximum routing layer mode that is set on this net. Valid
values are unknown, soft, allow_pin_connections, and hard. This is a settable attribute.
max_layer_mode_soft_cost
A string attribute representing the maximum routing layer mode soft cost that is set on this
net. Valid values are unknown, low, medium, and high. This is a settable attribute.
max_layer_name
A string attribute for the name of the maximum routing layer that is active on this net.
min_layer
A collection attribute with the minimum routing layer that is active on this net.
min_layer_mode
A string attribute representing minimum routing layer mode that is set on this net. Valid
values are unknown, soft, allow_pin_connections, and hard. This is a settable attribute.
min_layer_mode_soft_cost
A string attribute representing the minimum routing layer mode soft cost that is set on this
net. Valid values are unknown, low, medium, and high. This is a settable attribute.
min_layer_name
A string attribute for the name of the minimum routing layer that is active on this net.
net_type
A string attribute representing the type of the net. Valid values are analog_ground,
analog_power, analog_signal, clock, deep_nwell, deep_pwell, ground, nwell, power, pwell,
reset, scan, signal, tie_high, tie_low, and unset. This is a settable attribute.
object_class
Chapter 1:
net_attributes
363
1-363
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
parent_block
A collection attribute with the owner block object for this net.
parent_cell
A collection attribute with the owner cell object for this net.
parent_block_cell
A collection attribute with the parent block cell object for this net.
physical_status
A string attribute representing the physical modification status of the net routes. If status is
unrestricted, the router may freely reroute this net. If the status is minor_change, the router
may make minor changes to this net's routes. If the status is locked, the router may not
reroute this net. This is a settable attribute.
rc_setup_criticality
A string attribute representing the setup time criticality preference of a net. Router uses this
to decide whether the net should be routed on lower RC layers for setup time optimization.
Possible values are "none", "low", "medium", and "high. This is a settable attribute.
rc_hold_criticality
A string attribute representing the hold time criticality preference of a net. Router uses this
to decide whether the net should be routed on lower RC layers for hold time optimization.
Possible values are "none", "low", "medium", and "high. This is a settable attribute.
routing_blockage_group_id
A integer attribute in the range from 1 to 8 that specifies the group-id of routing_blockages
that associates with this net. For example, if a net's routing_blockage_group_id attribute is
set to value 3, then all routing_blockages assigned the blockage_group_id number 3 will
block routing of that net in the layers specified for the routing_blockages. This is a settable
attribute and setting this attribute is the only way to associates specific nets with
routing_blockages. This attribute is 0 by default and doesn't apply for the net_type based
association of routing_blockages.
net_attributes
364
routing_blockages
A collection attribute representing all the routing_blockages having the same
blockage_group_id as the routing_blockage_group_id attribute of this net. Doesn't apply for
the net_type based association of routing_blockages.
synonyms
A string attribute containing the synonym names of this net. An empty string indicates that
this net has no synonyms. Synonyms allow this net to be referenced by one of its synonym
names. This is a settable attribute.
top_block
A collection attribute with the top block object for this net.
voltage_range_max
A float attribute representing the maximum logic-one voltage of a net, across all corners. For
signal nets, it is based on the output voltage of the net's drivers. For power nets, it is based
on the voltage set on the corresponding supply_net.
voltage_range_min
A float attribute representing the minimum logic-one voltage of a net, across all corners. For
signal nets, it is based on the output voltage of the net's drivers. For power nets, it is based
on the voltage set on the corresponding supply_net.
SEE ALSO
get_attribute(2)
list_attributes(2)
Chapter 1:
net_attributes
365
1-365
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
opt.area.effort
Control the optimization effort for area recovery.
TYPE
String
DEFAULT
low
DESCRIPTION
Enable higher effort area recovery in preroute flows.
The area recovery effort can be: low, medium, high or ultra. Area recovery trades off
between TNS and area. Area recovery effort low recovers the least area and degrades TNS
the least, while area recovery effort ultra recovers the most area and degrades TNS the
most.
SEE ALSO
place_opt(2)
set_app_options(2)
opt.area.effort
366
opt.common.allow_physical_feedthrough
Set whether to allow physical feedthroughs in MVDD designs
TYPE
bool
DEFAULT
false
DESCRIPTION
This option determines if an MVDD design should allow physical feedthroughs. A physical
feedthrough cell is one that physically belongs to a voltage area, but logically does not. In
ICC2, these cells are marked with power domain on instance in the UPF.
SEE ALSO
place_opt(2)
clock_opt(2)
set_app_options(2)
Chapter 1:
opt.common.allow_physical_feedthrough
367
1-367
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
opt.common.buffer_area_effort
Effort level for buffer area usage in data path optimization.
TYPE
string
DEFAULT
low
DESCRIPTION
This option sets the effort level for reducing buffer area usage in data path optimization.
Default value is low. Effort level medium, high and ultra can be set for reducing buffer area
usage further. QoR degradation can occur, and it is not guaranteed that buffer area will
reduce at each effort level.
SEE ALSO
place_opt(2)
clock_opt(2)
set_app_options(2)
opt.common.buffer_area_effort
368
opt.common.do_physical_checks
TYPE
string
DEFAULT
never
DESCRIPTION
Specifies when physical design checks are performed during optimization. Recognized
values are never, legalize and always. The default value, never, usually gives the fastest
runtime, but there may be power strap, pin access or other violations reported by
check_legality after optimization.
Using the value of legalize causes physical design checks to be activated during
legalization. This may cause an increase in runtime, but should result in no violations after
optimization. Using the value of always will result in a significant increase in runtime. This
may produce better results if there are a significant number of cells that are highly restricted
in their placement due to pre-routed metal.
SEE ALSO
check_legality(2)
legalize_placement(2)
place_opt(2)
Chapter 1:
opt.common.do_physical_checks
369
1-369
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
opt.common.enable_target_library_subset_opt
TYPE
integer
DEFAULT
0
DESCRIPTION
Setting this option to 1 enables the target library subset flow in a design. By default this
option is not enabled.
Enabling this option may cause an increase in runtime, so it is advised to enable this option
only when the user has defined target library subsets in the design.
Note: If a design doesn't have any user defined target library subsets, then enabling this
option will create a default target library subset on the TOP hierarchy of the design with all
the reference libraries included as the target libraries for this default target library subset.
SEE ALSO
set_target_library_subset(2)
report_target_library_subset(2)
remove_target_library_subset(2)
set_app_options(2)
opt.common.enable_target_library_subset_opt
370
opt.common.max_fanout
Fanout constraint for data path optimization.
TYPE
int
DEFAULT
999
DESCRIPTION
This option sets a fanout constraint for optimization of data path cells in place_opt and
clock_opt. Optimization will try to ensure that data path cells do not drive more than
max_fanout cells. This is a soft constraint.
SEE ALSO
place_opt(2)
clock_opt(2)
set_app_options(2)
Chapter 1:
opt.common.max_fanout
371
1-371
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
opt.common.max_net_length
Net length constraint for data path optimization.
TYPE
float
DEFAULT
0.0
DESCRIPTION
This option sets a net length constraint in um for optimization of data path cells in place_opt
and clock_opt. Optimization will try to ensure that data path cells do not drive nets with
length more than max_net_length. The maximum driver to fanout pin distance is considered
to be the net length. Default value of 0.0 means this constraint is ignored. This is a soft
constraint.
SEE ALSO
place_opt(2)
clock_opt(2)
set_app_options(2)
opt.common.max_net_length
372
opt.common.preserve_pin_names
Controls sizing operations to only cells that are pin-name compatible.
TYPE
Enum
DEFAULT
"never"
DESCRIPTION
This option controls how the set of cells that can be used during sizing optimization is
determined. Possible values are "never" and "always". "never" is the default.
Assume that there are two buffer cells in the library. One buffer (buffA) has pins "A" and "O"
and the other (buffX) has pins "X" and "Z". When opt.common.preserve_pin_names is set
to "never", buffA can be replaced with buffX (and vice versa) during sizing optimization.
However, when opt.common.preserve_pin_names is set to "always", then buffA and
buffX are not interchangeable anymore.
SEE ALSO
place_opt(2)
clock_opt(2)
set_app_options(2)
Chapter 1:
opt.common.preserve_pin_names
373
1-373
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
opt.common.select_inverter
Select inverter directive for data path optimization.
TYPE
bool
DEFAULT
true
DESCRIPTION
This option directs data path optimization to not use inverters when false. By default,
inverters and buffers are both used as appropriate.
SEE ALSO
place_opt(2)
clock_opt(2)
set_app_options(2)
opt.common.select_inverter
374
opt.common.user_instance_name_prefix
The value of option opt.common.user_instance_name_prefix is used as prefix of names
of new cells created by place_opt, clock_opt, route_opt, create_buffer_trees, and
remove_buffer_trees.
TYPE
String
DEFAULT
""
DESCRIPTION
Users can specify a string to be prepended to new cell names in optimization by setting app
option value of opt.common.user_instance_name_prefix. This applies to cell names
created during data optimization. Names created during clock optimization are controlled by
cts.common.user_instance_name_prefix.
For example, if a cell is expected to be created by place_opt and to have name as
buft_p_60, then by setting opt.common.user_instance_name_prefix as "user_anno_"
before place_opt, the cell's name would be user_anno_buft_p_60 after place_opt.
Here is another example of usage:
set_app_option -name opt.common.user_instance_name_prefix -value
"place_opt_"
place_opt
"clock_opt_"
clock_opt
"route_opt_"
route_opt
SEE ALSO
set_app_options(2)
place_opt(2)
clock_opt(2)
Chapter 1:
375
1-375
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route_opt(2)
create_buffer_trees(2)
remove_buffer_trees(2)
cts.common.user_instance_name_prefix(3)
376
opt.dft.clock_aware_scan
Enable clock_opt to call clock driver aware dft optimization in post-cts optimization stage to
reduce hold violations along scan path.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
With this app_option turned on, clock_opt will call clock driver aware dft optimization in
post-cts optimization stage. This will typically result in scan connection structure which will
benefit hold violation reduction along scan path; however, the improvement will come at the
cost of increased total scan net length and possibly degraded timing QoR.
SEE ALSO
clock_opt(2)
set_app_options(2)
Chapter 1:
opt.dft.clock_aware_scan
377
1-377
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
opt.dft.optimize_scan_chain
Enable create_placement, place_opt and clock_opt to call dft optimization.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
With this app_option turned on, create_placement will run dft optimization step at then end.
place_opt and clock_opt will also have this step at each placement call. This will typically
result in better scan connection structure with shorted total scan wire length, which will
benefit routability or timing in later flow; however, these improvement will come at the cost
of increased tool runtime and possibly degraded timing QoR.
SEE ALSO
create_placement(2)
place_opt(2)
clock_opt(2)
set_app_options(2)
opt.dft.optimize_scan_chain
378
opt.leakage.effort
Enable mW leakage optimization in place_opt/clock_opt flows
TYPE
String
DEFAULT
off
DESCRIPTION
Preroute flows will run mW leakage optimization.
The leakage optimization effort can be: low, medium or high
It is recommended that the user specifies threshold voltage group for each library using the
command set_threshold_voltage_group_type.
For mW leakage optimization to run at least 1 corner should be power enabled.
SEE ALSO
place_opt(2)
set_threshold_voltage_group_type(2)
set_app_options(2)
Chapter 1:
opt.leakage.effort
379
1-379
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
opt.mcmm.dominant_scenarios
User specified dominant scenarios for optimization
TYPE
string
DEFAULT
null
DESCRIPTION
Optimization engine may combine scenarios or select a subset of scenarios to work on to
improve runtime. If specific scenarios needs more optimization, their names can be passed
to optimization engine through this app option.
SEE ALSO
opt.mcmm.use_synthetic_corners(2)
set_app_options(2)
opt.mcmm.dominant_scenarios
380
opt.mcmm.use_synthetic_corners
Enable synthetic corner technology to speed up optimization
TYPE
bool
DEFAULT
true
DESCRIPTION
Optimization engine can combine corners that have similar characteristics into synthetic
ones to reduce number of active corners and scenarios. With reduced number of corners
and scenarios, optimization can converge faster without losing QoR. The timing numbers for
scenarios with synthetic corners will be slightly pessimistic. In the optimization log, a QoR
summary will be printed after each optimization stage. The output for a regular scenario
would look like
Scenario Func.081v.125c_Cmax WNS = 1.217896, TNS = 264.570660
while the output for a synthetic scenario would look like
Scenario Func.081v.125c_Cmax+Func.081v.0c_Cmax WNS = 2.332123, TNS =
463.1123432 (pessimistic)
SEE ALSO
place_opt(2)
set_app_options(2)
Chapter 1:
opt.mcmm.use_synthetic_corners
381
1-381
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
opt.port.eliminate_verilog_assign
Ensure that there are no Verilog assigns in the output netlist of place_opt
TYPE
bool
DEFAULT
false
DESCRIPTION
This option ensures that the output Verilog netlist after place_opt has no assigns by
buffering such nets if they exist in the input Verilog, and avoiding punching ports during
optimization. false is the default.
opt.port.eliminate_verilog_assign
382
opt.power.mode
Enable dynamic power optimization in preroute flows.
TYPE
String
DEFAULT
none
DESCRIPTION
There are three modes for dynamic power optimization: none, dynamic and total. When this
option is set to none, dynamic power optimization will be turned off. When this option is set
to dynamic, only switching and internal power will be optimized. When this option is set to
total, the total power consumption comprising leakage, switching and internal power will be
optimized.
SEE ALSO
place_opt(2)
refine_opt(2)
clock_opt(2)
report_power(2)
set_app_options(2)
Chapter 1:
opt.power.mode
383
1-383
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
opt.preroute.physical_synthesis_effort
Control the effort level for physical exploration during synthesis
TYPE
enum
DEFAULT
none
DESCRIPTION
Allowed values are high, medium, and low. Setting it will affect how hard physical exploration
engine works during synthesis. Higher settings will induce higher CPU usage. Allowed
values are "none", "low", "medium", "high". Setting it to none and synthesis engine will not
explore physical space.
SEE ALSO
place_opt(2)
clock_opt(2)
refine_opt(2)
set_app_options(2)
opt.preroute.physical_synthesis_effort
384
opt.preroute_synthesis.architecture_booster_transform
Turn on re-synthesis of suboptimal arithmetic operators.
TYPE
boolean
DEFAULT
false
DESCRIPTION
Setting this variable to true will allow optimization engine to re-architecture suboptimal
arithmetic operators during physical synthesis. It can be used to speed up long data-path
chains by spending more resources.
Please note that re-architecture can induce regional area overhead so it is suggested only
used early in the optimization flow.
SEE ALSO
place_opt(2)
clock_opt(2)
refine_opt(2)
set_app_options(2)
Chapter 1:
opt.preroute_synthesis.architecture_booster_transform
385
1-385
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
opt.tie_cell.max_fanout
Maximum fanout a tie-cell can drive
TYPE
integer
DEFAULT
999
DESCRIPTION
During optimization, tie-cells will be inserted to drive constant pins if tie-cells were available
for optimization purpose. This option limits the maximum fanout each newly inserted tie-cell
can drive even if it can drive more pins without violating other constraints. If there are
pre-existing tie-cells in the design that violates max fanout constraint, they will be removed
and new tie-cells will inserted to satisfy the constraint unless pre-existing tie-cells have
dont_touch attribute.
SEE ALSO
place_opt(2)
set_lib_cell_purpose(2)
set_app_options(2)
opt.tie_cell.max_fanout
386
opt.timing.effort
Control the optimization effort for timing (WNS/TNS).
TYPE
String
DEFAULT
low
DESCRIPTION
Enable higher effort timing recovery in preroute flows.
The timing recovery effort can be: medium or high
SEE ALSO
place_opt(2)
set_app_options(2)
Chapter 1:
opt.timing.effort
387
1-387
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
outline_attributes
Description of the predefined attributes for outline modules.
DESCRIPTION
outline attributes are provided in the subsections that follow.
command.
Outline Attributes
is_outline
A Boolean attribute. The value will be "true" if this module is a outline module.
outline_file_name
A string attribute for the path name to the Verilog source file.
outline_file_line_start
An integer attribute for the starting line number of this module in the Verilog source file.
outline_file_line_end
An integer attribute for the ending line number of this module in the Verilog source file.
outline_file_size
An integer attribute for the size in bytes of the Verilog source file.
outline_file_timestamp
An integer attribute for the timestamp of the Verilog source file.
outline_attributes
388
outline_port_count
An integer attribute for the number of ports on this module.
outline_ref_count
A list attribute. It contains information on the leaf cells in the design, but not instantiated in
the outline design. The attribute value is a list of name-integer value pairs, where the name
is the name of the leaf cell reference, and the integer value is the number of instances of this
reference the full design module would have.
SEE ALSO
expand_outline(2)
get_attribute(2)
list_attributes(2)
Chapter 1:
outline_attributes
389
1-389
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
output_delay_attributes
Description of the predefined attributes for output delay objects.
DESCRIPTION
output_delay attributes are provided in the subsections that follow.
command.
Output_Delay Attributes
clock_name
A string attribute representing the name of the relative clock.
file_line_info
full_name
A string attribute representing a unique name for the output delay object.
is_clock_fall
A Boolean attribute. The value will be "true" if this output_delay is relative to the falling edge
of the clock, "false" otherwise.
is_level_sensitive
A Boolean attribute. The value will be "true" if this output_delay represents a level-sensitive
startpoint, "false" otherwise.
390
is_network_latency_included
A Boolean attribute. The value will be "true" if this output_delay includes clock network
is_source_latency_included
A Boolean attribute. The value will be "true" if this output_delay includes clock source
max_fall
A float attribute representing the maximum fall delay value.
max_rise
A float attribute representing the maximum rise delay value.
min_fall
A float attribute representing the minimum fall delay value.
min_rise
A float attribute representing the minimum rise delay value.
mode
A collection attribute returning the mode that contains the output_delay.
object_class
A string attribute with the value of "output_delay". Each object class has a different object
class value.
SEE ALSO
set_output_delay(2)
get_attribute(2)
list_attributes(2)
Chapter 1:
391
1-391
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
parasitic_tech_attributes
Description of the predefined attributes for parasitic_tech.
DESCRIPTION
voltage_area_shape attributes are provided in the subsections that follow.
command.
parasitic_tech Attributes
canonical_file_name
A string attribute for the absolute path of the source file used to create this parasitic_tech.
full_name
A string attribute for the full name of this parasitic_tech.
itf_technology_name
A string attribute for the technology name of this parasitic_tech.
layer_map_file_name
A string attribute for the layer mapping file used to create this parasitic_tech.
library_name
A string attribute for the name of library of this parasitic_tech.
library_parasitic_name
A string attribute for the library and parasitic name in <lib_name>:parasitic_name format.
392
name
A string attribute for the name of a parasitic_tech.
object_class
A string attribute with the value of "parasitic_tech".
source_file_name
A string attribute for the name of the source file used to create this parasitic_tech.
Chapter 1:
393
1-393
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
path_group_attributes
Lists the predefined attributes for path_group objects.
DESCRIPTION
path_group attributes are provided in the subsections that follow.
command.
command_text
mode
A collection attribute returning the mode that contains the path_group.
file_line_info
full_name
A string attribute returning a unique name for the path_group.
weight
A float attribute for path_groups. Specifies the weight value of the group.
object_class
A string attribute, with the value "path_group".
394
SEE ALSO
get_path_groups(2)
get_attribute(2)
list_attributes(2)
report_path_groups(2)
Chapter 1:
395
1-395
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
pg_region_attributes
Description of the predefined attributes for pg_regions.
DESCRIPTION
pg_region attributes are provided in the subsections that follow.
command.
pg_region Attributes
bbox
A rectangle attribute for the bounding-box of a pg_region. The format of a rectangle
the rectangle.
full_name
A string attribute for the full name of a pg_region.
in_edit_group
A boolean attribute stating if the pg_region belongs to an edit group.
is_shadow
A boolean attribute to specify whether a pg_region is pushed down from above.
name
A string attribute for the name of a pg_region. This attribute is settable.
396
object_class
A string attribute with the value of "pg_region".
parent_block
A collection attribute with the owner block object for this pg_region.
parent_block_cell
A collection attribute with the parent block cell object for this pg_region.
parent_cell
A collection attribute with the owner cell object for this pg_region.
region
A polyrect attribute for the boundary of this pg_region. The format of a boundary
specification is { {{llx1 lly1} {urx1 ury1}} {{llx2 lly2} {urx2 ury2}}...}. This attribute is settable.
shadow_status
A string attribute to represent the shadow status of a pg_region. Valid values are
top_block
A collection attribute with the top block object for this pg_region.
SEE ALSO
create_pg_region(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
397
1-397
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
pin_attributes
Lists the predefined attributes for pins.
DESCRIPTION
Attributes are properties assigned to objects such as pins, cells and nets. Definitions for pin
command.
Pin Attributes
bump_access_dir
A list attribute representing the accessible directions on a bump pin. This attribute is only
defined for pins that are on a bump cell. For octagonal bump pins, there are eight possible
access directions: N (North), NE (North East), E (East), SE (South East), S (South), SW
(South West), W (West), and NW (North West). For rectangular bump pins, only the
90-degree edges, N (North), E (East), S (South), W (West) are available. There is also a
"ALL" and "NONE" setting to enable and disable all directions. Note that "ALL" means 8
directions for octagonal bump pins and 4 directions for rectangular bump pins. This attribute
is settable.
case_sources
A collection of pins or ports that are the source of the case value on the given pin. The
sources of a case value are the locations where the user case or netlist constants have been
added. For example, a port "PE" fans out to a pin "u1/A" through only buffers and a case
value of 0 is set on port "PE". The case_sources attribute for pin u1/A will be port "PE". This
attribute is only defined for a pin if there is a case_value on that pin.
case_value
Specifies the value of case on this pin. The possible values are "0" or "1". This value may
come from user defined case or netlist defined constant value. The value may be because
pin_attributes
398
a case value was directly set on this pin or because the case value was propagated through
logic to this pin. If there is no case assigned or propagated to this pin this attribute is not
defined.
A float attribute representing the user-specified clock network latency for max fall. This
attribute is only defined on those pins where set_clock_latency has been directly set.
A float attribute representing the user-specified clock network latency for min fall. This
A float attribute representing the user-specified clock network latency for max rise. This
A float attribute representing the user-specified clock network latency for min rise. This
A float attribute representing the user-specified clock network latency for early max fall. This
attribute is only defined on those pins where set_clock_latency -source has been directly
set.
A float attribute representing the user-specified clock network latency for early min fall. This
set.
This attribute is only defined on those pins where set_clock_latency -source has been
directly set.
Chapter 1:
pin_attributes
399
1-399
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
A float attribute representing the user-specified clock network latency for early min rise. This
set.
A float attribute representing the user-specified clock network latency for late max fall. This
set.
A float attribute representing the user-specified clock network latency for late min fall. This
set.
A float attribute representing the user-specified clock network latency for late max rise. This
set.
A float attribute representing the user-specified clock network latency for late min rise. This
set.
clocks
A collection of clock objects that this pin is in the clock network of. The clocks in the
collection are just those clocks that this pin fans out directly from the clock sources. It does
not include the master clocks of any generated clock networks that this pin is in.
clocks_with_sense
A string attribute in the form of a list of clock names and clock senses this pin is in the clock
network of. The possible clock senses are: "positive", "negative",
"rise_triggered_high_pulse", "fall_triggered_high_pulse", "rise_triggered_low_pulse",
"fall_triggered_low_pulse". For example, the following script:
foreach_in_collection pin $pinList {
set pinName [get_attribute $pin full_name]
set senses [ get_attribute $pin clocks_with_sense]
pin_attributes
400
echo "For pin: " $pinName " " $senses;

}
might produce output such as:
For pin:
For pin:
For pin:
mux/A
mux/B
mux/Z
{ { "clk" "negative" } }
{ { "clk" "positive" } }
{ { "clk" "negative" } { "clk" "positive" } }
constant_value
A string attribute for the constant value on this pin. The possible values are "0" or "1".
Constant values are caused by a logic constant in the netlist or by a library cell such as a
pullup or pulldown having a constant logic function. A constant value is on the initial pin and
on any pins that have their case propagated as a result of that. For pins with the attribute
constant_value defined, the attribute case_value will also be defined and have the same
value.
direction
full_name
A string attribute returning the full instance path name to the pin.
hold_uncertainty
A float attribute representing the user-specified clock uncertainty for hold. This attribute will
is_clock_pin
A Boolean attribute that is true for clock pins of registers. A clock pin is any pin that has a
timing check from it to a data pin.
is_clock_used_as_clock
A Boolean attribute that is true if this pin is part of at least one clock network and the clock
network fanout of this pin reaches at least one register clock pin or output port.
is_clock_used_as_data
network fanout of this pin reaches at least one register data pin. If the attribute values for
Chapter 1:
pin_attributes
401
1-401
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
is_clock_used_as_data is TRUE and is_clock_used_as_clock is FALSE, the clocks through

this pin only acts a data and never as clock.
is_data_pin
A Boolean attribute that is true for data pins of registers. A data pin is any pin that has a
timing check to it. Data pins are legal endpoint for timing paths.
is_hierarchical
A Boolean attribute that is true if the pin's cell is hierarchical.
is_three_state
A Boolean attribute that is true if this pin is a three-state output (can become high impedance
when not enabled).
is_three_state_output_pin
A Boolean attribute that is true if this pin is a three-state output (can become high impedance
when not enabled).
lib_pin_name
A string attribute for the name of the library pin.
object_class
pg_type
A string attribute. The value is the pg-type of the given ground pin or the power pin.
pin_direction
pin_attributes
402
potential_clocks
A collection of clock objects that this pin would be in the clock network of, except these
clocks are blocked by some constraint. The command analyze_clock_networks can be used
to find the reason these clocks are blocked.
power_domain
A string attribute. The value is the power domain name of the given pin.
setup_uncertainty
A float attribute representing the user-specified clock uncertainty for setup. This attribute will
user_case_value
A string attribute for the case value set by the command set_case_analysis. This attribute
is only defined on those pins that set_case_analysis has been directly set on. Use the
attribute "case_value" for both directly set case values and propagated case values.
user_clock_sense
A string attribute for the sense set by the command set_clock_sense. This attribute is only
define on those pins where the set_clock_sense command was used directly.
parent_block
A collection attribute with the owner block object for this pin.
parent_cell
A collection attribute with the owner cell object for this pin.
parent_block_cell
A collection attribute with the parent block cell object for this pin.
top_block
A collection attribute with the top block object for this pin.
Chapter 1:
pin_attributes
403
1-403
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
topology_edges
A collection attribute with the set of topology_edge objects which have this pin as an
endpoint.
SEE ALSO
find(2)
get_attribute(2)
list_attributes(2)
pin_attributes
404
pin_blockage_attributes
Lists the predefined attributes for pin_blockages.
DESCRIPTION
pin_blockage attributes are provided in the subsections that follow.
command.
Pin Blockage Attributes
all_objects
A collection attribute with the layers blocked by the pin_blockage, and the ports, pins, or nets
which are explicitly blocked by this pin_blockage. If the pin_blockage implicitly blocks all
ports and pins, then this collection contains only the blocked layers.
bbox
A rectangle attribute for the bounding-box of the pin_blockage. The format of a rectangle
the rectangle.
boundary
A coordinate_list attribute for the boundary of the pin_blockage. The format of a
coordinate_list specification is {{x1 y1} {x2 y2}...}. This attribute is settable.
full_name
A string attribute for the name of the pin_blockage.
Chapter 1:
405
1-405
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
in_edit_group
A boolean attribute to specify whether the pin_blockage belongs to an edit_group.
is_shadow
A boolean attribute to specify whether the pin_blockage is pushed down from above.
layer_names
A string attribute for the names of the layers which are blocked by the pin_blockage.
layers
A collection attribute with the layers which are blocked by the pin_blockage. This attribute is
settable.
name
A string attribute for the name of the pin_blockage. This attribute is settable.
nets
A collection attribute with the nets which are explicitly blocked by the pin_blockage. A
pin_blockage may explicitly block ports, pins, or nets. If nets, all of the nets' ports and pins
are blocked. If none are explicitly blocked, then the pin_blockage blocks all ports and pins.
This attribute is settable.
object_class
A string attribute with the value of "pin_blockage".
parent_block
A collection attribute with the owner block object for this pin_blockage.
parent_block_cell
A collection attribute with the parent block cell object for this pin_blockage.
parent_cell
A collection attribute with the owner cell object for this pin_blockage.
406
physical_status
A string attribute representing the physical modification status of the pin_blockage. If status
is unrestricted, the pin_blockage may be moved or rotated. If the status is locked, the
pin_blockage may not be moved or rotated. This is a settable attribute.
pins
A collection attribute with the pins which are explicitly blocked by the pin_blockage. A
ports
A collection attribute with the ports which are explicitly blocked by the pin_blockage. A
shadow_status
A string attribute to represent the shadow status of the pin_blockage. Valid values are
copied_down, copied_up, normal, pulled_up, pushed_down, and virtual_flat. This attribute
is settable.
top_block
A collection attribute with the top block object for this pin_blockage.
SEE ALSO
get_attribute(2)
list_attributes(2)
Chapter 1:
407
1-407
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
pin_guide_attributes
Lists the predefined attributes for pin_guides.
DESCRIPTION
pin_guide attributes are provided in the subsections that follow.
command.
Pin Guide Attributes
bbox
A rectangle attribute for the bounding-box of the pin_guide. The format of a rectangle
the rectangle.
boundary
A coordinate_list attribute for the boundary of the pin_guide. The format of a coordinate_list
specification is {{x1 y1} {x2 y2}...}. This attribute is settable.
full_name
A string attribute for the name of the pin_guide.
in_edit_group
A boolean attribute to specify whether the pin_guide belongs to an edit_group.
408
is_exclusive
A boolean attribute to specify whether the pin_guide is exclusive. If exclusive, the ports,
pins, and ports/pins of nets constrained by this pin_guide may be placed within the
pin_guide, but all others must be placed outside of the pin_guide. This attribute is settable.
is_shadow
A boolean attribute to specify whether the pin_guide is pushed down from above.
layer_names
A string attribute for the names of the layers which are constrained by the pin_guide.
layers
A collection attribute with the layers which are constrained by the pin_guide. This attribute is
settable.
name
A string attribute for the name of the pin_guide. This attribute is settable.
nets
A collection attribute with the nets which are constrained by the pin_guide. A pin_guide may
constrain ports, pins, or nets. If nets, all of the nets' ports and pins are constrained. This
attribute is settable.
object_class
A string attribute with the value of "pin_guide".
parent_block
A collection attribute with the owner block object for this pin_guide.
parent_block_cell
A collection attribute with the parent block cell object for this pin_guide.
parent_cell
A collection attribute with the owner cell object for this pin_guide.
Chapter 1:
409
1-409
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
parents
A collection attribute with the macro and partition cells to which the pin_guide applies. If the
collection is empty, the pin_guide applies to the parent block. This attribute is settable.
pin_spacing
An integer attribute for the number of wire tracks between pins within the pin_guide. This
pins
A collection attribute with the pins which are constrained by the pin_guide. A pin_guide may
ports
A collection attribute with the ports which are constrained by the pin_guide. A pin_guide may
shadow_status
A string attribute to represent the shadow status of the pin_guide. Valid values are
is settable.
top_block
A collection attribute with the top block object for this pin_guide.
SEE ALSO
get_attribute(2)
list_attributes(2)
410
place.coarse.congestion_analysis_effort
Determines the accuracy of the router used by congestion driven placement.
TYPE
Enum
DEFAULT
"high"
DESCRIPTION
Determines the accuracy of the router used by congestion driven placement.
Possible values are "high", "medium" or "low.
specified globally or with respect to a design. Use report_app_options to show the value
of application options.
SEE ALSO
create_placement(2)
set_app_options(2)
place_opt(2)
refine_placement(2)
refine_opt(2)
clock
Chapter 1:
place.coarse.congestion_analysis_effort
411
1-411
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place.coarse.congestion_driven_max_util
Specifies the maximum design utilization after congestion driven padding.
TYPE
Float
DEFAULT
0.93
DESCRIPTION
Specifies the maximum design utilization after congestion driven padding during congestion
driven placement. Possible values are floating point numbers between 0.0 and 1.0. Setting
this value to a number below the overall design utilization will cause it to be ignored.
SEE ALSO
create_placement(2)
set_app_options(2)
place_opt(2)
refine_placement(2)
refine_opt(2)
clock
place.coarse.congestion_driven_max_util
412
place.coarse.detect_detours
Enables detour detection during coarse placement.
TYPE
Boolean
DEFAULT
"false"
DESCRIPTION
Enables detour detection during coarse placement.
Possible values are "true" or "false"
SEE ALSO
create_placement(2)
set_app_options(2)
place_opt(2)
refine_placement(2)
refine_opt(2)
clock
Chapter 1:
place.coarse.detect_detours
413
1-413
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place.coarse.enable_enhanced_soft_blockages
Enables enhanced soft blockage behavior.
TYPE
Boolean
DEFAULT
"false"
DESCRIPTION
Enables enhanced soft blockage behavior. When this app options is set to "true", the cells
that are already placed on top of soft blockages are allowed to remain overlapped with soft
blockages.
of the application options.
SEE ALSO
create_placement(2)
place_opt(2)
refine_opt(2)
refine_placement(2)
set_app_options(2)
clock
place.coarse.enable_enhanced_soft_blockages
414
place.coarse.enable_spare_cell_placement
Enables spare cell placement.
TYPE
Boolean
DEFAULT
"true"
DESCRIPTION
Enables spare cell placement. When this app option is set to "true", cells that are
unconnected will be distributed evenly over the placeable area.
SEE ALSO
create_placement(2)
place_opt(2)
refine_opt(2)
refine_placement(2)
set_app_options(2)
Chapter 1:
place.coarse.enable_spare_cell_placement
415
1-415
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place.coarse.fix_cells_on_soft_blockages
Treat cells on soft blockages as fixed for coarse placement.
TYPE
Boolean
DEFAULT
"true"
DESCRIPTION
Cells that are on top of soft blockages prior to placement are treated as fixed for coarse
placement. This only applies to incremental placements.
SEE ALSO
create_placement(2)
place_opt(2)
refine_opt(2)
refine_placement(2)
set_app_options(2)
clock
place.coarse.fix_cells_on_soft_blockages
416
place.coarse.fix_hard_macros
Specifies that the placer should treat all hard macros in the design as fixed
TYPE
Boolean
DEFAULT
"false"
DESCRIPTION
This option controls whether the create_placement command will place hard macros or
treat them as fixed objects.
of application options. This application option is global only.
SEE ALSO
create_placement(2)
set_app_options(2)
Chapter 1:
place.coarse.fix_hard_macros
417
1-417
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place.coarse.fix_ios
Treat IO cells as fixed for coarse placement.
TYPE
Boolean
DEFAULT
"true"
DESCRIPTION
Treat IO cells as fixed for coarse placement.
SEE ALSO
create_placement(2)
set_app_options(2)
place_opt(2)
refine_placement(2)
refine_opt(2)
clock
place.coarse.fix_ios
418
place.coarse.fix_soft_macros
Specifies that the placer should treat all soft macros in the design as fixed
TYPE
Boolean
DEFAULT
"true"
DESCRIPTION
This option controls whether the create_placement command will place soft macros or treat
them as fixed objects.
SEE ALSO
create_placement(2)
set_app_options(2)
Chapter 1:
place.coarse.fix_soft_macros
419
1-419
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place.coarse.icg_auto_bound
Enables the placer to utilize automatic placement bounds for ICGs and downstream
sequentials
TYPE
Boolean
DEFAULT
"false"
DESCRIPTION
This option controls whether placement will use the automatic group bounds created for
ICGs and sequentials. The ICG automatic bounds are created before each placement
invocations, and removed at the end of placement.
The tool does not bound the cells already belonging to any existing group bounds.
SEE ALSO
create_placement(2)
place_opt(2)
place.coarse.icg_auto_bound_fanout_limit(3)
set_app_options(2)
place.coarse.icg_auto_bound
420
place.coarse.icg_auto_bound_fanout_limit
Specifies fanout limit for the ICG automatic bound creation
TYPE
Integer
DEFAULT
100
DESCRIPTION
This option limits the maximum number of fanouts that can be included in an ICG automatic
bound.
SEE ALSO
place.coarse.icg_auto_bound(3)
create_placement(2)
place_opt(2)
set_app_options(2)
Chapter 1:
place.coarse.icg_auto_bound_fanout_limit
421
1-421
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place.coarse.low_power_placement
Enables switching activity-driven power aware placement.
TYPE
Boolean
DEFAULT
"false"
DESCRIPTION
This option controls whether placement runs in power-aware mode, driven by switching
activity information on nets. The switching activities can be read from a SAIF file by using
the read_saif, or with the set_switching_activity command, or tool's default values.
Low-power placement internally invokes switching activity propagation for scenarios with
power analysis enabled, before constraining and running placement. Low-power placement
requires the existing placement as a seed placement; you should run create_placement
with -use_seed_locs or -incremental.
When used for top-level flows with physical hierarchies, low-power placement only
optimizes the swtiching power of the nets in current_block.
specified globally or with respect to a design. Use the report_app_options command to
show the value of application options.
SEE ALSO
clock_opt(2)
create_placement(2)
place_opt(2)
refine_opt(2)
refine_placement(2)
set_app_options(2)
place.coarse.low_power_placement
422
place.coarse.max_density
Sets the maximum density for the coarse placement engine.
TYPE
Float
DEFAULT
0.0
DESCRIPTION
When this value is set, the coarse placer attempts to limit local density to less than this
setting. Default value of 0 indicates that the placer will try to spread cells evenly.
SEE ALSO
create_placement(2)
place_opt(2)
refine_opt(2)
refine_placement(2)
set_app_options(2)
clock
Chapter 1:
place.coarse.max_density
423
1-423
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place.coarse.perturbation_effort
Sets the perturbation effort in the core placer.
TYPE
String
DEFAULT
default
DESCRIPTION
Use this option to change the default perturbation effort used in the core placer. For
example, you may want to use a lower effort later in the flow.
Possible values are "default", "low", "medium", or "high".
SEE ALSO
create_placement(2)
set_app_options(2)
place_opt(2)
refine_placement(2)
refine_opt(2)
place.coarse.perturbation_effort
424
place.coarse.pin_density_aware
Enables pin density-aware coarse placement
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this value is set to true, the placer tries to control the maximum local pin density.
SEE ALSO
create_placement(2)
place_opt(2)
refine_opt(2)
refine_placement(2)
set_app_options(2)
clock
Chapter 1:
place.coarse.pin_density_aware
425
1-425
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place.coarse.target_routing_density
Controls the target routing density during congestion driven placement.
TYPE
Float
DEFAULT
0.0
DESCRIPTION
Controls the target routing density for congestion driven placement. The default value of 0.0
allows the placer to determine the value based on which router is used.
Possible values are floating values between 0.0 and 1.0.
SEE ALSO
create_placement(2)
place_opt(2)
refine_opt(2)
refine_placement(2)
set_app_options(2)
clock
place.coarse.target_routing_density
426
place.floorplan.density_aware_hard_movebounds
Specifies that the placer should treat all hard movebounds in the design as partitions.
TYPE
Boolean
DEFAULT
"false"
DESCRIPTION
This option controls whether the create_placement command will treat hard movebounds
as partitions.
SEE ALSO
create_placement(2)
set_app_options(2)
Chapter 1:
place.floorplan.density_aware_hard_movebounds
427
1-427
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place.floorplan.sliver_size
Specifies floorplan sliver size
TYPE
length
DEFAULT
0
DESCRIPTION
Specifies the minimum channel size to allow standard cell placement. The default is 0. The
option type is length, which means that it must be specified with the length unit.
SEE ALSO
create_placement(2)
place_opt(2)
refine_opt(2)
refine_placement(2)
set_app_options(2)
place.floorplan.sliver_size
428
place.legalize.enable_prerouted_net_check
This app_option enables checking of cell placement against pre-routed nets, including
Power and Ground nets, during legalization and legality checking. This is on by default in IC
CompilerII. Disabling pre-routed net checking throughout the flow will likely introduce design
rule errors and routing problems.
TYPE
Boolean
DEFAULT
"true"
DESCRIPTION
Enable checking of cell placement against pre-routed net shapes.
Possible values are "true" or "false". Default is "true".
SEE ALSO
legalize_placement
check_legality
Chapter 1:
place.legalize.enable_prerouted_net_check
429
1-429
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place.rp.allow_non_rp_cells
Allows non relative placement cells in the unused areas of relative placement groups.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When true, non relative placement cells are allowed in the unused areas of relative
placement groups during coarse placement and refine placement. When false (the default),
non relative placement cells are not allowed in the unused spaces of relative placement
groups. Note that non relative placement cells are allowed in unused spaces during
legalization and optimization irrespective of place.rp.allow_non_rp_cells is set to true or
false.
specified globally or with respect to a design. To determine the current value of this
application option on a specific design, use get_app_option_value -block $block -name
place.rp.allow_non_rp_cells. Use report_app_options to show the value of multiple
application options.
SEE ALSO
set_app_options(2)
set_clock_gating_check(2)
place.rp.allow_non_rp_cells
430
place.rp.allow_non_rp_cells_on_blockages
Allows overlap of non relative placement cells with relative placement blockages.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When true, non relative placement cells are allowed to overlap with relative placement
blockages during coarse placement, refine placement, legalization and optimization. Please
note that non relative placement cells are allowed in unused spaces of relative placement
groups too. When false (the default), non relative placement cells can not overlap with
relative placement blockages.
place.rp.allow_non_rp_cells_on_blockages. Use report_app_options to show the
value of multiple application options.
SEE ALSO
set_app_options(2)
Chapter 1:
place.rp.allow_non_rp_cells_on_blockages
431
1-431
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place.rules.vertical_abutment_mode
This app_option sets the mode for vertical abutment constraint generation to be used during
legalization and legality checking. User has option of three modes - 1. "user" which relies
solely on user provided values of attributes "vertical_abut_pattern_top" and
"vertical_abut_pattern_bottom" that are set on library cells and the value of app_option
"vertical_abutment_forbidden_pairs"; 2. "auto" which generates constraints automatically by
processing all library cells; and 3. "merge" which combines both the user-supplied
constraints and the automatically generated ones. This option is only valid if vertical
abutment rules are enabled with app_option
"place.legalize.enable_vertical_abutment_rules".
TYPE
String
DEFAULT
"user"
DESCRIPTION
Set vertical abutment rule generation mode..
Possible values are "user", "auto" or "merge". Default is "user".
SEE ALSO
legalize_placement
check_legality
place.rules.vertical_abutment_mode
432
place_opt.congestion.effort
TYPE
string
DEFAULT
medium
DESCRIPTION
Specifies the effort level for the congestion alleviation in place_opt. Allowed values are
place_opt will not run in a congestion mode.
SEE ALSO
create_placement(2)
place_opt(2)
clock_opt.congestion.effort(3)
refine_opt.congestion.effort(3)
Chapter 1:
place_opt.congestion.effort
433
1-433
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place_opt.final_place.effort
TYPE
string
DEFAULT
medium
DESCRIPTION
Specifies the CPU effort level for the final coarse placement invoked in place_opt. Allowed
values are medium or high.
SEE ALSO
create_placement(2)
place_opt(2)
clock_opt.place.effort(3)
place_opt.final_place.effort
434
place_opt.final_place.legalize
TYPE
Boolean
DEFAULT
true
DESCRIPTION
If set to true, the final placement stage in place_opt will include cell legalizations
immediately after timing driven placement.
SEE ALSO
place_opt(2)
refine_opt.place.legalize(3)
Chapter 1:
place_opt.final_place.legalize
435
1-435
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place_opt.flow.clock_aware_placement
Enables ICG timing criticality driven clock-aware placement in place_opt.
TYPE
Boolean
DEFAULT
"false"
DESCRIPTION
This option controls whether place_opt will utilize clock-aware placement, guided by ICG's
enable timing criticality. With this option, place_opt will try to improve ICG enable timing
(measured after clock_opt) by placing the timing critical ICGs and their fanout cells at better
locations for ICG enable paths. This option can be combined with place_opt ICG
optimization flow (place_opt.flow.optimize_icgs).
SEE ALSO
place_opt(2)
refine_opt(2)
place.coarse.low_power_placement(3)
place_opt.flow.optimize_icgs(3)
set_app_options(2)
place_opt.flow.clock_aware_placement
436
place_opt.flow.do_path_opt
Run path_opt in and after place_opt
TYPE
bool
DEFAULT
false
DESCRIPTION
This option enables running path_opt in and after place_opt for better timing QOR. false is
the default.
SEE ALSO
place_opt(2)
set_app_options(2)
Chapter 1:
place_opt.flow.do_path_opt
437
1-437
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place_opt.flow.do_spg
Run the SPG flow inside place_opt.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
place_opt will run the SPG flow that takes in a pre-placed netlist and optimizes it further,
based on ideal clocks.
SEE ALSO
set_app_options(2)
place_opt.flow.do_spg
438
place_opt.flow.optimize_icgs
Enable ICG optimization in place_opt
TYPE
Boolean
DEFAULT
false
DESCRIPTION
place_opt will run automatic ICG optimization that performs trial clock synthesis, timing
aware ICG splitting for critical enable paths, and clock-aware placement.
The trial clock tree synthesis is used regardless of the value of
place_opt.flow.trial_clock_tree, for critical ICG enable paths identification and all the
optimization steps in place_opt. Note that the end-of-place_opt timing QoR cannot be
directly comparable to conventional ideal clock based place_opt QoR, and the trial clock
tree is automatically removed and re-synthesized by clock_opt or synthesize_clock_trees.
The optimize_icgs flow does not merge ICGs, however, user can optionally run
merge_clock_gates before running place_opt.
The ICG oriented clock-aware placement is automatically used regardless of the value of
place_opt.flow.clock_aware_placement, which will further help ICG enable path timing
improvement.
The aggressiveness of ICG splitting can be controlled by
place_opt.flow.optimize_icgs_critical_range.
In order to maximize the benefit from the well-correlated trial clock tree in place_opt, apply
as much clock-related settings as possible for place_opt, such as clock NDRs or post-clock
uncertainties.
Top-level design support is limited. With read-only sub-blocks, ICG optimization will be
limited to current_block, and place_opt will immediately exit with an Error message if
modifiable sub-blocks are detected.
Chapter 1:
439
1-439
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
set_app_options(2)
place_opt(2)
place_opt.flow.optimize_icgs_critical_range(3)
place_opt.flow.trial_clock_tree(3)
place_opt.flow.clock_aware_placement(3)
440
place_opt.flow.optimize_icgs_critical_range
Critical range for ICG optimization in place_opt
TYPE
Float
DEFAULT
0.75
DESCRIPTION
This is a sub option for place_opt.flow.optimize_icgs, whose acceptable values are
between 1.0 and 0.0. When set to X, only ICGs whose EN violations are within {EN_WNS,
EN_WNS*(1-X)} will be considererd for splitting. The larger the value is, the more
aggressive ICG splitting is expected by including more ICGs for splitting consideration.
SEE ALSO
set_app_options(2)
place_opt(2)
Chapter 1:
place_opt.flow.optimize_icgs_critical_range
441
1-441
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place_opt.flow.optimize_layers
Enables layer optimization in place_opt
TYPE
String
DEFAULT
false
DESCRIPTION
It has three modes: {auto, true, false}. In auto mode, layer optimization will be automatically
activated if the design has fast metal layers. When layer optimization is activated, the
place_opt flow assigns long timing critical nets to upper metal layers to improve timing.
SEE ALSO
set_app_options(2)
place_opt.flow.optimize_layers
442
place_opt.flow.optimize_layers_critical_range
Set critical range for layer optimization when place_opt.flow.optimize_layers is set to true.
TYPE
Float
DEFAULT
0.9
DESCRIPTION
SEE ALSO
set_app_options(2)
place_opt.flow.optimize_layers(3)
Chapter 1:
place_opt.flow.optimize_layers_critical_range
443
1-443
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place_opt.flow.optimize_ndr
Enable NDR optimization in place_opt
TYPE
Boolean
DEFAULT
false
DESCRIPTION
Place_opt flows will run automatic non-default-routing rule optimization that assigns long
SEE ALSO
set_app_options(2)
place_opt.flow.optimize_ndr
444
place_opt.flow.trial_clock_tree
Enables early clock tree synthesis in place_opt.
TYPE
string
DEFAULT
"false"
DESCRIPTION
This option controls whether place_opt will utilize early clock tree synthesis, which is useful
for low power placement enabled place_opt and ICG optimization flow. Available values are
false (default) and true.
When it is set to true, the clock tree synthesis is performed during place_opt and the
propagated clocks are used throughout place_opt flow, hence the place_opt QoR is not
directly comparable to conventional ideal clock based place_opt flows. place_opt will place
and optimize based on the clock tree structure as well as the propagated clock from the trial
clock tree.
The trial clock tree is automatically removed and re-synthesized by clock_opt or
synthesize_clock_trees, where the finalized clock trees are built.
In order to maximize the benefit from the well-correlated trial clock tree in place_opt, apply
as much clock-related settings as possible for place_opt, such as clock NDRs or post-clock
uncertainties.
SEE ALSO
place_opt(2)
place_opt.flow.clock_aware_placement(3)
set_app_options(2)
Chapter 1:
place_opt.flow.trial_clock_tree
445
1-445
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place_opt.initial_drc.global_route_based
Run global route based buffering (GRopto flow) during HFSDRC.
TYPE
integer
DEFAULT
0
DESCRIPTION
When running the GRopto flow during HFSDRC, nets are globally routed and the topology
for buffering HFS and DRC violating nets is determined based on the global routes. After
buffering, all global routes are deleted, and the modified topologies will anchor buffers and
guide downstream optimization. Currently, the GRopto flow can be enabled one time during
place_opt at the HFSDRC buffering stage. To enable the flow, set the app options value to
1.
place_opt.initial_drc.global_route_based
446
place_opt.initial_place.effort
TYPE
string
DEFAULT
medium
DESCRIPTION
Specifies the CPU effort level for the initial coarse placement invoked in place_opt. This
effort option also controls both coarse placements in two-pass initial placement, if
place_opt is directed to use a two-pass initial placement. Allowed values are medium or
high.
SEE ALSO
create_placement(2)
place_opt(2)
place_opt.initial_place.two_pass(3)
Chapter 1:
place_opt.initial_place.effort
447
1-447
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
place_opt.initial_place.two_pass
Runs the two-pass flow for initial placement step inside the place_opt command.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
The place_opt command will run a two-pass flow to generate a better initial placement. The
two-pass flow performs wirelength-driven placement, followed by DRC fixing and another
timing-driven placement.
SEE ALSO
set_app_options(2)
place_opt.initial_place.two_pass
448
placement_blockage_attributes
Lists the predefined attributes for placement_blockages.
DESCRIPTION
placement_blockage attributes are provided in the subsections that follow.
command.
Placement Blockage Attributes
area
A float attribute for the area of the placement_blockage.
bbox
A rectangle attribute for the bounding-box of the placement_blockage. The format of a
rectangle specification is {{llx lly} {urx ury}}, which specifies the lower-left and upper-right
corners of the rectangle.
blockage_purpose
A string attribute indicating the purpose of the placement_blockage. Valid values are system
and user. This attribute is settable.
blockage_type
A string attribute indicating the type of the placement_blockage. Valid values are
allow_buffer_only, category, hard, hard_macro, partial, register, rp_group, shaping, and soft.
Chapter 1:
449
1-449
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
blocked_percentage
An integer attribute for the percentage of the blockage area that is blocked. This attribute is
applicable only for allow_buffer_only, partial, category, register, and rp_group
placement_blockages. This attribute is settable.
boundary
A coordinate_list attribute for the boundary of the placement_blockage. The format of a
category
A string attribute for the category name of a category placement_blockage. This attribute is
settable.
full_name
A string attribute for the name of the placement_blockage.
in_edit_group
A boolean attribute to specify whether the placement_blockage belongs to an edit_group.
is_derived
A boolean attribute to indicate whether the placement_blockage was automatically
generated by the application. For more details, see derive_placement_blockages and
plan.place.auto_generate_blockages. This attribute is settable.
is_pin_protect
A boolean attribute to specify whether the application is allowed to stack macros on the edge
of the hard_macro placement_blockage. If true, the macro placer is not allowed to stack
macros on the edge of the blockage. This is used to prevent the macro placer from stacking
macros against block pins. This attribute is settable.
is_shadow
A boolean attribute to specify whether the placement_blockage is pushed down from above.
name
A string attribute for the name of the placement_blockage. This attribute is settable.
450
object_class
A string attribute with the value of "placement_blockage".
parent_block
A collection attribute with the owner block object for this placement_blockage.
parent_block_cell
A collection attribute with the parent block cell object for this placement_blockage.
parent_cell
A collection attribute with the owner cell object for this placement_blockage.
physical_status
A string attribute representing the physical modification status of the placement_blockage.
If status is unrestricted, the placement_blockage may be moved or rotated. If the status is
locked, the placement_blockage may not be moved or rotated. This is a settable attribute.
shadow_status
A string attribute to represent the shadow status of the placement_blockage. Valid values
are copied_down, copied_up, normal, pulled_up, pushed_down, and virtual_flat. This
top_block
A collection attribute with the top block object for this placement_blockage.
SEE ALSO
get_attribute(2)
list_attributes(2)
Chapter 1:
451
1-451
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.budget.add_missing_feedthrough_clocks
When writing budgets, declare clock in blocks where new clock feedthrough have been
added
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When creating constraints for blocks, it is sometimes desirable include create_clock
definitions on at places where blocks feed through your block. Even though the clock net
may not fan out to any flops in your block, some tools might treat the clock feedthrough
differently because a create_clock statement exists. For example, the clock might be
shielded.
There is another app option (plan.budget.include_feedthrough_clocks) which signals the
split_constraints command to declare create_clock statements on clock feedthroughs. But
split_constraints will only see clock feedthroughs that are defined in your original verilog
netlist. If clock feedthroughs are added after split_constraints, no create_clock will be
declared.
If you set this option to true, the write_budgets command will add a create_clock statement
for clock feedthroughs that do not yet have one. Since write_budgets is generally run after
new clock feedthroughs are created, you can properly update your block constraints simply
by applying the budget.
Note that plan.budget.add_missing_feedthrough_clocks app option will only work if you
*also* set plan.budget.include_feedthrough_clocks. If you do not set the
plan.budget.include_feedthrough_clocks, the tool will assume that feedthrough clocks
should never get create_clock statements.
SEE ALSO
write_budgets(2)
plan.budget.include_feedthrough_clocks(3)
452
Chapter 1:
453
1-453
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.budget.all_design_subblocks
Controls the behavior of the write_budgets and split_constraints commands. When true,
the -design_subblocks option is automatically set for all blocks.
TYPE
boolean
DEFAULT
false
DESCRIPTION
When generating budget constraints, it is assumed that any subblock of a budgeted block is
represented by an abstract. The budget will "cut out" constraints that are not visible on the
boundary of the abstract. Setting this option causes the internal constraints of subblocks to
be kept in the budget.
When calculating "design_subblock" constraints, it is necessary for the write_budgets
command to time all of the internal paths of each budgeted block. If you are using abstracts
to represent some of your blocks, timing the internal paths of the block will not be possible.
So "full" constraints cannot be generated for abstracted blocks. If you want to generate "full"
constraints, you must also use a full design view (not an abstract) for the block.
Memory Considerations
When you set this option to "true", you must change all of your blocks to a full design view.
For large designs, this could result in a very large use of memory and runtime. To avoid this
memory impact, you should consider using the split_constraints command to generate the
internal constraints of your budgeted block. The split_constraints command is specifically
designed to use much less memory and runtime. After you have the results of
split_constraints, you run write_budgets its default incremental setting. See the man
page for details.
SEE ALSO
454
set_app_options(2)
split_constraints(2)
write_budgets(2)
plan.budget.all_full_budgets(3)
Chapter 1:
455
1-455
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.budget.all_full_budgets
Controls the behavior of the write_budgets command to choose between writing only
incremental boundary constraints or full constraints for a budgeted block.
TYPE
boolean
DEFAULT
false
DESCRIPTION
For each budgeted blockin your design, the write_budgets command is capable of
generating budgets in one of two styles. Budgets can include "full constraints" or budgets
can include "incremental constraints". Full constraints are a complete set of constraints for
a block. Incremental constraints preserve a block's internal constraints but updates the
constraints on the block interface.
If plan.budget.all_full_budgets is set to "true", then full constraints will be generated for

all budgeted blocks.
If plan.budget.all_full_budgets is set to "false", then incremental constraints will be

used by default. However, if you create a budget for the top level, using the -top option
of write_budgets, the top will always have a full budget. Also, you can dictate that some
budgeted blocks should get a full budget by using the -full_budget_blocks option of
write_budgets.
"Incremental" constraints apply only to the interface timing paths of a budgeted block.
These constraints are intended to be overlaid on top of the existing internal constraints
of the block. Using these constraints, you can incrementally change the block's interface
boundary constraints without disturbing the internal constraints. If you do not have
existing internal constraints for your block, you can obtain them by using the
split_constraints command.
"Full" constraints include constraints for both the interface of the budgeted block *and*
the internal block paths. If you use these constraints, any existing constraints on the
block will be removed and replaced.
When calculating "full" constraints, it is necessary for the write_budgets command to

time all of the internal paths of each budgeted block. If you are using abstracts to
456
represent some of your blocks, timing the internal paths of the block will not be possible.
So "full" constraints cannot be generated for abstracted blocks. If you want to generate
"full" constraints, you must also use a full design view (not an abstract) for the block.
Memory Considerations
When you set this option to "true", you will be required to change all of your blocks to a full
design view. For large designs, this could result in a very large use of memory and runtime.
To avoid this memory impact, you should consider using the split_constraints command to
generate the internal constraints of your budgeted block. The split_constraints command
is specifically designed to use much less memory and runtime. Once you have the results of
split_constraints, you run write_budgets its default incremental setting. Refer to the man
page for details.
SEE ALSO
write_budgets(2)
set_app_options(2)
plan.budget.all_design_blocks(3)
Chapter 1:
457
1-457
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.budget.allow_disconnected_gclocks
Allows problems with generated clocks to be ignored during split_constraints.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When creating split constraints, it is necessary to propagate clocks across the block
boundaries. And if you have a generated clock source in your block, it is necessary to
propagte the master clock from outside of the block to inside of the block.
If split_constraints is unable to propagate a master clock to the generated clock, you will
receive either an ABS-207 or ABS-286 error message, and the output constraints will not be
usable.
If you set this app option to true, split_constraints will work around the problem by
automatically changing your generated clock into a regular clock. This will allow you to
continue with your flow, but it is not recommended for the long term. When the generated
clock in your budget has been changed into a regular clock, the clock latency will no longer
be propagated to this clock. This will be a serious problem for post-CTS optimization.
Ultimately, you need to fix the underlying problem and set this app option back to false. The
man pages for ABS-207 and ABS-286 give you tips for this.
SEE ALSO
plan.budget.allow_disconnected_gclocks
458
plan.budget.allow_top_only_exceptions
Allows problems with generated clocks to be ignored during split_constraints.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When running write_budget, it is expected that the constraints used at the top level of your
design are consistent with the constraints that applied to your lower-level blocks. This allows
the budgeter to incrementally apply constraints to the boundary of your block, while
assuming that the constraints in the core of your block are already correct.
There are times, however, that you might want to adjust your top-level constraints without
touching your block. For example, you might want to use set_multicycle_path on a path the
crosses between two of your blocks.
If you set this app option to true, the budgeter will support changing exceptions
(set_false_path and set_multicycle_path) at the top level, without regenerating or modifying
your block-level constraints. The only rule is that your added constraint may not name any
pins *inside* of your blocks. For example, it is OK to add the following top-level exception.
set_multicycle_path -from block1/out1 -to block2/in1
It is not supported if your exception names pins inside the block. For example, this is not
supported:
set_multicycle_path -from block1/reg1/CK -to block2/reg1/D
If you want to change constraints that reach inside of the block, you need to also update your
block constraints. This can be done manually, or with the help of the split_constraints
command. Alternatively, you could consider using "full budgeting", but that carries a memory
and CPU penalty. Please refer to the man page for plan.budget.all_full_budgets for
details.
Chapter 1:
459
1-459
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
write_budget(2)
plan.budget.all_full_budgets(3)
460
plan.budget.bbt_fixed_delay
Control whether delays added with bbt commands are treated as fixed by automatic
budgeting.
TYPE
bool
DEFAULT
true
DESCRIPTION
Black-box timing (bbt) delays can be added to your circuit using the
create_blackbox_delay and create_blackbox_constraint commands. When automatic
budgeting runs, it must decide whether to treat these bbt delays as "fixed" or "variable". If
the bbt delay is variable, budgeting will assume that the delay might be improved by
synthesis. So budgeting will tighten the block constraint, if necessary, to meet top-level
timing.
If the bbt delay is fixed, budgeting will not try not to tighten constraints on bbt delays. The
constraint will only be tightened if there is no choice. For example, a constraint will only be
tightened on a fixed bbt delay if the budgeted path has negative slack and there is no
variable delay in the path to optimize. When this happens, you will receive ABS-220
warnings.
By default, bbt delays are treated as "fixed" by budgeting. Set this option to false to enable
"variable" bbt delays.
SEE ALSO
create_blackbox_constraint(2)
create_blackbox_delay(2)
set_app_options(2)
Chapter 1:
plan.budget.bbt_fixed_delay
461
1-461
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.budget.compute_rise_fall_latencies
Control whether latencies are separately calculated for rise and fall by the
compute_budget_constraints command.
TYPE
true | false
DEFAULT
false
DESCRIPTION
When true, the compute_budget_constraints command will calculate separate nominal
latency values for the rise and fall edge of each clock. Likewise, a separate nominal CRP
value will be calculated.
When false, the compute_budget_constraints command will combine the latencies of rise
and fall together, and the same nominal value will be used for both edges.
SEE ALSO
compute_bugdget_constraints(2)
set_app_options(2)
plan.budget.compute_rise_fall_latencies
462
plan.budget.estimate_timing_mode
Control whether automatic budgeting bases slack allocation on estimate_timing delays.
TYPE
true | false | auto
DEFAULT
auto
DESCRIPTION
The automatic budgeter can run in one of two modes. In regular mode, automatic budgeting
creates constraints based on the worst delays across all active timing corners. In
estimate_timing mode, the automatic budgeter will base the budget only on delays in the
estimated_corner. This is desirable when some or all of your design is unoptimized.
Setting the option to "false" will cause the budgeter to use regular mode. Setting this option
to "true" will cause the budgeter to use estimate_timing mode. Setting this option to "auto"
will cause the budgeter to use estimate_timing mode when the estimated_corner is defined
and regular mode otherwise.
SEE ALSO
compute_bugdget_constraints(2)
set_app_options(2)
Chapter 1:
plan.budget.estimate_timing_mode
463
1-463
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.budget.include_all_clock_inputs
When splitting constraints, declare clocks at block inputs, even if they don't feed clock pins.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
boundaries. By default, if a clock goes through a block without connecting to any clocked
elements, the clock will not be declared for the given block.
If you set this option to true, the clock will be declared regardless of whether it fans out to a
clock pin.
SEE ALSO
plan.budget.include_feedthrough_clocks(3)
plan.budget.add_missing_feedthrough_clocks(3)
plan.budget.include_all_clock_inputs
464
plan.budget.include_feedthrough_clocks
When splitting constraints, declare clock in blocks where they feed through
TYPE
Boolean
DEFAULT
false
DESCRIPTION
boundaries. By default, if a clock goes through a block without connecting to any clocked
elements, the clock will not be declared for the given block.
If you set this option to true, a clock will be declared as long as it fans out to a clocked
element somehwere downstream (not necessarily in the given block).
Note that this app option only applies to the split_constraints command. It therefore only
works on feedthroughs that are in your original verilog network. Please see the man page
for plan.budget.add_missing_feedthrough_clocks for details about clock feedthroughs that
are added later in the flow.
SEE ALSO
plan.budget.include_all_clock_inputs(3)
plan.budget.add_missing_feedthrough_clocks(3)
Chapter 1:
plan.budget.include_feedthrough_clocks
465
1-465
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.budget.pessimistic_driving_cells
Controls how the driving cell delay is counted at the input of a budgeted block.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
At a boundary between block A and block B, there are two delays associated with the driving
cell:
In block A, there is an actual cell that drives the block output. Part of that cell's delay is
caused by the load contributed to the output port.
In block B, there is a delay associated with the set_driving_cell constraint that is set on
the input port.
By default, budgeting charges both blocks with their respective driving cell delays for setup
timing. This is pessimistic, as the same delay is counted twice.
If you set this option to false, the budgeter maintains greater control over driving cell
pessimism. It adjusts delays so that block B is charged only with the driving cell delay that is
caused by an excess of capacitive load. The excess is determined by your budget
constraints. For example, consider an input pin has the following boundary constraints:
set_boundary_budget_constraints -name pin1_constr \
-driving_cell BUFX4 -library my_lib
set_boundary_budget_constraints -name pin1_constr -corner default \
-fanin_capacitance 0 -load_capacitance 0.005
The budget is adjusted so that block B is charged with driving cell delay only when it has
input network capacitance greater than 0.005.
Note that this option applies only to setup budgets at block inputs. Hold budgets at block
inputs always use the -load_capacitance information, because the timing would be
optimistic without it.
466
SEE ALSO
write_budget(2)
set_app_options(2)
Chapter 1:
467
1-467
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.budget.split_latencies
Redefine clock latencies during split_constraints
TYPE
none | prects | postcts
DEFAULT
none
DESCRIPTION
During the split_constraints commands, chip-level SDC constraints are split up and
separate constraint files are written for child subblocks. By default (when this app_option is
set to "none"), clock latencies are pushed from the chip level down to each block, without
change. For example, if the source clock latency of clock CLK1 is 2 at the top level, the
source clock latency will still be 2 at the port boundary in the split constraints for each block.
If you set this app_option to "prects", then split_constraints will modify the clock latencies in
the block -- based on the budget constraints you have set. For example, if you have set:
# Set the total (network+source) latency in all blocks
set_latency_budget_constraints -clock CLK1 \
-early_latency 0.50 -late_latency 0.60
# Set the source latency in block B1
set_latency_budget_constraints -clock CLK1:B1 -source \
-early_latency 0.42 -late_latency 0.50
The latencies of clock CLK1 in block B1 will be modified. The source latency of the clock will
be 0.42/0.50. And the network latency of the clock will be adjusted so that the total latency
of the block will be 0.50/0.60. If you do not specify a source or total latency with the
set_latency_budget_constraints command, the chip level value for the latency will be used.
Setting this app_option to "postcts" is similar to "prects", except that no latencies will be
written for generated clocks with sources inside the block. It is assumed that latencies
should propagate to the generated clock, and explicitly setting the latency of a generated
clock will cause propagation to fail.
468
SEE ALSO
set_latency_budget_constraints(2)
set_app_options(2)
Chapter 1:
469
1-469
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.budget.time_with_margins
Specifies how margins are timed when evaluating budget paths.
TYPE
ignore | regular | fixed
DEFAULT
fixed
DESCRIPTION
The compute_budget_constraints command evaluates paths in your current circuit and
allocates delays among the budgeted blocks. If you have set extra timing margins with the
set_budget_margins command, those margins can be taken into account when deciding
budgets.
If you set this app option to "ignore", the margins are ignored during path analysis. If you set
this app option to "regular", the margins are treated like extra optimizable delays during path
analysis. If you set this app option to "fixed", the margins are treated like extra fixed,
unoptimizable, delays during path analysis.
SEE ALSO
report_budget(2)
set_app_options(2)
set_budget_margins(2)
plan.budget.time_with_margins
470
plan.clock_trunk.estimate_block_latency
Perform latency estimation of clocks in child blocks when running estimate_timing.
TYPE
bool
DEFAULT
false
DESCRIPTION
This app option affects the behavior of the estimate_timing command. When set to true,
estimate_timing also performs a latency estimation of the clocks in each block, in addition
to its normal checks.
This latency estimation is for automatic clock trunk planning with the
synthesize_clock_trunks command or manual clock trunk planning with the
gui_synthesize_clock_trunk command.
SEE ALSO
estimate_timing(2)
gui_synthesize_clock_trunk(2)
synthesize_clock_trunks(2)
Chapter 1:
plan.clock_trunk.estimate_block_latency
471
1-471
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.distributed_run.block_host
Specifies which host option to be used for the block during distributed runs.
TYPE
string
DEFAULT
""
DESCRIPTION
This option allows the user to specify different host options for different blocks in the design.
Once this option is set, all distributed commands respect it. It allows the user to control the
type of host that distributed jobs for a specific block will run on, and to allocate more
resources to bigger or more difficult blocks. By default the block run will use the host option
specified in the distributed command.
The option is persistent and will be saved with the block. The host option definition, however
is not. The used host options need to be specified again for each new session.
specified globally or with respect to a block. This application option needs to be associated
with a block. Use report_app_options to show the value of application options.
EXAMPLE
In the following example, 3 different host options are defined:
prompt> set_host_options -name small_block -submit_command "bsub -q
normal"
prompt> set_host_options -name large_block -submit_command "bsub -q huge"
prompt> set_host_options -name special_block -submit_command "rsh"
local_machine
Then the block_host app option is set on specific blocks:

prompt> set_app_options -block [get_block block4] -list
{plan.distributed_run.block_host large_block }
472
{plan.distributed_run.block_host large_block }
{plan.distributed_run.block_host special_block }
Then, a distributed command is run:

create_placement -floorplan -host_options small_block
All the jobs associated with blocks that do not have the plan.distributed_run.block_host app
option specified will run using the small_block host option. The jobs for blocks block4 and
block5 will use the large_block host option. The job form block2 will use the special_block
host option.
SEE ALSO
set_host_options(2)
run_block_script(2)
set_app_options(2)
Chapter 1:
473
1-473
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.estimate_timing.abstract_add_feedthrough_buffer
Perform actual feedthrough buffer insertion when creating estimated abstract for child
blocks from the top level.
TYPE
bool
DEFAULT
true
DESCRIPTION
This app option controls the feedthrough buffer creation when creating estimated abstract
views for child blocks from the top level, either implicitly through estimate_timing command
or explicitly by calling create_abstract -all_blocks | -blocks.
When this app option is true, add_feedthrough_buffer would be performed on the child
blocks before create_abstract -estimate_timing.
There are 3 other app options that can be used to control what options to use for the
add_feedthrough_buffer operation in the blocks.
SEE ALSO
set_app_options(2)
plan.estimate_timing.abstract_feedthrough_buffer_side(3)
plan.estimate_timing.abstract_feedthrough_user_buffer(3)
plan.estimate_timing.abstract_feedthrough_logical(3)
plan.estimate_timing.abstract_add_feedthrough_buffer
474
plan.estimate_timing.abstract_feedthrough_buffer_side
Control the -buffer_side option for feedthrough buffer insertion when creating estimated
abstract for child blocks from the top level.
TYPE
string
DEFAULT
""
DESCRIPTION
This app option works with plan.estimate_timing.abstract_add_feedthrough_buffer. It
controls whether to add buffer on input side or output side or both of a feedthrough net.
SEE ALSO
set_app_options(2)
plan.estimate_timing.abstract_add_feedthrough_buffer(3)
Chapter 1:
plan.estimate_timing.abstract_feedthrough_buffer_side
475
1-475
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.estimate_timing.abstract_feedthrough_logical
Control the -logical option for add_feedthrough_buffers when creating estimated abstract
for child blocks from the top level.
TYPE
bool
DEFAULT
false
DESCRIPTION
This app option works with plan.estimate_timing.abstract_add_feedthrough_buffer and
controls whether to buffer logical feedthroughs that can lead to assign statement.
SEE ALSO
set_app_options(2)
plan.estimate_timing.abstract_feedthrough_logical
476
plan.estimate_timing.abstract_feedthrough_user_buffer
Controls the -user_buffer option for add_feedthrough_buffers when creating estimated
abstract for child blocks from the top level.
TYPE
string
DEFAULT
""
DESCRIPTION
This app option works with plan.estimate_timing.abstract_add_feedthrough_buffer and
controls the buffer that is used for feedthrough buffering.
SEE ALSO
set_app_options(2)
Chapter 1:
plan.estimate_timing.abstract_feedthrough_user_buffer
477
1-477
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.estimate_timing.optimize_layers
Perform layer promotion when estimating timing for child blocks or top level.
TYPE
bool
DEFAULT
false
DESCRIPTION
This app option controls the layer promotion feature in estimate_timing command or
create_abstract -estimate_timing.
When this app option is true, layer promotion would be performed on the child blocks by
create_abstract -estimate_timing or on top level by estimate_timing.
SEE ALSO
estimate_timing(2)
create_abstract(2)
set_app_options(2)
plan.estimate_timing.optimize_layers
478
plan.estimate_timing.optimize_layers_count
Define how many layers from top most will be used by layer promotion when estimating
timing for child blocks or top level.
TYPE
integer
DEFAULT
4
DESCRIPTION
This app option controls the total counts of layers used by layer promotion in
estimate_timing command or create_abstract -estimate_timing.
When this app option is set, tool will use those number of layers counted from top most
layers without ignored layers setting. If this app option is not set, tool will use the default
value count of layers.
SEE ALSO
plan.estimate_timing.optimize_layers(3)
estimate_timing(2)
create_abstract(2)
set_app_options(2)
Chapter 1:
plan.estimate_timing.optimize_layers_count
479
1-479
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.flow.create_block_abstract_options
Specifies the options for the create_abstract command when performing
load_block_constraints and estimate_timing.
TYPE
String
DEFAULT
""
DESCRIPTION
During the load_block_constraints and estimate_timing steps, the tool might automatically
perform create_abstract operations for the child blocks. Use this application option to control
the options that are performed for the create_abstract operation.
By default, the tool runs create_abstract -estimate_timing during the estimate_timing step.
This is performed for the child blocks that do not reference a design view or abstract view
with estimated_corner information. If this application option is set to a string with a length
greater than zero, the string is used to set options for create_abstract step for the child
block. If the setting for a block is an empty string (zero length), the tool checks the setting of
the top-level block and uses the top-level block settings if not empty.
During load_block_constraints, the tool automatically performs create_abstract for the child
blocks that reference an outline view or abstract view. By default, the tool derives the options
to use for the block level create_astract step based on the type of the existing abstract view.
If a block has no abstract view, the placement abstract view is to be created.
This is a design scoped application option.
plan.flow.create_block_abstract_options
480
plan.flow.overwrite_work_dir
Remove all files in the work directory of the command before running.
TYPE
bool
DEFAULT
false
DESCRIPTION
There are several commands in design planning that would run operations inside child
blocks of the current block. These commands need to create files for each child block under
a work directory. Running such a command repeated can produce many log files on disk
under a particular work directory.
This app option controls the command to remove all existing files in its corresponding work
directory before starting a new run.
SEE ALSO
set_app_options(2)
Chapter 1:
plan.flow.overwrite_work_dir
481
1-481
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.flow.segment_rule
Specify the segment parity rule type to honor in design planning.
TYPE
list
DEFAULT
""
DESCRIPTION
There are two types of segment parity rule in design planning: horizontal even, vertical even.
For horizontal even, all the horizontal edges of place-able area and all the place-able site
rows must be even number of site width. For vertical even, all the vertical edges of
place-able area and all the place-able site columns must be even number of site height.
This app option accepts two keywords, "horizontal_even" and "vertical_even". User can
specify either one of them, none of them or both of them.
SEE ALSO
set_app_options(2)
shape_blocks(2)
plan.flow.segment_rule
482
plan.flow.target_site_def
Specify the site def to honor in design planning if segment parity rule is honored.
TYPE
string
DEFAULT
""
DESCRIPTION
The site def specified in this app option will be used by initialize_floorplan and be used to
find the site rows by shape_blocks for the segment parity rule.
SEE ALSO
plan.flow.segment_rule(2)
set_app_options(2)
shape_blocks(2)
Chapter 1:
plan.flow.target_site_def
483
1-483
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.macro.auto_macro_array_max_height
Maximum height of an auto-generated macro array.
TYPE
length
DEFAULT
0
DESCRIPTION
This option specifies the maximum height of an auto-generated macro array created during
create_placement -floorplan; note that the value of 0 is an exception, it means no limit.
The default is 0. The option type is length, which means that it must be specified with the
length unit.
of application options. This application option is design specific.
SEE ALSO
create_placement(2)
set_app_options(2)
plan.macro.auto_macro_array_max_height
484
plan.macro.auto_macro_array_max_num_cols
Maximum number of columns in an auto-generated macro array.
TYPE
integer
DEFAULT
0
DESCRIPTION
This option specifies the maximum number of columns in an auto-generated macro array
created during create_placement -floorplan; note that the value of 0 is an exception, it
means no limit. The default is 0.
SEE ALSO
create_placement(2)
set_app_options(2)
Chapter 1:
plan.macro.auto_macro_array_max_num_cols
485
1-485
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.macro.auto_macro_array_max_num_rows
Maximum number of rows in an auto-generated macro array.
TYPE
integer
DEFAULT
0
DESCRIPTION
This option specifies the maximum number of rows in an auto-generated macro array
created during create_placement -floorplan; note that the value of 0 is an exception, it
means no limit. The default is 0.
SEE ALSO
create_placement(2)
set_app_options(2)
plan.macro.auto_macro_array_max_num_rows
486
plan.macro.auto_macro_array_max_width
Maximum width of an auto-generated macro array.
TYPE
length
DEFAULT
0
DESCRIPTION
This option specifies the maximum width of an auto-generated macro array created during
create_placement -floorplan; note that the value of 0 is an exception, it means no limit.
The default is 0. The option type is length, which means that it must be specified with the
length unit.
SEE ALSO
create_placement(2)
set_app_options(2)
Chapter 1:
plan.macro.auto_macro_array_max_width
487
1-487
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.macro.auto_macro_array_minimize_channels
Specifies the way macros belonging to auto generated arrays are oriented during hard
macro placement.
TYPE
Enum
DEFAULT
"none"
DESCRIPTION
This option controls the orientation of macros belonging to arrays created during
create_placement -floorplan. Possible values are "none", "pins_in", and "pins_out". The
default is "pins_in".
The option makes a difference only for macros with pins on one side only. For simplicity, let's
assume that the sides with pins are vertical (similar argument, with obvious changes, will
apply if they are horizontal).
If the value of the option is "none", there is no restriction how macros are flipped to minimize
wirelength. This will frequently produce situations where, within an array, all macro sides
with pins are facing the same way, typically towards the middle of the design, thus creating
a channel between any two columns of macros. If the value is "pins_in", macros are flipped
so that sides with the pins on neighboring macros are facing each other; the opposite sides
without pins will be back-to-back, hence producing channels every two columns. If the value
is "pins_out", macros are flipped so that sides without the pins on neighboring macros are
placed back-to-back; the opposite sides with pins will be facing each other. The values
pins_in and pins_out are similar in that they both reduce number of channels approximately
by half and they both produce pins facing and opposite sides back-to-back, but what is done
first - pins facing each other or back-to-back opposite sides - causes different results when
there is an even number of columns. With pins_in, the first and the last column will have pins
facing inside the array, while with pins_out, the first and the last column will have pins facing
outside the array, producing one channel less than pins_in. The exception is that in pins_out
case, if the first or last column is against the boundary, the macros in that column will be
flipped so that pins will face away from the boundary.
488
SEE ALSO
create_placement(2)
set_app_options(2)
Chapter 1:
489
1-489
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.macro.auto_macro_array_size
Specifies the amount of array packing to use during hard macro placement.
TYPE
Enum
DEFAULT
"high"
DESCRIPTION
This controls the amount of macro array packing to use during create_placement
-floorplan. Possible values are "none", "low", "medium", and "high". The default is "high". If
the value is "none", no array packing happens; "high" produces more array packing, i.e.
potentially larger arrays than "low", with "medium" being in between.
SEE ALSO
create_placement(2)
set_app_options(2)
plan.macro.auto_macro_array_size
490
plan.macro.buffer_channel_height
Specifies height of buffer channels between macros.
TYPE
length
DEFAULT
0
DESCRIPTION
During the execution of the command create_placement -floorplan, once the height of the
macro stack reaches the value specified using the plan.macro.max_buffer_stack_height
option, a channel will be created for the buffer placement. This option specifies the height of
that channel. The default value is 0, which means no channel will be created.
SEE ALSO
create_placement(2)
plan.macro.max_buffer_stack_height(3)
set_app_options(2)
Chapter 1:
plan.macro.buffer_channel_height
491
1-491
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.macro.buffer_channel_width
Specifies max width of macro stack before buffer channel will be inserted.
TYPE
length
DEFAULT
0
DESCRIPTION
During the execution of the command create_placement -floorplan, once the width of the
macro stack reaches the value specified using this option, a channel will be created for the
buffer placement; the width of that channel is specified using
plan.macro.buffer_channel_width option. The default value is 0, which means no channel
will be created.
SEE ALSO
create_placement(2)
plan.macro.buffer_channel_width(3)
set_app_options(2)
plan.macro.buffer_channel_width
492
plan.macro.congestion_iters
Specifies the number of congestion reduction iterations to do for macro placement.
TYPE
integer
DEFAULT
1
DESCRIPTION
During the execution of the command create_placement -floorplan -congestion, the
width of the channels between the macros is adjusted based on a congestion estimation.
This parameter determines the number of times the congestion is estimated and the
channels are adjusted. The default value is 1, which means the channel width are updated
once.
Application options are set using the set_app_options command. Use
report_app_options to show the value of application options. This application option is
design specific.
SEE ALSO
create_placement(2)
plan.macro.congestion_driven_mode(3)
set_app_options(2)
Chapter 1:
plan.macro.congestion_iters
493
1-493
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.macro.create_temporary_pg_grid
Specifies a command or script to use to create a temporary power and ground (PG) grid for
congestion estimation during macro placement
TYPE
String
DEFAULT
By default, no temporary PG grid is created.
DESCRIPTION
When executing create_placement -floorplan -congestion, the tool will use a
routing-based congestion estimation to try to reduce the congestion over and between
macros. To enhance the precision of the congestion estimation, you can let the tool do a
temporary PG grid insertion right before the congestion estimation routing is done. This
option enables the temporary PG grid creation.
If the option is set to the name of a Tcl script file, the tool sources the file. Otherwise, the
input is treated as a Tcl command. It will be sourced and executed just before congestion
estimation routing. After the congestion estimation routing is done, all power and ground
shapes and vias are removed from the design.
Note that the generated power and ground grid is only temporary for the congestion
estimation. To save run time, it might be wise to use the -ignore_drc option of compile_pg.
specified globally or with respect to a design. This application option is global only and is not
persistent.
SEE ALSO
compile_pg(2)
create_placement(2)
set_app_options(2)
plan.place.congestion_driven_mode(3)
plan.macro.create_temporary_pg_grid
494
plan.macro.cross_block_connectivity_planning
Specifies if and in what way cross block connectivity planning should be done for macro
placement.
TYPE
soft | hard | false
DEFAULT
false
DESCRIPTION
During the execution of the command create_placement -floorplan, the tool can analyze
the connectivity between sub-blocks and try to keep a section of the boundary between
blocks free of macros. The resulting free edge can then be used to place pins later in the
flow. To determine the edge width required for the pins, block level pin constraints are taken
into account.
When using the value soft, this will be interpreted as a soft constraint, which can be violated
if other considerations are deemed more important. When using hard, it is interpreted as a
hard constraint, which might lead to a solution that has the free edge space required, but
might have to sacrifice other properties to achieve this. The default value is false, which
means that no cross block communication planning is done.
This application option is design specific. When set for a design, it will also be applied for all
sub-designs. The behavior for sub-designs can be overwritten by setting a different value for
a sub-designs.
Application options are set using the set_app_options command. Use
report_app_options to show the value of application options.
SEE ALSO
create_placement(2)
set_block_pin_constraints(2)
set_app_options(2)
Chapter 1:
plan.macro.cross_block_connectivity_planning
495
1-495
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.macro.grid_error_behavior
Specifies what to do if there is a failure to assign grids to macros.
TYPE
Enum
DEFAULT
"continue"
DESCRIPTION
This options allows user to specify the behavior if assigning grids to macro fails. If the value
is "continue", create_placement -floorplan will print warnings and continue execution. If
the value is "macro_place_only", after printing warnings, the command will stop as soon as
macro locations have been decided, basically the same as if plan.macro.macro_place_only
option has been set to true. If the value is "quit", the command will print errors and stop
immediately. The default value is "continue".
SEE ALSO
create_placement(2)
set_app_options(2)
plan.macro.grid_error_behavior
496
plan.macro.macro_place_only
Specifies whether to stop the placement when macro locations are decided.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When true, this option stops the create_placement -floorplan command as soon as macro
locations are decided. This allows you to inspect macro locations with minimum runtime.
Note that the standard cell placement will not be useful. The default value is false.
SEE ALSO
create_placement(2)
set_app_options(2)
Chapter 1:
plan.macro.macro_place_only
497
1-497
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.macro.max_buffer_stack_height
Specifies max height of macro stack before buffer channel will be inserted.
TYPE
length
DEFAULT
0
DESCRIPTION
During the execution of the command create_placement -floorplan, once the height of the
buffer placement; the height of that channel is specified using
plan.macro.buffer_channel_height option. The default value is 0, which means no
channel will be created.
SEE ALSO
create_placement(2)
plan.macro.buffer_channel_height(3)
set_app_options(2)
plan.macro.max_buffer_stack_height
498
plan.macro.max_buffer_stack_width
Specifies max width of macro stack before buffer channel will be inserted.
TYPE
length
DEFAULT
0
DESCRIPTION
During the execution of the command create_placement -floorplan, once the width of the
buffer placement; the width of that channel is specified using
plan.macro.buffer_channel_width option. The default value is 0, which means no channel
will be created.
SEE ALSO
create_placement(2)
plan.macro.buffer_channel_width(3)
set_app_options(2)
Chapter 1:
plan.macro.max_buffer_stack_width
499
1-499
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.macro.pin_shape_track_match_threshold
Specifies the threshold size to use when color matching pin shapes and tracks.
TYPE
list
DEFAULT
Empty list
DESCRIPTION
This options allows user to specify the threshold size (width for vertical layers, height for
horizontal). Pin shapes larger than this size will not be considered for color matching with
tracks. The value is a list of pairs of layer names and lengths, i.e. the list format is: {
{layer_name1 size1} {layer_name2 size2} ... }
For a given layer, if value is not specified, the size used will be min width for that layer. The
default is an empty list.
EXAMPLES
The following example specifies threshold of 23 nm on layer M2 and 25nm on layer M3.
prompt> set_app_options set_app_options -block [current_design] -list {
plan.macro.pin_shape_track_match_threshold { {M2 23nm} {M3 25nm} } }
SEE ALSO
create_placement(2)
500
set_app_options(2)
Chapter 1:
501
1-501
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.macro.spacing_rule_heights
Set spacing rules heights for macro placement.
TYPE
pair of distances
DEFAULT
{ 0um 0um }
DESCRIPTION
The option specifies two values, the exact distance and the at least distance. In order to
satisfy the rule, the vertical distance between any two macros must either be equal to the
exact distance or be greater than or equal to the at least distance. Both distances are
expected to be non-negative, and at least distance is expected to be greater than the exact
distance. The default value is { 0um 0um }, which means there is no spacing rule to enforce.
This option is respected by create_placement -floorplan command.
SEE ALSO
create_placement(2)
plan.macro.spacing_rule_widths(3)
plan.macro.spacing_rule_heights
502
plan.macro.spacing_rule_widths
Set spacing rules widths for macro placement.
TYPE
pair of distances
DEFAULT
{ 0um 0um }
DESCRIPTION
The option specifies two values, the exact distance and the at least distance. In order to
satisfy the rule, the horizontal distance between any two macros must either be equal to the
exact distance or be greater than or equal to the at least distance. Both distances are
expected to be non-negative, and at least distance is expected to be greater than the exact
distance. The default value is { 0um 0um }, which means there is no spacing rule to enforce.
This option is respected by create_placement -floorplan command.
SEE ALSO
create_placement(2)
plan.macro.spacing_rule_heights(3)
Chapter 1:
plan.macro.spacing_rule_widths
503
1-503
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.mtcmos.allow_partial_power_strap_overlap
Specifies whether power switches are allowed if not fully covered by the strap to which it
should aligned.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, power switches are allowed if they are not fully covered by the power
straps to which they should align. Otherwise, power switches will be dropped. The default
value is false.
This application option is set using the set_app_options command, and may be specified
globally. To determine the current value of this application option on a specific design, use
get_app_option_value -name opt_name. Use report_app_options to show the value of
multiple application options.
SEE ALSO
create_power_switch_array(2)
plan.mtcmos.allow_partial_power_strap_overlap
504
plan.mtcmos.allow_power_switch_outside_core
Specifies whether power switches can be placed outside the core region.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, power switches can be placed outside the core region. Otherwise, power
switches will be dropped if they are outside the core region. The default value is false.
SEE ALSO
create_power_switch_ring(2)
Chapter 1:
plan.mtcmos.allow_power_switch_outside_core
505
1-505
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.mtcmos.snap_to_legal_index
Specifies if power switch cells should be snapped to legal index.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, power switch cells will be snapped to legal index. Note that this app option
is only valid when option -snap_to_site_row is true. By default, the value is false.
SEE ALSO
plan.mtcmos.snap_to_legal_index
506
plan.mtcmos.snap_to_siterow_orient
Specifies if power switch cells should only be snapped to siterows with specified orientation.
TYPE
string <R0|MX|"">
DEFAULT
""
DESCRIPTION
When set to R0, power switch cells will be snapped to siterows with R0 site orientation.
When set to MX, power switch cells will be snapped to siterows with MX site orientation. If
not specified, power switch cells can be snapped to all siterows. By default, the value is an
empty string "".
Note that this app option is only valid when option -snap_to_site_row is true. If power switch
is double height cell and needs to be snapped to every other row. This app option can be
used to control the snapping.
SEE ALSO
Chapter 1:
plan.mtcmos.snap_to_siterow_orient
507
1-507
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.mtcmos.treat_keepout_as_blockage
Specifies if power switch insertion should treat keepout regions as blockages.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
When set to true, keepout regions are treated as blockages for power switch insertion.
Otherwise, keepout regions will not be treated as blockages. By default, the value is true.
SEE ALSO
plan.mtcmos.treat_keepout_as_blockage
508
plan.mtcmos.treat_voltage_area_as_blockage
Specifies whether power switch insertion should treat other voltage areas as blockages.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
When set to true, voltage areas not associated with current power switch strategy are
treated as blockages for power switch insertion. Otherwise, voltage areas will not be treated
as blockages. By default, the value is true.
SEE ALSO
Chapter 1:
plan.mtcmos.treat_voltage_area_as_blockage
509
1-509
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.outline.dense_module_depth
Specifies the number of levels from the top of the module hierarchy to make dense modules.
TYPE
integer
DEFAULT
1
DESCRIPTION
This application option specifies the number of levels from the top of the module hierarchy
to make dense modules.
The default is 1, which means just the top level of the module hierarchy. A value of 2 makes
the top module and its immediate children dense, and so on. A value of -1 makes all
non-sparse modules dense.
SEE ALSO
expand_outline(2)
get_app_options(2)
set_app_option(2)
plan.outline.dense_module_depth
510
plan.outline.glue_cell_count
Specifies the target total number of leaf cells in small dense modules used as glue logic
between partitions.
TYPE
integer
DEFAULT
100,000
DESCRIPTION
This application option specifies the target total number of leaf cells in small dense modules
used as glue logic between partitions.
Module hierarchies in the outline design are marked dense from the top of the partition on
down, as long as the target is not exceeded. Inverter and buffer cells are not included in the
count.
A value of -1 skips marking any glue modules as dense.
SEE ALSO
expand_outline(2)
get_app_options(2)
set_app_option(2)
Chapter 1:
plan.outline.glue_cell_count
511
1-511
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.outline.keep_port_depth
Specifies the number of levels from the top of the module hierarchy to preserve module port
interfaces.
TYPE
integer
DEFAULT
1
DESCRIPTION
This application option specifies the number of levels from the top of the module hierarchy
to preserve module port interfaces.
The default is 1, which means just the top level of the module hierarchy. A value of 2
preserves the port interfaces of the top module and its immediate children, and so on. A
value of -1 preserves the port interfaces of all modules.
SEE ALSO
expand_outline(2)
get_app_options(2)
set_app_option(2)
plan.outline.keep_port_depth
512
plan.outline.large_threshold
Specifies the number of leaf cells a module can have before it is considered a large module
that should be represented as a sparse module.
TYPE
integer
DEFAULT
10000
DESCRIPTION
This application option specifies the number of leaf cells a module can have before it is
considered a large module that should be represented as a sparse module. Inverter and
buffer cells are not included in the count.
SEE ALSO
expand_outline(2)
get_app_options(2)
set_app_option(2)
Chapter 1:
plan.outline.large_threshold
513
1-513
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.outline.message_limit
Specifies the maximum number of 'Module not found in Verilog' warnings to issue for each
of the -dense_modules, -port_modules, or -sparse_modules options.
TYPE
integer
DEFAULT
4
DESCRIPTION
This application option specifies the maximum number of 'Module not found in Verilog'
warnings to issue for each of the -dense_modules, -port_modules, or -sparse_modules
options.
The default is four warnings for each option. A value of -1 removes the limit and issues a
warning for each module that is specified, but not found in the Verilog netlist.
SEE ALSO
expand_outline(2)
get_app_options(2)
set_app_option(2)
plan.outline.message_limit
514
plan.outline.partition
Selects whether the tool uses the allocation or partition method to determine dense or
sparse modules when reading the outline Verilog modules.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option selects whether the tool uses the allocation or partition method to
determine dense or sparse modules when reading the outline Verilog modules.
By default (false), the tool uses the allocation method. When set to true, the tool uses the
partition method.
SEE ALSO
expand_outline(2)
get_app_options(2)
set_app_option(2)
Chapter 1:
plan.outline.partition
515
1-515
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.outline.target_block_size
Specifies the target number of cells in each outline partition block.
TYPE
integer
DEFAULT
1000000
DESCRIPTION
This application option specifies the target number of cells in each outline partition block.
The partition outline method makes modules at the top of the module hierarchy dense until
the number cells below that module is less than a target number of cells. Below that
threshold, modules are marked sparse. Inverter and buffer cells are included in the
hierarchical count.
SEE ALSO
expand_outline(2)
get_app_options(2)
set_app_option(2)
plan.outline.target_block_size
516
plan.outline.target_cell_count
TYPE
integer
DEFAULT
1000000
DESCRIPTION
This application option specifies the target total number of leaf cells in the modules of an
outline design read by the read_verilog_outline command.
Modules in the outline design are marked dense from the top of the module hierarchy on
down, as long as the target is not exceeded. Inverter and buffer cells are not included in the
count.
SEE ALSO
expand_outline(2)
get_app_options(2)
set_app_option(2)
Chapter 1:
plan.outline.target_cell_count
517
1-517
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.path_analysis.enable_timing
Specifies whether timing evaluation should be done during path analysis.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
The analyze_paths command is used to analyze path connectivity between macros, ports,
and hierarchies in your floorplan. By default, both the number and timing criticality of paths
path examined. By setting this app option to false, you can disable the timing part of path
analysis. Doing this can save well over half of the analysis runtime, and give you results in
just a few minutes.
Set this option to true to get timing analysis for you paths between objects.
SEE ALSO
analyze_paths(2)
set_app_options(2)
plan.path_analysis.enable_timing
518
plan.pgcheck.check_signal_ports
Specifies if signal ports assigned with tied-off nets should be checked by
check_pg_connectivity.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
When set to true, tied-off signal ports will be checked by check_pg_connectivity. Otherwise,
these ports will not be checked. By default, the value is true.
SEE ALSO
check_pg_connectivity
Chapter 1:
plan.pgcheck.check_signal_ports
519
1-519
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.pgcheck.ignore_unfixed_std_cells
Specifies if unfixed std cells should be checked by check_pg_connectivity.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, check_pg_connectivity will only check std cells with fixed status. By
default, the value is false.
SEE ALSO
plan.pgcheck.ignore_unfixed_std_cells
520
plan.pgcheck.use_pin_as_bridge
Specifies if pins in a macro/std_cells should be considered as bridges to connect PG straps
by check_pg_connectivity.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, check_pg_connectivity will assume all the pin shapes of the same port in
a macro or std cell are internally connected. In this case, PG shapes connecting to disjoint
pins will be considered as connected using the pins as bridges. Otherwise, we assume the
disjoint PG pins are not connected. By default, the value is false.
SEE ALSO
Chapter 1:
plan.pgcheck.use_pin_as_bridge
521
1-521
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.pgroute.auto_connect_pg_net
Specifies whether or not PG route calls connect_pg_net under-the-hood.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When true, PG route commands call connect_pg_net command internally to update the
PG net-pin logic connectivity. By default, the value is false and connect_pg_net is not
called.
SEE ALSO
set_pg_strategy(2)
plan.pgroute.auto_connect_pg_net
522
plan.pgroute.disable_via_creation
Do not create any vias during compile_pg.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, PG route command compile_pg does not create any vias even though via
masters are specified. By default, the value is false.
SEE ALSO
compile_pg(2)
Chapter 1:
plan.pgroute.disable_via_creation
523
1-523
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.pgroute.drc_check_fast_mode
Specifies the DRC checking fast mode in PG router.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When true, PG route commands use low-effort or fast-mode DRC checking method for
runtime speed-up. By default, the value is false.
SEE ALSO
compile_pg(2)
create_pg_vias(2)
create_pg_strap(2)
plan.pgroute.drc_check_fast_mode
524
plan.pgroute.honor_signal_route_drc
Specifies if PG route commands should honor signal route for DRC check.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, PG route commands honor the existing signal route for DRC check.
Otherwise, signal route is ignored for DRC check. By default, the value is false.
SEE ALSO
compile_pg(2)
create_pg_vias(2)
create_pg_strap(2)
Chapter 1:
plan.pgroute.honor_signal_route_drc
525
1-525
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.pgroute.honor_std_cell_drc
Specifies if PG route commands should honor internal shapes of standard cells for DRC
check.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, PG route commands honor the internal shapes of standard cells for DRC
check. Otherwise, standard cell is ignored for DRC check. By default, the value is false.
SEE ALSO
compile_pg(2)
create_pg_vias(2)
create_pg_strap(2)
plan.pgroute.honor_std_cell_drc
526
plan.pgroute.max_undo_steps
Specifies the maximum number of undo steps for the compile_pg PG route command.
TYPE
Integer
DEFAULT
5
DESCRIPTION
This app option specifies the maximum number of undo steps of compile_pg PG route
command. By default, the number of steps is five and the last five steps of compile_pg
command can be reversed.
SEE ALSO
compile_pg(2)
create_pg_strap(2)
create_pg_vias(2)
Chapter 1:
plan.pgroute.max_undo_steps
527
1-527
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.pgroute.overlap_route_boundary
Specifies if PG route command allows PG wires being created partially overlapped with
routing area boundary.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, PG route command compile_pg allows PG wires being created partially
overlapped with routing area boundary. Otherwise, these PG wires will not be created. By
default, the value is false.
SEE ALSO
compile_pg(2)
plan.pgroute.overlap_route_boundary
528
plan.pgroute.snap_stdcell_rail
Specifies if PG route command allows PG straps being extended or snapped to standard
cell rails.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, PG route command compile_pg allows PG straps being extended or
snapped to standard cell rails. Otherwise, PG straps are not extended or snapped to
standard cell rails. By default, the value is false.
SEE ALSO
compile_pg(2)
Chapter 1:
plan.pgroute.snap_stdcell_rail
529
1-529
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.pgroute.verbose
Specifies PG route command in verbose mode.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, PG route command compile_pg may output more detailed information.
By default, the value is false.
SEE ALSO
compile_pg(2)
plan.pgroute.verbose
530
plan.pgroute.via_site_threshold
Specifies the minimum via site threshold for PG via creation during PG route.
TYPE
Double
DEFAULT
0.0
DESCRIPTION
This app option specifies the minimum via site ratio threshold for PG via creation during PG
route. By default, the value is 0.0, i.e. vias are created for all via sites. This app option can
be used to control if vias are needed between partially intersected PG wires or between PG
wires and macro pins.
SEE ALSO
compile_pg(2)
create_pg_vias(2)
create_pg_strap(2)
Chapter 1:
plan.pgroute.via_site_threshold
531
1-531
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.pins.exclude_clocks_from_feedthroughs
TYPE
boolean
DEFAULT
"true"
DESCRIPTION
Specifies whether feedthrough port creation is excluded on clock nets.
By default, this option is true (clock nets are excluded).
This option affects commands plan_pins, route_global -virtual_flat and route_group
-global_planning.
SEE ALSO
get_app_options(2)
set_app_option(2)
place_pins(2)
set_individual_pin_constraints(2)
plan.pins.exclude_clocks_from_feedthroughs
532
plan.pins.exclude_inout_nets_from_feedthroughs
TYPE
boolean
DEFAULT
"true"
DESCRIPTION
Specifies whether feedthrough port creation is excluded on nets that are connected to
multiple driver pins, or nets that are without driver pins, or nets that are connected to inout
pins. When this option is set to true, the feedthrough port and feedthrough net will be
disabled on all the nets that are connected to multiple driver pins, or nets that are without
driver pins, or nets that are connected to inout pins
By default, this option is false.
This option affects commands plan_pins, route_global -virtual_flat and route_group
-global_planning.
SEE ALSO
get_app_options(2)
set_app_option(2)
place_pins(2)
Chapter 1:
plan.pins.exclude_inout_nets_from_feedthroughs
533
1-533
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.pins.incremental
TYPE
boolean
DEFAULT
"false"
DESCRIPTION
Performs incremental pin placement. Use this option to rerun pin placement after making
changes to the floorplan. The placer reuses the existing pin location if no QoR degradation
occurs. QoR considers wirelength, congestion, and pin alignment. If the pin can be moved,
and if the QoR improves, and if the new location is within the specified pin_range and
layer_range, the tool moves the pin to the new location. If there are missing pins, the
command places the missing pins and ignores the pin_range and layer_range values.
This option affects commands place_pins, route_global -virtual_flat and route_group
-global_planning.
SEE ALSO
get_app_options(2)
set_app_option(2)
place_pins(2)
plan.pins.incremental
534
plan.pins.layer_range
Sets layer range for incremental pin placement
TYPE
int
DEFAULT
"2"
DESCRIPTION
Specifies the allowable layer displacement from the original layer for the pin when using the
plan.pins.incremental option. By default, the layer_range is 2 and pins can be moved up
or down by 2 metal layers.
-global_planning.
SEE ALSO
get_app_options(2)
set_app_option(2)
place_pins(2)
Chapter 1:
plan.pins.layer_range
535
1-535
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.pins.new_port_name_tag
TYPE
string
DEFAULT
"suffix"
DESCRIPTION
Specifies the naming suffix for newly created feedthrough ports and feedthrough nets in
place_pins or push_down_objects commands. When this option is specified, the tool uses
new_port_name_tag as a suffix for newly created feedthrough ports and feedthrough nets.
In particular, the new name is "net_name__name_tag_#", where "name_tag" is the string
specified by this option. By default, newly created feedthrough ports and nets are named
"net_name__FEEDTHRU_#" in place_pins and "net_name__PUSHDOWN_#" in
push_down_objects, where net_name is the name of the original net that connected this
feedthrough port or feedthrough net, and "#" is an index number.
This option affects commands plan_pins, push_down_objects.
SEE ALSO
get_app_options(2)
set_app_option(2)
place_pins(2)
push_down_objects(2)
set_push_down_object_options
plan.pins.new_port_name_tag
536
plan.pins.new_port_name_tag_style
TYPE
string
DEFAULT
"suffix"
DESCRIPTION
Specifies the naming style is suffix or prefix for newly created feedthrough ports and
feedthrough nets in place_pins or push_down_objects commands.
When this option is specified as "suffix", the tool puts the new port name tag as suffix for
newly created feedthrough ports and feedthrough nets. In particular, the new name is
"net_name__name_tag_#", where "name_tag" is the string specified by "place_pins
-new_port_name_tag" or specified by "set_push_down_object_options
-new_port_name_tag" and "#" is an index number.
When this option is specified as "prefix", the tool puts the new port name tag as prefix for
newly created feedthrough ports and feedthrough nets. In particular, the new name is
"name_tag_#__net_name", where "name_tag" is the string specified by
"plan.pins.new_port_name_tag" application option, and "#" is an index number.
By default, this option is set to "suffix"
This option affects commands plan_pins, push_down_objects.
SEE ALSO
get_app_options(2)
set_app_option(2)
place_pins(2)
set_push_down_object_options
Chapter 1:
plan.pins.new_port_name_tag_style
537
1-537
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.pins.pin_range
Sets pin location range for incremental pin placement
TYPE
float
DEFAULT
"10"
DESCRIPTION
Specifies the allowable displacement distance from the original pin location when using the
plan.pins.incremental option. The unit is in micron. The default is 10 micron.
-global_planning.
SEE ALSO
get_app_options(2)
set_app_option(2)
place_pins(2)
plan.pins.pin_range
538
plan.pins.reserved_channel_threshold
TYPE
float
DEFAULT
"site row's height"
DESCRIPTION
Specifies the maximum channel size to channel routing. The units are in microns. You must
specify a positive value for channel_size. The default is same as default site row's height.
A "channel" is the space between a block or module on which pins can be placed and an
adjacent module, hard macro, or I/O pad. For channel formation, all modules and cells
(except standard cells) are considered. At least one side of the channel must be formed by
a block. The space between two hard macros is not considered as a channel by this option.
The chip boundary is also considered during channel creation.
The plan.pins.reserved_channel_threshold option modifies the behavior of global route
and pin placement within channels. There is a higher cost for pins on modules that face the
channel, unless they are perfectly aligned across the channel, or are pins belonging to the
special nets (that don't have feedthrough allowed). Nets that are allowed for feedthrough
routing will create feedthrough instead of entering the channels. This creates feedthrough
pins for these nets.
This option is useful for floorplans with only narrow channel spaces between the modules.
In this case, feedthroughs should generally be allowed, except for the special nets where
feedthroughs are excluded.
When this option is specified, global route will use higher effort to avoid routings inside
channel area to achieve better pin alignment.
-global_planning.
Chapter 1:
539
1-539
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
EXAMPLES
The following example sets the plan.pins.reserved_channel_threshold option to 100
micron.
prompt> set_app_options -global {plan.pins.reserved_channel_threshold
100}
SEE ALSO
get_app_options(2)
set_app_option(2)
place_pins(2)
540
plan.pins.retain_bus_name
TYPE
boolean
DEFAULT
"true"
DESCRIPTION
When set to "false", causes all new feedthroughs nets and ports created during design
planning operations place_pins and push_down_objects to use a scalarized (non-bus)
notation in the names when it detects that the originally-derived name would, when written
out to Verilog by write_verilog, result in an escaped name (preceded by a back-slash).
The name substitution would be of the form:
NAME[0] ---> converts to ---> NAME__0
Of course, this change only applies to ports and nets that are not marked in the database as
bus ports/nets. If a port/net has a bus-style notation, AND it is marked as a bus in the
database, then it will not substitute the name with a non-bus notation since when written out
to Verilog, it will not require a back-slash at the beginning of the name.
This option affects commands place_pins and push_down_objects .
SEE ALSO
get_app_options(2)
set_app_option(2)
place_pins(2)
Chapter 1:
plan.pins.retain_bus_name
541
1-541
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.pins.synthesize_abutted_pins
TYPE
Boolean
DEFAULT
"true"
DESCRIPTION
Specify whether the in place_pins or push_down_objects commands create abutted pins
for block pins that do not connect to any other pins, or create abutted pins for unused
feedthrough pins for a design with MIBs in an abutted design. When this app option is
specified, the place_pins command creates a new pin on neighboring abutted block and
connects the new pin to the original single pin. The pin is placed such that there is no single
pin violation in fully abutted design.
For block pins that connect to a tie high or tie low net, place_pins first breaks the top-level
connections. Next, place_pins creates a new pin on neighboring abutted block for each pin
and connects those two pins together to eliminate any single pin violation in a fully abutted
design. After running place_pins in a fully abutted design at the top level, the original pins
that connected to a tie low or tie high net are disconnected from the tie low or tie high net
and are connected to new neighboring block pins. When the original pin connects to a tie low
net inside a neighboring child block, the new pin will be connected to tie low net. If the
original pin connects to tie high net inside the neighboring child block, the new pin will be
connected to tie high net.
By default, this option is false.
This option affects the place_pins and push_down_objects commands.
SEE ALSO
get_app_options(2)
place_pins(2)
542
set_app_options(2)
Chapter 1:
543
1-543
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.place.auto_generate_blockages
Specifies whether to create both derived soft placement blockages and derived routing
blockages.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This app option controls whether to create soft placement blockages in channels between
hard and soft objects during create_placement -floorplan. Hard objects include hard
macros, hard keepout margins, block boundaries, VA boundaries, and hard placement
blockages. Soft objects include soft placement blockages and soft keepout margins. If true,
the tool creates a soft placement blockage between all adjacent hard/soft objects. These
placement blockages have a special attribute, "is_derived", so that they can be selected with
the get_placement_blockages -filter "is_derived==true" command. The
derive_placement_blockages command can also be used to create these blockages.
It is important to have these soft blockages so that standard cells do not get placed in the
narrow channels between hard macros. Typically these blockages are added after design
planning is finished and the block is ready to go to implementation.
This also controls whether to create routing blockages from route blockage keepouts. The
keepouts are created by create_keepout_margin -type route_blockage. The primary
usage for these blockages is to avoid power vias from getting too close to the macro pins.
As with placement blockages, these routing blockages are assigned the "is_derived" special
attributed:
Note that the "is_derived" attribute will be removed if you move or change the blockage. This
is because if you change a blockage, that means you have taken ownership of the blockage
and do not want the tool to automatically delete it in the next run of create_placement
-floorplan or derive_placement_blockages.
For greater control on these blockages see the man page for the
plan.place.auto_generate_hard_blockage_channel_width and
plan.place.auto_generate_soft_blockage_channel_width app options.
544
SEE ALSO
create_placement(2)
derive_placement_blockages(2)
get_placement_blockages(2)
set_app_options(2)
plan.place.auto_generate_hard_blockage_channel_width(3)
plan.place.auto_generate_soft_blockage_channel_width(3)
Chapter 1:
545
1-545
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.place.auto_generate_blockages_smooth_rectilinear
Specifies whether to consider slightly rectilinear macros as rectangular.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This is a control for when creating automatically generated blockages. To understand what
are automatically generated blockages look at plan.place.auto_generate_blockages.
This controls whether slightly rectilinear macros are considered to be the shape of their
rectangular bounding box when determining blockages. Considering them as their bounding
box generally leads to a better set of placement blockages so that swimming pools are not
created. However sometimes it is better to not do this as you get more blockages than you
may expect.
It is recommended to use the default setting unless you see something wrong with auto
generated blockages around slightly rectilinear macros, in which case you can change the
setting to see if result is better.
SEE ALSO
create_placement(2)
set_app_options(2)
plan.place.auto_generate_blockages(3)
546
Chapter 1:
547
1-547
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.place.auto_generate_hard_blockage_channel_width
Specifies the maximum channel width for creating a hard blockage.
TYPE
pair(typed length, typed length)
DEFAULT
(-1m, -1m)
DESCRIPTION
This option provides additional user control on the blockages created by the
plan.place.auto_generate_blockages option. See the plan.place.auto_generate_blockages
man page for more information.
This option sets two lengths in a pair. The first length is the maximum width of a horizontal
channel for hard blockage creation. The second length is the maximum width of a vertical
channel for hard blockage creation. By default no hard blockages will be created.
Hard blockages will be considered only between hard objects like hard macros, hard
keepout margins, block boundaries, VA boundaries, and hard placement blockages. Hard
blockages will not be considered for soft objects like soft placement blockages and soft
keepout margins.
Be careful setting this option as it takes a typed length. The default length type is "m" which
is millimeters, so "10" means 10 millimeters. Most likely you want to set a length like "10um"
which is 10 microns.
SEE ALSO
create_placement(2)
548
set_app_options(2)
Chapter 1:
549
1-549
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.place.auto_generate_soft_blockage_channel_width
Specifies the maximum channel width for creating a soft blockage.
TYPE
pair(typed length, typed length)
DEFAULT
(-1m, -1m)
DESCRIPTION
This is used to give user more control on the blockages created by the
plan.place.auto_generate_blockages option. See the plan.place.auto_generate_blockages
man page for more information.
This option sets two lengths in a pair. The first length is the maximum width of a horizontal
channel for soft blockage creation. The second length is the maximum width of a vertical
channel for soft blockage creation. By default, the tool will determine a good maximum width
for soft blockages to be created.
Be careful setting this option as it takes a typed length. The default length type is "m" which
is millimeters, so "10" means 10 millimeters. Most likely you want to set a length like "10um"
which is 10 microns.
SEE ALSO
create_placement(2)
set_app_options(2)
plan.place.auto_generate_soft_blockage_channel_width
550
plan.place.auto_max_density
Specifies whether to automatically use max_density during standard cell placement.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This controls whether to allow clumping of standard cells during placement of a block that
has subblocks. Typically when the utilization is very low and for better QoR it is needed to
allow standard cells to clump (ie not spread out evenly).
Another control for clumping of standard cells is the app option place.max_density. The
plan.place.auto_max_density app option essentially sets the place.max_density app option
to 0.7 automatically when it thinks utilization is low. However if you set the
place.max_density app option then that setting will override this setting.
SEE ALSO
create_placement(2)
set_keepout_margin(2)
set_app_options(2)
Chapter 1:
plan.place.auto_max_density
551
1-551
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.place.congestion_driven_mode
Specifies the type of congestion reduction to perform during floorplan placement.
TYPE
Enum
DEFAULT
"macro"
DESCRIPTION
The create_placement -floorplan -congestion command can reduce congestion over and
between the macros, and reduce congestion in the standard cell area.
This option controls where congestion reduction is applied. Possible values are "macro",
"std_cell", and "both". The default value "macro" enables the macro congestion reduction
but disables the standard cell congestion reduction. The value "std_cell" will do the reverse,
while the value "both" will enable both strategies. To disable both strategies, remove the
"-congestion" command option, in which case the value of this option is irrelevant.
Note that runtime penalty for enabling the standard cell congestion reduction will generally
be much larger than the penalty for enabling the macro congestion reduction.
Application options are set by using the set_app_options command, and in this case
should be specified globally. Use report_app_options to show the value of application
options. Note that this application option is not persistent.
EXAMPLES
The flowing example enables both the macro and standard cell congestion reduction
strategies.
prompt> set_app_options -list {plan.place.congestion_driven_mode both}
SEE ALSO
create_placement(2)
552
set_app_options(2)
Chapter 1:
553
1-553
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.place.default_keepout
Specifies whether to use default keepouts during hard macro placement.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This controls what hard_macro keepout margin is considered on hard macros during
create_placement -floorplan. If true, then a default hard_macro keepout margin is created
on all hard macros which do not have a user set hard_macro keepout. If false, then no
default hard_macro keepout is created (i.e., it is zero). The default hard_macro keepout
created is pin count based so sides with more pins will have a larger keepout.
It is important to have hard_macro keepouts to ensure hard macros are placed far enough
from each other so that routing can access the hard macro pins.
SEE ALSO
create_placement(2)
set_keepout_margin(2)
set_app_options(2)
plan.place.default_keepout
554
plan.place.poly_rule
Specifies the narrow placeable site threshold used to check poly rule.
TYPE
integer
DEFAULT
0
DESCRIPTION
Before the execution of the command report_placement -poly_rule, user must specify a
positive narrow placeable site threshold. If user use the default value 0 as the threshold, the
command report_placement -poly_rule will report an error.
SEE ALSO
report_placement(2)
Chapter 1:
plan.place.poly_rule
555
1-555
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.place.trace_mode
Control tracing method for connectivity extraction in macro placement.
TYPE
string
DEFAULT
normal
DESCRIPTION
This option specifies which tracing method to use for connectivity extraction during macro
placement. The connectivity extraction is either performed by create_placement
-floorplan, or by create_abstract -placement in case of the high capacity flow.
There are two possible values for this app option, "normal" or "dfa". The default value
"normal" picks a tracing method that extracts direct connectivity and connectivity via buffers
and inverters. The value "dfa" enables an enhanced tracing method that traces connectivity
through combinatorial standard cells. This is similar to what is available in the data flow
flylines (compute_dff_connections). Note that this analysis requires more runtime.
SEE ALSO
create_placement(2)
create_abstract(2)
compute_dff_connections(2)
plan.place.trace_mode
556
plan.pna.power_switch_resistance
Specify power switch resistance value for the specific power switch lib cell.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option is used to specify the power switch resistance value for the specific
power switch lib cell. And the power switch resistance value will be used to perform PNA.
The format to specify the power switch resistance value for a power switch lib cell is
{{power_switch_lib_cell_name1 power_switch_resistance_value1} ...}
It will not check if the specified power switch lib cell can be found.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
plan.pna.power_switch_resistance
557
1-557
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
plan.shaping.snap_to_boundary_grid
Specifies that the block grid will be considered as the boundary grid.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This option allows user to use the block grid (refer to create_grid) as the boundary grid so
that shape_blocks will create the shape with its vertexes are on the grid. To achieve this,
the fixed snapping point of the block grid has to be at (0, 0).
SEE ALSO
shape_blocks(2)
create_grid(2)
set_app_options(2)
plan.shaping.snap_to_boundary_grid
558
poly_rect_attributes
Description of the predefined attributes for poly_rects.
DESCRIPTION
poly_rect attributes are provided in the subsections that follow.
command.
PolyRect Attributes
area
An area attribute which reports the area contained within the poly_rect boundary.
is_rectangle
A boolean attribute for whether the poly_rect boundary forms a rectangle.
object_class
A string attribute with the value of "poly_rect".
point_list
A coordinate list attribute for the points of the poly_rect boundary.
layer
A collection attribute with the (optional) layer on which the poly_rect resides.
layer_name
A string_attribute for the name of the layer on which the poly_rect (optionally) resides.
Chapter 1:
559
1-559
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
create_poly_rect(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
560
port_attributes
Lists the predefined attributes for ports.
DESCRIPTION
Attributes are properties assigned to objects such as pins, cells and nets. Definitions for port
command.
Port Attributes
bias_type
Specifies the type of bias for the port. It comes from the bias type of the net connected to
this port. Possible values are device_layer and routing_pin.
case_sources
A collection of pins or ports that are the source of the case value on the given port. The
sources of a case value are the locations where the user case or netlist constants have been
added. For example, a port "PE" fans out to a port "OUT34" through only buffers and a case
value of 0 is set on port "PE". The case_sources attribute for port "OUT34 will be port "PE".
This attribute is only defined for a port if there is a case_value on that port.
case_value
Specifies the value of case on this port. The possible values are "0" or "1". This value may
come from user defined case or netlist defined constant value. The value may be because
a case value was directly set on this port or because the case value was propagated through
logic to this port. If there is no case assigned or propagated to this port this attribute is not
defined.
Chapter 1:
port_attributes
561
1-561
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
A float attribute representing the user-specified clock network latency for max fall. This
attribute is only defined on those ports where set_clock_latency has been directly set.
A float attribute representing the user-specified clock network latency for min fall. This
A float attribute representing the user-specified clock network latency for max rise. This
A float attribute representing the user-specified clock network latency for min rise. This
A float attribute representing the user-specified clock network latency for early max fall. This
attribute is only defined on those ports where set_clock_latency -source has been directly
set.
A float attribute representing the user-specified clock network latency for early min fall. This
set.
This attribute is only defined on those ports where set_clock_latency -source has been
directly set.
A float attribute representing the user-specified clock network latency for early min rise. This
set.
port_attributes
562
A float attribute representing the user-specified clock network latency for late max fall. This
set.
A float attribute representing the user-specified clock network latency for late min fall. This
set.
A float attribute representing the user-specified clock network latency for late max rise. This
set.
A float attribute representing the user-specified clock network latency for late min rise. This
set.
clocks
A collection of clock objects that this port is in the clock network of. The clocks in the
collection are just those clocks that this port fans out directly from the clock sources. It does
not include the master clocks of any generated clock networks that this port is in.
clocks_with_sense
A string attribute in the form of a list of clock names and clock senses that propagate to this
port. The possible clock senses are: "positive", "negative", "rise_triggered_high_pulse",
"fall_triggered_high_pulse", "rise_triggered_low_pulse", "fall_triggered_low_pulse".
constant_value
A string attribute for the constant value on this port. The possible values are "0" or "1".
Constant values are caused by a logic constant in the netlist or by a library cell such as a
pullup or pulldown having a constant logic function. A constant value is on the initial port and
on any ports that have their case propagated as a result of that constant value. For ports
with the attribute constant_value defined, the attribute case_value will also be defined and
have the same value.
Chapter 1:
port_attributes
563
1-563
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
direction
A string attribute for the direction of a port. Possible values are in, out, inout, or unknown.
drive_resistance_fall_max
drive_resistance_fall_min
drive_resistance_rise_max
drive_resistance_rise_min
Floating point attributes for retrieving the values set with the set_drive command.
full_name
A string attribute for the name of a port.
hold_uncertainty
A float attribute.
input_transition_fall_max
input_transition_fall_min
input_transition_rise_max
input_transition_rise_min
Floating point attributes set with the command set_input_transition.
port_attributes
564
is_clock_used_as_clock
network fanout of this pin reaches at least one register clock pin or output port.
is_clock_used_as_data
network fanout of this pin reaches at least one register data pin. If the attribute values for
is_clock_used_as_data is TRUE and is_clock_used_as_clock is FALSE, the clocks through
this pin only acts a data and never as clock.
is_diode
A Boolean attribute which is true if this pin is a diode based on its library cell.
is_pad
A Boolean attribute which is true if this pin is a pad IO based on its library cell.
is_shadow
A Boolean attribute to specify whether this pin is pushed down from above. This attribute is
settable.
is_secondary_pg
A Boolean attribute that is true if this is a secondary PG pin.
must_join_port
A collection attribute returning the must join port of this pin.
object_class
pg_type
Specifies the PG type of the port. It comes from the PG type of the net connected to this port.
Possible values are primary, backup and internal.
Chapter 1:
port_attributes
565
1-565
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
pin_capacitance_max_fall
pin_capacitance_max_rise
pin_capacitance_min_fall
pin_capacitance_min_rise
Floating point attributes set with the command set_load.
port_direction
A string attribute for the direction of a port. Possible values are in, out, inout, or unknown.
potential_clocks
A collection attribute. Contents of the collection are clocks that did not propagate to this port,
but potentially would have propagated if they were not blocked by other constraints. The
command analyze_clock_networks can be used to find the reason these clocks are blocked.
power_domain
A string attribute. The value is the power domain name of the given port.
setup_uncertainty
A float attribute.
shadow_status
A string attribute to represent the shadow status of this pin. Valid values are coipied_down,
copied_up, normal, pulled_up, and pushed_down.
port_attributes
566
user_case_value
A string attribute for the case value set by the command set_case_analysis. This attribute
is only defined on those ports where set_case_analysis has been directly set. Use the
attribute "case_value" for both directly set case values and propagated case values.
user_clock_sense
define on those ports where the set_clock_sense command was used directly.
parent_block
A collection attribute with the owner block object for this port.
parent_cell
A collection attribute with the owner cell object for this port.
parent_block_cell
A collection attribute with the parent block cell object for this port.
physical_status
A string attribute representing the physical placement status of the port. Valid values are
unplaced, placed, fixed, and locked. If status is unplaced, the port has not been placed. If
status is placed, the port has been placed and may be moved. If status is fixed, the port is
fixed for automatic changes. If status is locked, the port is fixed for automatic and manual
changes. This is a settable attribute.
top_block
A collection attribute with the top block object for this port.
wire_capacitance_max_fall
wire_capacitance_max_rise
Chapter 1:
port_attributes
567
1-567
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
wire_capacitance_min_fall
wire_capacitance_min_rise
Floating point attributes set with the command set_load.
SEE ALSO
find(2)
get_attribute(2)
list_attributes(2)
port_attributes
568
power.clock_network_include_clock_gating_network
TYPE
boolean
DEFAULT
false
DESCRIPTION
This variable affects the categorization of power in report_power.
When the variable is set to true, discrete logic structure that functions as clock gating
belongs to the clock_network power group.
Only the typical clock gating logic is considered a qualified clock gating network included in
the clock network. The typical clock gating logic starts from the output of a level-sensitive
latch driven by a specific clock. The clock gating logic possibly goes through some buffers,
and returns to the specified clock network through one of the input pins of a cell. That input
pin must be a clock check enabled pin, either inferred or manually set. Therefore, the results
can be affected by clock gating check related commands or variables. When the clock
gating network is included in the clock network, the latch is regarded as part of the
clock_network power group, but not the register power group.
Note that total power is not affected, just the distribution over categories.
SEE ALSO
get_app_options(2)
set_app_options(2)
report_power(2)
Chapter 1:
power.clock_network_include_clock_gating_network
569
1-569
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
power.clock_network_include_clock_sink_pin_power
TYPE
string
DEFAULT
register
DESCRIPTION
If this app option is set to a power group, report_power includes the internal power of all the
clock pins of the cells for the specified power group into the clock_network power group.
Only the internal power of the clock pins will be included in the clock_network power group,
rest of the cell power which includes internal power of pins other than clock pins, leakage
power, and the switching power will be included in the power group to which the cell belongs.
When this option is 'off', all of the cell internal power is reported in the power group to which
the cell belongs. When this option is 'all', internal power of all the clock pins for every cell will
be included in the clock_network power group.
Valid power groups that can be specified for this app option are: "off", "all", "io_pad",
"memory", "black_box", "register", "sequential", "combinational"
SEE ALSO
get_app_options(2)
set_app_options(2)
report_power(2)
power.clock_network_include_clock_sink_pin_power
570
power.default_static_probability
Specifies the default static probability value.
TYPE
float
DEFAULT
0.5
DESCRIPTION
The power.default_static_probability app option determines the static probability value of
nets that have not been annotated, simulated, propagated or derived from static timing
analysis.
The value of the power.default_static_probability app option should be between 0.0 and 1.0,
both inclusive. If the value of the power.default_static_probability app option is 0.0 or 1.0, the
value of the power.default_toggle_rate app option should be 0.0. If the value of the
power.default_toggle_rate app option is 0.0, the value of the
power.default_static_probability should be either 0.0 or 1.0.
SEE ALSO
get_switching_activity(2)
set_app_options(2)
set_switching_activity(2)
Chapter 1:
power.default_static_probability
571
1-571
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
power.default_toggle_rate
Specifies the default toggle rate value.
TYPE
float
DEFAULT
0.1
DESCRIPTION
The power.default_toggle_rate app option is used to determine the toggle rate value of nets
that have not been annotated, simulated, propagated or derived from static timing analysis.
The value of the power.default_toggle_rate app option should be greater than or equal to
0.0. If the value of the power.default_static_probability app option is 0.0 or 1.0, the value of
the power.default_toggle_rate app option should be 0.0. If the value of the
power.default_toggle_rate app option is 0.0, then the value of the
power.default_static_probability app option should be either 1.0 or 0.0.
SEE ALSO
set_app_options(2)
power.default_toggle_rate
572
power.default_toggle_rate_reference_clock
Specifies whether to use the fastest or the related clock for determining default toggle rates.
TYPE
string
DEFAULT
fastest
DESCRIPTION
The power.default_toggle_rate_reference_clock app option determines whether to use the
fastest or the related clock for determining the default toggle rates.
If the toggle rate is not annotated, simulated, propagated or derived from static timing
analysis, then it is determined by using the following formula:
tr = def_tr * fclk
where fclk is the frequency of the clock (fastest or related) and def_tr is the value of the
power.default_toggle_rate app option.
Two values, fastest and related, are allowed for the value of the
power.default_toggle_rate_reference_clock app option. If the value "fastest" is specified, the
fastest clock in the design is used. If the value "related" is specified, the clock that is used
depends on which clock the object for which switching activity is required is associated with.
SEE ALSO
set_app_options(2)
Chapter 1:
power.default_toggle_rate_reference_clock
573
1-573
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
power.internal_mode
Determines whether 'report_power' command reports internal power or not. By default,
'report_power' reports internal power numbers.
TYPE
string
DEFAULT
on
DESCRIPTION
The app option determines whether 'report_power' command reports internal power or not.
If the option is 'on', 'report_power' will report internal power. If the option is 'off',
'report_power' will not report internal power. By default, the option is 'on'.
SEE ALSO
get_app_options(2)
set_app_options(2)
report_power(2)
power.internal_mode
574
power.leakage_mode
Determines whether 'report_power' command reports leakage power or not. The option also
specifies strategy for leakage power calculation.
TYPE
string
DEFAULT
average
DESCRIPTION
The app option determines whether 'report_power' command reports leakage power or not.
If the app option value is not'off', it specifies the strategy for leakage power calculation. If the
option value is 'off', 'report_power' will not report leakage power. If the option value is
'average', 'report_power' reports leakage power and average leakage data will be used
during leakage power calculation. If the option value is 'state', 'report_power' reports
leakage power and state leakage data will be used during leakage power calculation. If the
option value is 'unconditional', 'report_power' reports leakage power and unconditional
leakage data will be used during leakage power calculation. By default, the option value is
'average'.
SEE ALSO
get_app_options(2)
set_app_options(2)
report_power(2)
Chapter 1:
power.leakage_mode
575
1-575
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
power.propagation_effort
Specifies the effort level to be used for the propagation of switching activity during power
calculation by 'report_power' command.
TYPE
string
DEFAULT
low
DESCRIPTION
Specifies the effort level to be used during the propagation of switching activity. On higher
effort levels, the tool uses more randomly generated switching activities to propagate the
switching activity. The default value is low.
Specifying low effort results in the fastest runtime and the lowest accuracy of power
estimates. Specifying medium or high effort results in a longer run that has increased levels
of accuracy. The analysis effort is considered only during the estimation of switching activity
information, and, therefore, has an effect only when the design is not fully annotated with
switching activity.
Specifying off means no propagation of switching activity will be performed. This gives only
meaningful results if the design is fully annotated with switching activity, or if you are only
interested in leakage power and the leakage strategy is unconditional or average in
power.leakage_mode.
SEE ALSO
get_app_options(2)
set_app_options(2)
report_power(2)
power.leakage_mode(3)
power.propagation_effort
576
power.swcap_mode
Determines whether 'report_power' command reports swcap power or not. By default,
'report_power' reports swcap power numbers.
TYPE
string
DEFAULT
on
DESCRIPTION
The app option determines whether 'report_power' command reports swcap power or not. If
the option is 'on', 'report_power' will report swcap power. If the option is 'off', 'report_power'
will not report swcap power. By default, the option is 'on'.
SEE ALSO
get_app_options(2)
set_app_options(2)
report_power(2)
Chapter 1:
power.swcap_mode
577
1-577
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
power_domain_attributes
Describes the attributes related to power domains.
DESCRIPTION
power_domain attributes are provided in the subsections that follow.
command.
Power Domain Attributes
elements
A collection attribute with the element objects for this power domain object.
full_name
Specifies full name of a power domain object.
name
Specifies name of a power domain object.
object_class
Specifies object class name of a power domain object, which is power_domain.
scope
A collection attribute with the scope object for this power domain object.
voltage_areas
A collection attribute with the voltage area objects for this power domain object.
578
SEE ALSO
get_attribute(2)
list_attributes(2)
Chapter 1:
579
1-579
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
power_strategy_attributes
Describes the attributes related to power strategy.
DESCRIPTION
power_strategy attributes are provided in the subsections that follow.
command.
Power Strategy Attributes

full_name
Specifies full name of a power strategy object.
name
Specifies name of a power strategy object.
power_domain
A collection attribute with the power domain object for this power strategy object.
type
Specifies object type of a power strategy object, which can be ISO, LS, RETENTION, and
SWITCH.
SEE ALSO
get_attribute(2)
list_attributes(2)
power_strategy_attributes
580
query_objects_format
TYPE
string
DEFAULT
application specific
DESCRIPTION
This variable sets the format that the query_objects command uses to print its result. There
are two supported formats: Legacy and Tcl.
The Legacy format looks like this:
{"or1", "or2", "or3"}
The Tcl format looks like this:

{or1 or2 or3}
Please see the man page for query_objects for complete details.
SEE ALSO
query_objects(2)
Chapter 1:
query_objects_format
581
1-581
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
refine_opt.congestion.effort
TYPE
string
DEFAULT
medium
DESCRIPTION
Specifies the effort level for the congestion alleviation in refine_opt. Allowed values are
refine_opt will not run in a congestion mode.
SEE ALSO
create_placement(2)
refine_opt(2)
clock_opt.congestion.effort(3)
place_opt.congestion.effort(3)
refine_opt.congestion.effort
582
refine_opt.flow.clock_aware_placement
Enables ICG timing criticality driven clock-aware placement in refine_opt.
TYPE
Boolean
DEFAULT
"false"
DESCRIPTION
This option controls whether refine_opt will utilize clock-aware placement, guided by ICG's
enable timing criticality. With this option, refine_opt will try to improve ICG enable timing
(measured after clock_opt) by placing the timing critical ICGs and their fanout cells at better
locations for ICG enable paths.
SEE ALSO
refine_opt(2)
place_opt(2)
set_app_options(2)
Chapter 1:
refine_opt.flow.clock_aware_placement
583
1-583
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
refine_opt.flow.do_path_opt
Run path_opt in refine_opt
TYPE
bool
DEFAULT
true
DESCRIPTION
This option enables running path_opt in refine_opt for better timing QOR. true is the default.
SEE ALSO
refine_opt(2)
set_app_options(2)
refine_opt.flow.do_path_opt
584
refine_opt.flow.exclusive
Control the exclusive optimization flows.
TYPE
String
DEFAULT
none
DESCRIPTION
Enable exclusive area recovery, electrical DRC, power or hold optimization in refine_opt.
The exclusive flow can be: area, drc, power, hold or none.
SEE ALSO
refine_opt(2)
set_app_options(2)
Chapter 1:
refine_opt.flow.exclusive
585
1-585
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
refine_opt.flow.optimize_layers
Enable layer optimization in refine_opt.
TYPE
String
DEFAULT
false
DESCRIPTION
It has two modes: {true, false}. refine_opt flows will run layer optimization that assigns long
timing critical nets to upper metal layers to improve timing.
SEE ALSO
set_app_options(2)
refine_opt.flow.optimize_layers
586
refine_opt.flow.optimize_layers_critical_range
Set critical range for layer optimization when refine_opt.flow.optimize_layers is set to
true.
TYPE
Float
DEFAULT
0.9
DESCRIPTION
SEE ALSO
set_app_options(2)
refine_opt.flow.optimize_layers(3)
Chapter 1:
refine_opt.flow.optimize_layers_critical_range
587
1-587
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
refine_opt.flow.optimize_ndr
Enable NDR optimization in refine_opt
TYPE
Boolean
DEFAULT
false
DESCRIPTION
refine_opt flows will run automatic non-default-routing rule optimization that assigns long
SEE ALSO
set_app_options(2)
refine_opt.flow.optimize_ndr
588
refine_opt.flow.optimize_rp_groups
Enable RP group optimization in refine_opt.
TYPE
String
DEFAULT
false
DESCRIPTION
It has two modes: {true, false}. refine_opt flows will improve relatively-placed groups using
path_opt to improve timing.
SEE ALSO
refine_opt(2)
set_app_options(2)
Chapter 1:
refine_opt.flow.optimize_rp_groups
589
1-589
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
refine_opt.hold.effort
Control the optimization effort for hold fixing in refine_opt.
TYPE
String
DEFAULT
none
DESCRIPTION
Enable higher effort hold fixing in refine_opt flows.
The hold fixing effort can be: none, low, medium, high, or exclusive. Setting to "none"
disables hold fixing. Setting to "exclusive" runs only hold fixing without any other
optimization.
The high effort option may result in slight degradation in setup TNS.
SEE ALSO
refine_opt(2)
set_app_options(2)
refine_opt.hold.effort
590
refine_opt.path_opt.fixed_cell_disturbance
Allow fixed cells to move in path_opt
TYPE
bool
DEFAULT
false
DESCRIPTION
This option allows fixed cells to move in path_opt for better timing QOR. false is the default.
SEE ALSO
refine_opt(2)
set_app_options(2)
Chapter 1:
refine_opt.path_opt.fixed_cell_disturbance
591
1-591
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
refine_opt.place.effort
TYPE
string
DEFAULT
medium
DESCRIPTION
Specifies the CPU effort level for coarse placements invoked in refine_opt. Allowed values
are medium or high.
SEE ALSO
create_placement(2)
refine_opt(2)
place_opt.final_place.effort(3)
refine_opt.place.effort
592
refine_opt.place.legalize
TYPE
Boolean
DEFAULT
true
DESCRIPTION
If set to true, the placement stage in refine_opt will include cell legalizations immediately
after the timing driven placement.
SEE ALSO
refine_opt(2)
place_opt.final_place.legalize(3)
Chapter 1:
refine_opt.place.legalize
593
1-593
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.allow_pg_as_shield
Controls whether the router treats power and ground nets as shields.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option controls whether the router treats power and ground nets as shields.
When true (the default), the router treats power and ground nets as shields and does not
reserve additional space around the nets to be shielded.
If set to false, the router tries to reserve space around the nets to be shielded if they are
close to a power or ground net.
Note that this option changes the routing behavior.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.allow_pg_as_shield
594
route.common.check_shield
Controls whether the shield data checker is enabled in all Zroute commands (except
check_routability).
TYPE
Boolean
DEFAULT
True
DESCRIPTION
When this option is true, all Zroute commands (except check_routability) do various data
checks related to shields at the start of command execution. When an illegal or suspicious
input shape is detected, an error or warning would be issued. This data checker checks the
attributes of routing and shield shapes for known problems in shielding flow. It does not
check the correctness of shielding shapes.
For check_routability command, shield data checker is enabled by check_routability
-check_shield true.
EXAMPLES
The following example enables the shield data checker in all Zroute commands (except
check_routability).
prompt> set_app_options \
-name route.common.check_shield \
-value true
SEE ALSO
check_routability(2)
get_app_options(2)
Chapter 1:
595
1-595
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
set_app_options(2)
596
route.common.clock_topology
Specifies the clock routing topology.
TYPE
string
DEFAULT
normal
DESCRIPTION
This application option specifies the clock routing topology.
Valid values are
normal (default)
Use normal routing for clock nets.
comb
Use comb routing for clock nets with a mesh or trunk.
EXAMPLE
The following example sets the route.common.clock_topology application option to
comb.
prompt> set_app_options -name route.common.clock_topology -value comb
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.clock_topology
597
1-597
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.color_based_dpt_flow
This application option implies if color based dpt flow is enabled.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When false (the default), color based dpt flow is disabled. When true, color based dpt flow
is enabled.
SEE ALSO
route.common.color_based_dpt_flow
598
route.common.comb_distance
Specifies the number of global routing cells within which to connect clock pins to the clock
mesh.
TYPE
integer
DEFAULT
2
DESCRIPTION
This application option specifies the number of global routing cells within which to connect
clock pins to the clock mesh. You must specify a value between 0 and 10, inclusive.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.comb_distance
599
1-599
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.concurrent_redundant_via_effort_level
Specifies the effort level for the concurrent redundant via insertion flow.
TYPE
string
DEFAULT
low
DESCRIPTION
This application option specifies the effort level for the concurrent redundant via insertion
flow.
Valid values are low (the default), medium, and high.
The default effort level is low. The higher effort levels result in a better redundant via
conversion rate at the expense of runtime.
This option takes effect only if the route.common.concurrent_redundant_via_mode
option is set to a value other than off.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.concurrent_redundant_via_effort_level
600
route.common.concurrent_redundant_via_mode
Specifies the concurrent redundant via insertion mode for initial routing.
TYPE
string
DEFAULT
off
DESCRIPTION
This application option specifies the concurrent redundant via insertion mode for initial
routing.
The valid modes are
off (the default)

Concurrent redundant via insertion is turned off.
reserve_space
Concurrent redundant via insertion reserves space for redundant vias but does not
instantiate them. The space reservation is done by generating internal soft rules for
redundant vias and performing soft-rule-based optimization. The actual instantiation is
done later by explicitly calling the add_redundant_vias command or by setting the
route.common.post_detail_route_redundant_via_insertion option to a value other
than off.
insert_at_high_cost
Concurrent redundant via insertion creates hard design rules for redundant vias and tries
to insert them. Use this mode if only you need a nearly 100 percent conversion rate. It
can lead to very long runtimes if the design is congested or the technology parameters
are not friendly to redundant via insertion. This mode should be used with caution.
SEE ALSO
get_app_options(2)
Chapter 1:
601
1-601
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
set_app_option(2)
602
route.common.connect_floating_shapes
Specifies whether the router should connect just the pins or the pins and all floating shapes.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option specifies whether the router should connect just the pins or the pins
and all floating shapes.
When false (the default), the router connects just the pins. The router might utilize the
floating shapes; however, it does not have to connect the floating shapes.
When true, the router connects the pins and all floating shapes.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.connect_floating_shapes
603
1-603
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.connect_within_pins_by_layer_name
Specifies, for each layer, whether to connect to pins by using vias or wires contained within
the pin shapes.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option specifies, for each layer, whether to connect to pins by using vias or
wires contained within the pin shapes. You can specify this option only when the top-level
block is open.
The syntax for specifying the setting for each layer is
{routing_layer mode}
You must specify the routing layers by using the layer names in the technology file.
The valid mode values are
off (the default)

Connect by using wires or vias anywhere on the pins.
via_standard_cell_pins
Connect to standard cell pins by using vias contained within the pin shapes.
via_wire_standard_cell_pins
Connect to standard cell pins by using vias and wires contained within the pin shapes.
via_all_pins
Connect to any pins by using vias contained within the pin shapes.
via_wire_all_pins
Connect to any pin by using vias and wires contained within the pin shapes.
604
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
605
1-605
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.eco_route_concurrent_redundant_via_effort_level
Specifies the effort level for the concurrent redundant via insertion flow in ECO routing.
TYPE
string
DEFAULT
low
DESCRIPTION
This application option specifies the effort level for the concurrent redundant via insertion
flow in ECO routing.
The valid values are low, medium, and high. The default effort level is low. The higher
effort levels result in a better redundant via conversion rate at the expense of runtime.
This option takes effect only if the route.common.eco_concurrent_redundant_via_mode
option is set to a value other than off.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.eco_route_concurrent_redundant_via_effort_level
606
route.common.eco_route_concurrent_redundant_via_mode
Specifies the concurrent redundant via insertion mode for ECO routing.
TYPE
string
DEFAULT
off
DESCRIPTION
This application option specifies the concurrent redundant via insertion mode for ECO
routing.
The definition for each mode is
off (the default)

Concurrent redundant via insertion is turned off.
reserve_space
Concurrent redundant via insertion reserves space for redundant vias in ECO routing but
does not instantiate them. The space reservation is done by generating internal soft rules
for redundant vias and performing soft-rule-based optimization. The actual instantiation
is done later by explicitly calling the add_redundant_vias command or by setting the
route.common.post_detail_route_redundant_via_insertion option to a value other
than off.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.eco_route_concurrent_redundant_via_mode
607
1-607
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.extra_nonpreferred_direction_wire_cost_multiplie
r_by_layer_name
Specifies the cost multiplier for routing in the nonpreferred direction.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option specifies the cost multiplier for routing in the nonpreferred direction.
You can specify this option only when the top-level block is open.
The format to specify the cost multiplier for a routing layer is
{layer multiplier}
The multiplier must be a float value between 0.0 and 20.0. The multiplier affects the routing
cost in the nonpreferred direction as follows:
cost = baseCost * (1 + multiplier)
If you specify a large multiplier value, it can prevent the router from routing in the
nonpreferred direction. If your design requires nonpreferred direction routing, use smaller
multiplier values.
If you do not specify the multiplier for a layer, the tool uses the default of 0.0.
EXAMPLE
The following example shows how to set the non-preferred direction wire cost multipler by
layer name.
route.common.extra_nonpreferred_direction_wire_cost_multiplier_by_layer_name
608
-block [current_block] -list
{route.common.extra_nonpreferred_direction_wire_cost_multiplier_by_layer_
name { {M4 3} {M5 2} }}
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.extra_nonpreferred_direction_wire_cost_multiplier_by_layer_name
609
1-609
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.extra_preferred_direction_wire_cost_multiplier_b
y_layer_name
Specifies the cost multiplier for routing in the preferred direction.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option specifies the cost multiplier for routing in the preferred direction. You
can specify this option only when the top-level block is open.
The format to specify the cost multiplier for a routing layer is
{layer multiplier}
The multiplier must be a float value between 0.0 and 20.0. The multiplier affects the routing
cost in the preferred direction as follows:
cost = baseCost * (1 + multiplier)
EXAMPLE
The following example shows how to set the preferred direction wire cost multipler by layer
name.
{route.common.extra_preferred_direction_wire_cost_multiplier_by_layer_nam
e { {M4 3} {M5 2} }}
route.common.extra_preferred_direction_wire_cost_multiplier_by_layer_name
610
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.extra_preferred_direction_wire_cost_multiplier_by_layer_name
611
1-611
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.extra_via_cost_multiplier_by_layer_name
Specifies the cost multiplier for vias.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option specifies the cost multiplier for vias. You can specify this option only
when the top-level block is open.
The format to specify the cost multiplier for a via layer is
{layer multiplier}
You must specify the via layers by using the layer names in the technology file.
The multiplier must be a float value between 0.0 and 20.0. It affects the via cost on the
specified layer as follows:
viaCost = baseViaCost * (1 + multiplier)
EXAMPLE
The following example sets the extra via cost multiplier to 0.5 on the VIA12 layer and to 1.5
on the VIA23 layer.
-name route.common.extra_via_cost_multiplier_by_layer_name \
-value {{VIA12 0.5} {VIA23 1.5}}
612
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
613
1-613
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.extra_via_off_grid_cost_multiplier_by_layer_nam
e
Specifies the cost multiplier for vias that are off grid with respect to the specified metal
layers.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option specifies the cost multiplier for vias. You can specify this option only
when the top-level block is open.
The format to specify the cost multiplier for a via layer is
{layer multiplier}
You must specify the via layers by using the layer names in the technology file.
The multiplier must be a float value between 0.0 and 20.0. It affects the via cost on the
specified layer as follows:
viaCost = baseViaCost * (1 + multiplier)
EXAMPLE
If the technology file defines the VIA12 via layer between the M1 and M2 metal layers and
the VIA23 via layer between the M2 and M3 metal layers, the following example sets the
extra off-grid via cost multiplier on the VIA12 and VIA23 layers to 0.5. Note that you specify
the metal layer, but the multiplier is set on the adjacent via layers.
route.common.extra_via_off_grid_cost_multiplier_by_layer_name
614
-name route.common.extra_via_off_grid_cost_multiplier_by_layer_name \
-value {{M2 0.5}}
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.extra_via_off_grid_cost_multiplier_by_layer_name
615
1-615
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.forbid_new_metal_by_layer_name
Controls whether ECO routing with the route_eco command can remove, but not add, metal
on the specified layers. You must specify the routing layers by using the layer names in the
technology file.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option controls whether ECO routing with the route_eco command can
remove, but not add, metal on the specified routing layers. You can set this option only when
the block is open.
Note that for all other routing commands, this option acts the same as the
route.common.freeze_layer_by_layer_name option and controls whether routing cannot
add or remove metal on the specified layers.
The format for specifying the setting for a layer is
{routing_layer true|false}
When false (the default), the router can add or remove metal from the layer.
When true, the ECO router can remove, but not add, metal from the layer. The ECO router
can remove metal if it is dangling or is not fully contained within fixed user shapes, such as
pins. All other routing phases cannot add or remove metal from the layer. If the router adds
metal on the layer, and that metal is not fully contained within a fixed user shape, the router
reports a "Forbidden metal" DRC violation.
You would use this option if you want to freeze a layer when running core commands, such
as route_opt, but give the router the flexibility to remove some shapes during ECO routing.
If a layer is frozen with the route.common.freeze_layer_by_layer_name option, the router
cannot touch any shapes, which can result in dangling wires and unfixable shorts if the
616
placement changes during ECO. The route.common.forbid_new_metal_by_layer_name

option gives the router the flexibility to remove such shapes while otherwise treating the
layer as frozen.
If you specify both the route.common.freeze_layer_by_layer_name and
route.common.forbid_new_metal_by_layer_name options, the stricter
route.common.freeze_layer_by_layer_name option takes precedence.
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
617
1-617
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.freeze_layer_by_layer_name
Controls whether routing layers are frozen to prevent them from changing during routing.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option controls whether routing layers are frozen to prevent them from
changing during routing. You can specify this option only when the block is open.
Use the following format to specify the setting for each layer:
When false (the default), the layer is not frozen.
When true, the layer is frozen.
EXAMPLE
The following example sets the route.common.freeze_layer_by_layer_name application
option to true for the m3 and m4 metal layers.
-name route.common.freeze_layer_by_layer_name \
-value {{m3 true} {m4 true}}
SEE ALSO
618
get_app_options(2)
set_app_option(2)
Chapter 1:
619
1-619
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.freeze_via_to_frozen_layer_by_layer_name
Controls the treatment of vias that touch the specified frozen layers on one side.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option controls the treatment of vias that touch the specified frozen layers
on one side.
You must specify the routing layers by using the layer names in the technology file. The
specified layers must be frozen layers.
By default, all the frozen layers are set as false, which indicates that the vias whose
surroundings on a frozen layer are enclosed by other metal shapes can be removed or
rerouted as long as they do not make a change on the frozen metal layer. Special vias such
as H-shape vias are not removed or rerouted even though they do not change the frozen
metal layer.
When you set this option to true on one or more frozen layers, the vias adjacent to these
frozen layers are frozen and cannot be changed. Note that no change is allowed on a cut
layer adjacent to two frozen metal layers.
EXAMPLE
The following example shows how to set the option freeze via on frozen layer by layer name.
{route.common.freeze_via_to_frozen_layer_by_layer_name { {MET4 true}
620
{MET5 true} }}
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
621
1-621
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.global_max_layer_mode
Controls the application of the maximum routing layer constraint set for the design.
TYPE
string
DEFAULT
soft
DESCRIPTION
This application option controls the application of the maximum routing layer constraint set
for the design. This global constraint is set by using the set_ignored_layers command.
soft (the default)

Routing above the maximum layer is discouraged, but not disallowed. DRC violations
are not flagged on any metal above the maximum layer.
allow_pin_connection
Routing is allowed above the maximum layer only for pin connections. DRC violations
are flagged on metal above the maximum layer if the metal is not along a path that
connects to a pin. DRC violations are flagged on metal above the maximum layer if the
metal is along a path that connects to a pin and the path is long. A path is considered
long by the detail router if its length exceeds approximately 10 average track pitches. A
path is considered long by the check_routes command if its length exceeds
approximately 15 average track pitches.
hard
No routing can occur above the maximum layer. DRC violations are flagged on metal
above the maximum layer.
Note that the route.common.number_of_vias_over_global_max_layer option can relax

the maximum layer constraint, but only for vias.
SEE ALSO
622
get_app_options(2)
set_app_option(2)
Chapter 1:
623
1-623
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.global_min_layer_mode
Controls the application of the minimum routing layer constraint for the design.
TYPE
string
DEFAULT
soft
DESCRIPTION
This application option controls the application of the minimum routing layer constraint for
the design. This global constraint is set by using the set_ignored_layers command.
soft (the default)

Routing below the minimum layer is discouraged, but not disallowed. DRC violations are
not flagged on any metal below the minimum layer.
Routing is allowed below the minimum layer only for pin connections. DRC violations are
flagged on metal below the minimum layer if the metal is not along a path that connects
to a pin. DRC violations are flagged on metal below the minimum layer if the metal is
along a path that connects to a pin and the path is long. A path is considered long by the
detail router if its length exceeds approximately 10 average track pitches. A path is
considered long by the check_routes command if its length exceeds approximately 15
average track pitches.
hard
No routing can occur below the minimum layer. DRC violations are flagged on metal
below the minimum layer.
Note that the route.common.number_of_vias_under_global_min_layer option can relax

the minimum layer constraint, but only for vias.
SEE ALSO
624
get_app_options(2)
set_app_option(2)
Chapter 1:
625
1-625
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.high_resistance_flow
Specifies whether to enable the high-resistance feature durint timing driven route.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When set to true, enables the high-resistance feature for timing driven routing. The
high-resistance feature is especially targeted for emerging nodes that are 20 nm and below
where the net resistance is large comparing to the cell resistance. This feature tries to
reduce the resistance by maintaining a balance between metal wire resistance and via
resistance through changes in routing.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.high_resistance_flow
626
route.common.ignore_var_spacing_to_blockage
Controls whether the spacing defined in a nondefault routing rule is ignored against
blockages.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.ignore_var_spacing_to_blockage
627
1-627
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.ignore_var_spacing_to_pg
Controls whether the spacing defined in a nondefault routing rule is ignored against all wires
on power and ground nets.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.ignore_var_spacing_to_pg
628
route.common.ignore_var_spacing_to_shield
Controls whether the spacing defined in a nondefault routing rule is ignored against shield
wires on power and ground nets.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
route.common.ignore_var_spacing_to_shield
629
1-629
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.mark_clock_nets_minor_change
Controls whether changes on clock tree nets are limited during routing.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option controls whether changes on clock tree nets are limited during
routing.
When true (the default), the router can make only limited changes to nets marked as clock
tree nets in the database.
When false, nets marked as clock tree nets in the database are routed normally (the router
can make any changes to these nets).
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.mark_clock_nets_minor_change
630
route.common.min_edge_offset_for_macro_pin_connection_by_l
ayer_name
Specifies the minimum edge offset for macro pin connections for one or more metal layers.
TYPE
list
DEFAULT
""
DESCRIPTION
Specifies the minimum edge offset for macro pin connections for one or more metal layers.
The minimum edge for macro pin connection rule enforces exactly aligned connections
between metal wires and macro pins where they connect. If the macro pin and wire have
different widths, the short edges resulting at the connection point must have at least the
specified length.
The settings specified in this option override the minEdgeOffsetForMacroPinConnection
values specified in the Layer section of the technology file for the specified layers. The
technology file values are used for any layers not specified in this option.
{routing_layer offset}
EXAMPLE
The following example sets the
min_edge_offset_for_macro_pin_connection_by_layer_name application option to 0.5
for the M3 and M4 metal layers.
-name min_edge_offset_for_macro_pin_connection_by_layer_name \
-value {{M3 0.5} {M4 0.5}}
Chapter 1:
route.common.min_edge_offset_for_macro_pin_connection_by_layer_name
631
1-631
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_app_options(2)
set_app_options(2)
route.common.min_edge_offset_for_macro_pin_connection_by_layer_name
632
route.common.min_shield_length_by_layer_name
Specifies the minimum shielded length in microns on each layer. The router skips shielding
net wires with lengths less than these values.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option specifies the minimum shielded length for each layer.
The format for specifying the minimum shielded length for a layer is
{layer length}
Wires with a length that is less than the minimum shielded length are always unshielded.
After creating a shield for a net, when reporting shielding ratio in create_net_shielding
command, wires that are less than the specified minimum shielded length are not counted.
Specify the layer by using the layer name from the technology file.
EXAMPLES
The following example sets the route.common.min_shield_length_by_layer_name
option on M1, M2, and M5.
{route.common.min_shield_length_by_layer_name \
{ {M1 0.1} {M2 0.18} {M5 0.256} }}
The default length for each layer is 4-layer-pitch. Using -1 could set it back to the default
value while a layer value.
Chapter 1:
633
1-633
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
create_net_shielding(2)
get_app_options(2)
route_auto(2)
route_detail(2)
route_opt(2)
set_app_options(2)
634
route.common.net_max_layer_mode
Specifies the default mode for the net-based maximum routing layer constraints set by the
set_routing_rule command.
TYPE
string
DEFAULT
hard
DESCRIPTION
This application option specifies the default mode for the net-based maximum routing layer
constraints set by the set_routing_rule command. This setting applies only to nets whose
maximum routing layer mode is not set by the set_routing_rule command.
hard (the default)

No routing can occur above the maximum layer. DRC violations are flagged on metal
above the maximum layer.
soft
Routing above the maximum layer is discouraged, but not disallowed. DRC violations
are not flagged on any metal above the maximum layer.
Routing is allowed above the maximum layer only for pin connections. DRC violations
are flagged on metal above the maximum layer if the metal is not along a path that
connects to a pin. DRC violations are flagged on metal above the maximum layer if the
metal is along a path that connects to a pin and the path is long. A path is considered
long by the detail router if its length exceeds approximately 10 average track pitches. A
path is considered long by the check_routes command if its length exceeds
approximately 15 average track pitches.
Note that the route.common.number_of_vias_over_net_max_layer option can relax the

maximum layer constraint, but only for vias.
Chapter 1:
635
1-635
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_app_options(2)
set_app_option(2)
636
route.common.net_max_layer_mode_soft_cost
Specifies the default cost for routing above the net-based maximum routing layer when
using the soft maximum layer mode.
TYPE
string
DEFAULT
medium
DESCRIPTION
This application option specifies the default cost for routing above the net-based maximum
routing layer when using the soft maximum layer mode. Valid values are low, medium, and
high.
This setting applies only to nets whose soft mode maximum routing layer cost is not set by
the set_routing_rule command.
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
route.common.net_max_layer_mode_soft_cost
637
1-637
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.net_min_layer_mode
Specifies the default mode for the net-based minimum routing layer constraints set by the
set_routing_rule command.
TYPE
string
DEFAULT
soft
DESCRIPTION
This application option specifies the default mode for the net-based minimum routing layer
constraints set by the set_routing_rule command. This setting applies only to nets whose
minimum routing layer mode is not set by the set_routing_rule command.
soft (the default)

Routing below the minimum layer is discouraged, but not disallowed. DRC violations are
not flagged on any metal below the minimum layer.
Routing is allowed below the minimum layer only for pin connections. DRC violations are
flagged on metal below the minimum layer if the metal is not along a path that connects
to a pin. DRC violations are flagged on metal below the minimum layer if the metal is
along a path that connects to a pin and the path is long. A path is considered long by the
detail router if its length exceeds approximately 10 average track pitches. A path is
considered long by the check_routes command if its length exceeds approximately 15
average track pitches.
hard
No routing can occur below the minimum layer. DRC violations are flagged on metal
below the minimum layer.
Note that the route.common.number_of_vias_under_net_min_layer option can relax the

minimum layer constraint, but only for vias.
638
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
639
1-639
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.net_min_layer_mode_soft_cost
Specifies the default cost for routing below the net-based minimum routing layer when using
the soft minimum layer mode.
TYPE
string
DEFAULT
medium
DESCRIPTION
This application option specifies the default cost for routing below the net-based minimum
routing layer when using the soft minimum layer mode. Valid values are low, medium, and
high.
This setting applies only to nets whose soft mode minimum routing layer cost is not set by
the set_routing_rule command.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.net_min_layer_mode_soft_cost
640
route.common.number_of_secondary_pg_pin_connections
Specifies the maximum number of secondary power and ground (PG) pins in a cluster.
TYPE
integer
DEFAULT
0
DESCRIPTION
This application option specifies the maximum number of secondary PG pins in a cluster.
The definition of a cluster is a set of connected secondary PG pins. Each cluster has one
connection with a PG strap or ring. If the value is greater than 0, a cluster should not contain
more than the specified number of secondary PG pins.
By default, the setting is 0, which means that there is no maximum.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.number_of_secondary_pg_pin_connections
641
1-641
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.number_of_vias_over_global_max_layer
Allows the router to use stacked vias to access pins or fixed routes above the global
maximum layer.
TYPE
integer
DEFAULT
1
DESCRIPTION
This application option allows the router to use stacked vias to access pins or fixed routes
above the global maximum layer. If the global maximum layer mode is set to soft, this option
is ignored, because in that case access above the maximum layer is allowed.
The value range is between 0 and 15. This value specifies the number of via layers that can
be traversed to access a pin without triggering a DRC violation. For example, if the
maximum layer is M6 and you specify a value of 2, the tool does not flag violations on vias
from M6 to M7 or M7 to M8 if these vias are needed to access pins on layers above the
maximum layer.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.number_of_vias_over_global_max_layer
642
route.common.number_of_vias_over_net_max_layer
Allows the router to use stacked vias to access pins or fixed routes above the net-specific
maximum layer.
TYPE
integer
DEFAULT
1
DESCRIPTION
above the net-specific maximum layer. If the net-specific maximum layer mode is set to soft,
this option is ignored, because in that case access above the maximum layer is allowed.
be traversed to access a pin without triggering a DRC violation. For example, if the
maximum layer is M6 and you specify a value of 2, the tool does not flag violations on vias
from M6 to M7 or M7 to M8 if these vias are needed to access pins on layers above the
maximum layer.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.number_of_vias_over_net_max_layer
643
1-643
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.number_of_vias_under_global_min_layer
Allows the router to use stacked vias to access pins or fixed routes below the global
minimum layer.
TYPE
integer
DEFAULT
1
DESCRIPTION
below the global minimum layer. If the global minimum layer mode is set to soft, this option
is ignored, because in that case access below the minimum layer is allowed.
be traversed to access a pin without triggering a DRC violation. For example, if the minimum
layer is M2 and you specify a value of 1, violations are not flagged on vias from M1-to-M2 if
these vias are needed to access pins on M1.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.number_of_vias_under_global_min_layer
644
route.common.number_of_vias_under_net_min_layer
Allows the router to use stacked vias to access pins or fixed routes below the net-specific
minimum layer.
TYPE
integer
DEFAULT
1
DESCRIPTION
below the net-specific minimum layer. If the net-specific minimum layer mode is set to soft,
this option is ignored, because in that case access below the minimum layer is allowed.
be traversed to access a pin without triggering a DRC violation. For example, if the minimum
layer is M2 and you specify a value of 1, violations are not flagged on vias from M1-to-M2 if
these vias are needed to access pins on M1.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.number_of_vias_under_net_min_layer
645
1-645
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.pg_shield_distance_threshold
Specifies the distance threshold in microns for the router to consider the existing power and
ground structure as shielding when calculating the shielding ratio.
TYPE
float
DEFAULT
0
DESCRIPTION
This application option specifies the distance threshold in microns for the router to consider
the existing power and ground structure as shielding when calculating the shielding ratio.
Note that this option does not change the routing behavior. It affects only the shielding ratio
report generated by the create_shields and report_shields commands.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.pg_shield_distance_threshold
646
route.common.post_detail_route_fix_soft_violations
Enables automatic optimization of soft rules that are fixable postroute, after the detail routing
step.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option enables automatic optimization of soft rules that are fixable
postroute, after the detail routing step.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.post_detail_route_fix_soft_violations
647
1-647
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.post_detail_route_redundant_via_insertion
Enables automatic redundant via insertion after each detail routing step.
TYPE
string
DEFAULT
off
DESCRIPTION
This application option enables automatic redundant via insertion after each detail routing
step.
Valid values are off (the default), low, medium, and high.
If the value is set to low, medium, or high, the tool performs redundant via insertion after
each detail routing change, including initial detail routing, ECO routing, and incremental
routing. Enabling this option keeps the redundant vias in the design up-to-date with routing
changes. The low, medium, or high setting specifies the effort level used for redundant via
insertion.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.post_detail_route_redundant_via_insertion
648
route.common.post_eco_route_fix_soft_violations
Enables automatic optimization of soft rules that are fixable postroute, after the ECO routing
step.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
postroute, after the ECO routing step.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.post_eco_route_fix_soft_violations
649
1-649
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.post_group_route_fix_soft_violations
Enables automatic optimization of soft rules that are fixable postroute, after the group
routing step.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
postroute, after the group routing step.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.post_group_route_fix_soft_violations
650
route.common.post_incremental_detail_route_fix_soft_violations
Enables automatic optimization of soft rules that are fixable postroute, after the incremental
routing step.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
postroute, after the incremental routing step.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.post_incremental_detail_route_fix_soft_violations
651
1-651
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.rc_driven_setup_effort_level
Enables the router to automatically bias layer preference based on RC values for better
setup timing.
TYPE
string
DEFAULT
medium
DESCRIPTION
This application option enables the router to automatically bias layer preference based on
RC values for better setup timing.
Valid values are low, medium (the default), and high.
This option takes effect only if timing-driven routing is enabled.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.rc_driven_setup_effort_level
652
route.common.report_local_double_pattern_odd_cycles
Controls whether local double pattern odd cycles are reported.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option controls whether local double pattern odd cycles are reported.
For double-patterning technology designs, a mask is split into two masks for lithography
success. To check whether a mask can be split into two masks, the tool creates
double-pattern links between any two polygons whose distance is smaller than the
double-pattern spacing defined in technology file. A cycle is formed when a set of polygons
is connected in a ring topology by double-pattern links.
A double-pattern odd cycle is a cycle that consists of an odd number of double-pattern links.
Double-pattern odd cycles must be avoided or fixed because they prevent the mask from
splitting into two masks. A local double-pattern odd cycle is a double-pattern odd cycle that
is contained in a bounding box that is 20 global routing cells high by 20 global routing cells
wide.
By default (false), the router does not report local double-pattern odd cycles.
When this option is true, the router reports local double-pattern odd cycles that are caused
by signal detail routes. The router does not report local double-pattern cycles that contain
only shapes that cannot be changed by the router. For example, the router does not report
a local double-pattern odd cycle that contains only PG preroutes, pins, and standard-cell
obstacles.
To check for local double-pattern odd cycles, use the check_routes command. This
command guarantees the reporting of local double-pattern odd cycles when this option is
true. Note that the route_detail command and other routing commands do not guarantee
the reporting of double-pattern odd cycles.
Chapter 1:
653
1-653
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_app_options(2)
set_app_option(2)
654
route.common.reroute_clock_shapes
Specifies whether the router can reroute fixed clock wires and vias.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option specifies whether the router can reroute fixed clock wires and vias.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.reroute_clock_shapes
655
1-655
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.reroute_user_shapes
Specifies whether the router can reroute user-created wires and vias.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option specifies whether the router can reroute user-created wires and vias.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.reroute_user_shapes
656
route.common.reshield_modified_nets
Specifies whether to automatically unshield or reshield modified shielded nets during
routing.
TYPE
string
DEFAULT
off
DESCRIPTION
This application option specifies whether to automatically unshield or reshield modified
shielded nets during routing.
off (the default)

The router does not unshield or reshield modified shielded nets.
reshield
The router unshields modified shielded nets, automatically reshields them, and then
reconnects the floating shielding. If the router cannot reconnect the floating shielding, it
removes it. Shielded nets might have been modified by routing or outside of routing by
manual editing, route optimization, and other commands.
unshield
The router deletes existing shielding that is associated with modified shielded nets and
reconnects the floating shielding if necessary. The nets might be reshielded at a later
stage.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.reshield_modified_nets
657
1-657
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.rotate_default_vias
Specifies whether the router can rotate default vias.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option specifies whether the router can rotate default vias.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.rotate_default_vias
658
route.common.route_soft_rule_effort_level
Specifies the effort level for rip up and reroute to fix soft rule design rule violations.
TYPE
string
DEFAULT
medium
DESCRIPTION
This application option specifies the effort level for rip up and reroute to fix soft rule design
rule violations.
The definition for each effort level is
off
The router does not perform rip up and reroute passes to resolve soft rule design rule
violations.
min
The router uses the smallest number of rip up and reroute passes to resolve soft rule
design rule violations.
low
The router uses a small number of rip up and reroute passes to resolve soft rule design
rule violations.
medium (the default)

Uses a medium number of rip up and reroute passes to resolve soft rule design rule
violations.
high
Treats soft rule design rule violations the same as regular design rule violations during
rip up and reroute.
SEE ALSO
Chapter 1:
659
1-659
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
get_app_options(2)
set_app_option(2)
660
route.common.route_top_boundary_mode
Controls the routing behavior near the top boundary.
TYPE
string
DEFAULT
stay_inside
DESCRIPTION
Controls the routing behavior near the top boundary.
stay_half_min_space_inside
The routing must be inside the boundary by half of the minimum spacing.
stay_inside (the default)

The routing must be inside or abut the boundary.
ignore
Wires can extend outside the boundary.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.route_top_boundary_mode
661
1-661
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.routing_rule_effort_level
Specifies detailed, layer-by-layer effort levels on the various spacings of soft nondefault
routing rules.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option specifies detailed, layer-by-layer effort levels on the various spacings
of soft nondefault routing rules. For each nondefault routing rule, you can specify the effort
for each spacing value defined for a layer. The rule name corresponds to a previously
defined nondefault routing rule. For each layer defined in the -spacings option of the
create_routing_rule command, you specify the effort level for each of the spacings defined
for that layer.
low
Uses a small number of rip up and reroute passes to resolve soft rule design rule
violations.
med
Uses a medium number of rip up and reroute passes to resolve soft rule design rule
violations.
high
Treats soft rule design rule violations the same as regular design rule violations during
rip up and reroute.
For example, suppose you have defined the following two soft routing rules:
create_routing_rule soft_rule_1 \
-spacings {M1 {0.12 0.24 }
M2 {0.14 0.28 }
M3 {0.14 0.28 }
M4 {0.14 0.28 }
M5 {0.14 0.28 }} \
-spacing_weight_levels {M1 {hard high}
662
M2
M3
M4
M5
{hard
{hard
{hard
{hard
high}
high}
high}
high}}
create_routing_rule soft_rule_2 \
-spacings {M1 {0.24 0.36}
M2 {0.28 0.42}
M3 {0.28 0.42}
M4 {0.28 0.42}
M5 {0.28 0.42}}
-spacing_weight_levels {M1
M2 {high
M3 {high
M4 {high
M5 {high
\
{high medium}
medium}
medium}
medium}
medium}}
You would specify the detailed effort levels for these rules as shown in the following
example:
set_app_options \
-name route.common.routing_rule_effort_level \
-value { {soft_rule_1 { {M1 {high med}}
{M2 {high med}}
{M3 {high med}}
{M4 {high med}}
{M5 {high med}}
}
}
{soft_rule_2 { {M1 {high med}}
{M2 {low high}}
{M3 {med high}}
{M4 {med high}}
{M5 {high high}}
}
}
}
EXAMPLE
The following example shows how to set the routing rue effort level for a rule soft_rule_2 on
MET4 layer.
-block [current_block] -list {route.common.routing_rule_effort_level
{ { soft_rule_2 { MET4 HIGH MED} } } }
Chapter 1:
663
1-663
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_app_options(2)
set_app_option(2)
664
route.common.separate_tie_off_from_secondary_pg
Specifies whether to separate the tie-off connections from the secondary PG power
connections.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
By default (false), tie-off connections and secondary PG power connections are considered
the same nets, so nondefault routing rules, minimum and maximum layer constraints, and
other constraints on the net apply to both tie-off connections and secondary PG power
connections.
When you separate the tie-off connections from the secondary PG power connections by
setting this option to true, you can apply nondefault routing rules, minimum and maximum
layer constraints, and other constraints only to the secondary PG power connections.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.separate_tie_off_from_secondary_pg
665
1-665
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.shielding_nets
Specifies the power and ground nets to be used for shielding by the create_shields
command.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option specifies the power and ground nets to be used for shielding by the
create_shields command.
When routing signal nets, if the route.common.allow_pg_as_shield application option is
true (the default), the router tries to route the shielded nets adjacent to any of the specified
power and ground nets while considering other routing metrics such as congestion and wire
length.
If the route.common.allow_pg_as_shield application option is false, this option has no
effect.
If you do not specify this option, by default, the create_shields command uses the ground
net for shielding.
You can also specify the power or ground net used for shielding by using the -with_ground
option with the create_shields command; however, this option supports only a single power
or ground net.
If you specify both the route.common.shielding_nets application option and the
create_shields -with_ground option, the tool issues a warning message and uses the
route.common.shielding_nets setting.
SEE ALSO
get_app_options(2)
666
set_app_option(2)
Chapter 1:
667
1-667
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.single_connection_to_pins
Specifies whether the router can connect to a pin only once.
TYPE
string
DEFAULT
off
DESCRIPTION
This application option specifies whether the router can connect to a pin only once.
Valid values are off, standard_cell_pins, macro_cell_pins, top_cell_pins,
standard_and_macro_cell_pins, standard_and_top_cell_pins,
macro_and_top_cell_pins, standard_and_macro_and_pad_cell_pins, and all_pins.
If the value is off (the default), the router is allowed to connect to a pin any number of times.
If the value is all_pins, all the pins in the design have the single-connection constraint and
the router can connect to any pin only once. The other values specify the subset of pins that
have the single-connection constraint.
The default is off, except for nets that use a nondefault width routing rule. For those nets,
the value is always all_pins.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.single_connection_to_pins
668
route.common.soft_rule_weight_to_effort_level_map
Specifies a global mapping from soft weight level to soft effort level.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option specifies a global mapping from soft weight level to soft effort level.
The weight level must be one of the following values: low, medium, or high.
The effort level must be one of the following values: off, low, medium, or high.
off (the default)

The router does not perform rip up and reroute passes to resolve soft rule design rule
violations.
low
The routers uses a small number of rip up and reroute passes to resolve soft rule design
rule violations.
medium
The router uses a medium number of rip up and reroute passes to resolve soft rule
design rule violations.
high
The router treats soft rule design rule violations the same as regular design rule
violations during rip up and reroute.
This mapping is applied whenever soft rules are defined using the -spacing_weight_levels
option of the create_routing_rule command.
Each weight level should appear only once in the map.
The following mappings are not allowed:
Chapter 1:
669
1-669
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
Low weight with medium effort
Low weight with high effort
K-2015.06-SP4
For example, suppose you have defined the following mapping:

set_app_options \
-name soft_rule_weight_to_effort_level_map \
-value { {low low}
{medium medium}
{high medium} }
This means that
Soft rules with low weight should use low effort.
Soft rules with medium weight should use medium effort.
Soft rules with high weight should use medium effort.
SEE ALSO
get_app_options(2)
set_app_options(2)
670
route.common.standard_cell_blockage_as_thin
Specifies whether to treat wide blockages in standard cells as thin wires.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option specifies whether to treat wide blockages in standard cells as thin
wires.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.standard_cell_blockage_as_thin
671
1-671
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.threshold_noise_ratio
Specifies the static noise threshold as a ratio of the voltage.
TYPE
float
DEFAULT
0.35
DESCRIPTION
This application option specifies the static noise threshold as a ratio of the voltage. This is
used by the router to determine the crosstalk criticality of a net.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.threshold_noise_ratio
672
route.common.tie_off_mode
Controls whether the router can connect tie-off nets to any power or ground (PG) structures,
such as straps, rails, or pins, or only to a PG rail.
TYPE
string
DEFAULT
all
DESCRIPTION
This application option controls whether the router can connect tie-off nets to any power or
ground (PG) structures, such as straps, rails, or pins, or only to a PG rail.
all (the default)

Tie-off nets can be connected to any PG structures.
rail_only
Tie-off nets can be connected only to a PG rail.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.tie_off_mode
673
1-673
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.track_auto_fill
Specifies whether to fill empty space with routing tracks.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option specifies whether to fill empty space with routing tracks.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.track_auto_fill
674
route.common.verbose_level
Sets the verbosity level for the routing log file.
TYPE
integer
DEFAULT
0
DESCRIPTION
This application option sets the verbosity level for the routing log file. Valid values are 0, 1,
or 2.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.verbose_level
675
1-675
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.via_array_mode
Specifies the types of rotated via arrays that can be used during signal routing and
redundant via insertion when using the default routing rules.
TYPE
string
DEFAULT
all
DESCRIPTION
This application option specifies the types of rotated via arrays that can be used during
signal routing and redundant via insertion when using the default routing rules.
off
Do not rotate or swap via arrays.
swap
Use 1 x N and N x 1 via arrays as rotated equivalent vias.
rotate
Rotate line via arrays instead of swapping row and column numbers.
all (the default)

Use all four possible via arrays.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.common.via_array_mode
676
route.common.via_on_grid_by_layer_name
Controls whether vias and their associated via enclosures must be routed on-grid. This
option controls the same functionality as the onGrid attribute for a via layer in the
technology file.
TYPE
list
DEFAULT
""
DESCRIPTION
If you use this option, the tool ignores all onGrid attributes defined in the technology file
(both for metal layers and via layers). The default setting for any unspecified onGrid
attribute is false; therefore, on-grid routing is required only for the via layers specified with a
setting of true in this option and metal layers specified with a setting of true in the
route.common.wire_on_grid_by_layer_name option. You can set this option only when
the block is open. This option controls only onGrid attributes; it has no impact if the
technology file defines onWireTrack attributes.
Use the following sytnax to specify the setting for each layer:
EXAMPLES
The following example sets the route.common.via_on_grid_by_layer_name application
option to true for the V3 and V4 cut layers.
-name route.common.via_on_grid_by_layer_name \
-value {{V3 true} {V4 true}}
Chapter 1:
677
1-677
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_app_options(2)
set_app_option(2)
678
route.common.virtual_flat
Specifies the common routing effort level.
TYPE
string
DEFAULT
off
DESCRIPTION
This application option specifies whether the physical block constraints are obeyed during
global routing. This option does not affect track assignment or detail routing.
When you specify a mode other than off for this option, the global router gives priority to
clock net routing. The "comb" topology for clocks is unsupported in virtual flat routing.
Valid values are
off (default)
The global router ignores physical block constraints and routes the design flat.
all_routing
The global router routes all nets and preserves the physical hierarchy and pin constraints
for later pin placement.
top_and_interface_routing_only
The global router preserves the hierarchy and pin constraints, but it ignores nets totally
inside child block and routes only those nets that have top-level connections. This mode
saves CPU time.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_global(2)
route_group(2)
place_pins(2)
Chapter 1:
679
1-679
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
680
route.common.wide_macro_pin_as_fat_wire
Specifies whether a wide macro pin or pad pin should have an implicit depth the same as its
width.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option specifies whether a wide macro pin or pad pin should have an implicit
depth the same as its width.
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.common.wide_macro_pin_as_fat_wire
681
1-681
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.common.wire_on_grid_by_layer_name
Controls whether wires must be routed on-grid. This option controls the same functionality
as the onGrid attribute for a metal layer in the technology file.
TYPE
list
DEFAULT
""
DESCRIPTION
If you use this option, the tool ignores all onGrid attributes defined in the technology file
(both for metal layers and via layers). The default setting for any unspecified onGrid
attributes is false; therefore, on-grid routing is required only for the metal layers specified
with a setting of true in this option and via layers specified with a setting of true in the
-via_on_grid_by_layer_name option. You can specify this option only when the block is
open. This option is to control onGrid attributes only. It has no impact if onWireTrack is
defined in the technology file.
EXAMPLES
The following example sets the route.common.wire_on_grid_by_layer_name application
option to true for the M3 and M4 metal layers.
-name route.common.wire_on_grid_by_layer_name \
-value {{M3 true} {M4 true}}
682
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
683
1-683
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.antenna
Enables (true) or disables (false) antenna analysis.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option enables (true) or disables (false) antenna analysis.
EXAMPLE
The following example disables antenna analysis.
-name route.detail.antenna -value false
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.antenna
684
route.detail.antenna_fixing_preference
Specifies the preferred technique used to fix antenna violations.
TYPE
string
DEFAULT
hop_layers
DESCRIPTION
This application option specifies the preferred technique used to fix antenna violations: layer
hopping or diode insertion.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.antenna_fixing_preference
685
1-685
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.antenna_on_iteration
Specifies the detail routing iteration at which antenna analysis and optimization is turned on.
TYPE
integer
DEFAULT
1
DESCRIPTION
This application option specifies the detail routing iteration at which antenna analysis and
optimization is turned on.
The range is from 1 to 19 (the routing iteration number starts at 0).
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.antenna_on_iteration
686
route.detail.antenna_verbose_level
Specifies the verbosity level to print extra information for antenna analysis and optimization.
TYPE
integer
DEFAULT
1
DESCRIPTION
This application option specifies the verbosity level to print extra information for antenna
analysis and optimization. This option does not affect the actual analysis or optimization.
The range is from 0 to 2.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.antenna_verbose_level
687
1-687
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.check_antenna_on_pg
Enables (true) or disables (false) analysis and optimization of
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option enables (true) or disables (false) analysis and optimization of
antennas on power and ground nets.
For designs with high fanout power or ground nets, enabling this option can result in longer
runtime for routing commands to analyze and optimize antenna violations for these nets.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.check_antenna_on_pg
688
route.detail.check_patchable_drc_from_fixed_shapes
Enables (true) or disables (false) checking of patchable DRCs for
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option enables (true) or disables (false) checking of patchable DRCs for
fixed routes.
When this option is enabled, patchable DRCs (minimum area, minimum length, and
end-of-line spacing) are checked between fixed routes. Violations are resolved by metal
patching.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.check_patchable_drc_from_fixed_shapes
689
1-689
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.check_pin_min_area_min_length
Enables (true) or disables (false) checking for minimum area and minimum
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option enables (true) or disables (false) checking for minimum area and
minimum length rules on pins.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.check_pin_min_area_min_length
690
route.detail.check_port_min_area_min_length
Enables (true) or disables (false) checking for minimum area and minimum
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option enables (true) or disables (false) checking for minimum area and
minimum length rules on physical ports (terminals).
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.check_port_min_area_min_length
691
1-691
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.continue_after_large_design_rule_value_error
Controls whether to continue on large design rule values.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
The tool has an internal threshold for the fatTblExtensionRange, fatTblXExtensionRange,
fatTblYExtensionRange, and protrusionLengthLimitTbl attributes in the technology file.
By default (false), the detail router fails if the value specified for any of these attributes
exceeds the internal threshold.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.continue_after_large_design_rule_value_error
692
route.detail.default_diode_protection
Specifies the diode protection value used for pins during antenna analysis if the value is not
specified in the frame view of the cell.
TYPE
float
DEFAULT
0.0
DESCRIPTION
This application option specifies the diode protection value used for pins during antenna
analysis if the value is not specified in the frame view of the cell. This option has no effect
when the frame view specifies a diode protection value.
Depending on the diode mode, the diode protection value can be used to calculate antenna
ratio requirements, equivalent metal area, or equivalent gate area.
The range is from 0.0 to 1,000,000.00. There is no unit for diode protection.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.default_diode_protection
693
1-693
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.default_gate_size
Specifies the gate size used for pins during antenna analysis if the gate size is not specified
in the frame view of the cell.
TYPE
float
DEFAULT
-1.0
DESCRIPTION
This application option specifies the gate size used for pins during antenna analysis if the
gate size is not specified in the frame view of the cell.
The range is from -1.0 to 1,000,000.00. The unit is the square of the unitLengthName
specified in the technology file.
The tool uses this option only when you set it to a value of 0.0 or greater and the frame view
does not specify the gate size for the pin. This option has no effect when the frame view
specifies a gate size value.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.default_gate_size
694
route.detail.default_port_external_antenna_area
Specifies the antenna area value used for ports (top-level pins) during antenna analysis if
the antenna area is not specified in the frame view of the cell.
TYPE
float
DEFAULT
0.0
DESCRIPTION
This application option specifies the antenna area value used for ports (top-level pins)
during antenna analysis if the antenna area is not specified in the frame view of the cell. The
antenna area is the metal area from the gate input pin to the external port.
The range is from 0.0 to 1,000,000.00. The unit is the square of the unitLengthName
specified in the technology file.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.default_port_external_antenna_area
695
1-695
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.default_port_external_gate_size
Specifies the gate size used for ports (top-level pins) during antenna analysis if the gate size
is not specified in the frame view of the cell.
TYPE
float
DEFAULT
-1.0
DESCRIPTION
This application option specifies the gate size used for ports (top-level pins) during antenna
analysis if the gate size is not specified in the frame view of the cell.
The range is from -1.0 to 1,000,000.00. The unit is square of unitLengthName specified in
the technology file.
The tool uses this option only when you set it to a value of 0.0 or greater and the frame view
does not specify the gate size for the port. This option has no effect when the frame view
specifies a gate size value.
If the gate size is not set for a port, Zroute issues a ZRT-311 message and does not perform
antenna analysis on the port.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.default_port_external_gate_size
696
route.detail.detail_route_special_design_rule_fixing_stage
Specifies the stage at which to fix special design rules when running the route_detail,
route_auto, and route_opt commands.
TYPE
string
DEFAULT
late_routing
DESCRIPTION
This application option specifies the stage at which to fix special design rules when running
the route_detail, route_auto, and route_opt commands.
The special design rules include the iso-dense via enclosure rule. Fixing the special design
rules requires significant routing resources, so you might not want to fix them at all stages.
You can fix these rules at the following stages:
late_routing (the default) Check and fix these rules in the postroute stage, after the
other DRC rules.
early_routing
Check and fix these rules along with the other DRC rules.
none
Never check and fix these rules.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.detail_route_special_design_rule_fixing_stage
697
1-697
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.diagonal_min_width
Specifies whether to use diagonal distance for minimum width violations.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option specifies whether to use diagonal distance for minimum width
violations.
If true (the default), diagonal distance is used.
If false, manhattan distance is used.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.diagonal_min_width
698
route.detail.diode_insertion_mode
Specifies whether to fix antenna violations by using both new and spare diodes, spare
diodes only, or new diodes only.
TYPE
string
DEFAULT
new_and_spare
DESCRIPTION
This application option specifies whether to fix antenna violations by using both new and
spare diodes (new_and_spare), spare diodes only (spare), or new diodes only (new).
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.diode_insertion_mode
699
1-699
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.diode_libcell_names
Specifies the diode library cells to use for antenna fixing.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option specifies the diode library cells to use for antenna fixing.
The default is an empty list, in which case diodes are detected automatically.
EXAMPLE
The following example shows how to set the diode libcell names so they can be used for
Zroute diode insertion.
-block [current_block] -list {route.detail.diode_libcell_names
{ANTENNA ANTENNA2} }
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.diode_libcell_names
700
route.detail.diode_preference
Specifies the preference for fixing antenna violations by inserting a new diode or using an
existing spare diode.
TYPE
string
DEFAULT
none
DESCRIPTION
This application option specifies the preference for fixing antenna violations by inserting a
new diode or using an existing spare diode.
The default is none. In this case, the tool selects the method to use based on whether an
empty location for a new diode or an existing spare diode is closer to the required location.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.diode_preference
701
1-701
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.drc_convergence_effort_level
Specifies the effort level to use before early termination of detail routing when design rule
checking (DRC) does not converge.
TYPE
string
DEFAULT
medium
DESCRIPTION
This application option specifies the effort level to use before early termination of detail
routing when design rule checking (DRC) does not converge.
Set the effort level to high to run more detail routing iterations when DRC does not
converge. Set the effort level to low to run fewer detail route iterations when DRC does not
converge.
This option is ignored if the route.detail.force_max_number_iterations application option
is set to true.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.drc_convergence_effort_level
702
route.detail.eco_max_number_of_iterations
Controls the number of detail route iterations during route_eco and route_opt command.
TYPE
integer
DEFAULT
-1
DESCRIPTION
Specifies the maximum number of detail routing iterations during route_eco as well as
route_opt. You can specify an integer between -1 and 1000. The default value is -1 which
means route_eco and route_opt will determine the number of iterations. For the default
value of detail route iteration of each engine, please refer the man page for the details.
When max_detail_route_iteration switch exists from route_eco command line, the
max_detail_route_iteration switch number will determine the number of detail route
iterations.
EXAMPLES
The following example runs 10 detail route iteration during route_eco
prompt> set_app_options -global
{route.detail.eco_max_number_of_iterations
prompt> route_eco
10}
The following example runs 7 detail route iteration during route_opt

prompt> route_opt
7}
The following example runs 5 detail route iteration during route_eco

Chapter 1:
10}
703
1-703
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
prompt> route_eco -max_detail_route_iterations 5
SEE ALSO
get_app_options(2)
set_app_options(2)
route_eco(2)
route_opt(2)
704
route.detail.eco_route_special_design_rule_fixing_stage
Specifies the stage at which to fix special design rules when running the route_eco
command.
TYPE
string
DEFAULT
late_routing
DESCRIPTION
the route_eco command.
other DRC rules.
early_routing
none
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.eco_route_special_design_rule_fixing_stage
705
1-705
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.eco_route_use_soft_spacing_for_timing_optimizatio
n
Enables (true) or disables (false) soft-rule-based timing optimization during ECO routing.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option enables (true) or disables (false) soft-rule-based timing optimization
during ECO routing.
This option works only if the route.detail.timing_driven application option is set to true.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.eco_route_use_soft_spacing_for_timing_optimization
706
route.detail.elapsed_time_limit
Specifies the limit for elapsed wall-clock time in minutes.
TYPE
integer
DEFAULT
-1
DESCRIPTION
This application option specifies the limit for elapsed wall-clock time in minutes.
The range is from -1 to MAX_INT.
The default is -1, which means no limit.
EXAMPLE
The following example sets the maximum elapsed time to 60 minutes.
-name route.detail.elapsed_time_limit \
-value 60
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.elapsed_time_limit
707
1-707
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.force_max_number_iterations
Controls whether the maximum number of iterations must be run when DRCs do not
converge.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option controls whether the maximum number of iterations must be run
when DRCs do not converge.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.force_max_number_iterations
708
route.detail.generate_extra_off_grid_pin_tracks
Specifies whether to generate extra off-grid routing tracks for pin connections.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option specifies whether to generate extra off-grid routing tracks for pin
connections.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.generate_extra_off_grid_pin_tracks
709
1-709
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.generate_off_grid_feed_through_tracks
Specifies the effort level used to generate extra off-grid routing tracks for feedthrough nets
between blockages.
TYPE
string
DEFAULT
low
DESCRIPTION
This application option specifies the effort level used to generate extra off-grid routing tracks
for feedthrough nets between blockages.
Valid values are low, medium, and high.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.generate_off_grid_feed_through_tracks
710
route.detail.group_route_special_design_rule_fixing_stage
Specifies the stage at which to fix special design rules when running the route_group
command.
TYPE
string
DEFAULT
late_routing
DESCRIPTION
the route_group command.
other DRC rules.
early_routing
none
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.group_route_special_design_rule_fixing_stage
711
1-711
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.hop_layers_to_fix_antenna
Controls whether the router performs layer hopping to fix antenna violations.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option controls whether the router performs layer hopping to fix antenna
violations.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.hop_layers_to_fix_antenna
712
route.detail.ignore_drc
Controls whether the router ignores specific routing design rule checks (DRCs).
TYPE
list
DEFAULT
""
DESCRIPTION
This application option controls whether the router ignores specific routing design rule
checks (DRCs). When a DRC is ignored, the router neither analyzes nor fixes those
violations.
The valid DRC keywords are
same_net_metal_space
Ignore all same net metal spacing violations.
same_net_enclosed_cut_space
Ignore same net enclosed cut spacing violations.
all_same_net_drc_for_frozen_net
Ignore all same net violations on frozen nets.
The default is false for all DRC types, which means that none of them are ignored.
EXAMPLE
The following example tells the router to ignore the same net metal spacing violations but
not the same net enclosed cut spacing violations.
-name route.detail.ignore_drc
-value { {same_net_metal_space true} \
{same_net_enclosed_cut_space false} }
Chapter 1:
713
1-713
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
714
route.detail.incremental_detail_route_special_design_rule_fixing
_stage
Specifies the stage at which to fix special design rules during incremental detail routing (the
route_detail -incremental true command).
TYPE
string
DEFAULT
late_routing
DESCRIPTION
This application option selects the stage at which to fix special design rules during
incremental detail routing (the route_detail -incremental true command).
other DRC rules.
early_routing
none
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.incremental_detail_route_special_design_rule_fixing_stage
715
1-715
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.insert_diodes_during_routing
Specifies whether the router can use diode insertion to fix antenna violations.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option specifies whether the router can use diode insertion to fix antenna
violations.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.insert_diodes_during_routing
716
route.detail.macro_pin_antenna_mode
Specifies how macro cell pins are treated for antenna considerations.
TYPE
string
DEFAULT
normal
DESCRIPTION
This application option specifies how macro cell pins are treated for antenna considerations.
The valid modes are
normal (the default)

Treat macro cell pins as normal standard cell output pins.
jump
Treat macro cell output pins as if they are connected to a huge antenna and break the
antenna, which requires a jumper at the top metal layer.
top_layer
Connect all input pins to macro cell output pins only through the highest routing layer of
the net.
EXAMPLE
The following example sets the macro pin antenna mode to jump.
-name route.detail.macro_pin_antenna_mode -value jump
SEE ALSO
Chapter 1:
717
1-717
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
718
route.detail.max_antenna_pin_count
Specifies the maximum number of pins on a net on which antenna checking is performed.
TYPE
integer
DEFAULT
-1
DESCRIPTION
This application option specifies the maximum number of pins on a net on which antenna
checking is performed. If a net has more than the specified number of pins, antenna
checking is skipped; otherwise, antenna checking is performed.
The range is from -1 to 1,000,000.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.max_antenna_pin_count
719
1-719
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.merge_gates_for_antenna
Enables (true) or disables (false) merging gates for antenna analysis.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option enables (true) or disables (false) merging gates for antenna analysis.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.merge_gates_for_antenna
720
route.detail.optimize_tie_off_effort_level
Specifies the effort level used to optimize wire length and via counts for tie-off nets.
TYPE
string
DEFAULT
low
DESCRIPTION
This application option specifies the effort level used to optimize wire length and via counts
for tie-off nets.
The valid values are
off
No extra effort to optimize wire length and via counts for tie-off nets.
low (the default)

Low effort to optimize wire length and via counts for tie-off nets.
high
High effort to optimize wire length and via counts for tie-off nets.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.optimize_tie_off_effort_level
721
1-721
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.optimize_wire_via_effort_level
Specifies the effort level used to optimize wire length and via counts.
TYPE
string
DEFAULT
low
DESCRIPTION
This application option specifies the effort level used to optimize wire length and via counts.
off
No extra effort to optimize wire length and via counts.
low (the default)

Low effort to optimize wire length and via counts.
medium
Medium effort to optimize wire length and via counts.
high
High effort to optimize wire length and via counts.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.optimize_wire_via_effort_level
722
route.detail.pin_taper_mode
Specifies the pin tapering mode.
TYPE
string
DEFAULT
default_width
DESCRIPTION
This application option specifies the pin tapering mode.
default_width (the default)

Nondefault rule connections to pins are tapered to the default rule width.
pin_width
Nondefault rule connections to pins are tapered to the pin width.
off
Pin tapering is not performed.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.pin_taper_mode
723
1-723
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.port_antenna_mode
Specifies how the ports (top-level pins) are treated for antenna considerations.
TYPE
string
DEFAULT
float
DESCRIPTION
This application option specifies how the ports (top-level pins) are treated for antenna
considerations.
float (the default)

Treat ports as floating wires.
jump
Treat ports as if they are connected to a huge antenna and break the antenna, which
requires a jumper at the top metal layer.
top_layer
Connect all input pins to ports only through the highest routing layer of the net.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.port_antenna_mode
724
route.detail.post_process_special_design_rule_fixing_stage
Specifies the stage at which to fix special design rules during post-processing commands
such as add_redundant_vias.
TYPE
string
DEFAULT
late_routing
DESCRIPTION
This application option specifies the stage at which to fix special design rules during
post-processing commands such as add_redundant_vias,.
other DRC rules.
early_routing
none
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.post_process_special_design_rule_fixing_stage
725
1-725
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.repair_shorts_over_macros_effort_level
Controls the effort level applied to the automatic repairing of shorts over macros.
TYPE
string
DEFAULT
off
DESCRIPTION
This application option controls the effort level applied to the automatic repairing of shorts
over macros.
If enabled, any shorts over macros that remain after detail routing can trigger the deletion of
the involved wires and a full ECO rerouting of the involved nets (global routing, track
assignment, and detail routing). Higher effort levels can increase the number of ECO repair
iterations, which might decrease the final DRC count at the expense of runtime.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.repair_shorts_over_macros_effort_level
726
route.detail.report_ignore_drc
Enables an additional DRC report and specifies the DRC types to be suppressed from this
report.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option enables an additional DRC report and specifies the DRC types to be
suppressed from this report.
The additional report is printed after the DRC summary and includes all DRC violations,
except internal-only types and those specified in the list.
The valid DRC name values are
"Access preference area"
"Antenna"
"Asymmetric via-cut to metal spacing"
"Cluster bbox"
"Comb routing direct connection"
"Comb routing maximum connections"
"Comb routing daisy-chain distance"
"Compute all drcs"
"Connection not within pin"
"Convex metal cut enclosure"
"Convex metal cut keepout"
"Crossing top-cell boundary"
"Dangling wire"
"Dense end of line enclosure"
"Dense short metal spacing"
"Diff net fat extension spacing"
"Diff net spacing"
"Diff net var rule spacing"
"Diff net via-cut spacing"
"Diff net via-cut to metal spacing"
"Dog bone spacing"
"Edge-line via spacing"
"Enclosed unaligned via center spacing"
"Enclosed via spacing"
Chapter 1:
727
1-727
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
"End of line enclosure"

"End of line spacing"
"End of line to concave corner distance"
"End of line wire via enclosure"
"Fat metal via asymmetric enclosure"
"Fat shape"
"Fat wire via keepout area"
"Fat wire via keepout enclosure"
"Forbidden metal"
"Forbidden Pitch"
"Frozen layer"
"Greater than maximum width"
"h-shape"
"Illegal Bridge"
"Illegal width route"
"Jog Wire via Enclosure"
"Jog wire via keepout area"
"Joint wire via enclosure"
"Less than minimum area"
"Less than minimum edge length"
"Less than minimum enclosed area"
"Less than minimum length"
"Less than minimum width"
"Less than NDR width"
"Less than taper width"
"Line-end to short-edge (minEdgeLengthTbl)"
"Macro pin connection by offset"
"Maximum utilization"
"Min-max layer"
"Minimum extension"
"Minimum utilization"
"MisAligned via wire"
"Multiple pin connections"
"NDR contact code mismatch"
"Needs fat contact"
"Needs fat contact on extension"
"Needs redundant via"
"Non-preferred direction route"
"Off-grid"
"Offset via"
"One grid jog in non-preferred direction"
"Over max stack level"
"Protrusion length"
"Redundant via"
"Same net fat extension spacing"
"Same net spacing"
"Same net via-cut spacing"
"Secondary pg pin direct connection"
"Secondary pg pin maximum connections"
"Self aligned via cluster"
"Self aligned via cut spacing"
"Self aligned via invalid enclosure"
"Self aligned via with neighbor cut spacing"
"Self aligned zig-zag via with neighbor cut spacing"
"Self aligned zig-zag via cut spacing"
"Self aligned diagonal via cut spacing"
"Shielding unintended overlap"
"Short"
728
"Small jog"
"Soft spacing"
"Special notch spacing"
"T junction"
"T shape wire via enclosure"
"Tie to rail"
"Tie to rail directly"
"Two sided end/joint spacing"
"U shape spacing"
"Via-cut to metal spacing"
"Via-Metal Concave corner rule"
"Voltage area"
"Wide Metal Jog"
Note that the double quotation marks are required for any DRC name that includes spaces.
By default, the additional report is not generated.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
729
1-729
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.reuse_filler_locations_for_diodes
Specifies whether to reuse filler cell locations for inserting diodes.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option specifies whether to reuse filler cell locations for inserting diodes.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.reuse_filler_locations_for_diodes
730
route.detail.save_after_iterations
Saves the intermediate cell after the specified iterations.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option saves the intermediate cell after the specified iterations.
EXAMPLE
The following example shows how to save the design after DR iterations 0 and 1.
-block [current_block] -list {route.detail.save_after_iterations { 0
1 } }
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.save_after_iterations
731
1-731
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.save_cell_prefix
Specifies the prefix to be used in the saved cell name.
TYPE
string
DEFAULT
DR
DESCRIPTION
This application option specifies the prefix to be used in the saved cell name.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.save_cell_prefix
732
route.detail.skip_antenna_fixing_for_nets
Specifies the nets to be skipped for antenna fixing.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option specifies the nets to be skipped for antenna fixing. You must specify
the nets as a Tcl list; this option does not take a Tcl collection as input.
By default, the router fixes the antenna violations for all signal and clock nets.
EXAMPLE
The following example shows how to skip a net for antenna analysis.
{route.detail.skip_antenna_fixing_for_nets n3567}
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.skip_antenna_fixing_for_nets
733
1-733
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.timing_driven
Specifies whether timing-driven routing is enabled.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option specifies whether timing-driven routing is enabled.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.timing_driven
734
route.detail.top_layer_antenna_fix_threshold
Specifies the threshold for fixing antenna violations on the top routing layer.
TYPE
integer
DEFAULT
-1
DESCRIPTION
This application option specifies the threshold for fixing antenna violations on the top routing
layer. Antenna violations on the top routing layer are fixed if they are within ((safe_ratio) * (1
+ top_layer_antenna_fix_threshold * 0.1)).
The range is from -1 to 10.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.top_layer_antenna_fix_threshold
735
1-735
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.use_default_width_for_min_area_min_len_stub
Specifies whether to use default width stubs to fix minimum area and minimum length
violations.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option specifies whether to use default width stubs to fix minimum area and
minimum length violations.
When false (the default), stubs are the same width as the via surround. When true, stubs
are the default width.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.use_default_width_for_min_area_min_len_stub
736
route.detail.use_lower_hierarchy_for_port_diodes
Controls the logic hierarchy in which diodes are inserted to fix antenna violations of physical
ports (terminals).
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option controls the logic hierarchy in which diodes are inserted to fix
antenna violations of physical ports (terminals).
By default (false), the diodes are inserted at the top level.
If set to true and the port belongs to a voltage area, the diodes are inserted in the logic
hierarchy associated with the voltage area. If the port does not belong to a voltage area, the
diodes are inserted at the top level regardless of the setting of this option.
Note that the diodes are inserted in the same physical block as the boundary pin regardless
of the setting of this option.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.use_lower_hierarchy_for_port_diodes
737
1-737
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.use_wide_wire_effort_level
TYPE
String
DEFAULT
off
DESCRIPTION
Specifies the effort level to use NDR vias and wires as much as possible within taper limit.
The pin tapering is defined by the NDR rule and by the option
"route.detail.use_wire_wire_to_xx_pin". This effort level works only on the pin connection
where tapering is allowed. Once this option is set to low or high, we should see less tapering
but longer runtime. This is because that we would spend more time to optimize the NDR pin
connection to use bigger NDR vias and wires. The higher the effort, the longer the runtime
and the higher the NDR wire and via usage.
Valid values are off, low, and high.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.use_wide_wire_effort_level
738
route.detail.use_wide_wire_to_input_pin
Specifies whether pin tapering to input pins is disallowed.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option specifies whether pin tapering to input pins is disallowed.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.use_wide_wire_to_input_pin
739
1-739
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.use_wide_wire_to_macro_pin
Specifies whether pin tapering to macro pins is disallowed.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option specifies whether pin tapering to macro pins is disallowed.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.use_wide_wire_to_macro_pin
740
route.detail.use_wide_wire_to_output_pin
Specifies whether pin tapering to output pins is disallowed.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option specifies whether pin tapering to output pins is disallowed.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.use_wide_wire_to_output_pin
741
1-741
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.use_wide_wire_to_pad_pin
Controls pin tapering to pad pins.
TYPE
string
DEFAULT
same_as_macro_pin
DESCRIPTION
This application option controls pin tapering to pad pins.
same_as_macro_pin (the default)

The setting is taken from the route.detail.use_wide_wire_to_macro_pin application
option.
true
Disallow pin tapering to pad pins.
false
Allow pin tapering to pad pins.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.use_wide_wire_to_pad_pin
742
route.detail.use_wide_wire_to_port
Controls pin tapering to ports.
TYPE
string
DEFAULT
same_as_macro_pin
DESCRIPTION
This application option controls pin tapering to ports.
same_as_macro_pin (the default)

The setting is taken from the route.detail.use_wide_wire_to_macro_pin application
option.
true
Disallow pin tapering to ports.
false
Allow pin tapering to ports.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
route.detail.use_wide_wire_to_port
743
1-743
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.user_defined_partition
Specifies the coordinates, in database units, of a rectangular partition to be added for
routing.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option specifies the coordinates, in database units, of a rectangular partition
{llx lly urx ury} to be added for routing.
In general, the detail router automatically generates partitions to fix the DRCs in the design.
In some situations, it might not generate the right-sized partitions to fix the DRCs. In this
case, you can assist Zroute by adding the right-sized partitions. This option is intended only
for advanced users. There is a limit on the size of the partition as it can cause huge memory
and runtime overhead. As a rough guide, the area of the partition should be less than 600
pitches by 600 pitches on metal1.
EXAMPLE
The following example adds a user-defined partition for routing.
-name route.detail.user_defined_partition \
-value {100 200 500 3000}
SEE ALSO
get_app_options(2)
set_app_option(2)
744
route_opt(2)
route_auto(2)
route_detail(2)
Chapter 1:
745
1-745
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.detail.var_spacing_to_same_net
Specifies if nondefault spacing is to be applied to shapes of the same net.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option specifies if nondefault spacing is to be applied to shapes of the same
net.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_auto(2)
route_detail(2)
route.detail.var_spacing_to_same_net
746
route.global.coarse_grid_refinement
Enables the coarse grid refinement technique in global routing
TYPE
boolean
DEFAULT
true
DESCRIPTION
This application option specifies if the tool will use a uniform or non-uniform coarse grid for
its global routing. The default behavior is to enable a non-uniform coarse grid. Non-uniform
grids have an advantage of providing better QoR in difficult routing areas like channels at the
expense of slightly increased runtime.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_global(2)
route_auto(2)
route_eco(2)
route_group(2)
Chapter 1:
route.global.coarse_grid_refinement
747
1-747
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.global.connect_pins_outside_routing_corridor
Enables (true) or disables (false) to connect to the pins outside the routing corridor.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option enables (true) or disables (false) the global routing to connect the
pins outside the routing corridor.
SEE ALSO
create_routing_corridor(2)
create_routing_corridor_shape(2)
report_routing_corridors(2)
route.global.connect_pins_outside_routing_corridor
748
route.global.crosstalk_driven
Enables (true) or disables (false) crosstalk-driven global routing.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option enables (true) or disables (false) crosstalk-driven global routing.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_global(2)
route_auto(2)
route_eco(2)
route_group(2)
Chapter 1:
route.global.crosstalk_driven
749
1-749
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.global.deterministic
Specifies the determinstic mode of global router in multicore routing.
TYPE
string
DEFAULT
off
DESCRIPTION
This application option specifies if the global router results will be repeatable among
different multi-threaded runs (single-thread global router is always repeatable). To enable
this, set the value of the option to "on". To disable the feature, set the value of the option to
"off". The default value is "off".
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_global(2)
route_auto(2)
route_eco(2)
route_group(2)
route.global.deterministic
750
route.global.double_pattern_utilization_by_layer_name
Specifies the double patterning utilization percentage for each layer.
TYPE
list
DEFAULT
""
DESCRIPTION
This application option specifies the double-patterning utilization percentage for each layer.
The format for specifying the double-patterning utilization for a layer is
{layer utilization}
Specify the layer by using the layer name from the technology file.
The range for the utilization percentage is from 0 to 100. The default is 80 for M1 and M2,
85 for M3, and 90 for any higher double-patterning layers. The value is 100 for
non-double-patterning layers.
EXAMPLE
The following example sets the route.global.double_pattern_utilization_by_layer_name
option on M1, M2, and M5.
prompt> set_app_options -list \
{route.global.double_pattern_utilization_by_layer_name \
{ {M1 85} {M2 85} {M5 70} }}
SEE ALSO
get_app_options(2)
Chapter 1:
751
1-751
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
set_app_option(2)
route_opt(2)
route_global(2)
route_auto(2)
route_eco(2)
route_group(2)
752
route.global.effort_level
Specifies the global routing effort level.
TYPE
string
DEFAULT
medium
DESCRIPTION
This application option specifies the global routing effort level.
Valid values are
minimum
Very fast run time. Runs a maximum of two phases.
low
Fast run time. Runs a maximum of three phases.
medium (default)
Medium run time. Runs a maximum of four phases.
high
Slow run time, but better quality of results. Runs a maximum of five phases.
ultra
Slower run time. Use on really congested designs. Runs a maximum of seven phases.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_global(2)
route_auto(2)
route_eco(2)
Chapter 1:
753
1-753
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route_group(2)
754
route.global.exclude_blocked_gcells_from_congestion_report
Controls whether blocked global routing cells (gcells) are included in the overflow
percentage calculation.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option controls whether blocked global routing cells (gcells) are included in
the overflow percentage calculation.
By default (false), the total number of global routing cells is used to calculate the overflow
percentages in the congestion report.
If the option is set to true, the overflow percentage calculation excludes the global routing
cells that are blocked for routing. In cases where the global router has to route through
blocked global routing cells to find a solution, those global routing cells are counted in the
overflow number, but not in the total number.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_global(2)
route_auto(2)
route_eco(2)
route_group(2)
Chapter 1:
route.global.exclude_blocked_gcells_from_congestion_report
755
1-755
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.global.extra_blocked_layer_utilization_reduction
Specifies the percentage of additional utilization to be reduced for areas where either the
upper or lower layer is blocked and switching to the opposite layer would take more than one
track resource.
TYPE
integer
DEFAULT
0
DESCRIPTION
This application option specifies the percentage of additional utilization to be reduced for
areas where either the upper or lower layer is blocked and switching to the opposite layer
would take more than one track resource. You must specify a value from 0 to 100, inclusive.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_global(2)
route_auto(2)
route_eco(2)
route_group(2)
route.global.extra_blocked_layer_utilization_reduction
756
route.global.force_full_effort
Forces the maximum number of global routing iterations based on the effort level.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option forces the maximum number of global routing iterations based on the
effort level to try to achieve better results with longer runtime. The effort level is determined
from the setting of the route.global.effort_level application option or the route_global
-effort_level option.
By default (false), the global router might stop before the maximum number of iterations,
based on the incremental congestion reduction.
If set to true, the global router always performs the maximum number of routing phases
based on the specified effort level. For example, if this option is set to true and the
route.global.effort_level option is set to high, the global router always runs five routing
phases.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_global(2)
route_auto(2)
route_eco(2)
route_group(2)
Chapter 1:
route.global.force_full_effort
757
1-757
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.global.macro_boundary_track_utilization
Specifies the percentage of tracks to be used along macro boundaries.
TYPE
integer
DEFAULT
100
DESCRIPTION
This application option specifies the percentage of tracks to be used along macro
boundaries. You must specify a value between 0 and 100, inclusive.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_global(2)
route_auto(2)
route_eco(2)
route_group(2)
route.global.macro_boundary_track_utilization
758
route.global.macro_boundary_width
Specifies the width of the macro boundary in terms of global route cells.
TYPE
integer
DEFAULT
5
DESCRIPTION
This application option specifies the width of the macro boundary in terms of global route
cells. You must specify a value between 0 and 10, inclusive.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_global(2)
route_auto(2)
route_eco(2)
route_group(2)
Chapter 1:
route.global.macro_boundary_width
759
1-759
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.global.macro_corner_track_utilization
Specifies the percentage of tracks to be used along macro corners.
TYPE
integer
DEFAULT
100
DESCRIPTION
This application option specifies the percentage of tracks to be used along macro corners.
You must specify a value between 0 and 100, inclusive.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_global(2)
route_auto(2)
route_eco(2)
route_group(2)
route.global.macro_corner_track_utilization
760
route.global.timing_driven
Enables (true) or disables (false) timing-driven global routing.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option enables (true) or disables (false) timing-driven global routing.
EXAMPLE
The following example sets the route.global.timing_driven option to true.
prompt> set_app_options -as_user_default -list
{route.global.timing_driven true}
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_global(2)
route_auto(2)
route_eco(2)
route_group(2)
Chapter 1:
route.global.timing_driven
761
1-761
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.global.timing_driven_effort_level
Specifies the effort level for timing-driven global routing.
TYPE
string
DEFAULT
high
DESCRIPTION
This application option specifies the effort level for timing-driven global routing. The effort
levels trade off between timing QoR and DRC convergence, with the high effort level
emphasizing timing QoR and the low effort level emphasizing DRC convergence.
This option takes effect only if the route.global.timing_driven application option is set to
true.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_global(2)
route_auto(2)
route_eco(2)
route_group(2)
route.global.timing_driven_effort_level
762
route.global.voltage_area_corner_track_utilization
Specifies the percentage of tracks to be used in the region within five global routing cells of
a voltage area corner.
TYPE
integer
DEFAULT
100
DESCRIPTION
This application option specifies the percentage of tracks to be used in the region within five
global routing cells of a voltage area corner. You must specify a value between 0 and 100,
inclusive.
A smaller utilization reduces the number of global routes that can go through a global routing
cell by artificially setting the congestion in that area higher. If the neighboring global routing
cells have lower congestion, the routing might be pushed to them; however, this is a function
of many other metrics in the global router.
SEE ALSO
get_app_options(2)
set_app_option(2)
route_opt(2)
route_global(2)
route_auto(2)
route_eco(2)
route_group(2)
Chapter 1:
route.global.voltage_area_corner_track_utilization
763
1-763
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route.track.crosstalk_driven
Enables (true) or disables (false) crosstalk-driven track assignment.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option enables (true) or disables (false) crosstalk-driven track assignment.
SEE ALSO
get_app_options(2)
set_app_option(2)
route.track.crosstalk_driven
764
route.track.timing_driven
Enables (true) or disables (false) timing-driven track assignment.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option enables (true) or disables (false) timing-driven track assignment.
EXAMPLE
The following example sets the route.track.timing_driven application option to true.
-name route.track.timing_driven \
-value true
SEE ALSO
get_app_options(2)
set_app_option(2)
Chapter 1:
route.track.timing_driven
765
1-765
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route_opt.eco_route.mode
TYPE
string
DEFAULT
detail
DESCRIPTION
Specifies mode of the eco_route step that is getting performed at the end of the route_opt
flow. Allowable options are "detail" and "track".
SEE ALSO
route_opt(2)
766
route_opt.flow.enable_ccd
TYPE
boolean
DEFAULT
false
DESCRIPTION
Specifies whether concurrent clock and data optimization is enabled in the route_opt
command. Enabling concurrent clock and data optimization helps setup timing closure.
SEE ALSO
route_opt(2)
Chapter 1:
route_opt.flow.enable_ccd
767
1-767
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route_opt.flow.enable_cto
TYPE
boolean
DEFAULT
false
DESCRIPTION
Specifies whether clock tree optimization is enabled in the route_opt command.
SEE ALSO
route_opt(2)
route_opt.flow.enable_cto
768
route_opt.flow.enable_power
TYPE
boolean
DEFAULT
false
DESCRIPTION
Specifies whether the route_opt command runs the flow that reduces leakage power.
Expect improvement in leakage power when the power flow is turned on.
SEE ALSO
route_opt(2)
Chapter 1:
route_opt.flow.enable_power
769
1-769
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
route_opt.flow.xtalk_reduction
TYPE
boolean
DEFAULT
false
DESCRIPTION
Specifies whether the route_opt command performs routing-based crosstalk reduction prior
to logic optimization.
SEE ALSO
route_opt(2)
route_opt.flow.xtalk_reduction
770
routing_blockage_attributes
Lists the predefined attributes for routing_blockages.
DESCRIPTION
routing_blockage attributes are provided in the subsections that follow.
command.
Routing Blockage Attributes
area
A float attribute for the area of the routing_blockage.
bbox
A rectangle attribute for the bounding-box of the routing_blockage. The format of a rectangle
the rectangle.
boundary
A coordinate_list attribute for the boundary of the routing_blockage. The format of a
design_rule_width
A distance attribute that specifies the design rule width of a routing_blockage. This is the
effective width used for spacing calculations.
full_name
A string attribute for the name of the routing_blockage.
Chapter 1:
771
1-771
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
in_edit_group
A boolean attribute to specify whether the routing_blockage belongs to an edit_group.
is_derived
A boolean attribute to indicate whether the routing_blockage was automatically generated
by the application. For more details, see derive_placement_blockages and
plan.place.auto_generate_blockages. This attribute is settable.
is_design_rule_blockage
A boolean attribute to specify whether the routing_blockage is created for the purpose of
design rule checking. This attribute is settable if the layer type blocked by this
routing_blockage is VIA_CUT or LOCAL_VIA_CUT.
is_shadow
A boolean attribute to specify whether the routing_blockage is pushed down from above.
layer
A collection attribute with the layer which is blocked by this routing_blockage. This attribute
is settable. If the layer type changes from VIA_CUT or LOCAL_VIA_CUT to other types as
result of setting this attribute, the is_design_rule_blockage attriute will be re-set to false.
layer_name
A string attribute for the name of the layer which is blocked by this routing_blockage.
min_spacing
A distance attribute that specifies the minimum spacing between a routing_blockage and
any other routing. This attribute is settable.
name
A string attribute for the name of the routing_blockage. This attribute is settable.
net_types
A string attribute representing the net types blocked by the routing_blockage. If the string is
empty, then the routing_blockage blocks all net types. This attribute is settable.
772
blockage_group_id
A integer attribute in the range from 1 to 8 that represents the blockage group identification
number assigned to this routing_blockage created by the create_routing_blockage
command. Multiple blockages can be assigned the same blockage group ID number using
multiple create_routing_blockage commands. All routing_blockages with the same
blockage_group_id attribute belong to the same group. This attribute is 0 by default and
doesn't apply for the net_type based association.
nets
A collection attribute representing the specific nets associated with the blockage_group_id
of this routing_blockage. Doesn't apply for the net_type based association.
number_of_nets
An integer attribute with the number of specific nets associated with the blockage_group_id
of this routing_blockage. Doesn't apply for the net_type based association.
object_class
A string attribute with the value of "routing_blockage".
parent_block
A collection attribute with the owner block object for this routing_blockage.
parent_block_cell
A collection attribute with the parent block cell object for this routing_blockage.
parent_cell
A collection attribute with the owner cell object for this routing_blockage.
physical_status
A string attribute representing the physical modification status of the routing_blockage. If
status is unrestricted, the routing_blockage may be moved or rotated. If the status is locked,
the routing_blockage may not be moved or rotated. This is a settable attribute.
Chapter 1:
773
1-773
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
reserve_for_top_level_routing
A boolean attribute to specify whether the routing_blockage reserves the area for top level
routing. Routes in the top block may route through this routing_blockage, but routes in this
block are blocked by this routing_blockage. This attribute is settable.
shadow_status
A string attribute to represent the shadow status of the routing_blockage. Valid values are
is settable.
top_block
A collection attribute with the top block object for this routing_blockage.
SEE ALSO
get_attribute(2)
list_attributes(2)
774
routing_corridor_attributes
Description of the predefined attributes for routing corridors.
DESCRIPTION
routing_corridor attributes are provided in the subsections that follow.
command.
routing_corridor Attributes
name
A string attribute for the name of a routing_corridor.
full_name
A string attribute for the name of a routing_corridor.
object_class
A string attribute with the value of "routing_corridor".
is_connected
A Boolean attribute to specify whether all shapes of the routing_corridor are connected.
is_cover_all_pin_port
A Boolean attribute to specify whether shapes of the routing_corridor cover all pins and
ports connected by the associated nets.
Chapter 1:
775
1-775
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
is_manhattan
A Boolean attribute to specify whether all shapes of the routing_corridor are manhattan.
has_tile
A Boolean attribute to indicate whether corridor has rectangle or rectilinear shape.
has_path
A Boolean attribute to indicate whether corridor has path shape.
objects
Specifies the nets associated with the routing corridor. The data type of objects is collection.
number_of_objects
An integer attribute with the number of objects associated the routing_corridor.
parent_block
A collection attribute with the owner block object for this routing_corridor.
parent_cell
A collection attribute with the owner cell object for this routing_corridor.
parent_block_cell
A collection attribute with the parent block cell object for this routing_corridor.
physical_status
A string attribute representing the physical modification status of the routing_corridor. If
status is unrestricted, the routing_corridor may be moved or rotated. If the status is locked,
the routing_corridor may not be moved or rotated. This is a settable attribute.
top_block
A collection attribute with the top block object for this routing_corridor.
776
SEE ALSO
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
777
1-777
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
routing_corridor_shape_attributes
Contains attributes related to routing corridor shape.
DESCRIPTION
routing_corridor_shape attributes are provided in the subsections that follow.
command.
routing_corridor_shape Attributes
name
A string attribute for the name of a routing_corridor_shape object.
full_name
A string attribute for the name of a routing_corridor_shape object.
object_class
A string attribute with the value of "routing_corridor_shape".
shape_type
A string attribute for the routing_corridor_shape type. Valid values are "rectangle", "polygon"
and "path".
bbox
A rectangle attribute for the bounding-box of a routing corridor shape. The format of a
This attribute is settable only for rectangle routing_corridor_shape.
778
points
A coordinate list attribute for the points of the routing_corridor_shape. The format of
coordinate list specification is {{x1 y1} {x2 y2} ...}, which specifies a list of points defining the
boundary for region, or centerline for path.
number_of_points
An integer attribute for the number of points of the routing_corridor_shape.
width
A distance attribute for the width of a path routing_corridor_shape.
start_endcap
A string attribute for the starting end alignment type of a path routing_corridor_shape. Valid
value is "flush".
end_endcap
A string attribute for the ending end alignment type of a path routing_corridor_shape. Valid
value is "flush".
is_manhattan
A Boolean attribute to specify whether the routing_corridor_shape is Manhattan.
max_routing_layer
A string attribute for the layer name of the max layer constraint for this
routing_corridor_shape. The format of a coordinate specification is float number. This
min_routing_layer
A string attribute for the layer name of the min layer constraint for this
routing_corridor_shape. This attribute is settable.
Chapter 1:
779
1-779
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
routing_corridor
A collection attribute for the routing corridor owning this routing_corridor_shape.
parent_block
A collection attribute with the owner block object for this routing_corridor_shape.
parent_cell
A collection attribute with the owner cell object for this routing_corridor_shape.
parent_block_cell
A collection attribute with the parent block cell object for this routing_corridor_shape.
physical_status
A string attribute representing the physical modification status of the
routing_corridor_shape. Valid values are unrestricted and locked. If status is unrestricted,
the routing_corridor_shape may be freely modified. If status is locked, the
routing_corridor_shape is fixed for automatic and manual changes. This is a settable
attribute.
top_block
A collection attribute with the top block object for this routing_corridor_shape.
SEE ALSO
create_routing_corridor_shape(2)
get_attribute(2)
list_attribute(2)
set_attribute(2)
780
routing_guide_attributes
Description of the predefined attributes for routing_guide.
DESCRIPTION
routing_guides attributes are provided in the subsections that follow.
command.
the attributes of a class of objects, use the list_attributes -application\P command.
Routing Guide Attributes
access_preference
A string attribute representing access_preference data. Output is in format {"layer name"
{wire/via_access_preference {rect} strength} ..}. Example {M1 {wire_access_preference
{{20 20} {55 55}} .5} ...}
area
A area attribute. The value is area of routing_guide.
bbox
A rect attribute. The value is bounding box of routing_guide.
boundary
A rect attribute. The value is bounding box of routing_guide.
design
A collection attribute with the design object for this routing_guide.
Chapter 1:
781
1-781
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
full_name
horizontal_track_utilization
A int attribute. The value is horizontal track utilization of routing_guide.
is_shadow
A Boolean attribute. The value is true if shadow status is normal for routing_guide, false if
not.
layers
A collection of layers. The value is collection of layers of the routing_guide.
layer_names
A string attribute. The value is all the layer names of the routing_guide.
max_patterns
A string attribute representing max_patterns data. Output is tcl list of sets. Each set consist
of "layer name", "pattern type" and "constraint". Example { {M2 non_pref_dir_edge 3} {M4
non_pref_dir_edge 1} }
name
object_class
A string attribute with the value of "routing_guide".
parent_block
A collection attribute with the owner block object for this routing_guide.
parent_block_cell
A collection attribute with the parent block cell object for this routing_guide.
782
parent_cell
A collection attribute with the owner cell object for this routing_guide.
physical_status
A string attribute representing the physical modification status of the site row. If status is
unrestricted, the site_row may be moved or rotated. If the he status is locked, the site_row
may not be moved or rotated. This is a settable attribute.
preferred_direction_only
A Boolean attribute. The value is true if preffered direction only is set on the routing_guide.
routing_guide_type
A string attribute. The value is type of routing guide. It will have one of the following values
river_routing, switched_direction_only, max_patterns, access_preference.
shadow_status
A string attribute. The value is shadow status of the routing_guide. It will have one of the
following values copied_down, copied_up, normal, pulled_up, pushed_down, virtual_flat.
switch_preferred_direction
A Boolean attribute. The value is true if switch preferred direction is set on the routing_guide.
top_block
A collection attribute with the top block object for this routing_guide.
vertical_track_utilization
A int attribute. The value is vertical track utilization of routing_guide.
SEE ALSO
create_routing_guide(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
783
1-783
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
routing_rule_attributes
Description of the predefined attributes for routing_rule.
DESCRIPTION
routing_rule attributes are provided in the subsections that follow.
command.
the attributes of a class of objects, use the list_attributes application\P command.
Routing Rule Attributes
cuts
A string attribute representing the cuts specification from which the routing_rule vias were
derived. The string format is "{cut_layer_name {cut_name num_of_cuts} ...} ...". The
attribute value exists if and only if the cuts specification was specified through the
create_routing_rule -cuts option and the via list was not subsequently modified.
driver_taper_distance
A string attribute representing the driver taper distance of the routing_rule.
full_name
has_shield
A Boolean attribute. The value is true if any shielding constraints exists, false otherwise.
ignore_spacing_to_blockage
A boolean attribute indicating whether or not the router should ignore this routing_rule's
spacing constraints when considering the distance to blockages. If this value does not exist,
784
the router uses the setting specified by the application option,

route.common.ignore_var_spacing_to_blockage.
ignore_spacing_to_pg
spacing constraints when considering the distance to power and ground nets. If this value
does not exist, the router uses the setting specified by the application option,
route.common.ignore_var_spacing_to_pg.
ignore_spacing_to_shield
spacing constraints when considering the distance to shield nets. If this value does not exist,
the router uses the setting specified by the application option,
route.common.ignore_var_spacing_to_shield.
is_snap_to_track
A Boolean attribute. The value is true if snap to track flag is set on layer, false otherwise.
mask_constraints
A string attribute listing the mask constraint for each routing layer. The string format is
"{layer_name mask_name [fixed]}...". The keyword, fixed, appears next to the mask_name
if the mask is fixed on the layer. If does not appear if the mask is not fixed on the layer. A
layer is listed if and only if it has a mask constraint. This attribute is settable.
name
object_class
A string attribute with the value of "routing_rule".
rdl_taper_distances
A string attribute specifying the maximum length for tapering wires on each redistribution
layer. This is supported only by the flip-chip router. The string format is "layer_name
distance ...".
Chapter 1:
785
1-785
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
rdl_taper_widths
A string attribute specifying the tapering width for each redistribution layer. This is supported
only by the flip-chip router. The string format is "layer_name width ...".
shield_spacings
A string attribute specifying the minimum shield spacing allowed between wires on each
routing layer. The string format is "layer_name shield_spacing ...".
shield_widths
A string attribute specifying the shield widths on each routing layer. The string format is
"layer_name shield_width ...".
spacing_length_thresholds
A string attribute specifying the length thresholds for each spacing in this routing_rule's
spacings attribute. The string format is "layer_name {spacing_length_threshold ...} ...".
spacing_multiplier
A float attribute indicating the multiplier applied to the layer spacings in this routing_rule.
spacing_weight_levels
A string attribute specifying the weight levels for each spacing in this routing_rule's spacings
attribute. The string format is "layer_name {spacing_weight_level ...} ...".
spacings
A string attribute specifying the minimum different-net spacing allowed between wires on
each routing layer. The string format is "layer_name {spacing ...} ...".
taper_distance
A string attribute representing the taper distance of the routing_rule.
taper_over_pin_layers
A integer attribute indicating the number of routing layers over the pin layer that the router
may use for tapering.
786
taper_under_pin_layers
A integer attribute indicating the number of routing layers under the pin layer that the router
may use for tapering.
via_spacings
A string attribute specifying the via spacings between via layers. The string format is
"{layer_name layer_name spacing} ...".
vias
A string attribute specifying the vias which can be created during routing. The string format
is "{via_definition_name site_spec rotation_spec} ...". The site_spec is formatted MxN in
which M is the horizontal site count (i.e., the number of columns in the via) and N is the
vertical site count (i.e., the number of rows in the via), separated by the x character. The
rotation_spec is specified by r or nr, where r indicates a rotated via and nr indicates an
unrotated via.
width_multiplier
A float attribute indicating the multiplier applied to the layer widths in this routing_rule.
widths
A string attribute specifying the wire widths on each routing layer. The string format is
"layer_name width ...".
SEE ALSO
create_routing_rule(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
787
1-787
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
rp_blockage_attributes
Description of the predefined attributes for rp_blockage.
DESCRIPTION
rp_blockage attributes are provided in the subsections that follow.
All attributes are read-only. Read-only attributes are informational, and you cannot set its
value.
rp_blockage Attributes
allow_overlap
A boolean attribute that specifies that the relative placement blockage can be overlapped
with fixed objects.
override_alignment
relative placement blockage in the column of its parent rp_group.
bbox
A rectangle attribute for the bounding-box of a rp_blockage. The format of a rectangle
the rectangle.
column
An integer attribute that specifies the column position of rp_blockage.
full_name
A string attribute for the name of rp_blockage.
788
height
An integer attribute that specifies the height of rp_blockage.
name
A string attribute for the name of rp_blockage.
object_class
A string attribute with the value "rp_blockage".
parent_block
A collection attribute with the owner block object for rp_blockage.
parent_block_cell
A collection attribute with the parent block cell object for rp_blockage.
parent_cell
A collection attribute with the owner cell object for rp_blockage.
parent_rp_group
A string attribute that specifies the parent rp_group name of rp_blockage.
physical_status
A string attribute representing the physical placement status of the relative placement
blockage. The valid values are unplaced and placed. If status is unplaced, the relative
placement blockage has not been placed. If status is placed, the relative placement
blockage has been placed. This is a not a settable attribute.
row
An integer attribute that specifies the row position of rp_blockage.
top_block
A collection attribute with the top block object for rp_blockage.
Chapter 1:
789
1-789
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
top_rp_group
A string attribute that specifies the top rp_group name of rp_blockage.
width
An integer attribute that specifies the column position of rp_blockage.
SEE ALSO
add_to_rp_group(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
790
rp_group_attributes
Description of the predefined attributes for rp_group.
DESCRIPTION
rp_group attributes are provided in the subsections that follow.
All attributes are read-only. Read-only attributes are informational, and you cannot set its
value.
rp_group Attributes
alignment
A string attribute that specifies the alignment to be used to align objects in a column of
rp_group.
anchor_corner
A string attribute that specifies the corner for anchor point specified using attributes x_offset
and y_offset
bbox
A rectangle attribute for the bounding-box of a rp_group. The format of a rectangle
the rectangle.
utilization
A double attribute that specifies the utilization percentage for placement of relative
placement group.
column
An integer attribute that specifies the column position of rp_group.
Chapter 1:
rp_group_attributes
791
1-791
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
columns
An Integer attribute that specifies the number of columns in rp_group.
full_name
A string attribute for the name of rp_group.
group_orient
A string attribute that specifies the orientation of a rp_group.
move_effort
A string attribute for controlling the movement of rp_group.
name
A string attribute for the name of rp_group.
object_class
A string attribute with the value "rp_group".
optimization_restriction
A string attribute for controlling optimization of relative placement cells.
override_alignment
relative placement group in the column of its parent rp_group.
parent_block
A collection attribute with the owner block object for rp_group.
parent_block_cell
A collection attribute with the parent block cell object for rp_group.
parent_cell
A collection attribute with the owner cell object for rp_group.
rp_group_attributes
792
parent_rp_group
A string attribute that specifies the parent rp_group name of rp_group.
pin_name
A string attribute for the name of pin on which the cells of a column of rp_group will be
aligned.
physical_status
A string attribute representing the physical placement status of the relative placement group.
The valid values are unplaced and placed. If status is unplaced, the relative placement
group has not been placed. If relative placement group is failed then also status will be
unplaced. If status is placed, the relative placement group has been placed. This is a not a
settable attribute.
row
An integer attribute that specifies the row position of rp_group.
rows
An Integer attribute that specifies the number of rows in rp_group.
rp_only_keepout_margin
A margin_list attribute consisting of the relative placement only keepout margin values in the
following order : left, bottom, right and top. The format of a margin_list specification is {l b r t}.
tiling_type
A string attribute which specifies the tiling pattern of cells of rp_group.
top_block
A collection attribute with the top block object for rp_group.
top_rp_group
A string attribute that specifies the top rp_group name of rp_group.
Chapter 1:
rp_group_attributes
793
1-793
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
x_offset
An integer attribute that specifies X-coordinate for anchor_corner of rp_group.
y_offset
An integer attribute that specifies Y-coordinate for anchor_corner of rp_group.
SEE ALSO
create_rp_group(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
rp_group_attributes
794
scenario_attributes
Description of the predefined attributes for scenarios.
DESCRIPTION
scenario attributes are provided in the subsections that follow.
command.
Scenario Attributes
active
A boolean attribute that will be true if the scenario is active. If true, the configured analysis
types (if any) will be done. If false, no analysis will be done.
auto_named
A boolean attribute that will be true of the scenario name was automatically generated.
corner
A collection attribute representing the corner of the scenario.
full_name
A string attribute representing the scenario's full name (the same as its name).
hold
A boolean attribute that will be true if the scenario is configured for hold analysis.
Chapter 1:
scenario_attributes
795
1-795
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
max_cap
A boolean attribute that will be true if the scenario is configured for max_capacitance DRC
analysis.
max_tran
A boolean attribute that will be true if the scenario is configured for max_transition DRC
analysis.
min_cap
A boolean attribute that will be true if the scenario is configured for min_capacitance DRC
analysis.
mode
A collection attribute representing the scenario's mode.
name
A string attribute representing the scenaio's name (either user-named or auto-generated).
object_class
A string attribute with the value of "scenario".
power
A boolean attribute that will be true if the scenario is configured for power analysis.
setup
A boolean attribute that will be true if the scenario is configured for setup analysis. All
scenario attributes are read-only, and they will always have valid values.
SEE ALSO
get_attribute(2)
list_attributes(2)
create_scenario(2)
set_scenario_status(2)
get_scenario(2)
report_scenario(2)
scenario_attributes
796
Chapter 1:
scenario_attributes
797
1-797
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
search_path
search_path Shows a list of directory names that contain design and library files that are
specified without directory names.
TYPE
list
DEFAULT
"" (empty)
DESCRIPTION
A list of directory names that specifies directories to be searched for design and library files
that are specified without directory names. Normally, search_path is set to a central library
directory. The default value of search_path is the empty string, "". The read_db and
link_design commands particularly depend on search_path.
You can cause the source command to search for scripts using search_path, by setting the
sh_source_uses_search_path variable to true.
To determine the current value of this variable, type printvar search_path or echo
$search_path.
SEE ALSO
link_design(2)
printvar(2)
read_db(2)
sh_source_uses_search_path(3)
source(2)
search_path
798
sh_allow_tcl_with_set_app_var
Allows the set_app_var and get_app_var commands to work with application variables.
TYPE
string
DEFAULT
DESCRIPTION
Normally the get_app_var and set_app_var commands only work for variables that have
been registered as application variables. Setting this variable to true allows these
commands to set a Tcl global variable instead.
These commands issue a CMD-104 error message for the Tcl global variable, unless the
variable name is included in the list specified by the
sh_allow_tcl_with_set_app_var_no_message_list variable.
SEE ALSO
get_app_var(2)
set_app_var(2)
sh_allow_tcl_with_set_app_var_no_message_list(2)
Chapter 1:
sh_allow_tcl_with_set_app_var
799
1-799
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
sh_allow_tcl_with_set_app_var_no_message_list
Suppresses CMD-104 messages for variables in this list.
TYPE
string
DEFAULT
DESCRIPTION
This variable is consulted before printing the CMD-104 error message, if the
sh_allow_tcl_with_set_app_var variable is set to true. All variables in this Tcl list receive
no message.
SEE ALSO
get_app_var(2)
set_app_var(2)
sh_allow_tcl_with_set_app_var(2)
sh_allow_tcl_with_set_app_var_no_message_list
800
sh_arch
Indicates the system architecture of your machine.
TYPE
string
DEFAULT
platform-dependent
DESCRIPTION
The sh_arch variable is set by the application to indicate the system architecture of your
machine. Examples of machines being used are sparcOS5, amd64, and so on. This variable
is read-only.
Chapter 1:
sh_arch
801
1-801
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
sh_command_abbrev_mode
Sets the command abbreviation mode for interactive convenience.
TYPE
string
DEFAULT
DESCRIPTION
This variable sets the command abbreviation mode as an interactive convenience. Script
files should not use any command or option abbreviation, because these files are then
susceptible to command changes in subsequent versions of the application.
Although the default value is Anywhere, it is recommended that the site startup file for the
application set this variable to Command-Line-Only. It is also possible to set the value to
None, which disables abbreviations altogether.
To determine the current value of this variable, use the get_app_var
sh_command_abbrev_mode command.
SEE ALSO
sh_command_abbrev_options(3)
get_app_var(2)
set_app_var(2)
sh_command_abbrev_mode
802
sh_command_abbrev_options
Turns off abbreviation of command dash option names when false.
TYPE
boolean
DEFAULT
DESCRIPTION
When command abbreviation is currently off (see sh_command_abbrev_mode) then setting
this variable to false will also not allow abbreviation of command dash options. This variable
also impacts abbreviation of the values specified to command options that expect values to
be one of an allowed list of values.
This variable exists to be backward compatible with previous tool releases which always
allowed abbreviation of command dash options and option values regardless of the
command abbreviation mode.
It is recommended to set the value of this variable to false.
sh_command_abbrev_options command.
SEE ALSO
sh_command_abbrev_mode(3)
get_app_var(2)
set_app_var(2)
Chapter 1:
sh_command_abbrev_options
803
1-803
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
sh_command_log_file
Specifies the name of the file to which the application logs the commands you executed
during the session.
TYPE
string
DEFAULT
empty string
DESCRIPTION
This variable specifies the name of the file to which the application logs the commands you
run during the session. By default, the variable is set to an empty string, indicating that the
application's default command log file name is to be be used. If a file named by the default
command log file name cannot be opened (for example, if it has been set to read only
access), then no logging occurs during the session.
This variable can be set at any time. If the value for the log file name is invalid, the variable
is not set, and the current log file persists.
sh_command_log_file command.
SEE ALSO
get_app_var(2)
set_app_var(2)
sh_command_log_file
804
sh_continue_on_error
Allows processing to continue when errors occur during script execution with the source
command.
TYPE
Boolean
DEFAULT
DESCRIPTION
This variable is deprecated. It is recommended to use the -coninue_on_error option to the
source command instead of this variable because that option only applies to a single script,
and not the entire application session.
When set to true, the sh_continue_on_error variable allows processing to continue when
errors occur. Under normal circumstances, when executing a script with the source
command, Tcl errors (syntax and semantic) cause the execution of the script to terminate.
When sh_continue_on_error is set to false, script execution can also terminate due to new
error and warning messages based on the value of the sh_script_stop_severity variable.
To determine the current value of the sh_continue_on_error variable, use the
get_app_var sh_continue_on_error command.
SEE ALSO
get_app_var(2)
set_app_var(2)
source(2)
sh_script_stop_severity(3)
Chapter 1:
sh_continue_on_error
805
1-805
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
sh_deprecated_is_error
Raise a Tcl error when a deprecated command is executed.
TYPE
Boolean
DEFAULT
DESCRIPTION
When set this variable causes a Tcl error to be raised when an deprecated command is
executed. Normally only a warning message is issued.
SEE ALSO
get_app_var(2)
set_app_var(2)
sh_deprecated_is_error
806
sh_dev_null
Indicates the current null device.
TYPE
string
DEFAULT
platform dependent
DESCRIPTION
This variable is set by the application to indicate the current null device. For example, on
UNIX machines, the variable is set to /dev/null. This variable is read-only.
SEE ALSO
get_app_var(2)
Chapter 1:
sh_dev_null
807
1-807
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
sh_enable_page_mode
Displays long reports one page at a time (similar to the UNIX more command.
TYPE
Boolean
DEFAULT
DESCRIPTION
This variable displays long reports one page at a time (similar to the UNIX more command),
when set to true. Consult the man pages for the commands that generate reports to see if
they are affected by this variable.
sh_enable_page_mode command.
SEE ALSO
get_app_var(2)
set_app_var(2)
sh_enable_page_mode
808
sh_enable_stdout_redirect
Allows the redirect command to capture output to the Tcl stdout channel.
TYPE
Boolean
DEFAULT
DESCRIPTION
When set to true, this variable allows the redirect command to capture output sent to the Tcl
stdout channel. By default, the Tcl puts command sends its output to the stdout channel.
SEE ALSO
get_app_var(2)
set_app_var(2)
Chapter 1:
sh_enable_stdout_redirect
809
1-809
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
sh_help_shows_group_overview
Changes the behavior of the "help" command.
TYPE
string
DEFAULT
DESCRIPTION
This variable changes the behavior of the help command when no arguments are specified
to help. Normally when no arguments are specified an informational message with a list of
available command groups is displayed.
When this variable is set to false the command groups and the commands in each group is
printed instead. This variable exists for backward compatibility.
SEE ALSO
help(2)
set_app_var(2)
sh_help_shows_group_overview
810
sh_obsolete_is_error
Raise a Tcl error when an obsolete command is executed.
TYPE
Boolean
DEFAULT
DESCRIPTION
When set this variable causes a Tcl error to be raised when an obsolete command is
executed. Normally only a warning message is issued.
Obsolete commands have no effect.
SEE ALSO
get_app_var(2)
set_app_var(2)
Chapter 1:
sh_obsolete_is_error
811
1-811
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
sh_output_log_file
This variable is used to name the file to record console output. Set the variable to the empty
string to disable output capture.
TYPE
String
DEFAULT
""
DESCRIPTION
This variable can be used to save almost all console output to a log file. The log file is useful
for bug reproduction and reporting.
The first time the variable is set to a valid filename, all previously logged output is written to
the specified file, overwriting any previous contents of the file. All subsequent logged output
is appended to the file unless the variable is later reset.
If the variable is later changed to an empty string, all logged output is disabled.
If the variable is later set to an non-empty string that is an invalid filename, the new value is
ignored and the old value is restored.
If the variable is later set to an non-empty string that is an valid filename, all subsequent
logged output is written to this file. Any previous contents of the file are overwritten.
The log file may not capture the banner text from the beginning of the session, and does not
capture the stack trace that is printed following a fatal error. You can use the UNIX tee
command or redirect the output to capture this information.
This variable is not available in de_shell mode.
SEE ALSO
printvar(2)
sh_output_log_file
812
sh_product_version
Indicates the version of the application currently running.
TYPE
string
DESCRIPTION
This variable is set to the version of the application currently running. The variable is read
only.
To determine the current value of this variable, use the get_app_var sh_product_version
command.
SEE ALSO
get_app_var(2)
Chapter 1:
sh_product_version
813
1-813
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
sh_script_stop_severity
Indicates the error message severity level that would cause a script to stop running before it
completes.
TYPE
string
DEFAULT
DESCRIPTION
When a script is run with the source command, there are several ways to get it to stop
running before it completes. One is to use the sh_script_stop_severity variable. This
variable can be set to none, W, or E.
When set to E, the generation of one or more error messages by a command causes a
script to stop.
When set to W, the generation of one or more warning or error messages causes a script
to stop.
Note that sh_script_stop_severity is ignored if sh_continue_on_error is set to true.

sh_script_stop_severity command.
SEE ALSO
get_app_var(2)
set_app_var(2)
source(2)
sh_continue_on_error(3)
sh_script_stop_severity
814
sh_source_emits_line_numbers
Indicates the error message severity level that causes an informational message to be
issued, listing the script name and line number where that message occurred.
TYPE
string
DEFAULT
DESCRIPTION
When a script is executed with the source command, error and warning messages can be
emitted from any command within the script. Using the sh_source_emits_line_numbers
variable, you can help isolate where errors and warnings are occurring.
This variable can be set to none, W, or E.
When set to E, the generation of one or more error messages by a command causes a
CMD-082 informational message to be issued when the command completes, giving the
name of the script and the line number of the command.
When set to W, the generation of one or more warning or error messages causes a the
CMD-082 message.
The setting of sh_script_stop_severity affects the output of the CMD-082 message. If the
setting of sh_script_stop_severity causes a CMD-081 message, then it takes precedence
over CMD-082.
sh_source_emits_line_numbers command.
SEE ALSO
get_app_var(2)
set_app_var(2)
source(2)
sh_continue_on_error(3)
sh_script_stop_severity(3)
Chapter 1:
815
1-815
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
CMD-081(n)
CMD-082(n)
816
sh_source_logging
Indicates if individual commands from a sourced script should be logged to the command
log file.
TYPE
Boolean
DEFAULT
DESCRIPTION
When you source a script, the source command is echoed to the command log file. By
default, each command in the script is logged to the command log file as a comment. You
can disable this logging by setting sh_source_logging to false.
To determine the current value of this variable, use the get_app_var sh_source_logging
command.
SEE ALSO
get_app_var(2)
set_app_var(2)
source(2)
Chapter 1:
sh_source_logging
817
1-817
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
sh_source_uses_search_path
Indicates if the source command uses the search_path variable to search for files.
TYPE
Boolean
DEFAULT
DESCRIPTION
When this variable is set to \ftrue the source command uses the search_path variable to
search for files. When set to false, the source command considers its file argument literally.
sh_source_uses_search_path command.
SEE ALSO
get_app_var(2)
set_app_var(2)
source(2)
search_path(3)
sh_source_uses_search_path
818
sh_tcllib_app_dirname
Indicates the name of a directory where application-specific Tcl files are found.
TYPE
string
DESCRIPTION
The sh_tcllib_app_dirname variable is set by the application to indicate the directory
where application-specific Tcl files and packages are found. This is a read-only variable.
SEE ALSO
get_app_var(2)
Chapter 1:
sh_tcllib_app_dirname
819
1-819
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
sh_user_man_path
Indicates a directory root where you can store man pages for display with the man
command.
TYPE
list
DEFAULT
empty list
DESCRIPTION
The sh_user_man_path variable is used to indicate a directory root where you can store
man pages for display with the man command. The directory structure must start with a
directory named man. Below man are directories named cat1, cat2, cat3, and so on. The
man command will look in these directories for files named file.1, file.2, and file.3,
respectively. These are pre-formatted files. It is up to you to format the files. The man
command effectively just types the file.
These man pages could be for your Tcl procedures. The combination of defining help for
your Tcl procedures with the define_proc_attributes command, and keeping a manual
page for the same procedures allows you to fully document your application extensions.
The man command will look in sh_user_man_path after first looking in application-defined
paths. The user-defined paths are consulted only if no matches are found in the
application-defined paths.
To determine the current value of this variable, use the get_app_var sh_user_man_path
command.
SEE ALSO
define_proc_attributes(2)
get_app_var(2)
man(2)
set_app_var(2)
sh_user_man_path
820
shape_attributes
Description of the predefined attributes for shapes.
DESCRIPTION
shape attributes are provided in the subsections that follow.
command.
Shape Attributes
access_direction
A list attribute representing the accessible directions on the shape's pin.
bbox
A rectangle attribute for the bounding-box of a shape. The format of a rectangle specification
is {{llx lly} {urx ury}}, which specifies the lower-left and upper-right corners of the rectangle.
design_name
A string attribute specifying the name of the design which owns the shape.
end_endcap
A string attribute specifying the style of the end endcap of the shape. This attribute only
applies to shapes with shape_type "path".
end_extension
A distance attribute specifying the distance the shape extends past its end endpoint. This
attribute only applies to shapes with shape_type "path".
Chapter 1:
shape_attributes
821
1-821
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
full_name
A string attribute for the name of the shape.
height
A distance attribute specifying the height of the shape. This attribute only applies to shapes
with shape_type "text".
in_edit_group
A boolean attribute indicating whether the shape belongs to an edit group.
is_45
A boolean attribute indicating whether the shape has one or more edges at a 45 degree
angle from an axis, but no edges that aren't at horizontal, vertical, or 45 degree angles.
is_manhattan
A boolean attribute indicating whether the shape has edges that are exclusively at horizontal
or vertical angles.
is_mask_fixed
A boolean attribute indicating whether the mask of the shape is fixed.
is_shadow
A boolean attribute to specify whether the shape is pushed down from above.
justification
A string attribute specifying the justification of the text string corresponding to the shape.
This attribute only applies to shapes with shape_type "text".
layer
A collection attribute with the layer on which the shape exists.
layer_name
A string attribute for the name of the layer on which the shape exists.
shape_attributes
822
layer_number
An integer attribute for the number of the layer on which the shape exists.
length
A distance attribute specifying the length of the shape. This attribute only applies to shapes
with shape_type "path".
mask_constraint
A string attribute representing the multi-patterning mask_constraint of the shape.
name
A string attribute representing the name of the shape.
net_type
The net type of the net which owns the shape.
number_of_points
An integer attribute for the number of points of the shape.
object_class
A string attribute with the value of "shape".
object_id
An integer attribute specifying the I.D. number of the shape object.
orientation
A coordinate attribute representing the orientation of the shape.
origin
A coordinate attribute representing the origin of the shape.
owner
A collection attribute with the terminal or net which owns the shape.
Chapter 1:
shape_attributes
823
1-823
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
parent_block
A collection attribute with the owner block object for this shape.
parent_block_cell
A collection attribute with the parent block cell object for this shape.
parent_cell
A collection attribute with the owner cell object for this shape.
physical_status
A string attribute representing the physical modification status of the shape. Valid values are
unrestricted, application_fixed, fixed, and locked. If status is unrestricted, the shape may be
freely modified. If the status is application_fixed, the shape is fixed by the application for
automatic changes (the application may change this status). If status is fixed, the shape is
fixed by the user for automatic changes. If status is locked, the shape is fixed for automatic
and manual changes. This is a settable attribute.
points
A coordinate list attribute for the points of the shape. The format of coordinate list
specification is {{x1 y1} {x2 y2} ...}, which specifies a list of points defining the boundary of
the shape, or the centerline of the shape in the case where shape_type is "path".
purpose
An integer attribute representing the purpose number of the shape.
shadow_status
A string attribute to represent the shadow status of the shape. Valid values are
copied_down, copied_up, normal, pulled_up, and pushed_down.
shape_type
A string attribute representing the type of the shape, for example "rect", "polygon", "path",
"text", etc.
shape_use
A string attribute representing the shape use.
shape_attributes
824
start_endcap
A string attribute specifying the style of the start endcap of the shape. This attribute only
applies to shapes with shape_type "path".
start_extension
A distance attribute specifying the distance the shape extends past its start endpoint. This
attribute only applies to shapes with shape_type "path".
text
A string attribute representing the text string corresponding to the shape. This attribute only
applies to shapes with shape_type "text".
top_block
A collection attribute with the top block object for this shape.
width
A distance attribute specifying the width of the shape. This attribute only applies to shapes
with shape_type "path".
is_via_ladder
A bool attribute specifying whether shape is part of a via ladder. This is not a settable
attribute.
SEE ALSO
create_shape(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
shape_attributes
825
1-825
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
shaping_blockage_attributes
Lists the predefined attributes for shaping_blockages.
DESCRIPTION
shaping_blockage attributes are provided in the subsections that follow.
Attributes are read-only unless marked as settable. A read-only attributes is informational,
command.
Shaping Blockage Attributes
area
A float attribute for the area of the shaping_blockage.
bbox
A rectangle attribute for the bounding-box of the shaping_blockage. The format of a
blockage_purpose
A string attribute indicating the purpose of the placement_blockage. Valid values are system
and user. This attribute is settable.
boundary
A coordinate_list attribute for the boundary of the shaping_blockage. The format of a
full_name
A string attribute for the name of the shaping_blockage.
826
is_shadow
A boolean attribute to specify whether the shaping_blockage is pushed down from above.
name
A string attribute for the name of the shaping_blockage. This attribute is settable.
object_class
A string attribute with the value of "shaping_blockage".
parent_block
A collection attribute with the owner block object for this shaping_blockage.
parent_block_cell
A collection attribute with the parent block cell object for this shaping_blockage.
parent_cell
A collection attribute with the owner cell object for this shaping_blockage.
physical_status
A string attribute representing the physical modification status of the shaping_blockage. If
status is unrestricted, the shaping_blockage may be moved or rotated. If the status is
locked, the shaping_blockage may not be moved or rotated. This is a settable attribute.
shadow_status
A string attribute to represent the shadow status of the shaping_blockage. Valid values are
is settable.
top_block
A collection attribute with the top block object for this shaping_blockage.
Chapter 1:
827
1-827
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_attribute(2)
list_attributes(2)
828
shell.common.collection_result_display_limit
Sets the maximum number of objects that can be displayed by any command that displays
a collection.
TYPE
int
DEFAULT
100
DESCRIPTION
This application option sets the maximum number of objects that can be displayed by any
command that displays a collection. The default is 100.
When a command (for example, add_to_collection) is issued at the command prompt, its
result is implicitly queried, as though query_objects had been called. You can limit the
number of objects displayed by setting this application option to an appropriate integer. A
value of -1 displays all objects; a value of 0 displays the collection handle id instead of the
names of any objects in the collection.
To determine the current value of this application option, use get_app_option_value
-name shell.common.collection_result_display_limit.
SEE ALSO
collections(2)
query_objects(2)
set_app_options(2)
Chapter 1:
shell.common.collection_result_display_limit
829
1-829
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
shell.common.copyright_year
The copyright year for the application. (Read-Only)
TYPE
string
DEFAULT
not applicable
DESCRIPTION
This application exposes the copyright year of the application to the interpreter. It is a
read-only value.
-name shell.common.copyright_year.
SEE ALSO
set_app_options(2)
shell.common.copyright_year
830
shell.common.enable_line_editing
Enables the command line editing capabilities.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
If set to true it enables advanced unix like shell capabilities.
This application option needs to be set in .synopsys_icc2.setup file to take effect.
Key Bindings
The list_key_bindings command displays current key bindings and the edit mode. To
change the edit mode, application option shell.common.line_editing_mode can be set in
either the .synopsys_icc2.setup file or directly in the shell.
Command Completion
The editor will be able to complete commands, options, variables and files given a unique
abbreviation. User need to type part of a word and hit the tab key to get the complete
command, variable or file. For command options, users need to type '-' and hit tab key to get
the options list.
If no match is found, the terminal bell rings. If the word is already complete a space is added
to the end, if it isn't already there, to speed typing and provide a visual indicator of successful
completion. Completed text pushes the rest of the line to the right. If there are multiple
matches then all the matching commands/options/files or variables are autolisted.
Completion works in following context sensitive way :The first token of a command line : completes commands
Token that begins with "-" after a command : completes command arguments
After a ">", "|" or a "sh" command : completes filenames
After a set, unset or printvar command : completes the variables
Chapter 1:
831
1-831
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
After '$' symbol : completes the variables

After the help command : completes command
After the man command : completes commands or variables
Any token which is not the first token and doesn't match any of the above rules : completes
filenames
SEE ALSO
shell.common.line_editing_mode(3)
list_key_bindings(2)
832
shell.common.line_editing_mode
Enables vi or emacs editing mode in the tool's shell.
TYPE
String
DEFAULT
emacs
DESCRIPTION
This application option can be used to set the command line editor mode to either vi or
emacs. Valid values are emacs or vi.
Use list_key_bindings command to display the current key bindings and edit mode.
This application option can be set in the either .synopsys_icc2.setup file or directly in the
shell. The shell.common.enable_line_editing application option must be set to true.
SEE ALSO
shell.common.enable_line_editing(3)
list_key_bindings(2)
Chapter 1:
shell.common.line_editing_mode
833
1-833
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
shell.common.product_abbreviation
The product abbreviation for the application. (Read-Only)
TYPE
string
DEFAULT
not applicable
DESCRIPTION
This application exposes the product abbreviation of the application to the interpreter. The
abbreviation is a short string without spaces or punctuation that is used in the generation of
the names of shared setup files. It is a read-only value.
-name shell.common.product_abbreviation.
SEE ALSO
set_app_options(2)
shell.common.product_abbreviation
834
shell.common.product_name
The product name for the application. (Read-Only)
TYPE
string
DEFAULT
not applicable
DESCRIPTION
This application exposes the product name of the application to the interpreter. It is a
read-only value.
-name shell.common.product_name.
SEE ALSO
set_app_options(2)
Chapter 1:
shell.common.product_name
835
1-835
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
shell.common.product_version
The product version for the application. (Read-Only)
TYPE
string
DEFAULT
not applicable
DESCRIPTION
This application exposes the version of the application to the interpreter. It is a read-only
value.
-name shell.common.product_version.
SEE ALSO
set_app_options(2)
shell.common.product_version
836
shell.common.report_default_significant_digits
The default number of significant digits used to display values in reports.
TYPE
int
DEFAULT
2
DESCRIPTION
Sets the default number of significant digits for many reports. Allowed values are 0-13; the
default is 2. Most report commands have a -significant_digits option that overrides the
value of this application option.
Not all reports respond to this application option. Check the man page of individual reports
to determine whether they support this feature.
To determine the current value of this application option, use this command:
get_app_option_value -name shell.common.report_default_significant_digits
SEE ALSO
Chapter 1:
shell.common.report_default_significant_digits
837
1-837
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
shell.common.shell_name
The shell name for the application. (Read-Only)
TYPE
string
DEFAULT
not applicable
DESCRIPTION
This application exposes the shell name of the application to the interpreter. The shell name
is used in the prompt and setup files to denote the values that are specific to this particular
executable of the product. It is a read-only value.
-name shell.common.shell_name.
SEE ALSO
set_app_options(2)
shell.common.shell_name
838
shell.common.single_line_messages
When set to true, Error, Warning, and Information messages which contain newlines are
written without newlines.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
-name shell.common.single_line_messages.
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
shell.common.single_line_messages
839
1-839
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
shell.common.tmp_dir_path
Sets the directory that the tool uses for temporary storage.
TYPE
string
DEFAULT
/tmp (the local /tmp partition)
DESCRIPTION
Specifies a directory for the tool to use as temporary storage. By default, the value is "/tmp".
You can set this application option to any directory with proper read/write permissions, such
as ".", the current directory.
-name shell.common.tmp_dir_path.
SEE ALSO
set_app_options(2)
shell.common.tmp_dir_path
840
signoff.antenna.contact_layer
Option to specify contact layer for antenna property extraction flow.
TYPE
string
DEFAULT
Empty.
DESCRIPTION
If you do not specify this option, the tool tries to get the contact layer from the technology file.
If the technology file does not have the mask name set for conatct layer, the user needs to
pass the contact layer from command line to successfully run the flow.
This option also supports the boolean NOT operation. If it is required to derive contact layer
from more than one layers using OR/NOT operation, then it could be passed using logical
unary NOT operator.
EXAMPLES
The following example sets the contact layer as layer number 30 in the design in antenna
property extraction during library creation:
prompt> set_app_options -name signoff.antenna.contact_layer -value 30
The following example sets the contact layer as NOT of layer number 30 and layer number
30:1 in the design in antenna property extraction during library creation:
prompt> set_app_options -name signoff.antenna.contact_layer -value { {30}
!{30:1} }
Chapter 1:
841
1-841
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
842
signoff.antenna.contact_layers_between_m0_diffusion
Specifies the contact layers (contact layers are the layers that connect metal0 to diffusion).
You can specify the layers by using the layer names from the technology file.
TYPE
string
DEFAULT
Empty.
DESCRIPTION
Specifies the contact layers (contact layers are the layers that connect metal0 to diffusion).
You can specify the layers by using the layer names from the technology file.
The contact_layers_between_m0_diffusion and contact_layers options are mutually
exclusive; you can specify only one.
EXAMPLES
The following example sets the contact_layers_between_m0_diffusion as layer number 28
in antenna property extraction during library creation:
signoff.antenna.contact_layers_between_m0_diffusion\
-value 28
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
Chapter 1:
signoff.antenna.contact_layers_between_m0_diffusion
843
1-843
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.antenna.custom_runset_file
Option to specify custom runset file in case of advanced gate layers.
TYPE
string
DEFAULT
Empty.
DESCRIPTION
The custom runset file is passed when the metal layers are derived from boolean operations
of more than layers. For instance, at advanced nodes, METAL1 layers can be derived from
CUT layers. In those cases, this option could be used to pass the custom runset file that
would be included as a part of main runset in antenna flow.
The custom runset follows syntax of standard ICV runset and would contain first assign
section and then boolean operation in a sequential order.
EXAMPLES
The following example pass the custom runset include file in antenna property extraction
during library creation:
prompt> set_app_options -name signoff.antenna.custom_runset_file -value
custom.rs
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
signoff.antenna.custom_runset_file
844
signoff.antenna.diffusion_layer
Option to specify diffusion layer for antenna property extraction flow.
TYPE
string
DEFAULT
Empty.
DESCRIPTION
If you do not specify this option, the tool tries to get the diffusion layer from the technology
file. If the technology file does not have the mask name set for diffusion layer, the user needs
to pass the diffusion layer from command line to successfully run the flow.
This option also supports the boolean NOT operation. If it is required to derive diffusion layer
unary NOT operator.
EXAMPLES
The following example sets the diffusion layer as layer number 6 in the design in antenna
prompt> set_app_options -name signoff.antenna.diffusion_layer -value 6
The following example sets the diffusion layer as NOT of layer number 6 and layer number
2 in the design in antenna property extraction during library creation:
prompt> set_app_options -name signoff.antenna.diffusion_layer -value {
{6} !{2} }
Chapter 1:
845
1-845
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
846
signoff.antenna.enabled
Option to run antenna property extraction flow during check_workspace command. Enable
the antenna property extraction flow.
TYPE
boolean
DEFAULT
false
DESCRIPTION
If you do not specify this option, the tool does not extract the antenna properties during
library creation.
EXAMPLES
The following example runs the antenna property extraction flow during check_workspace.
prompt> set_app_options -name signoff.antenna.enabled -value true
prompt> check_workspace
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
Chapter 1:
signoff.antenna.enabled
847
1-847
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.antenna.extract_via_antenna_property
Specifies whether to extract antenna properties for via layers. This option is used during
antenna extraction.
TYPE
bool
DEFAULT
false
DESCRIPTION
This application option specifies whether to extract antenna properties for via layers. By
default, this option is false and the flow extracts antenna properties only for metal layers.
EXAMPLES
The following example sets the extract via antenna prop to true.
prompt> set_app_options -list
{signoff.antenna.extract_via_antenna_property {true}}
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
signoff.antenna.extract_via_antenna_property
848
signoff.antenna.gate_class1_layers
Specifies the marking layers for gate thickness class 1. You can specify the layers by using
the layer names from the technology file.
TYPE
string
DEFAULT
Empty.
DESCRIPTION
EXAMPLES
The following example sets the gate 1 layer as layer number 3 in antenna property
extraction during library creation:
prompt> set_app_options -name signoff.antenna.gate_class1_layers -value 3
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
Chapter 1:
849
1-849
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
TYPE
string
DEFAULT
Empty.
DESCRIPTION
EXAMPLES
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
850
TYPE
string
DEFAULT
Empty.
DESCRIPTION
EXAMPLES
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
Chapter 1:
851
1-851
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.antenna.hierarchical_gate_class_include_file
Specifies the location of gate class include file in case of advanced gate class marker layers.
TYPE
string
DEFAULT
null
DESCRIPTION
The \"hier_gate_class_include_file\" app option gives the file name of a valid, partial ICV
runset to be used for identifying the marking layers. The runset should have the following
syntax. The example shows a complex relationship between four different marking layers.
The intermediate layer names ??OD1?? through ??OD4?? can be named differently. If you
don??t need all three marking layers, you ca- n define only the GATES1 or GATES2 TEMP
layers, and set the max_ga- te_class_name variable accordingly.
The \"signoff.antenna.hierarchical_gate_class_include_file\" option gives the file name of a
valid, partial ICV runset to be used for identifying the marking layers. The runset should have
the following syntax. The example shows a complex relationship between four different
marking layers. The intermediate layer names \"OD1\" through \"OD4\" can be named
differently.
If you don??t need all three marking layers, you can define only the GATES1 or GATES2
layers, and set the \"signoff.antenna.max_gate_class_name\" variable accordingly.
Specifies the maximum gate class name when the gate class layers are passed through
custom runset. This option is necessary to specify when
\"signoff.antenna.hier_gate_class_include_file\" is passed.
EXAMPLES
The following example sets the gate class include file as complex_gates.rs.
prompt> set_app_options -name signoff.antenna.hier_gate_class_includefile -value complex_gates.rs
852
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
Chapter 1:
853
1-853
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.antenna.m0_layers_for_diffusion_connection
Specifies the m0 layers for diffusion connection. You can specify the layers by using the
layer names from the technology file.
TYPE
string
DEFAULT
Empty.
DESCRIPTION
Specifies the m0 layers for diffusion connection. You can specify the layers by using the
layer names from the technology file.
The m0_layers_for_diffusion_connection and contact_layers options are mutually
EXAMPLES
The following example sets the poly layer as layer name M0_OD in antenna property
signoff.antenna.m0_layers_for_diffusion_connection \
-value M0_OD
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
signoff.antenna.m0_layers_for_diffusion_connection
854
signoff.antenna.m0_layers_for_poly_connection
Specifies the m0 layers for poly connection. You can specify the layers by using the layer
names from the technology file.
TYPE
string
DEFAULT
Empty.
DESCRIPTION
Specifies the m0 layers for poly connection. You can specify the layers by using the layer
names from the technology file.
The m0_layers_for_poly_connection and contact_layers options are mutually exclusive;
you can specify only one.
EXAMPLES
The following example sets the m0_layers_for_poly_connection layer as layer number 19 in
antenna property extraction during library creation:
signoff.antenna.m0_layers_for_poly_connection -value 19
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
Chapter 1:
signoff.antenna.m0_layers_for_poly_connection
855
1-855
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.antenna.max_gate_class_name
custom runset.
TYPE
string
DEFAULT
null
DESCRIPTION
custom runset. This option is necessary to specify when
signoff.antenna.hier_gate_class_include_file is passed.
If the marking layers have a more complex structure than a simple OR relationship, you can
provide a partial ICV runset. To do so, you need to define the
\"signoff.antenna.max_gate_class_name\" and
\"signoff.antenna.hierarchical_gate_class_include_file\" app options.
The \"signoff.antenna.max_gate_class_name\" options tells ICV how many gate class
definitions to expect and must have one of the following values: GATES1, GATES2, or
GATES3.
EXAMPLES
The following example sets the max gate class name as GATES1.
prompt> set_app_options -name signoff.antenna.max_gates_class_name -value
GATES1
SEE ALSO
get_app_options(2)
856
set_app_options(2)
check_workspace(2)
Chapter 1:
857
1-857
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.antenna.poly_layer
Option to specify poly layer for antenna property extraction flow.
TYPE
string
DEFAULT
Empty.
DESCRIPTION
If you do not specify this option, the tool tries to get the poly layer from the technology file. If
the technology file does not have the mask name set for poly layer, the user needs to pass
the poly layer from command line to successfully run the flow.
This option also supports the boolean NOT operation. If it is required to derive poly layer
unary NOT operator.
EXAMPLES
The following example sets the poly layer as layer number 17 in the design in antenna
prompt> set_app_options -name signoff.antenna.poly_layer -value 17
The following example sets the poly layer as NOT of layer number 17 and layer number 17:1
in the design in antenna property extraction during library creation:
prompt> set_app_options -name signoff.antenna.poly_layer -value { {17}
!{17:1} }
858
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
Chapter 1:
859
1-859
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.antenna.report_diodes
Controls whether the tool reports the location of generated protection diodes.
TYPE
bool
DEFAULT
true
DESCRIPTION
Controls whether the tool reports the location of generated protection diodes.
The default is true.
EXAMPLES
The following example sets the report_diodes option to false in antenna property extraction
during library creation:
prompt> set_app_options -name signoff.antenna.report_diodes -value false
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
signoff.antenna.report_diodes
860
signoff.antenna.top_cell_pin_only
Controls whether the tool extracts hierarchical antenna properties only for nets that connect
to pins in the top-level of the hard macro.
TYPE
bool
DEFAULT
true
DESCRIPTION
Controls whether the tool extracts hierarchical antenna properties only for nets that connect
to pins in the top-level of the hard macro.
If you set this option to false, the command extracts hierarchical antenna properties for nets
that connect to pins in the top-level of the hard macro, as well as to pins in the child cells
contained within the hard macro.
EXAMPLES
The following example sets the top_cell_pin_only option to true in antenna property
prompt> set_app_options -name signoff.antenna.top_cell_pin_only -value
false
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
861
1-861
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
check_workspace(2)
862
signoff.antenna.treat_source_drain_as_diodes
Controls whether the tool treats the MOS source and drain as protection diodes and
considers any MOS source and drain regions that are connected to a net to be a part of the
diode protection area available to that net.
TYPE
bool
DEFAULT
true
DESCRIPTION
Controls whether the tool treats the MOS source and drain as protection diodes and
considers any MOS source and drain regions that are connected to a net to be a part of the
diode protection area available to that net.
EXAMPLES
The following example sets the treat_source_drain_as_diodes option to false in antenna
signoff.antenna.treat_source_drain_as_diodes -value false
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
Chapter 1:
signoff.antenna.treat_source_drain_as_diodes
863
1-863
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.antenna.user_defined_options
Option for the antenna flow. Specifies strings as part of IC Validator command line options.
TYPE
string
DEFAULT
null
DESCRIPTION
This application option specifies additional options for the IC Validator command line. The
string that you specify is added to the command line used to invoke design rule checking in
IC Validator. IC Compiler II does not perform any checking on the specified string.
By default, no user-defined options are included.
EXAMPLES
The following example specifies the user-defined options named -turbo.
"signoff.calculate_hier_antenna_property.user_defined_options" -value
"-turbo"}
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
signoff.antenna.user_defined_options
864
signoff.antenna.v0_layers_between_m1_m0
Specifies the v0 layers (v0 layers are the layers that connect metal1 to metal0). You can
specify the layers by using the layer names from the technology file.
TYPE
string
DEFAULT
Empty.
DESCRIPTION
Specifies the v0 layers (v0 layers are the layers that connect metal1 to metal0). You can
specify the layers by using the layer names from the technology file.
The options v0_layers_between_m1_m0 and contact_layers options are mutually
EXAMPLES
The following example sets the v0_layers_between_m1_m0 as layer number 50 in antenna
prompt> set_app_options -name signoff.antenna.v0_layers_between_m1_m0
-value 50
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
Chapter 1:
signoff.antenna.v0_layers_between_m1_m0
865
1-865
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.calculate_hier_antenna_property.extract_via_antenna_pr
op
Option for the signoff_calculate_hier_antenna_property command. Specifies to extract
the antenna properties for via layers.
TYPE
bool
DEFAULT
false
DESCRIPTION
This application option specifies to extract the antenna properties for via layers as well. By
default, it is set to false and the flow extracts the antenna properties only for metal layers.
EXAMPLES
The following example sets the extract via antenna prop to true.
{signoff.calculate_hier_antenna_property.extract_via_antenna_prop "true"}
prompt> signoff_calculate_hier_antenna_property
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_calculate_hier_antenna_property(2)
signoff.calculate_hier_antenna_property.extract_via_antenna_prop
866
signoff.calculate_hier_antenna_property.user_defined_options
Option for the signoff_calculate_hier_antenna_property command. Specifies strings as
part of IC Validator command line options.
TYPE
string
DEFAULT
null
DESCRIPTION
EXAMPLES
{signoff.calculate_hier_antenna_property.user_defined_options "-turbo"}
prompt> signoff_calculate_hier_antenna_property
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_calculate_hier_antenna_property(2)
Chapter 1:
signoff.calculate_hier_antenna_property.user_defined_options
867
1-867
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.check_design.generate_runset_only
Option for the signoff_check_design command. Specifies whether to generate only runset
or generate runset and run IC Validator with generated runset. By default, it generates the
runset and runs IC Validator with the runset.
TYPE
bool
DEFAULT
false
DESCRIPTION
When it is set as true, only the runset is generated. When it is set as false, runset is
generated and IC Validator is run with the runset.
EXAMPLES
The following example generates only the runset for the signoff_check_design command.
{signoff.check_design.generate_runset_only true}
prompt> signoff_check_design
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_check_design(2)
signoff.check_design.generate_runset_only
868
signoff.check_design.max_errors_per_rule
Option for the signoff_check_design command. Specifies the maximum number of errors
per rule for the IC Validator run.
TYPE
integer
DEFAULT
Max Integer limit
DESCRIPTION
This application option specifies the maximum number of errors per rule for the IC Validator
run. The value must be greater than or equal to 1. The default value is max integer limit.
EXAMPLES
The following example runs IC Validator for design rule checking and sets the maximum
number of errors per rule to 8000.
prompt> set_app_options -global {signoff.check_design.max_errors_per_rule
8000}
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
signoff.check_design.max_errors_per_rule
869
1-869
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.check_design.run_dir
Option for the signoff_check_design command. Specifies the path of working directory.
TYPE
string
DEFAULT
signoff_check_design_run
DESCRIPTION
If you do not specify this option, the tool uses a directory called signoff_check_design_run
under the current working directory. The path can be either relative or absolute.
EXAMPLES
The following example runs IC Validator under the working directory named
my_signoff_run.
prompt> set_app_options -global {signoff.check_design.run_dir
"my_signoff_run"}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff.check_design.run_dir
870
signoff.check_design.runset
Option for the signoff_check_design command. Specifies the runset to use for
signoff_check_design utilities such as to check the shorts between signal and metal fill
shapes. By default, the tool generates the runset on the fly.
TYPE
string
DEFAULT
null
DESCRIPTION
The runset will be used while tool invokes IC Validator for checking violations related to
shorts and other specific checks.
EXAMPLES
The following example specifies the runset drc.rs for the signoff_check_design
command.
prompt> set_app_options -global {signoff.check_design.runset "drc.rs"}
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
signoff.check_design.runset
871
1-871
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.check_design.user_defined_options
Option for the signoff_check_design command. Specifies strings as part of IC Validator
command line options.
TYPE
string
DEFAULT
null
DESCRIPTION
EXAMPLES
{signoff.check_design.user_defined_options "-turbo"}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff.check_design.user_defined_options
872
signoff.check_drc.always_read_fill
Option for the signoff_check_drc command. Reads FILL data even though its timestamp
is older than timestamp of design view.
TYPE
bool
DEFAULT
false
DESCRIPTION
If true, the command reads FILL data even though its timestamp is older than timestamp of
design view.
By default (false), the FILL data is read only when its timestamp is newer than the timestamp
of design view.
EXAMPLES
The following example reads the FILL data even though its timestamp is older than the
timestamp of the design view.
prompt> set_app_options -name signoff.check_drc.always_read_fill -value
true
prompt> signoff_check_drc
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_check_drc(2)
Chapter 1:
signoff.check_drc.always_read_fill
873
1-873
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.check_drc.auto_eco_threshold_value
Option for the signoff_check_drc command. Specifies the threshold for allowed change in
design s.t incremental drc can be run. Default: 20%.
TYPE
integer
DEFAULT
20
DESCRIPTION
This application option specifies the threshold for allowed change in design s.t incremental
drc can be run. The default value is 20.
EXAMPLES
The following example runs incremental drc by setting a max allowed diff percent to 30.
prompt> set_app_options -name signoff.check_drc.auto_eco_threshold_value
-value 30
prompt> signoff_check_drc -auto_eco true
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff.check_drc.auto_eco_threshold_value
874
signoff.check_drc.excluded_cell_types
Option for the signoff_check_drc command. Specifies a list of the cell types to exclude
from design rule checking. Cell types include {lib_cell, macro, pad, filler}.
TYPE
list_of_cell_types
DEFAULT
null
DESCRIPTION
This application option specifies the cell types to exclude from design rule checking. You
can specify a list of one or more cell types. The valid values for cell type are lib_cell, macro,
pad, and filler. These cell types are defined as follows:
lib_cell is for standard cells
macro is for macro cells
pad is for I/O pad cells
filler is for filler cells
By default, all cell types are checked (no cell types are excluded).
EXAMPLES
The following example excludes standard cells and macro cells from design rule checking.
prompt> set_app_options -name signoff.check_drc.excluded_cell_types
-value {lib_cell macro}
SEE ALSO
get_app_options(2)
Chapter 1:
875
1-875
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
set_app_options(2)
876
signoff.check_drc.ignore_blockages_in_cells
Option for the signoff_check_drc command. Controls whether blockages in macros are
read during the signoff_check_drc command.
TYPE
bool
DEFAULT
true
DESCRIPTION
If set to true (default), the blockages from the FRAME view of macros will not be read. Only
the pins will be read. The design views of standard library cells will be read.
If set to false, the blockages from the FRAME view of macros and standard library cells will
be read along with the pins.
EXAMPLES
The following example runs design rule checking, which attempts to read the cell instance
data for all library cells from the design view and only the pins from the FRAME view of the
macros.
prompt> set_app_options -name signoff.check_drc.ignore_blockages_in_cells
-value true
data for the M1 macro from the design view. If the design view for this macro cannot be
found the FRAME view is used. The cell instance data for all other macros and standard
library cells will read the FRAME view with blockages and pins. for all other library cells is
read from the design view.
prompt> set_app_options -name signoff.check_drc.read_design_views -value
{M1}
prompt> set_app_options -name signoff.check_drc.ignore_blockages_in_cells
-value false
Chapter 1:
877
1-877
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_app_options(2)
set_app_options(2)
878
signoff.check_drc.ignore_child_cell_errors
Option for the signoff_check_drc command. Skips the DRC violations inside all cell
instances (reference libraries).
TYPE
bool
DEFAULT
false
DESCRIPTION
If true, the command skips the DRC violations inside all cell instances (reference libraries).
By default (false), DRC violations inside cell instances are reported.
EXAMPLES
The following example skips the DRC violations inside all cell instances (reference libraries).
prompt> set_app_options -name signoff.check_drc.ignore_child_cell_errors
-value true
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
signoff.check_drc.ignore_child_cell_errors
879
1-879
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.check_drc.max_errors_per_rule
Option for the signoff_check_drc command. Specifies the maximum number of errors per
rule for the IC Validator run.
TYPE
integer
DEFAULT
1000
DESCRIPTION
run. The value must be greater than or equal to 1. The default value is 1000.
EXAMPLES
prompt> set_app_options -name signoff.check_drc.max_errors_per_rule
-value 8000
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff.check_drc.max_errors_per_rule
880
signoff.check_drc.merge_base_error_name
Option for the signoff_check_drc command. Specifies the name of the error data used to
merge when signoff_check_drc -auto_eco is used and
signoff.check_drc.merge_incremental_error_data is set to true. Default:
signoff_check_drc.err.
TYPE
string
DEFAULT
signoff_check_drc.err
DESCRIPTION
This application option specifies the name of the error data used as a base to merge when
signoff_check_drc -auto_eco is used to specify an incremental DRC run and the
signoff.check_drc.merge_incremental_error_data is set to true. Normally there is no need to
set this application option but it is required when the previous full DRC run was run with the
signoff_check_drc -error_data option set. The default value is signoff_check_drc.err.
EXAMPLES
The following example runs incremental drc and merges the result with a previous error data
called "pre_eco_drc.err".
signoff.check_drc.merge_incremental_error_data -value true
prompt> set_app_options -name signoff.check_drc.merge_base_error_name
-value "pre_eco_drc.err"
SEE ALSO
get_app_options(2)
Chapter 1:
881
1-881
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
set_app_options(2)
882
signoff.check_drc.merge_incremental_error_data
Option for the signoff_check_drc command. Specifies the whether the signoff_check_drc
-auto_eco true command should merge incremental error data with the result of a previous
signoff_check_drc result. Default: false.
TYPE
boolean
DEFAULT
false
DESCRIPTION
This application option specifies whether or not to merge incremental error data from a
signoff_check_drc -auto_eco true with a previous result from a signoff_check_drc run. The
resulting name of the merged error data signoff_check_drc
signoff_check_drc_incremental_merged.err. The default value is false.
EXAMPLES
The following example runs incremental drc and merges the result with a previous
signoff_check_drc run.
signoff.check_drc.merge_incremental_error_data -value true
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
signoff.check_drc.merge_incremental_error_data
883
1-883
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.check_drc.read_design_view
Option for the signoff_check_drc command. Reads the data of cell instances from the
design view.
TYPE
bool
DEFAULT
false
DESCRIPTION
If true, the cell instance data is read from the design view. If the design view of a cell instance
cannot be found, a warning message is printed and the command reads the FRAME view
instead.
By default (false), the cell instance data is read from the FRAME view. If the FRAME view of
a cell instance cannot be found, the command ignores this cell instance for design rule
checking and continues to check other cell instances. The command issues a warning
message for the ignored cell instance in the error file.
EXAMPLES
data from the design view. If the design view cannot be found, the command reads the
FRAME view instead.
prompt> set_app_options -name signoff.check_drc.read_design_view -value
true
SEE ALSO
get_app_options(2)
884
set_app_options(2)
Chapter 1:
885
1-885
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.check_drc.read_design_views
Option for the signoff_check_drc command. Reads the data of cell instances from the
design view.
TYPE
list_of_macro_master_names
DEFAULT
none
DESCRIPTION
If set, the cell instance data of each named cell master is read from the design view. If the
design view of a cell instance cannot be found, a warning message is printed and the
command reads the FRAME view instead. For convenience, all cells can be specified by the
{*} wildcard. Macros instances that are not selected by this option are read from the FRAME
view as below.
By default (none), the macro instance data is read from the FRAME view. If the FRAME view
of a macro instance cannot be found, the command ignores this instance for design rule
checking and continues to check other cell instances. The command issues a warning
message for the ignored cell instance in the error file.
EXAMPLES
data for all cells from the design view. If the design view cannot be found, the command
reads the FRAME view instead.
{*}
data for the M1 macro from the design view. If the design view for this macro cannot be
found the command reads the FRAME view instead. The cell instance data for all other cells
886
is read from the FRAME view. If the FRAME view cannot be found for any of those cells, the
cell is ignored.
{M1}
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
887
1-887
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.check_drc.run_dir
Option for the signoff_check_drc command. Specifies the path of working directory.
TYPE
string
DEFAULT
signoff_check_drc_run
DESCRIPTION
If you do not specify this option, the tool uses a directory called signoff_check_drc_run
EXAMPLES
my_signoff_run.
prompt> set_app_options -name signoff.check_drc.run_dir -value
"my_signoff_run"
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff.check_drc.run_dir
888
signoff.check_drc.runset
Option for the signoff_check_drc command. Specifies the foundry runset to use for design
rule checking (DRC).
TYPE
string
DEFAULT
null
DESCRIPTION
The foundry runset will be used while tool invokes IC Validator for design rule checking in
the current design.
EXAMPLES
The following example specifies the DRC runset drc.rs for the signoff_check_drc
command.
prompt> set_app_options -name signoff.check_drc.runset -value "drc.rs"
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
signoff.check_drc.runset
889
1-889
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.check_drc.user_defined_options
Option for the signoff_check_drc command. Specifies strings as part of IC Validator
TYPE
string
DEFAULT
null
DESCRIPTION
EXAMPLES
prompt> set_app_options -name signoff.check_drc.user_defined_options
-value "-turbo"
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff.check_drc.user_defined_options
890
signoff.color_macro.enabled
Option to run color macro pins flow during check_workspace command. Enable the color
macro pins flow.
TYPE
boolean
DEFAULT
false
DESCRIPTION
If you do not specify this option, the tool does not color the pins shapes during library
creation.
EXAMPLES
The following example runs the color macro pins flow during check_workspace.
prompt> set_app_options -name signoff.color_macro.enabled -value true
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
Chapter 1:
signoff.color_macro.enabled
891
1-891
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.color_macro.input_gds
Option to specify the input gds.
TYPE
string
DEFAULT
null
DESCRIPTION
Option to specify input gds when color macro pin flow is run on GDSII files. This option does
not work when color macro pin flow runs with ICC2 LM Shell.
EXAMPLES
The following example sets the name of input gds as "hard_macro."
prompt> set_app_options -name signoff.color_macro.input_gds -value
"hard_macro.gds"
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff.color_macro.input_gds
892
signoff.color_macro.layer_map
Option to specify the layer map file.
TYPE
string
DEFAULT
null
DESCRIPTION
Option to specify the layer map file. It is used when color macro pins flow is run from
icc2_shell. It is only required when the color macro ins flow is run on GDSII files.
EXAMPLES
The following example reads layer map file from layer.map
prompt> set_app_options -name signoff.color_macro.layer_map -value
"layer.map"
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
signoff.color_macro.layer_map
893
1-893
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.color_macro.macro_name
Option to run color macro pins flow during check_workspace command. Enable the color
macro pins flow.
TYPE
string
DEFAULT
null
DESCRIPTION
This is a required option. It specifies the macro design to be read to run the color macro pins
flow.
EXAMPLES
The following example reads the "hard_macro" in color macro pins flow during library
creation.
prompt> set_app_options -name signoff.color_macro.macro_name -value
hard_macro
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
signoff.color_macro.macro_name
894
signoff.color_macro.output_gds
Option to specify the output gds.
TYPE
string
DEFAULT
null
DESCRIPTION
Option to specify output gds when color macro pin flow is run on GDSII files. This option
does not work when color macro pin flow runs with ICC2 LM Shell.
EXAMPLES
The following example sets the name of output gds as "hard_macro."
prompt> set_app_options -name signoff.color_macro.output_gds -value
"hard_macro.gds"
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
signoff.color_macro.output_gds
895
1-895
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.color_macro.preferred_routing_direction
Option to specify routig direction of metals.
TYPE
List of string string
DEFAULT
as present in design.
DESCRIPTION
Option to specify the preferred routing direction in color macro pins flow. If this is not
specified for the block, the user could specify the preferred routing direction for first two
layers. The rest of the layers will be alte- nater of the previous layer's routing direction.
The user specifies the routing direction with layer name and keyword \'H\' for horizontal and
\'V\' for vertical.
EXAMPLES
The following example sets the preferred routing direction as given by user in color macro
pins flow:
{signoff.color_macro.preferred_routing_direction \
"{M1 H} {M2 V}"}
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
signoff.color_macro.preferred_routing_direction
896
signoff.color_macro.rule_type
Option for the color macro pins flow. Specifies the type of node and foundry.
TYPE
string
DEFAULT
tsmc20
DESCRIPTION
If you do not specify this option, the tool uses tsmc20 as rule type to run the color macro pin
flow. The valid values of rule_type is tsmc20, tsmc16, samsung20, samsung16 and
samsung10.
EXAMPLES
The following example runs the color macro pins flow for rule type samsung20.
prompt> set_app_options -name signoff.color_macro.rule_type -value
"samsung20"
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
Chapter 1:
signoff.color_macro.rule_type
897
1-897
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.color_macro.run_dir
Option for the color macro pins flow. Specifies the path of working directory.
TYPE
string
DEFAULT
pin_color_<design_name>
DESCRIPTION
If you do not specify this option, the tool uses a directory called pin_color_<design_name>
EXAMPLES
my_signoff_run_<design_name>.
prompt> set_app_options -name signoff.color_macro.run_dir -value
"my_signoff_run"
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
signoff.color_macro.run_dir
898
signoff.color_macro.technology_file
Option to specify the technology file.
TYPE
string
DEFAULT
null
DESCRIPTION
Option to specify the technology files when the color macro pins flow is run from icc2_shell.
The technology is to be passed with macro_name to get the details of layers when the flow
is run on GDSII files.
This option does not work with icc2_lm_shell.
EXAMPLES
The following example read the technology file as icc2.tf.
prompt> set_app_options -name signoff.color_macro.technology_file -value
"icc2.tf"
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
signoff.color_macro.technology_file
899
1-899
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.color_macro.track_color_preference
Option to specify the color pattern in the design.
TYPE
list of string string
DEFAULT
nocolor
DESCRIPTION
In the case of pre-color information not present in design, this option is used to specify the
color pattern of tracks. By default, it uses the colors pre-assigned to the tracks.
There are only two valid values that could be passed with each layer - color1 and color2.
EXAMPLES
The following example sets the track color preference in color macro pins flow.
prompt> \fset_app_options -list
{signoff.color_macro.track_color_preference "{M1 color1} \
{M2 color2} {M3 color1}"}
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
signoff.color_macro.track_color_preference
900
signoff.color_macro.track_offset
Option to specify the track information for the macro block.
TYPE
List of string double
DEFAULT
zero.
DESCRIPTION
Option to derive correct track information for the macro block from the library. There is no
easy way to derive track information from newly created library, this is an user option to
provide track offset values. The offset is the distance between the first track and the bottom
left corner of the boundary of the macro. The offset values is referred to bottom most track
for horizontal tracks and left most track for vertical tracks.
EXAMPLES
The following example sets the track offset values for each layer's track in color macro pins
flow:
prompt> set_app_options -list {signoff.color_macro.track_offset \
"{M1 0.05} {M2 0.05} {M3 0.065} {M4 0.05}"}
SEE ALSO
get_app_options(2)
set_app_options(2)
check_workspace(2)
Chapter 1:
signoff.color_macro.track_offset
901
1-901
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.create_metal_fill.apply_nondefault_rules
Option for the signoff_create_metal_fill command. Specifies the option to enable honoring
of NDR rules during fill creation.
TYPE
boolean
DEFAULT
false
DESCRIPTION
If user specifies the option, NDR rules are honored during fill creation flow, ie. no fill will be
created in NDR blocked area.
EXAMPLES
The following example enables honoring of NDR rules.
signoff.create_metal_fill.apply_nondefault_rules -value true
prompt> signoff_create_metal_fill
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_create_metal_fill(2)
signoff.create_metal_fill.apply_nondefault_rules
902
signoff.create_metal_fill.auto_eco_threshold_value
Option for the signoff_create_metal_fill command. Specifies the threshold for allowed
change in design s.t incremental fill can be run. Default: 20%.
TYPE
integer
DEFAULT
20
DESCRIPTION
This application option specifies the threshold for allowed change in design s.t incremental
fill can be run. The default value is 20.
EXAMPLES
The following example runs incremental fill by setting a max allowed diff percent to 30.
signoff.create_metal_fill.auto_eco_threshold_value -value 30
prompt> signoff_create_metal_fill -auto_eco true
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
signoff.create_metal_fill.auto_eco_threshold_value
903
1-903
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.create_metal_fill.fill_over_net_on_adjacent_layer
Option for the signoff_create_metal_fill command. Insert metal fill on the vertical
extension regions of critical nets on adjacent layers.
TYPE
bool
DEFAULT
false
DESCRIPTION
The option only takes effect when signoff_create_metal_fill option -nets and/or
-timing_preserve_setup_slack_threshold are specified.
If true, metal fills are inserted on adjacent layers of timing critical nets.
By default (false), the vertical extension regions of critical nets on adjacent layers are
blocked with the minimum spacing.
EXAMPLES
The following example fills all empty regions with metal fill, except for the regions within two
times the minimum spacing away from critical nets on the same layer. The adjacent layers
of timing critical nets are also filled. The critical nets are n1, n2, and n3.
signoff.create_metal_fill.fill_over_net_on_adjacent_layer -value true
prompt> signoff_create_metal_fill -nets {n1 n2 n3}
SEE ALSO
get_app_options(2)
set_app_options(2)
904
Chapter 1:
905
1-905
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.create_metal_fill.fix_density_errors
Option for the signoff_create_metal_fill command. Specifies the option to enable fixing of
density errors when generating timing aware fill.
TYPE
boolean
DEFAULT
false
DESCRIPTION
If user specifies the option, density errors would be fixed during timing aware fill creation
flow.
EXAMPLES
The following example runs density aware fill flow.
signoff.create_metal_fill.fix_density_errors -value true
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff.create_metal_fill.fix_density_errors
906
signoff.create_metal_fill.flat
Option for the signoff_create_metal_fill command. Force IC Validator generate flat fill.
TYPE
bool
DEFAULT
false
DESCRIPTION
There are two modes of fill: hierarchical fill and flat fill.
If true, the command forces IC Validator generate flat fill.
By default (false), the mode in the runset is used.
EXAMPLES
The following example forces IC Validator generate flat fill.
prompt> set_app_options -name signoff.create_metal_fill.flat -value true
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
signoff.create_metal_fill.flat
907
1-907
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.create_metal_fill.max_density_threshold
Option for the signoff_create_metal_fill command. Specifies the max density threshold
value for a track fill layer.
TYPE
list
DEFAULT
{}
DESCRIPTION
User shoud provide list of {layerName value} pairs to control max density threshold value for
a track fill layer. When this option is given a post proessing stage is run when for metal layers
having high metal density, fill will be trimmed to bring its denisity close to max density
threshold specified by user.
EXAMPLES
The following example sets a max density threshold of 40 percent for M2, M3, M4.
signoff.create_metal_fill.max_density_threshold -value {{M2 40} {M3 40}
{M4 40}}
prompt> signoff_create_metal_fill -track_fill
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff.create_metal_fill.max_density_threshold
908
signoff.create_metal_fill.run_dir
Option for the signoff_create_metal_fill command. Specifies the path of working directory.
TYPE
string
DEFAULT
signoff_fill_run
DESCRIPTION
If you do not specify this option, the tool uses a directory called signoff_fill_run under the
current working directory. The path can be either relative or absolute.
EXAMPLES
my_signoff_run.
prompt> set_app_options -name signoff.create_metal_fill.run_dir -value
"my_signoff_run"
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
signoff.create_metal_fill.run_dir
909
1-909
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.create_metal_fill.runset
Option for the signoff_create_metal_fill command. Specifies the foundry runset to use for
metal fill insertion.
TYPE
string
DEFAULT
null
DESCRIPTION
The foundry runset will be used while tool invokes IC Validator for metal fill insertion in the
current design.
EXAMPLES
The following example specifies the fill runset fill.rs for the signoff_create_metal_fill
command.
prompt> set_app_options -name signoff.create_metal_fill.runset -value
"fill.rs"
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff.create_metal_fill.runset
910
signoff.create_metal_fill.space_to_clock_nets
Option for the signoff_create_metal_fill command. Specifies the fill spacing parameters to
clock nets.
TYPE
list
DEFAULT
{}
DESCRIPTION
User shoud provide list of {layerName value} pairs to control fill spacing to clock nets.
EXAMPLES
The following example provides spacing info for clock polygons on metal1 and metal2.
signoff.create_metal_fill.space_to_clock_nets -value {{M1 3x} {M2 3x}}
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
signoff.create_metal_fill.space_to_clock_nets
911
1-911
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.create_metal_fill.space_to_nets
Option for the signoff_create_metal_fill command. Specifies the fill-to-critical-nets spacing
ratio for each given metal layer.
TYPE
list
DEFAULT
null
DESCRIPTION
This option only takes effect when signoff_create_metal_fill option -nets and/or
-timing_preserve_setup_slack_threshold are specified. This option specifies the
fill-to-critical-nets spacing to min spacing ratio for each given metal layer. The list format is:
{{layer_name1 ratio1}
{layer_name2 ratio2}
{layer_name3 ratio3} ...}
You must specify the layer name by using the layer name from technology file.
By default, this command uses two times of minimum spacing specified in the technology file
for each layer.
EXAMPLES
The following example specifies 3 times of minimum spacing to layer_name1. The critical
nets are n1, n2, and n3.
prompt> set_app_options -name signoff.create_metal_fill.space_to_nets
-value {{layer_name1 3}}
prompt> signoff_create_metal_fill -nets {n1 n2 n3}
912
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
913
1-913
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.create_metal_fill.space_to_nets_on_adjacent_layer
Option for the signoff_create_metal_fill command. Specifies the fill spacing on adjacent
layers to critical nets polygons.
TYPE
list
DEFAULT
{}
DESCRIPTION
User shoud provide list of {layerName value} pairs to control fill spacing on adjacent layers
to critical nets polygons.
EXAMPLES
In the following example, from a M3 net shape, M2 fill will be blocked till 3 times M2
minSpacing, and M4 fill will be blocked till 4 times M4 minSpacing.
signoff.create_metal_fill.space_to_nets_on_adjacent_layers -value {{M2
3x} {M3 2x} {M4 4x}}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff.create_metal_fill.space_to_nets_on_adjacent_layer
914
signoff.create_metal_fill.tcd_fill
Option for the signoff_create_metal_fill command. Specifies to handle TCD structures of
foundry metal fill runsets in signoff_create_metal_fill flow.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This option specifies to add handling of TCD structures of foundry metal fill runsets for 28/
20/16nm nodes in signoff_create_metal_fill flow.
signoff_create_metal_fill flow only handles fill for routing layers. flow does not save fill data
for non-routing layers. TCD structures have data on typically non routing layers, So even if
runset outputs these layers, data is not saved to ndm db.
This option supports insertion and removal of TCD structures in conjunction with all
signoff_create_metal_fill flow options.
By default it is false.
EXAMPLES
The following example will create fill along with the TCD structures if runset outputs any.
prompt> set_app_options -name signoff.create_metal_fill.tcd_fill -value
true
SEE ALSO
get_app_options(2)
Chapter 1:
915
1-915
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
set_app_options(2)
916
signoff.create_metal_fill.user_defined_options
Option for the signoff_create_metal_fill command. Specifies strings as part of IC Validator
TYPE
string
DEFAULT
null
DESCRIPTION
string that you specify is added to the command line used to invoke metal fill insertion in IC
Validator. IC Compiler II does not perform any checking on the specified string.
EXAMPLES
signoff.create_metal_fill.user_defined_options -value "-turbo"
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
signoff.create_metal_fill.user_defined_options
917
1-917
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.fix_drc.advanced_guidance_for_rules
Option for the signoff_fix_drc command. Specifies whether rule specific heuristics should
be applied during ADR fixing flow.
TYPE
string
DEFAULT
off
DESCRIPTION
If you do not specify this option, the tool uses default "off", which essentially means that no
rule specific heuristics are applied. If you specify "all", then all the available rule specific
heuristics are applied.
EXAMPLES
The following example runs ADR fixing flow while using the rule specific heuristics.
{signoff.fix_drc.advanced_guidance_for_rules "all"}
prompt> signoff_fix_drc
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_fix_drc(2)
signoff.fix_drc.advanced_guidance_for_rules
918
signoff.fix_drc.check_drc
Option for the signoff_fix_drc command. Specifies whether the intermediate DRC runs
should be done on complete design or the regions which have been changed during ADR
fixing flow.
TYPE
string
DEFAULT
local
DESCRIPTION
If you do not specify this option, the tool uses "local", which means that the regions which
have been changed during ADR fixing flow will be checked for DRCs. If you select "global",
then it means that all the region of the design will be checked for DRCs.
EXAMPLES
The following example runs ADR fixing flow with DRC being run on the complete design.
prompt> set_app_options -list {signoff.fix_drc.check_drc "global"}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_fix_drc(2)
Chapter 1:
signoff.fix_drc.check_drc
919
1-919
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.fix_drc.config_file
Option for the signoff_fix_drc command. Specifies the path of configuration file.
TYPE
string
DEFAULT
auto
DESCRIPTION
If you do not specify this option, the tool uses "auto", which is automatically generated
configuration file.
EXAMPLES
The following example runs with my_config_file as the configuration file.
prompt> set_app_options -list {signoff.fix_drc.config_file
"my_config_file"}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_fix_drc(2)
signoff.fix_drc.config_file
920
signoff.fix_drc.custom_guidance
Option for the signoff_fix_drc command. This option is used for specifying if DPT fixing is
being done.
TYPE
string
DEFAULT
off
DESCRIPTION
This option need to be specified when ADR is used for DPT fixing.
EXAMPLES
The following example runs ADR for DPT fixing.
prompt> set_app_options -list {signoff.fix_drc.custom_guidance dpt}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_fix_drc(2)
Chapter 1:
signoff.fix_drc.custom_guidance
921
1-921
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.fix_drc.fix_detail_route_drc
Option for the signoff_fix_drc command. This option is used to specify how the detail route
DRCs are fixed while fixing Signoff DRCs.
TYPE
string
DEFAULT
global
DESCRIPTION
After fixing Signoff DRCs ADR also try to fix detail route DRCs. This option specifies if the
fixing need to be done only near to signoff DRC or full chip.
local : Detail route DRCs near to Signoff DRCs are tried for fixing.
global : Detail route DRCs in full chip are tried for fixing.
By default, full chip detail route DRCs are tried for fixing.
EXAMPLES
The following example runs ADR with local detail route DRC fixing.
prompt> set_app_options -list {signoff.fix_drc.fix_detail_route_drc
local}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_fix_drc(2)
signoff.fix_drc.fix_detail_route_drc
922
signoff.fix_drc.init_drc_error_db
Specifies the initial DRC error database path for the signoff_fix_drc command.
TYPE
string
DEFAULT
This is a required option.
DESCRIPTION
Specifies the path of the directory that contains the initial DRC error database generated by
IC Validator. The path can be either relative or absolute. This option is required.
EXAMPLES
The following example runs ADR using the initial DRC error database from working directory
named my_signoff_check_run.
prompt> set_app_options -list {signoff.check_drc.run_dir
"my_signoff_check_run"}
prompt> set_app_options -list {signoff.fix_drc.initial_drc_error_db
"my_signoff_check_run"}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_fix_drc(2)
Chapter 1:
signoff.fix_drc.init_drc_error_db
923
1-923
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.fix_drc.last_run_full_chip
Option for the signoff_fix_drc command. Specifies if the last run during
incremental_drc_level=high is run on complete design or not.
TYPE
boolean
DEFAULT
false
DESCRIPTION
If you do not specify this option, the tool will run the last drc on the sub-design with changes
due to ADR. This causes in-accuracy during reporting, but is fast compared to complete
design DRC.
EXAMPLES
The following example runs ADR with last DRC being complete design DRC.
prompt> set_app_options -list {signoff.fix_drc.last_run_full_chip true}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_fix_drc(2)
signoff.fix_drc.last_run_full_chip
924
signoff.fix_drc.max_detail_route_iterations
Specifies the number of router search and repair loops for the signoff_fix_drc command to
run after router guidance fixing.
TYPE
integer
DEFAULT
5
DESCRIPTION
Specifies the number of search and repair loops to run after route guidance fixing. This is
mainly for cleaning up DRC violations generated during route guidance fixing. The router
runs the specified number of detail route iterations if you set the
route.detail.force_max_number_iterations option to true.
You can specify an integer between 0 and 1000. The default value is 5.
EXAMPLES
The following example runs 10 search and repair loop after route guidance fixing.
{signoff.fix_drc.max_detail_route_iterations 10}
The following example forces the maximum number of detail route iterations.
prompt> set_app_options -list {route.detail.force_max_number_iterations
true}
{signoff.fix_drc.max_detail_route_iterations 10}
Chapter 1:
925
1-925
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_fix_drc(2)
926
signoff.fix_drc.max_errors_per_rule
Option for the signoff_fix_drc command. Specifies the maximum number of errors per rule
for the IC Validator run.
TYPE
integer
DEFAULT
1000
DESCRIPTION
run. The value must be greater than or equal to 1. The default value is 1000.
If the number of errors exceeds the specified value, the entire rule is skipped during the
signoff fixing flow. A reasonable value should be relative to the design size. For a typical
design, the default value of 1000 makes sense. For a huge design, targeting more than 1000
errors per rule might be a valid request.
EXAMPLES
prompt> set_app_options -list {signoff.fix_drc.max_errors_per_rule 8000}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_fix_drc(2)
Chapter 1:
signoff.fix_drc.max_errors_per_rule
927
1-927
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.fix_drc.read_frame_view_only
Option for the signoff_fix_drc command. Specifies the usage of frame views during DRC
identification for ADR flow.
TYPE
boolean
DEFAULT
false
DESCRIPTION
If you do not specify this option, the tool will try to read design view for DRC identification.
EXAMPLES
The following example runs ADR on DRC identified with FRAME view data for child cells.
prompt> set_app_options -list {signoff.fix_drc.read_frame_view_only true}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_fix_drc(2)
signoff.fix_drc.read_frame_view_only
928
signoff.fix_drc.run_dir
Option for the signoff_fix_drc command. Specifies the path of working directory.
TYPE
string
DEFAULT
signoff_fix_drc_run
DESCRIPTION
If you do not specify this option, the tool uses a directory called signoff_fix_drc_run under
the current working directory. The path can be either relative or absolute.
EXAMPLES
The following example runs ADR under the working directory named my_signoff_fix_run.
prompt> set_app_options -list {signoff.fix_drc.run_dir
"my_signoff_fix_run"}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_fix_drc(2)
Chapter 1:
signoff.fix_drc.run_dir
929
1-929
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.fix_drc.target_clock_nets
Option for the signoff_fix_drc command. Specifies if errors associated with clock nets
should be targeted by ADR.
TYPE
bool
DEFAULT
false
DESCRIPTION
If you do not specify this app option, the tool would not target errors associated with clock
nets. If this app option is set to true, the tool would target errors associated with clock nets
during ADR fixing.
Note: When the option "signoff.fix_drc.target_clock_nets" is set to false, the router does
NOT have big routing topology changes on clock nets, but it does allow minor shape
changes in local area for fixing DRC violations.
EXAMPLES
The following example enables targeting of errors associated with clock nets during ADR
fixing.
prompt> set_app_options -list {signoff.fix_drc.target_clock_nets true}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_fix_drc(2)
signoff.fix_drc.target_clock_nets
930
signoff.fix_drc.user_defined_options
Option for the signoff_fix_drc command. Specifies strings as part of IC Validator command
line options.
TYPE
string
DEFAULT
null
DESCRIPTION
EXAMPLES
prompt> set_app_options -list {signoff.fix_drc.user_defined_options
"-turbo"}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_fix_drc(2)
Chapter 1:
signoff.fix_drc.user_defined_options
931
1-931
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.fix_isolated_via.avoid_net_types
Option for the signoff_fix_isolated_via command. Specifies net types to be avoided for
isolated via fixing.
TYPE
list
DEFAULT
null
DESCRIPTION
This application option specifies the net types to be avoided for iso via fixing. You can
specify a list of one more more net types. The valid values for net types are clock, pg, none.
These net types are defined as follows:
clock is for clock nets
pg is for pg nets
none is for none of the nets
By default, both clock and pg nets are avoided for iso via fixing.
EXAMPLES
The following example specifies clock nets to be avoided for isolated via fixing.
prompt> set_app_options -list {signoff.fix_isolated_via.avoid_net_types
{clock}}
prompt> signoff_fix_isolated_via
The following example specifies both clock and pg nets to be avoided for isolated via fixing.
{clock pg}}
The following example specifies both clock and pg nets to be used for isolated via fixing.
932

{none}}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff_fix_isolated_via(2)
Chapter 1:
933
1-933
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.fix_isolated_via.isolated_via_max_range
Option for the signoff_fix_isolated_via command. Specifies the isolated via range for each
given via layer.
TYPE
list
DEFAULT
null
DESCRIPTION
This option specifies the isolated via range for each given via layer. The list format is:
{{layer_name1 value1}
{layer_name2 value2}
{layer_name3 value3} ...}
You must specify the layer name by using the layer mask name from technology file.
EXAMPLES
The following example specifies 3.0 isolated via range to layer_name1.
{signoff.fix_isolated_via.isolated_via_max_range {{layer_name1 3.0}}}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff.fix_isolated_via.isolated_via_max_range
934
signoff.fix_isolated_via.run_dir
Option for the signoff_fix_isolated_via command. Specifies the path of working directory.
TYPE
string
DEFAULT
signoff_fix_isolated_via_run
DESCRIPTION
If you do not specify this option, the tool uses a directory called signoff_fix_isolated_via_run
EXAMPLES
my_signoff_run.
prompt> set_app_options -list {signoff.fix_isolated_via.run_dir
"my_signoff_run"}
SEE ALSO
get_app_options(2)
set_app_options(2)
Chapter 1:
signoff.fix_isolated_via.run_dir
935
1-935
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
signoff.fix_isolated_via.user_defined_options
Option for the signoff_fix_isolated_via command. Specifies strings as part of IC Validator
TYPE
string
DEFAULT
null
DESCRIPTION
EXAMPLES
{signoff.fix_isolated_via.user_defined_options "-turbo"}
SEE ALSO
get_app_options(2)
set_app_options(2)
signoff.fix_isolated_via.user_defined_options
936
signoff.physical.layer_map_file
Specifies the layer mapping file for the signoff_check_drc or signoff_create_metal_fill
command. This file is to map IC Compiler II layers to runset (GDSII) stream layers.
TYPE
string
DEFAULT
null
DESCRIPTION
This application option specifies the layer mapping file for the signoff_check_drc or
signoff_create_metal_fill command. This file maps IC Compiler II layers to runset (GDSII)
stream layers. The format of the file is same as the layer map file used by read_gds and
write_gds commands.
For the information about the layer mapping file format, see the Library Data Preparation for
IC Compiler II User Guide.
By default, no mapping file is required.
EXAMPLES
The following example specifies the layer mapping file layer.map for the
signoff_check_drc or signoff_create_metal_fill command.
prompt> set_app_options -list {signoff.physical.layer_map_file
"layer.map"}
The following example shows a layer mapping file that maps IC Compiler II all the purpose
on IC Compiler II layer 15 to GDSII data type 70 on GDSII layer 35.
15 35:70
Chapter 1:
937
1-937
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_app_options(2)
set_app_options(2)
read_gds(2)
write_gds(2)
938
signoff.physical.merge_stream_files
Specifies the list of stream (GDS or OASIS) files that would be merged into the current
design for the signoff_check_drc or signoff_create_metal_fill command.
TYPE
list
DEFAULT
null
DESCRIPTION
This application option specifies specifies list of stream (GDS or OASIS) files that would be
merged into the current design for the signoff_check_drc or signoff_create_metal_fill
command. Cells in the stream files with the same name as in the current design will replace
those cells in the reference library. The file names can be relative to the current run or
absolute path names. The results of the signoff_check_drc or signoff_create_metal_fill
command are expected to be the same as if run directly on a stream version of the entire
design.
By default, no mapping file is required.
EXAMPLES
The following example specifies the list of stream files for the signoff_check_drc
command.
prompt> set_app_options -list {signoff.physical.merge_stream_files
{stream_file1.gds stream_file2.oas}}
The following example specifies the list of stream files for the signoff_create_metal_fill
command from a file.
prompt> set file_handle [open stream_files.list r]
prompt> set stream_files [read $file_handle]
prompt> set_app_option -name signoff.physical.merge_stream_files -value
$stream_files
Chapter 1:
939
1-939
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_app_options(2)
set_app_options(2)
940
site_array_attributes
Description of the predefined attributes for site_arrays.
DESCRIPTION
site_array attributes are provided in the subsections that follow.
command.
Site Array Attributes
boundary
A polygon attribute for the boundary of this site_array. The format of a boundary
attribute and changing its value can cause changes in other site arrays in the stack.
full_name
A string attribute for the name of the site_array.
is_alternate_rows_flipped
A Boolean attribute specifying if alternate rows of the site array are flipped. This is a settable
attribute.
is_default
A boolean attribute specifying if the site array is default site array.
is_first_row_flipped
A Boolean attribute specifying if first row of the site array is flipped. This is a settable
attribute.
Chapter 1:
941
1-941
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
is_horizontal
A Boolean attribute specifying if site array is horizontal or vertical. This is a settable attribute.
is_shadow
A Boolean attribute to specify whether this site array is pushed down from above.
is_transparent
A Boolean attribute specifying if site array is transparent or opaque. This is a settable
attribute and changing its value will cause changes in other site arrays in the stack.
name
A string attribute for the name of the site_array. This is a settable attribute.
object_class
A string attribute with the value of "site_array".
site_name
A string attribute for the name of the site that is used to create the site array.
x_core_offset
A distance attribute for the x offset of sites grid from block's origin. By default the site rows
created within a site array align with a grid passing through block's origin.
x_margin
A distance attribute for the x offset of sites within a row of the site array. This is a settable
attribute.
y_core_offset
A distance attribute for the y offset of sites grid from block's origin. By default the site rows
created within a site array align with a grid passing through block's origin.
y_margin
A distance attribute for the y offset of site rows of the site array. This is a settable attribute.
942
parent_block
A collection attribute with the owner block object for this site array.
parent_cell
A collection attribute with the owner cell object for this site array.
parent_block_cell
A collection attribute with the parent block cell object for this site array.
physical_status
A string attribute representing the physical modification status of the site array. If status is
unrestricted, the site array may be moved or rotated. If the status is locked, the site array
top_block
A collection attribute with the top block object for this site array.
SEE ALSO
create_site_array(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
943
1-943
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
site_def_attributes
Description of the predefined attributes for site_defs.
DESCRIPTION
site_def attributes are provided in the subsections that follow.
command.
Site Def Attributes
full_name
A string attribute for the name of the site_def. This is a settable attribute.
height
A distance attribute specifying the height of the site_def. This is a settable attribute.
is_default
A boolean attribute to specify whether the site_def is the default of its tech. This is a settable
attribute.
legal_orientations
An orientations attribute specifying the allowed orientations of the site_def.
name
A string attribute for the name of the site_def. This is a settable attribute.
site_def_attributes
944
object_class
A string attribute with the value of "site_def".
symmetry
A string attribute to represent if the site_def is symetrical about the X and/or Y and/or 90
degree rotation. Valid values is a set composed with the strings "X", "Y" and "R90".
Example: { X } or { Y R90 } or { X Y R90 } etc. This is a settable attribute.
tech
A collection attribute specifying the owning tech of the site_def.
type
A string attribute for the type of the site_def as either core or pad. This is a settable attribute.
width
A distance attribute specifying the width of site_def. This is a settable attribute.
SEE ALSO
create_site_def(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
site_def_attributes
945
1-945
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
site_row_attributes
Description of the predefined attributes for site_rows.
DESCRIPTION
site_row attributes are provided in the subsections that follow.
command.
Site Row Attributes
bbox
A rectangle attribute for the bounding-box of a site row. The format of a rectangle
the rectangle.
design_name
A string attribute specifying the name of the design owning the site row.
full_name
A string attribute for the name of the site_row.
in_edit_group
A Boolean attribute to specify whether a site row belongs to an edit_group.
is_derived
A Boolean attribute to specify whether a site row belongs to a site array.
site_row_attributes
946
is_shadow
A Boolean attribute to specify whether a site row is pushed down from above.
is_site_r90symmetrical
A Boolean attribute to specify whether the site definition used for the site row is symmetrical
with 90 degree orientation.
is_site_xsymmetrical
about x axis.
is_site_ysymmetrical
about y axis.
legal_orientations
An orientations attribute specifying the allowed orientations of the site definition used for the
site row.
name
A string attribute for the name of the site_row. This is a settable attribute.
object_class
A string attribute with the value of "site_row".
object_id
An integer attribute specifying the id of the site row object.
orientation
A string attribute specifying the orientation of the site row. This is a settable attribute.
origin
A coordinate attribute representing the origin of the site row. This is a settable attribute.
Chapter 1:
site_row_attributes
947
1-947
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
parent_block
A collection attribute with the owner block object for this site row.
parent_block_cell
A collection attribute with the parent block cell object for this site row.
parent_cell
A collection attribute with the owner cell object for this site row.
physical_status
A string attribute representing the physical modification status of the site row. If status is
unrestricted, the site_row may be moved or rotated. If the he status is locked, the site_row
shadow_status
A string attribute to represent the shadow status of a site row. Valid values are copied_down,
copied_up, normal, pulled_up, and pushed_down. This is a settable attribute.
site_array
A collection attribute specifying the owning site array of the site row, if the site row belongs
to any site array.
site_count
An integer attribute specifying the number of sites in the site row. This is a settable attribute.
site_height
A distance attribute specifying the height of site definition used for the site row.
site_name
A string attribute for the name of the site definition that is used to create the site row.
site_orientation
A string attribute representing the orientation of sites within the site row. This is relative to
the site row orientation. This is a settable attribute.
site_row_attributes
948
site_space
A distance attribute specifying the spacing between sites inside the site row. This is a
settable attribute.
site_width
A distance attribute specifying the width of site definition used for the site row.
top_block
A collection attribute with the top block object for this site row.
SEE ALSO
create_site_row(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
site_row_attributes
949
1-949
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
skew_group_attributes
Lists the predefined attributes for skew_group objects.
DESCRIPTION
Attributes are properties assigned to objects. Definitions for skew_group attributes are
by the application.
Skew Group Attributes
clock
Collection of clocks for which this skew group has been created.
command_text
A string attribute which recreates the create_skew_group constraint command used to
create this skew_group.
file_line_info
A string attribute. If it exists, the value contains the Tcl or SDC source file name and line
number pair of the command which was used to create this object.
full_name
A string attribute returning a unique name for the skew_group. This is the user given name
or a tool generated one if user doesnt specify any.
mode
A collection object but contains only a single mode in which this skew group has been
created.
950
objects
A collection of clock pin which have been grouped together with this skew group constraint.
object_class
A string attribute, with the value "skew_group".
SEE ALSO
get_skew_groups(2)
get_attribute(2)
list_attributes(2)
report_skew_group(2)
create_skew_groups(2)
Chapter 1:
951
1-951
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
supernet_attributes
Lists the predefined attributes for supernets.
DESCRIPTION
supernet attributes are provided in the subsections that follow.
command.
Supernet Attributes
name string read-only

The name of the supernet.
is_master boolean read-only

True if this supernet is the master, false otherwise.
master supernet read-only

The supernet which is the master.
anchor term read-only

The pin or port to which the supernet is anchored.
transparent_cells cell_collection read-only

The transparent cells on this supernet.
supernet_attributes
952
boundary_terms term_collection read-only

All pins and ports connected to the supernet which are on the boundary, i.e. the opposite
term (if it exists) is not part of the supernet. These terms are either pins on non-transparent
cells or toplevel ports.
drivers term_collection read-only

Boundary terms which are net drivers. These include bidirectional terms.
loads term_collection read-only

Boundary terms which are net loads. These include bidirectional terms.
SEE ALSO
find(2)
get_attribute(2)
list_attributes(2)
get_supernets(2)
remove_supernets(2)
Chapter 1:
supernet_attributes
953
1-953
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
supply_net_attributes
Describes the attributes related to supply nets.
DESCRIPTION
supply_net attributes are provided in the subsections that follow.
command.
Supply Net Attributes

full_name
Specifies full name of a supply net object.
name
Specifies name of a supply net object. This is a settable attribute.
object_class
Specifies object class name of a supply net object.
reference_only
A string attribute specifying if the supply net is reference only. It can specify if supply net is
internal.
resolve_type
A string attribute representing the resolution for this supply net object.
scope
A collection attribute with the scope object for this supply net object.
supply_ports
A collection attribute with all supply ports connected to this supply net object.
954
voltage_areas
A collection attribute with the voltage area objects for this supply net object.
SEE ALSO
get_attribute(2)
list_attributes(2)
Chapter 1:
955
1-955
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
supply_port_attributes
Describes the attributes related to supply ports.
DESCRIPTION
supply_port attributes are provided in the subsections that follow.
command.
Supply Port Attributes

direction
Specifies direction of a supply port object.
full_name
Specifies full name of a supply port object.
name
Specifies name of a supply port object.
object_class
Specifies object class name of a supply port object, which is supply_port.
scope
A collection attribute with the scope object for this supply port object.
supply_nets
A collection attribute with all supply nets connected to this supply port object.
SEE ALSO
get_attribute(2)
956
list_attributes(2)
Chapter 1:
957
1-957
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
supply_set_attributes
Describes the attributes related to supply sets.
DESCRIPTION
supply_set attributes are provided in the subsections that follow.
command.
Supply Set Attributes

full_name
Specifies full name of a supply set object.
name
Specifies name of a supply set object.
object_class
Specifies object class name of a supply set object, which is supply_set.
function
A string attribute specifying the power and ground functions. If supply set functions are not
resolved this attribute is empty.
power_supply_net
A collection attribute representing the supply net used in resolving the power function for this
supply set object.If not resolved, this attribute is not reported.
ground_supply_net
A collection attribute representing the supply net used in resolving the ground function for
this supply set object.If not resolved, this attribute is not reported.
scope
958
A collection attribute with the scope object for this supply set object.
SEE ALSO
get_attribute(2)
list_attributes(2)
Chapter 1:
959
1-959
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
synopsys_program_name
Indicates the name of the program currently running.
TYPE
string
DESCRIPTION
This variable is read only, and is set by the application to indicate the name of the program
you are running. This is useful when writing scripts that are mostly common between some
applications, but contain some differences based on the application.
To determine the current value of this variable, use get_app_var
synopsys_program_name.
SEE ALSO
get_app_var(2)
synopsys_program_name
960
synopsys_root
Indicates the root directory from which the application was run.
TYPE
string
DESCRIPTION
This variable is read only, and is set by the application to indicate the root directory from
which the application was run.
To determine the current value of this variable, use get_app_var synopsys_root.
SEE ALSO
get_app_var(2)
Chapter 1:
synopsys_root
961
1-961
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
tech_attributes
Lists the predefined attributes for technology objects.
DESCRIPTION
Attributes are properties assigned to objects such as pins, cells and nets. Definitions for tech
command.
Tech Attributes
antenna_cut_to_metal
A Boolean attribute.This attribute will be true if antenna is cut to metal.
antenna_diode_distance
A Distance Attribute that specifies antenna diode distance.
antenna_max_area
An area attribute that specifies antenna maximum area.
antenna_metal_to_cut
A Boolean attribute.This attribute will be true if antenna is metal to cut.
capacitance_precision
An integer attribute that specifies capacitance precision.
capacitance_unit
A string attribute that specifies capacitance unit.
tech_attributes
962
corner_spacing_mode
An integer attribute that specifies corner spacing mode.
current_precision
An integer attribute that specifies current precision.
current_unit
A string attribute that specifies current unit.
date
A string attribute that specifies date.
dielectric
A double attribute that specifies dielectric.
fat_table_min_enclosed_area_mode
An integer attribute that specifies fat table minimum enclosed area mode.
fat_table_spacing_mode
An integer attribute that specifies fat table spacing mode.
fat_wire_extension_mode
An integer attribute that specifies fat wire extension mode.
grid_resolution
A integer attribute that specifies grid resolution. grid resolution must be greater than zero.
inductance_precision
An integer attribute that specifies inductance precision.
inductance_unit
A string attribute that specifies induction unit.
Chapter 1:
tech_attributes
963
1-963
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
lib
A collection attribute of library of this technology.
length_precision
An integer attribute that specifies length precision.
max_baseline_temperature
A double attribute that specifies maximum baseline temperature.
max_stack_level_mode
An integer attribute that specifies maximum stack level mode.
min_baseline_temperature
A double attribute that specifies minimum baseline temperature.
min_edge_mode
An integer attribute that specifies minimum edge mode.
min_length_mode
An integer attribute that specifies minimum length mode.
name
A string attribute that specifies technology name.
nom_baseline_temperature
A double attribute that specifies nominal baseline temperature.
object_class
A string attribute that specifies class of the tech object, that is tech for technology object.
parallel_length_mode
An integer attribute that specifies parallel length mode.
tech_attributes
964
power_precision
An integer attribute that specifies power precision.
power_unit
A string attribute that specifies power unit.
resistance_precision
An integer attribute that specifies resistance precision.
resistance_unit
A string attribute that specifies resistance unit.
time_precision
An integer attribute that specifies time precision.
time_unit
A string attribute that specifies time unit.
unit_length
A string attribute that specifies unit length.
voltage_precision
An integer attribute that specifies voltage precision.
voltage_unit
A string attribute that specifies voltage unit.
SEE ALSO
find(2)
get_attribute(2)
list_attributes(2)
Chapter 1:
tech_attributes
965
1-965
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
tech_purpose_attributes
Lists the predefined attributes for tech purpose objects.
DESCRIPTION
Attributes are properties assigned to objects such as pins, cells and nets. Definitions for tech
command.
Tech Purpose Attributes
full_name
A String Attribute that specifies name of the tech purpose.
name
A String Attribute that specifies name of the tech purpose.
object_class
A String Attribute that specifies object class of the tech purpose object. This is a read only
attribute, that always returns tech_purpose as the value for this attributes.
purpose_number
An Integer Attribute that specifies purpose number of the tech purpose.
SEE ALSO
find(2)
get_attribute(2)
list_attributes(2)
966
Chapter 1:
967
1-967
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
terminal_attributes
Description of the predefined attributes for terminals.
DESCRIPTION
terminal attributes are provided in the subsections that follow.
command.
Terminal Attributes
access_direction
Access direction for the terminal.
bbox
the rectangle.
class
A string attribute for the class of the terminal. The value is one of, bump, core or none.
direction
A string attribute for the direction of the terminal. The value is one of, driver, in, inout, load
or out.
full_name
A string attribute for the full name of a terminal.
terminal_attributes
968
is_fixed
A Boolean attribute. The value will be "true" if this terminal is fixed.
layer
A collection representing the layer on which the terminal exists.
matching_type
A collection representing the matching_type for the terminal.
must_join_group
A string showing the must_join_group for the terminal.
name
A string attribute for the name of a terminal.
object_class
A string attribute with the value of "terminal".
physical_status
A string attribute representing the physical modification status of the terminal. Valid values
are unrestricted, application_fixed, fixed, and locked. If status is unrestricted, the terminal
may be freely modified. If the status is application_fixed, the terminal is fixed by the
application for automatic changes (the application may change this status). If status is fixed,
the terminal is fixed by the user for automatic changes. If status is locked, the terminal is
fixed for automatic and manual changes. This is a settable attribute.
port
A collection representing the port for the terminal.
shape
A collection representing the shape for the terminal.
top_block
A collection representing the block for the terminal.
Chapter 1:
terminal_attributes
969
1-969
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_terminals(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
terminal_attributes
970
time.all_clocks_propagated
Specifies whether or not all subsequent clocks are created as propagated clocks.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When true, all clocks subsequently created by create_clock or create_generated_clock
are created as propagated clocks. When false (the default), clocks are created as
nonpropagated clocks.
By default, create_clock and create_generated_clock create only nonpropagated clocks.
You can subsequently define some or all clocks to be propagated clocks using the
set_propagated_clock command. However, if you set this option to true, create_clock and
create_generated_clock subsequently create only propagated clocks. Setting this option
to true or false affects only clocks created after the setting is changed. Clocks created before
the setting is changed retain their original condition (propagated or non-propagated).
application option on a specific design, use get_app_option -design $design -name
opt_name. Use report_app_options to show the value of multiple application options.
SEE ALSO
create_clock(2)
create_generated_clock(2)
set_app_options(2)
Chapter 1:
time.all_clocks_propagated
971
1-971
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.aocvm_analysis_mode
Configures advanced on-chip variation (AOCV) analysis.
TYPE
String
DEFAULT
separate_launch_capture_depth
DESCRIPTION
This option sets the configuration for advanced on-chip variation (AOCV) analysis. To
perform AOCV analysis, the time.ocvm_enable_analysis option must be set to aocvm.
In AOCV analysis, the derating factor for a path depends on the path depth, which is defined
as the number of successive cell (or net) delay timing arcs in a path from the common point
to the endpoint. The depth ranges and corresponding derating factors are specified in a
table, which is read into the tool with the read_ocvm command. Separate depth values are
calculated for cells and nets, and for launch and capture paths.
When this option is set to separate_launch_capture_dept, both clock and data networks
objects are included in the depth computation.
When this option is set to combined_launch_capture_depth, launch and capture depths
are not calculated separately. The launch and capture paths are considered together and a
combined depth is calculated for the entire path.
When this option is set to separate_data_and_clock_metrics, separate depths are
computed for the clock and data paths.
SEE ALSO
read_ocvm(2)
remove_ocvm(2)
report_ocvm(2)
report_timing(2)
time.ocvm_enable_analysis(3)
time.ocvm_enable_distance_analysis(3)
time.ocvm_precedence_compatibility(3)
972
time.aocvm_enable_clock_network_only(3)
Chapter 1:
973
1-973
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.aocvm_enable_analysis
Enable the advanced on-chip variation (advanced OCV) analysis.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When you set this option to true, the advanced OCV timing update is performed as part of
the update_timing command or any other functionality needing a timing update.
When this option is set to its default value, the advanced OCV timing update is not
performed.
SEE ALSO
read_ocvm(2)
remove_ocvm(2)
report_ocvm(2)
report_timing(2)
time.aocvm_analysis_type(3)
time.aocvm_enable_analysis
974
time.aocvm_enable_clock_network_only
Enables advanced on-chip variation (AOCV) analysis only for the clock network.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this option is set to true, advanced OCV derating is applied to arc delays in the clock
network only. Constant (OCV) derating is applied to data paths, if constant derating factors
have been annotated for data objects; otherwise they are not derated. Depth is calculated
based on clock network topology only; delay timing arcs in the data network are excluded
from depth calculations. This option is only effective when advanced on-chip variation
analysis has been enabled by setting the time.ocvm_enable_analysis option to aocvm.
SEE ALSO
read_ocvm(2)
remove_ocvm(2)
report_ocvm(2)
report_timing(2)
time.aocvm_enable_analysis(3)
Chapter 1:
time.aocvm_enable_clock_network_only
975
1-975
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.aocvm_enable_single_path_metrics
Configures advanced on-chip variation (AOCV) analysis.
TYPE
boolean
DEFAULT
false
DESCRIPTION
This variable determines if advanced OCV analysis accounts for depth and distance metrics
for cell arcs and net arcs separately. By default seperate accounts are kept and when
looking up cell derates the cell metrics are used and when looking net derates the net
metrics are used.
When this this variable is set to true, only cell arc metrics are computed and used to look
up both cell and net derates.
To restrict advanced OCV analysis to use only cell arc metrics, enter the following
command:
icc2_shell> set_app_options -name time.aocvm_enable_single_path_metrics -value true
To determine the current value of this variable, enter the following command:
icc2_shell> report_app_options time.aocvm_enable_single_path_metrics
SEE ALSO
read_ocvm(2)
remove_ocvm(2)
report_ocvm(2)
report_timing(2)
time.ocvm_enable_analysis(3)
time.aocvm_enable_single_path_metrics
976
time.case_analysis_propagate_through_icg
Determines whether case analysis is propagated through integrated clock gating cells.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this application option is set to false (the default), constants propagating throughout
the design will stop propagating when an integrated clock gating cell is encountered.
Regardless of whether the integrated clock gating cell is enabled or disabled, no logic values
will propagate in the fanout of the cell.
When the value is true, constants propagated throughout the design will propagate through
an integrated clock gating cell, provided the cell is enabled. An integrated clock gating cell
is enabled when its enable pin (or test enable pin) is set to a high logic value. If the cell is
disabled, then the disable logic value for the cell is propagated in its fanout. For example, for
a latch_posedge ICG, when it is disabled, it will propagate a logic 0 in its fanout.
Application options are set using the set_app_options command, and they may be specified
globally or with respect to a design. To determine the current value of this application option
on a specific design, use get_app_option_value -design $design -name
time.case_analysis_propagate_through_icg. Use report_app_options to show the value of
SEE ALSO
set_app_options(2)
remove_case_analysis(2)
set_case_analysis(2)
Chapter 1:
time.case_analysis_propagate_through_icg
977
1-977
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.case_analysis_sequential_propagation
Specifies whether case analysis is propagated across sequential cells.
TYPE
string
DEFAULT
never
DESCRIPTION
Determines whether case analysis is propagated across sequential cells. Allowed values
are never (the default) or always. When set to never, case analysis is not propagated across
the sequential cells. When set to always, case analysis is propagated across the sequential
cells.
application option on a specific design, use get_app_option_value -design $design
-name time.case_analysis_sequential_propagation. Use report_app_options to show
the value of multiple application options.
SEE ALSO
set_app_options(2)
time.case_analysis_sequential_propagation
978
time.clock_gating_propagate_enable
Allows the gating enable signal delay to propagate through the gating cell.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
When set to true (the default), the tool allows the delay and slew from the data line of the
gating check to propagate. When set to false, the tool blocks the delay and slew from the
data line of the gating check from propagating. Only the delay and slew from the clock line
is propagated.
If the output goes to a clock pin of a latch, setting this option to false produces the most
desirable behavior.
If the output goes to a data pin, setting this option to true produces the most desirable
behavior.
-name time.clock_gating_propagate_enable. Use report_app_options to show the
SEE ALSO
set_app_options(2)
Chapter 1:
time.clock_gating_propagate_enable
979
1-979
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.clock_gating_user_setting_only
When clock gating checks are not disabled, this application option controls whether
auto-inferred clock-gating checks for setup and hold violations are made.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When the time.disable_clock_gating_checks application option is set to true, the value of
the time.clock_gating_user_setting_only application option has no effect.
When the time.disable_clock_gating_checks application option is set to false (default),
this application option controls which set of clock-gating checks are created.
When the time.clock_gating_user_setting_only application option is set to true, it
disables auto-inferred clock-gating checks on objects that have not also had a
set_clock_gating_check command run against them.
This application option has no effect on library-specific clock-gating checks.
This application option has no equivalent application variable in PrimeTime.
Setting this application option to true may cause miscorrelation between IC Compiler II and
PrimeTime.
Setting this application option to true may allow better correlation between IC Compiler II
and IC Compiler since IC Compiler does not automatically infer clock-gating checks based
pin commonality along the clock network.
See the Solvnet article 015769 "How Are Clock Gating Checks Inferred?" for further
information on how clock-gating checks are inferred.
time.clock_gating_user_setting_only may only be set in the global and block-specific
context and is persistent.
980

-name time.use_pin_capacitance_ranges. Use report_app_options to show the value
of multiple application options.
SEE ALSO
set_app_options(2)
remove_clock_gating_check(2)
set_disable_clock_gating_check(2)
time.disable_clock_gating_checks(3)
report_clock_gating_checks(2)
Chapter 1:
981
1-981
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.clock_reconvergence_pessimism
Selects signal transition sense matching for computing clock reconvergence pessimism
removal.
TYPE
String
DEFAULT
normal
DESCRIPTION
Determines how the value of the clock reconvergence pessimism removal(CRPR) is
computed with respect to transition sense. Allowed values are as follows:
normal (default value)
same_transition
When set to normal, the CRPR value is computed even if the clock transitions to the source
and destination latches are in different directions on the common clock path. It is computed
separately for rise and fall transitions and the value with smaller absolute value is used.
When set to same_transition, the CRPR value is computed only when the clock transition
to the source and destination latches have a common path and the transition is in the same
direction on each pin of the common path. If the source and destination latches are triggered
by different edge types, CRPR is computed at the last common pin at which the launch and
capture edges match.
application option, use:
get_app_option_value -user_default -name
Use report_app_options to show the value of multiple application options.
982
SEE ALSO
set_app_options(2)
report_crpr(2)
time.remove_clock_reconvergence_pessimism(3)
time.crpr_remove_clock_to_data_crp(3)
Chapter 1:
983
1-983
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.convert_constraint_from_bc_wc
Specify conversion style to apply min/max values of timing constraints.
TYPE
Enum
DEFAULT
"none"
DESCRIPTION
This application option can be used to specify how the "-min" and "-max" values of timing
constraints are applied. Possible values are "none", "bc_only" and "wc_only". "none" is the
default.
Behavior for conversion styles:
- none : do nothing. Apply the constraint as given.
- bc_only : if -max value is given without -min, ignore the value.
Otherwise the value will be used for both max and min.
- wc_only : if -min value is given without -max, ignore the value.
Otherwise value will be used for both max and min.
This application option is global only, so cannot be specified on a design.
SEE ALSO
set_clock_latency(2)
set_clock_transition(2)
set_input_transition(2)
set_drive(2)
set_driving_cell(2)
set_load(2)
set_input_delay(2)
set_output_delay(2)
set_timing_derate(2)
time.convert_constraint_from_bc_wc
984
time.create_clock_no_input_delay
Specifies .
TYPE
Boolean
DEFAULT
false
DESCRIPTION
Affects delay propagation characteristics of clock sources created using create_clock.
When false (the default), clock sources used in the data path are established as timing
startpoints. The clock sources in the design propagate rising delays on every rising clock
edge, and propagate falling delays on every falling clock edge. When true, clock sources
are not considered as startpoints of data paths.
-name time.create_clock_no_input_delay. Use report_app_options to show the value
SEE ALSO
create_clock(2)
set_app_options(2)
Chapter 1:
time.create_clock_no_input_delay
985
1-985
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.crpr_remove_clock_to_data_crp
Allows the removal of Clock Reconvergence Pessimism (CRP) from paths that fan out
directly from clock source to the data pins of sequential devices.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this option is set to true then CRP will be removed for all paths that fan out directly
from clock source pins to the data pins of sequential devices.
When this option is set to false, only the CRP up to the clock source pin which fans out to
the data pin of the sequential device would be removed. This is because the path up to a
clock source pin is considered to be a clock path.
Consider the following example, where GCLK1 is a generated clock with CLK as its master
clock. In this case, the CRP between pins A and B would removed irrespective of the value
of the variable. However, when the variable is set to true, additional CRP between pins B
and C would also be removed.
+-- buff3 (D) --- FF1/D
|
A (CLK) --- buff1 (B GCLK1) --- buff2 (C) --- +-- buff4 (E) --- FF1/CP
application option use:
get_app_option_value -user_default -name
SEE ALSO
986
set_app_options(2)
report_crpr(2)
time.remove_clock_reconvergence_pessimism(3)
time.clock_reconvergence_pessimism(3)
Chapter 1:
987
1-987
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.delay_calculation_style
Controls how the timer calculates cell and net delays and slews.
TYPE
Enum
DEFAULT
"auto"
DESCRIPTION
This option controls how the timer calculates cell and net delays and slews. Possible values
are "auto", and "zero_interconnect". "auto" is the default. In "zero_interconnect" mode, cell
delays will be calculated assuming zero interconnect capacitance, and net delays will be
zero. Zero-interconnect analysis is always used for unplaced designs. In "auto" mode, tool
uses its default engine for net delay calculations.
specified globally or with respect to a design. To determine the current value of an
-name <app_option_name>. Use report_app_options to show the value of multiple
SEE ALSO
set_app_options(2)
time.delay_calculation_style
988
time.disable_case_analysis
Specifies whether case analysis is disabled.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When false (the default), constant propagation is performed in the design from pins either
that are tied to a logic constant value, or for which a set_case_analysis command is
specified. For example, a typical design has several pins set to a constant logic value. By
default, this constant value propagates through the logic to which it connects. When the app
option time.disable_case_analysis is true, case analysis and constant propagation are not
performed.
-name time.disable_case_analysis. Use report_app_options to show the value of
SEE ALSO
report_case_analysis(2)
set_app_options(2)
time.disable_case_analysis_ti_hi_lo(3)
Chapter 1:
time.disable_case_analysis
989
1-989
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.disable_case_analysis_ti_hi_lo
Determines whether case analysis is propagated from pins that are tied to a logic constant
value.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this variable is set to its default of false, constant propagation is performed from pins
that are tied to a logic constant value. For example, a typical design has several pins set to
a constant logic value. By default, this constant value propagates through the logic to which
it connects. When you set this variable to true, constant propagation is not performed from
these pins.
This current value of this variable does not alter the propagation of logic values from pins
where the logic value has been set by the set_case_analysis command.
If you set the time.disable_case_analysis app_option to true, all constant propagation is
disabled regardless of the current value of this app_option.
Application options are set using the set_app_options command, and they may be specified
globally or with respect to a design. To determine the current value of this application option
on a specific design, use get_app_option_value -design $design -name
time.disable_case_analysis_ti_hi_lo. Use report_app_options to show the value of multiple
SEE ALSO
set_app_options(2)
time.disable_case_analysis_ti_hi_lo
990
time.disable_clock_gating_checks
Controls whether or not checks for clock-gating setup and hold violations are inferred.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
The application option is equivalent to the PrimeTime
timing_disable_clock_gating_checks application variable. By default, both are false.
When set to false, all clock-gating checks, whether inferred or due to library cell checks, are
analyzed.
To achieve the same behaviour in IC Compiler as the default clock-gating behaviour in IC
Compiler II and PrimeTime, you would specify in IC Compiler
set_clock_gating_check setup 0 hold 0 [current_design]
When set to true, neither inferred clock gating checks, nor library specified checks will occur.
See the Solvnet article 015769 "How Are Clock Gating Checks Inferred?" for a complete
description of what constitutes a clock-gating situation.
This application option may be set in the global and block-specific context and is persistent.
-name time.disable_clock_gating_checks. Use report_app_options to show the value
SEE ALSO
remove_clock_gating_check(2)
Chapter 1:
991
1-991
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
set_app_options(2)
set_disable_clock_gating_check(2)
time.clock_gating_user_setting_only(3)
992
time.disable_cond_default_arcs
Disables the default, non-conditional timing arc between pins that have conditional arcs.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When true, disables nonconditional timing arcs between any pair of pins that have at least
one conditional arc. When false (the default), these nonconditional timing arcs are not
disabled. This application option is primarily intended to deal with the situation between two
pins that have conditional arcs, where there is always a default timing arc with no condition.
Set this application option to true when the specified conditions cover all possible
state-dependent delays, so that the default arc is useless. For example, consider a 2-input
XOR gate with inputs as A and B and with output as Z. If the delays between A and Z are
specified with 2 arcs with respective conditions 'B' and 'B~", the default arc between A and
Z is useless and should be disabled.
-name time.disable_cond_default_arcs. Use report_app_options to show the value of
SEE ALSO
report_disable_timing(2)
set_app_options(2)
Chapter 1:
time.disable_cond_default_arcs
993
1-993
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.disable_internal_inout_net_arcs
Controls whether bidirectional feedback paths across nets are disabled or not.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
When true (the default), the tool automatically disables bidirectional feedback paths that
involve more than one cell; no path segmentation is required. Note that only the feedback
net arc between non-bidirectional driver and load is disabled. When false, these bidirectional
feedback paths are enabled.
-name time.disable_internal_inout_net_arcs. Use report_app_options to show the
SEE ALSO
set_app_options(2)
time.disable_internal_inout_net_arcs
994
time.disable_recovery_removal_checks
Disable or enable the timing analysis of recovery and removal checks in the design.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When true, disables recovery and removal timing analysis. When false (the default), the tool
performs recovery and removal checks; for descriptions of these checks, see the man page
for the report_constraint command.
-name time.disable_recovery_removal_checks. Use report_app_options to show the
SEE ALSO
set_app_options(2)
Chapter 1:
time.disable_recovery_removal_checks
995
1-995
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.early_launch_at_latch_loop_breaker
Removes clock latency pessimism from the launch times for paths which begin at the data
pins of transparent latch loop breakers.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
When a latch loop breaker is in its transparent phase, data arriving at the D-pin passes
through the element as though it were combinational. To model this scenario, whenever IC
Compiler II determines that time borrowing occurs at such a D-pin, paths which originate at
the D-pin are created.
Sometimes there is a difference between the launching and capturing latch latencies, due
either to reconvergent paths in the clock network or different min and max delays of cells in
the clock network. For setup paths, IC Compiler II uses the late value to launch and the early
value to capture. This achieves the tightest constraint and avoids optimism. However, for
paths starting from latch D-pins this is pessimistic since data simply passes through and
thus does not even "see" the clock edge at the latch.
When this application option is set to true (the default), such pessimism is eliminated by
using the early latch latency to launch such paths. Note that only paths which originate from
a latch D-pin are affected. When the variable is set to false, late clock latency is used to
launch all setup paths in the design.
It is recommended that the user avail of this form of pessimism removal since it does not
cause the run-time of the analysis to increase. However, it is also advised that the user
disable it when clock reconvergence pessimism removal (CRPR) is enabled (i.e. when
time.remove_clock_reconvergence_pessimism is true). CRPR may not be applied to
paths which have been launched using an early latency or the results may be optimistic.
Since CRPR is a more sophisticated and accurate means of pessimism removal, the user
should disable time.early_launch_at_borrowing_latches when CRPR is enabled so that
CRPR applies to all paths in the design. In this mode, note that the D-pin launch time is not
modified by the open edge CRP - since late launch latency is used at the path startpoint, to
additionally add CRP would be pessimistic, representing a "double-counting" of early-late
996
differences. To determine the current value of this variable, type get_app_option_value

-name time.early_launch_at_latch_loop_breaker
SEE ALSO
set_app_options(2)
Chapter 1:
997
1-997
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.edge_specific_source_latency
Controls whether or not the generated clock source latency computation considers edge
relationship.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
When true, only paths with the same sense relationship derived from generated clock
definition are considered.
When this variable is set to false, all paths that fanout to a generated clock source pin are
considered and the worst path is selected for generated clock source latency computation.
When this variable is set to true, and the is no path with the sense relationship that matches
the generated clock definition a warning (GRF-011) is given and zero latency is used.
SEE ALSO
set_app_options(2)
time.edge_specific_source_latency
998
time.enable_clock_propagation_through_preset_clear
Enables propagation of clock signals through preset and clear pins.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this option is set to true, clock signals will be propagated through the preset and clear
pins of a sequential device. Naturally, this will only occur when clock signals are incident on
such pins.
If clock reconvergence pessimism removal (CRPR) is enabled it will consider any sequential
devices in the fanout of such pins for analysis.
-name time.enable_clock_propagation_through_preset_clear. Use
SEE ALSO
set_app_options(2)
Chapter 1:
time.enable_clock_propagation_through_preset_clear
999
1-999
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.enable_clock_propagation_through_three_state_enable_pin
s
Allow clocks to propagate through the enable pin of a three-state cell.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When true, clocks can propagate through the enable pins of three-state cells. When false
(the default), the tool will not propagate clocks between a pair of pins if there is at least one
timing arc with a disable sense between those pins.
-name time.enable_clock_propagation_through_three_state_enable_pins. Use
SEE ALSO
set_app_options(2)
time.enable_clock_propagation_through_three_state_enable_pins
1000
time.enable_clock_to_data_analysis
Enables ideal clock transition and network latency for clock-to-data interface pins
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When true, this option enables timing analysis of clock-to-data pins when the clock is ideal.
The ideal clock latency is used as the data arrival time at the clock-to-data pin, and the ideal
transition is used as data transition time at that pin. If more than one clock drives the data
pin, the worst latency and transition values apply.
When the variable is set to false (the default), the tool uses the actual propagated clock
latency and transition time at the clock-to-data pin, if any, and ignores any ideal clock latency
and transition time set for the clock.
You can set the ideal latency and ideal transition time of a clock by using the
set_clock_latency and set_clock_transition commands.
application option on a specific block, use: get_app_option_value -block $block -name
time.enable_clock_to_data_analysis get_app_option_value -user_default -name
time.enable_clock_to_data_analysis Use report_app_options to show the value of
SEE ALSO
create_clock(2)
set_clock_latency(2)
set_clock_transition(2)
Chapter 1:
time.enable_clock_to_data_analysis
1001
1-1001
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.enable_io_path_groups
Specifies whether I/O path groups are enabled or disabled.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When true, this option enables I/O path group costing and reporting. I/O path group is a new
special group path under group_path category. This enables user to group and report
boundary and I/O paths. It comes under inbuilt group paths.
I/O path group has following three sub-groups, each having their reserved names :
1. Input port to register
2. Register to Output port
3. Input port to Output port
(**in2reg_default **)
(**reg2out_default **)
(**in2out_default **)
I/O path group has following properties:

1. They belong to special inbuilt path group category.
2. By default they are disabled.
3. Default weight of each I/O path group is 1.0, which is
configurable.
4. They exists event before timer is created and can be listed using
commands: report_constraints or report_path_groups.
5. They cannot be removed using remove_path_groups command.
6. Toggling or setting value of this app option invalidates timer.
When false (the default), the tool disables I/O path group costing and reporting.
application option on a specific design, use: get_app_option_value -block $block -name
time.enable_io_path_groups get_app_option_value -user_default -name
time.enable_io_path_groups Use report_app_options to show the value of multiple
1002
SEE ALSO
set_app_options(2)
Chapter 1:
1003
1-1003
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.enable_non_sequential_checks
Enables or disables library nonsequential data checks in the design during timing analysis.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
This application option enables or disables analysis of library nonsequential data checks in
the design. The nonsequential arcs defined in the library will not be used for constraint
checking if this option is set to false. This option does not affect the data checks defined by
the set_data_check command.
Application options are set using the set_app_options command, and they can be
specified with respect to a design. Use get_app_option_value -name
time.enable_non_sequential_checks to retrieve the current value. Use set_app_options
-design <design_name> {time.enable_non_sequential_checks true|false} to set the
new value for a given design. Use report_app_options to show the value of multiple
SEE ALSO
set_data_check(2)
set_app_options(2)
time.enable_non_sequential_checks
1004
time.enable_preset_clear_arcs
Specifies whether preset and clear timing arcs are enabled or not.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When true, permanently enables asynchronous preset and clear timing arcs, so that you use
them to analyze timing paths. When false (the default), the tool disables all preset and clear
timing arcs.
-name time.enable_preset_clear_arcs. Use report_app_options to show the value of
SEE ALSO
set_app_options(2)
Chapter 1:
time.enable_preset_clear_arcs
1005
1-1005
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.gclock_source_network_num_master_registers
Specifies the maximum number of register clock pins clocked by the master clock allowed
in generated clock source latency paths.
TYPE
int
DEFAULT
10000000
DESCRIPTION
This option specifies the maximum number of register clock pins clocked by the master
clock allowed in generated clock source latency paths. This option does not affect the
number of registers traversed in a single path that do not have a clock assigned or are
clocked by another generated clock that has the same primary master as the generated
clock in question.
Register clock pins or transparent-D pins of registers clocked by unrelated clocks are not
traversed in determining generated clock source latency paths. An unrelated clock is any
clock that primary master clock differs from the generated clock whose source latency paths
are being computed.
-name time.gclock_source_network_num_master_registers. Use report_app_options
to show the value of multiple application options.
SEE ALSO
set_app_options(2)
time.gclock_source_network_num_master_registers
1006
time.high_fanout_net_pin_capacitance
Sets the pin capacitance of a high fanout net (HFN).
TYPE
Typed
DEFAULT
1pF
DESCRIPTION
This application option specifies the pin capacitance of a single terminal of a high fanout net.
The default value is 1pF.
This application option is used during net estimation. If a net has a number of terminals that
is greater than or equal to time.high_fanout_net_threshold, it is processed as a high
fanout net. For a high fanout net, actual net estimation is not performed in the design flow.
For a high fanout net, zero wire capacitance, saturated load capacitance, and default
thresholds are considered. The saturated load capacitance is calculated as: Saturated Load
Capacitance = {time.high_fanout_net_threshold *
time.high_fanout_net_pin_capacitance}
time.high_fanout_net_pin_capacitance to get the current value of this application option
on a specific design.
Use get_app_option_value -name time.high_fanout_net_pin_capacitance to retrieve
the current value. Use set_app_options {time.high_fanout_net_pin_capacitance
capacitance_value>} to set the new value.
Examples: prompt> get_app_option_value -name
time.high_fanout_net_pin_capacitance 1pF prompt> set_app_options
{time.high_fanout_net_pin_capacitance 1uF} prompt> get_app_option_value -name
time.high_fanout_net_pin_capacitance 1uF
Chapter 1:
1007
1-1007
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
set_app_options(2)
time.high_fanout_net_threshold(3)
1008
time.high_fanout_net_threshold
Sets the minimum number of net terminals or loads to classify a net as a high fanout net
(HFN).
TYPE
int
DEFAULT
1000
DESCRIPTION
This application option specifies the minimum number of net terminals which a net should
have to be considered as a high fanout net. The default value is 1000. This application
option is used during net estimation.
If a net has number of terminals greater than or equal to time.high_fanout_net_threshold,
it is processed as a high fanout net. For a high fanout net, actual net estimation is not
performed in the design flow. For a high fanout net, zero wire capacitance, saturated load
capacitance, and default thresholds are considered during net estimation. The saturated
load capacitance is calculated as:
Saturated Load Capacitance = {time.high_fanout_net_threshold *
time.high_fanout_net_pin_capacitance}
Use get_app_option_value -design $design -name time.high_fanout_net_threshold to
get the current value of this application option on a specific design.
Use get_app_option_value -name time.high_fanout_net_threshold to retrieve the
current value. Use set_app_options {time.high_fanout_net_threshold <value>} to set
the new value. Use report_app_options to show the value of multiple application options.
SEE ALSO
Chapter 1:
1009
1-1009
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
set_app_options(2)
time.high_fanout_net_pin_capacitance(3)
1010
time.ideal_clock_zero_default_transition
Specifies whether or not a zero transition value is assumed for sequential devices clocked
by ideal clocks.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
Specifies how transitions are treated at clock pins of a flip-flop. If set_clock_transition
command is used and the clock is ideal, the specified transition value will be used. If the
clock transition is not set by the set_clock_transition command, and the clock is ideal, then
this option will have the following effect. When true (the default), the tool uses a zero
transition value for ideal clocks. When false, the tool uses a propagated transition value.
Note that set_clock_transition will override the effect of this option for ideal clocks.
-name time.ideal_clock_zero_default_transition. Use report_app_options to show the
SEE ALSO
set_app_options(2)
Chapter 1:
time.ideal_clock_zero_default_transition
1011
1-1011
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.ocvm_enable_distance_analysis
Enables distance analysis support in advanced on-chip variation (AOCV) analysis.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this option is set to true, the tool calculates derating values for timing arcs based on
both the distance of the path (physical range of the path) and the depth of the path (the
number of successive gates in the path).
When this option is set to false, the tool uses only uses the worst-case distance information
in the table to calculate the derating values, which is more pessimistic than using all of the
distance information.
This option setting has an effect only under the following conditions:
Advanced on-chip variation analysis has been enabled by setting the

time.ocvm_enable_analysis option to aocvm.
The AOCV data tables contain distance dependency information.
The tool has access to information about the physical locations of the cells and nets in
the timing paths, so it can calculate the physical span of each timing arcs.
SEE ALSO
read_ocvm(2)
remove_ocvm(2)
report_ocvm(2)
report_timing(2)
time.ocvm_enable_distance_analysis
1012
time.ocvm_precedence_compatibility
Control the fallback to on-chip variation (OCV) derates when advanced OCV is enabled.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this option is set to true, the OCV derate settings are completely ignored if AOCV
tables are available.
When this option is set to false, for each object, both OCV and AOCV derate settings are
considered, and the more specific setting is used. This is the default order of usage, from
highest to lowest priority:
i.
ii.
iii.
iv.
v.
vi.
vii.
OCV leaf cell derate setting

AOCV lib-cell derate setting
OCV lib-cell derate setting
AOCV hier-cell derate setting
OCV hier-cell derate setting
AOCV design derate setting
OCV design derate
This option is effective only when time.ocvm_enable_analysis is set to do advanced OCV

analysis.
SEE ALSO
read_ocvm(2)
remove_ocvm(2)
report_ocvm(2)
report_timing(2)
Chapter 1:
1013
1-1013
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
1014
time.pocvm_corner_sigma
Specifies the standard deviation used to calculate worst-case values from statistical
parameters during parametric on-chip variation analysis.
TYPE
float
DEFAULT
3
DESCRIPTION
Parametric on-chip variation (POCV) analysis internally computes arrival times, required
times, and slack values based on statistical distributions. When performing comparisons
between these statistical quantities, the tool needs to know what values in the distribution
are considered worst-case.
The default behavior is to choose values at 3.0 standard deviations away from the mean
value. In other words, for an arrival time distribution, the worst-case early arrival is 3.0
standard deviations below the mean, and the worst-case late arrival is 3.0 standard
deviations above the mean.
You can use this variable set a different number of standard deviations away from the mean
to determine the worst-case values for timing reports. Use a lower value such as 2.5 for less
worst-case variation and more relaxed timing constraints. Conversely, use a higher value
such as 3.5 for more worst-case variation and more restrictive timing constraints.
SEE ALSO
time.pocvm_enable_analysis(3)
Chapter 1:
time.pocvm_corner_sigma
1015
1-1015
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.pocvm_enable_analysis
Enable the parametric on-chip variation (POCV) analysis.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When you set this option to true, the parametric on-chip variation timing update is performed
as part of the update_timing command or any other functionality needing a timing update.
When this option is set to its default value, the POCV timing update is not performed.
SEE ALSO
read_ocvm(2)
remove_ocvm(2)
report_ocvm(2)
report_timing(2)
time.pocvm_enable_analysis
1016
time.port_input_threshold_fall
Specifies the threshold voltage that defines the startpoint of the falling cell or net delay
calculation.
TYPE
float
DEFAULT
50.0
DESCRIPTION
This application option specifies the threshold voltage that defines the startpoint of the falling
cell or net delay calculation. The value is a percentage of the voltage source. Allowed values
are 0.0 through 100.0, inclusive.
This option is one of eight application options that affect delay and transition time
computations for detailed RC networks.
time.port_slew_lower_threshold_rise (default is 20.0)
time.port_slew_lower_threshold_fall (default is 20.0)
time.port_slew_upper_threshold_rise (default is 80.0)
time.port_slew_upper_threshold_fall (default is 80.0)
time.port_input_threshold_rise (default is 50.0)
time.port_input_threshold_fall (default is 50.0)
time.port_output_threshold_rise (default is 50.0)
time.port_output_threshold_fall (default is 50.0)
These application options interpret the cell delays and transition times from the reference
library. The trip-point values specified in the library override the values specified by these
options, so normally it should not be necessary to set the options. The specified values are
applied only to libraries that do not contain trip-point specifications.
The default values specify that a cell delay is defined from 50 percent of the voltage value
for the input transition to 50 percent of the voltage value for the output transition. The default
Chapter 1:
1017
1-1017
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
values also specify that a transition time, or slew, is defined from 20 percent to 80 percent of
the voltage.
-name time.port_input_threshold_fall command. For a list of all calc application options
and their current values, use the report_app_options calc.* command.
EXAMPLES
The following example specifies that cell delays are computed from 50 percent of the input
transition to 55 percent of the output transition. In addition, the example specifies that
transition times represent the delay from 10 percent to 90 percent of the voltage source.
prompt> set_app_options -list {
{time.port_slew_lower_threshold_fall
{time.port_slew_lower_threshold_rise
{time.port_slew_upper_threshold_fall
{time.port_slew_upper_threshold_rise
{time.port_input_threshold_rise
{time.port_input_threshold_fall
{time.port_output_threshold_rise
{time.port_output_threshold_fall
}
10}
10}
90}
90}
50}
50}
55}
55}
SEE ALSO
set_app_options(2)
time.port_input_threshold_rise(3)
time.port_output_threshold_fall(3)
time.port_output_threshold_rise(3)
time.port_slew_lower_threshold_fall(3)
time.port_slew_lower_threshold_rise(3)
time.port_slew_upper_threshold_fall(3)
time.port_slew_upper_threshold_rise(3)
1018
time.port_input_threshold_rise
Specifies the threshold voltage that defines the startpoint of the rising cell or net delay
calculation.
TYPE
float
DEFAULT
50.0
DESCRIPTION
This application option specifies the threshold voltage that defines the startpoint of the rising
Chapter 1:
1019
1-1019
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
the voltage.
-name time.port_input_threshold_rise command. For a list of all calc application options
EXAMPLES
}
10}
10}
90}
90}
50}
50}
55}
55}
SEE ALSO
set_app_options(2)
time.port_input_threshold_fall(3)
1020
time.port_output_threshold_fall
Specifies the threshold voltage that defines the endpoint of the falling cell or net delay
calculation.
TYPE
float
DEFAULT
50.0
DESCRIPTION
This application option specifies the threshold voltage that defines the endpoint of the falling
Chapter 1:
1021
1-1021
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
the voltage.
-name time.port_output_threshold_fall command. For a list of all calc application options
EXAMPLES
}
10}
10}
90}
90}
50}
50}
55}
55}
SEE ALSO
set_app_options(2)
1022
time.port_output_threshold_rise
Specifies the threshold voltage that defines the endpoint of the rising cell or net delay
calculation.
TYPE
float
DEFAULT
50.0
DESCRIPTION
This application option specifies the threshold voltage that defines the endpoint of the rising
Chapter 1:
1023
1-1023
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
the voltage.
-name time.port_output_threshold_rise command. For a list of all calc application options
EXAMPLES
}
10}
10}
90}
90}
50}
50}
55}
55}
SEE ALSO
set_app_options(2)
1024
time.port_slew_derate_from_library
Specifies the derating needed for the transition times in the reference library to match the
transition times between the characterization trip points.
TYPE
float
DEFAULT
1.0
DESCRIPTION
This application option specifies a floating-point number between 0.0 and 1.0 that indicates
the derating needed for the transition times in the reference library to match the transition
times between the characterization trip points.
The default is 1.0, which means that the transition times in the reference library are used
without change.
The slew-derating values specified in the reference library override this value, so it should
not be necessary to set this application option. The specified value applies only to libraries
that do not contain slew-derating specifications.
Use a slew-derating value of 1.0 if the transition times specified in the library represent the
exact transition times between the characterization trip points, which is usually the case.
Use a slew-derating value of less than 1.0 for libraries where the transition times have been
extrapolated to the rail voltages. For example, if the transition times are characterized as
between 30 percent and 70 percent and then extrapolated to the rails, the slew-derating
value is 0.4 = (70 - 30) / 100.
-name time.port_slew_derate_from_library command. For a list of all calc application
options and their current values, use the report_app_options calc.* command.
Chapter 1:
1025
1-1025
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
EXAMPLE
The following example specifies that transition times were computed by measuring the delay
from 30 percent to 70 percent of the voltage source and then multiplying the measured
transition times by 2.5 = (100-0)/(70-30) to extrapolate to 0-100 percent of the rail voltages.
-name time.port_slew_derate_from_library -value 0.4
SEE ALSO
set_app_options(2)
1026
time.port_slew_lower_threshold_fall
Specifies the threshold voltage that defines the endpoint of the falling slew calculation.
TYPE
float
DEFAULT
20.0
DESCRIPTION
This application option specifies the threshold voltage that defines the endpoint of the falling
slew calculation. The value is a percentage of the voltage source. Allowed values are 0.0
through 100.0, inclusive.
Chapter 1:
1027
1-1027
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
the voltage.
-name time.port_slew_lower_threshold_fall command. For a list of all calc application
EXAMPLES
}
10}
10}
90}
90}
50}
50}
55}
55}
SEE ALSO
set_app_options(2)
1028
time.port_slew_lower_threshold_rise
Specifies the threshold voltage that defines the startpoint of the rising slew calculation.
TYPE
float
DEFAULT
20.0
DESCRIPTION
This application option specifies the threshold voltage that defines the startpoint of the rising
Chapter 1:
1029
1-1029
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
the voltage.
-name time.port_slew_lower_threshold_rise command. For a list of all calc application
EXAMPLES
}
10}
10}
90}
90}
50}
50}
55}
55}
SEE ALSO
set_app_options(2)
1030
time.port_slew_upper_threshold_fall
Specifies the threshold voltage that defines the startpoint of the falling slew calculation.
TYPE
float
DEFAULT
80.0
DESCRIPTION
This application option specifies the threshold voltage that defines the startpoint of the falling
Chapter 1:
1031
1-1031
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
the voltage.
-name time.port_slew_upper_threshold_fall command. For a list of all calc application
EXAMPLES
}
10}
10}
90}
90}
50}
50}
55}
55}
SEE ALSO
set_app_options(2)
1032
time.port_slew_upper_threshold_rise
Specifies the threshold voltage that defines the endpoint of the rising slew calculation.
TYPE
float
DEFAULT
80.0
DESCRIPTION
This application option specifies the threshold voltage that defines the endpoint of the rising
Chapter 1:
1033
1-1033
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
the voltage.
-name time.port_slew_upper_threshold_rise command. For a list of all calc application
EXAMPLES
}
10}
10}
90}
90}
50}
50}
55}
55}
SEE ALSO
set_app_options(2)
1034
time.remove_clock_reconvergence_pessimism
Enables or disables clock reconvergence pessimism removal.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
When this option is set to true, the tool removes clock reconvergence pessimism from the
slack calculation.
Clock reconvergence pessimism (CRP) is the difference in delay along the common part of
the launching and capturing clock paths. The most common causes of CRP are
reconvergent paths in the clock network, and the difference in early and late arrivals in the
clock network.
CRP is independently calculated for rise and fall clock paths. You can use the
time.clock_reconvergence_pessimism option to control CRP calculation method with
respect to transition sense.
If the capturing device is a level-sensitive latch, two CRP values will be calculated:
crp_open, which is the CRP corresponding to the opening edge of the latch
crp_close, which is the CRP corresponding to the closing edge of the latch
CRP does not support paths that fan out directly from clock source pins to the data pins of
sequential devices. To enable support for such paths, set the
time.crpr_remove_clock_to_data_crp option to true.
application option, use the following command:
get_app_option_value -name time.remove_clock_reconvergence_pessimism
Chapter 1:
1035
1-1035
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
report_crpr(2)
set_app_options(2)
time.crpr_remove_clock_to_data_crp(3)
1036
time.report_with_clock_path_edrc
Report with clock path electrical drc constraints.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
Clock path constraints are set on clocks using set_max_transtion and set_max_capacitance
commands with option, -clock_path.
When this global option is set to false, the report commands, report_constraint and
report_qor, ignore clock path constraints on clocks in reporting max_transition and
max_capacitance violations. This is non-default reporting. When max_transition and max
capacitances are reported, such reports are generated with a comment, at the top of the
report, as follows:
"Generated with option time.report_with_clock_path_edrc false."
When set to true, it generates normal(default) reports considering clock path constraints.
This can be used to generate reports that are comparable to other tools where clock path
constraints are not supported in report commands.
The app option, when set to true(default), does not have any runtime overhead. When set to
false, the report commands check and recompute costs of some nets to generate new costs
and violation counts. This will increase runtime for non-default reports. But, this does not
invalidate stored costs, so rest of the flow has no runtime impact.
application option, use:
get_app_option_value -name time.report_with_clock_path_edrc.
Chapter 1:
1037
1-1037
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
set_app_options(2)
report_qor(2)
report_constraint(2)
set_max_transition(2)
set_max_capacitance(2)
1038
time.scenario_auto_name_separator
Specifies the string used to format auto-generated scenario names.
TYPE
string
DEFAULT
"::"
DESCRIPTION
If create_scenario is used to create a scenario without specifying the -name option, the
new name for the scenario will be auto-generated by concatenating the mode name, the
separator string, and the corner name. The default separator string is "::", so a command like
create_scenario -mode modeX -corner cornerY creates a scenario named
"modeX::cornerY". This app option can be used to specify a different separator string, such
as "/", instead of "::".
timer.enable_preset_clear_arcs. Use report_app_options to show the value of multiple
SEE ALSO
create_scenario(2)
report_scenarios(2)
set_app_options(2)
Chapter 1:
time.scenario_auto_name_separator
1039
1-1039
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.si_enable_analysis
Enables crosstalk analysis during timing analysis.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This application option controls crosstalk analysis during timing analysis. By default,
crosstalk analysis is not enabled. Turning this option on clears the existing delay data and
any stored parasitics in the timer. When set to "true", this application option also sets up the
extraction of the routed nets along with their coupling caps.
Use get_app_option_value -design $design -name time.si_enable_analysis to get the
current value of this application option on a specific design.
Use get_app_option_value -name time.si_enable_analysis to retrieve the current value.
Use set_app_options -as_user_default {time.si_enable_analysis true|false} to set the
new value. Use report_app_options to show the value of multiple application options.
SEE ALSO
set_app_options(2)
time.si_enable_analysis
1040
time.use_lib_cell_generated_clock_name
Specifies how generated clock names are derived from library files.
TYPE
Boolean
DEFAULT
false
DESCRIPTION
This variable specifies how generated clock names are derived from library files; you must
set this variable before linking the design:
false - Derives the name of the generated clock from the name of its source pin or the
first source pin name in case of multisource generated clocks.
true - Takes the generated clock name directly taken from the explicit specification in the
library.
SEE ALSO
link_design(2)
report_clock(2)
Chapter 1:
time.use_lib_cell_generated_clock_name
1041
1-1041
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
time.use_pin_capacitance_ranges
Controls the usage of library pin capacitance range data.
TYPE
Boolean
DEFAULT
true
DESCRIPTION
Affects calculation of libcell pin capacitances. If a libcell pin's library definition contains
capacitance range parameters, they will by default be used to calculate the best-case and
worst-case capacitances of the pin. The best-case value will be used for early timing
analysis, and the worst-case for late timing analysis. If this option is set to false, any
capacitance range parameters will be ignored, and the nominal pin capacitance will be used
for early and late analysis.
-name time.use_pin_capacitance_ranges. Use report_app_options to show the value
SEE ALSO
set_app_options(2)
time.use_pin_capacitance_ranges
1042
timing_arc_attributes
Lists the predefined attributes for timing arcs.
DESCRIPTION
timing_arc attributes are provided in the subsections that follow.
command.
Timing Arc Attributes
from_pin
A collection attribute returning the from pin for a timing_arc. If this timing_arc is for a timing
check such as setup or hold, the from pin is the clock pin of the check.
invalid_reason
A string attribute for the reason why the timing arc is not an active arc. See the description
of is_disable and is_invalid attributes. The possible invalid_reason strings are:
set_disable_timing
auto_loop_breaking
inherited_loop_breaking
user_case_0
user_case_1
netlist_tie_0
netlist_tie_1
case_disabled
case_0
case_1
conditional_arc_disabled
default_arc_disabled
mode_values_disabled
pin_disabled
lib_arc_disabled
preset_clear_disabled
Chapter 1:
1043
1-1043
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
is_cellarc
A Boolean attribute that is true if this timing arc is for a cell. If this attribute is true both the
from_pin and to_pin will be on the same cell.
is_db_inherited_disabled
A Boolean attribute that is true if the timing_arc is disabled because of a property from
another tool.
is_disabled
A Boolean attribute for whether this timing arc is disabled. This attribute has the same
definition as it does in PrimeTime. It is true only if the arc has been directly disabled by
set_disable_timing, case propagation, loop breaking, and arc modes or conditions
disabled. This attribute is true for a subset of the timing arcs that is_invalid attribute is true
for. It does not include timing_arcs that are disabled indirectly. Examples of timing_arcs that
are disabled indirectly are timing arcs where the lib_timing_arc are disable or those with
either the from or to pin disabled.
is_invalid
A Boolean attribute for whether this timing arc is not active. This attribute is true for a
superset of the timing arcs that is_disable attribute is true for. See the description of the
attribute "invalid_reason" for the possible reasons a timing_arc might be invalid.
is_user_disabled
A Boolean attribute for whether this timing arc has been disabled by the user.
mode
A string attribute with the name of the mode this timing arc is active for. The attribute will is
only defined for moded arcs.
object_class
A string attribute with the value of "timing_arc". Each object class has a different object class
value.
sense
A string attribute for the sense of a timing_arc. Possible values are
rising_edgerising_to_rise falling_to_rise
1044
falling_edge rising_to_fall falling_to_fall

rise_to_rise fall_to_rise rise_to_fall
fall_to_fall positive_unate negative_unate
non_unate clear_high clear_low
clear_both preset_high preset_low
preset_both disable_high disable_low
disable_both disable_high_rise
disable_low_rise disable_both_rise
disable_high_fall disable_low_fall
disable_both_fall
enable_high enable_low enable_both
enable_high_rise enable_low_rise enable_both_rise
enable_high_fall enable_low_fall enable_both_fall
retain_rising_edge retain_rise_to_rise
retain_fall_to_rise retain_falling_edge
retain_rise_to_fall retain_fall_to_fall
retain_positive_unate retain_negative_unate
retain
max_clock_tree_positive_unate max_clock_tree_rise_to_rise
max_clock_tree_fall_to_fall max_clock_tree_negative_unate
max_clock_tree_rise_to_fall max_clock_tree_fall_to_rise
max_clock_tree_non_unate min_clock_tree_positive_unate
min_clock_tree_rise_to_rise min_clock_tree_fall_to_fall
min_clock_tree_negative_unate min_clock_tree_rise_to_fall
min_clock_tree_fall_to_rise min_clock_tree_non_unate
nonseq_setup_clk_rise nonseq_setup_rise_clk_rise
nonseq_setup_fall_clk_rise nonseq_setup_clk_fall
nonseq_setup_rise_clk_fall nonseq_setup_fall_clk_fall
nonseq_hold_clk_rise nonseq_hold_rise_clk_rise
nonseq_hold_fall_clk_rise nonseq_hold_clk_fall
nonseq_hold_rise_clk_fall nonseq_hold_fall_clk_fall
clock_gating_setup_clk_rise clock_gating_setup_rise_clk_rise
clock_gating_setup_fall_clk_rise clock_gating_setup_clk_fall
clock_gating_setup_rise_clk_fall clock_gating_setup_fall_clk_fall
clock_gating_hold_clk_rise clock_gating_hold_rise_clk_rise
to_pin
A collection attribute returning the to pin for a timing_arc. If this timing_arc is for a timing
check such as setup or hold, the from pin is the data pin of the check.
user_clock_sense
define on those pins where the set_clock_sense command was used directly. The possible
values are: "positive", "negative", "rise_triggered_low_pulse", "rise_triggered_high_pulse",
"fall_triggered_low_pulse", "fall_triggered_high_pulse".
when
A string attribute returning the when value for the timing_arc.
Chapter 1:
1045
1-1045
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
SEE ALSO
get_attribute(2)
list_attributes(2)
1046
timing_exception_attributes
Lists the predefined attributes for timing_exception objects.
DESCRIPTION
timing_exception attributes are provided in the subsections that follow.
command.
command_text
exception_type
A string attribute indicating the type of exception. Valid values are "false_path",
"multicycle_path", and "max_min_delay".
mode
A collection attribute returning the mode that contains the exception.
file_line_info
full_name
A string attribute returning a unique name for the exception.
hold_fall_end
A Boolean attribute; true if the exception is multicycle and the hold fall multiplier is relative to
the end clock.
Chapter 1:
1047
1-1047
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
hold_fall_multiplier
An int attribute for multicycle_path exceptions, specifying the multiplier value for hold fall.
hold_rise_end
A Boolean attribute; true if the exception is multicycle and the hold rise multiplier is relative
to the end clock.
hold_rise_multiplier
An int attribute for multicycle_path exceptions, specifying the multiplier value for hold rise.
is_hold_fall_false
A Boolean attribute; true if the exception is false_path, and the hold fall timing is set to be
false.
is_hold_rise_false
A Boolean attribute; true if the exception is false_path, and the hold rise timing is set to be
false.
is_setup_fall_false
A Boolean attribute; true if the exception is false_path, and the setup fall timing is set to be
false.
is_setup_rise_false
A Boolean attribute; true if the exception is false_path, and the setup rise timing is set to be
false.
max_fall_delay
A float attribute for max_min_delay exceptions. Specifies the delay value for max_fall.
max_rise_delay
A float attribute for max_min_delay exceptions. Specifies the delay value for max_rise.
min_fall_delay
A float attribute for max_min_delay exceptions. Specifies the delay value for min_fall.
1048
min_rise_delay
A float attribute for max_min_delay exceptions. Specifies the delay value for min_rise.
object_class
A string attribute, with the value "timing_exception".
setup_fall_multiplier
An int attribute for multicycle_path exceptions, specifying the multiplier value for setup fall.
setup_fall_start
A Boolean attribute; true if the exception is multicycle and the setup fall multiplier is relative
to the start clock.
setup_rise_multiplier
An int attribute for multicycle_path exceptions, specifying the multiplier value for setup rise.
setup_rise_start
A Boolean attribute; true if the exception is multicycle and the setup rise multiplier is relative
to the start clock.
through_group_count
An int attribute specifying the number of -through, -rise_through, and/or -fall_through
options that were specified with the exception command. For example, if the exception was
specified as "-through {a1 a2 a3} -rise_through {b1 b2 b3}", the through_group_count
attribute value will be 2.
SEE ALSO
get_exceptions(2)
get_attribute(2)
list_attributes(2)
report_exceptions(2)
set_false_path(2)
set_max_delay(2)
set_min_delay(2)
set_multicycle_path(2)
Chapter 1:
1049
1-1049
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
timing_path_attributes
Description of the predefined attributes for timing_paths.
DESCRIPTION
timing_path attributes are provided in the subsections that follow.
command.
All timing_path attributes are read-only.
All time-valued attributes will be based on the user output units in effect when the attribute
value is gotten, not when the timing path was originally created.
The object-valued attributes (such as startpoint_clock, mode, corner, etc.) are not
guaranteed to have valid values if the design has been modified since the timing_path was
created. However, the corresponding "name" attributes (for example,
startpoint_clock_name) will always be valid, even if the object itself no longer exists.
Timing_path Attributes
arrival
A float attribute representing the timing_path's endpoint arrival time.
capture_clock_paths
A collection attribute representing the timing_path's capture clock path.
check_value
A float attribute representing the timing_path's check value: the setup or hold time for a
latch, or the output delay for a port.
1050
clock_uncertainty
A float attribute representing the timing_path's clock uncertainty time.
common_path_pessimism
A float attribute representing the timing_path's CRPR common_path pessimism time.
corner
A collection attribute representing the timing_path's corner.
corner_name
A string attribute representing the name of timing_path's corner.
crpr_common_point
A collection attribute representing the timing_path's CRPR common point.
design_name
A string attribute representing the name of the timing_path's design.
driving_cell_adjustment
A float attribute representing the timing_path's driving_cell adjustment time, for paths
starting at input ports.
endpoint
A collection attribute representing the timing_path's endpoint.
endpoint_clock
A collection attribute representing the timing_path's endpoint clock.
endpoint_clock_arrival_close_edge_type
A string attribute representing the timing_path's capture clock edge, as measured at the
endpoint. The value will be either "rise" or "fall".
Chapter 1:
1051
1-1051
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
endpoint_clock_close_edge_arrival
A float attribute representing the arrival time of the close edge of the capture clock, at the
endpoint.
endpoint_clock_close_edge_type
A string attribute representing the timing_path's capture clock edge, as measured at the
endpoint_clock_close_edge_value
A float attribute representing the time of the close edge of the capture clock, measured at
the clock source.
endpoint_clock_name
A string attribute representing the name of the timing_path's endpoint clock.
endpoint_clock_period
A float attribute representing the period of the timing_path's endpoint clock.
endpoint_name
A string attribute representing the name of the timing_path's endpoint.
full_name
A string attribute representing the timing_path's name, which is synthesized from some of its
input_delay
A float attribute representing the timing_path's startpoint input delay, if the startpoint has a
set_input_delay constraint.
launch_clock_paths
A collection attribute representing the timing_path's launch clock path.
lib_name
A string attribute representing the name if the library containig the timing_path's design.
1052
mode
A collection attribute representing the timing_path's mode
mode_name
A string attribute representing the name of timing_path's mode.
name
A string attribute representing the timing_path's name, which is synthesized from some of its
network_latency
A float attribute representing the timing_path's
object_class
A string attribute with the value "timing_path".
path_group
A collection attribute representing the timing_path's pathgroup.
path_group_name
A string attribute representing the name of the timing_path's pathgroup.
path_type
A string attribute representing the timing_path's analysis type, either "min" or "max".
points
A collection attribute representing the timing_path's points.
propagation_type
Equivalent to the path_type attribute, with a value of "min" or "max".
required
A float attribute representing the timing_path's required time.
Chapter 1:
1053
1-1053
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
scenario
A collection attribute representing the timing_path's scenario.
scenario_name
A string attribute representing the name of the timing_path's scenario.
slack
A float attribute representing the timing_path's slack.
source_latency
A float attribute representing the timing_path's startpoint source latency.
startpoint
A collection attribute representing the timing_path's startpoint.
startpoint_clock
A collection attribute representing the timing_path's launch clock
startpoint_clock_arrival_open_edge_type
A string attribute representing the timing_path's launch clock edge, as measured at the
startpoint. The value will be either "rise" or "fall".
startpoint_clock_name
A string attribute representing the name of the timing_path's launch clock.
startpoint_clock_open_edge_arrival
A float attribute representing the arrival time of the open edge of the launch clock, at the
startpoint.
startpoint_clock_open_edge_type
A string attribute representing the timing_path's launch clock edge, as measured at the
1054
startpoint_clock_open_edge_value
A float attribute representing the time of the open edge of the launch clock, measured at the
clock source.
startpoint_clock_period
A float attribute representing the timing_path's launch clock period.
startpoint_name
A string attribute representing the name of the timing_path's startpoint.
SEE ALSO
get_attribute(2)
list_attributes(2)
get_timing_paths(2)
report_timing(2)
set_user_units(2)
Chapter 1:
1055
1-1055
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
timing_point_attributes
Description of the predefined attributes for timing_points.
DESCRIPTION
timing_point attributes are provided in the subsections that follow.
command.
All timing_point attributes are read-only.
All time-valued or capacitnace-valued attributes will be based on the user output units in
effect when the attribute value is gotten, not when the timng_point was originally created.
The object-valued attributes (such as object) are not guaranteed to have valid values if the
design has been modified since the timing_point was created. However, the corresponding
"name" attributes (for example, object_name) will always be valid, even if the object itself no
longer exists.
Timing_point Attributes
arrival
A float attribute representing the timing_point's arrival time.
capacitance
A float attribute representing the timing_point's net capacitance.
delay
A float attribute representing the timing_point's delay, relative to the previous point in the
path.
1056
delta_delay
A float attribute representing the timing_point's SI delta-delay time. This will not be valid
unless SI analysis is turned on.
fanout
An integer attribute representing the timing_point's fanout. This will be valid only for net
drivers.
full_name
An string attribute representing the timing_point's name. This will be synthesized based on
the object name.
name
An string attribute representing the timing_point's name. This will be synthesized based on
the object name.
object
A collection attribute representing the timing_point's object: either a pin or a port.
object_class
A string attribute with the value "timing_point".
object_name
A string attribute representing the name of the timing_point's object.
rise_fall
A string attribute representing the timing_point's r/f value: either "rise" or "fall"..
transition
A float attribute representing the timing_point's transition time.
SEE ALSO
get_attribute(2)
Chapter 1:
1057
1-1057
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
list_attributes(2)
get_timing_paths(2)
report_timing(2)
set_user_units(2)
1058
topological_constraint_attributes
Description of the predefined topological pin feedthrough constraint attributes.
DESCRIPTION
Attributes are properties assigned to objects such as pins, cells and nets. Definitions for the
topological constraint attributes are provided in the subsections that follow.
command.
attributes available for the class of objects use the list_attributes -application command.
topological_constraint Attributes
full_name
A string attribute for the full name of a topological pin feedthrough constraint.
name
A string attribute for the name of a topological pin feedthrough constraint.
object_class
owner
start_object
end_object
Chapter 1:
1059
1-1059
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
start_sides
end_sides
start_offset
end_offset
start_offset_range
end_offset_range
start_layers
end_layers
SEE ALSO
create_topological_constraint(2)
get_topological_constraints(2)
remove_topological_constraints(2)
report_topological_constraints(2)
1060
topology_edge_attributes
Description of the predefined attributes for topology_edges.
DESCRIPTION
topology_edge attributes are provided in the subsections that follow.
command.
Topology Edge Attributes
constraint_groups
A collection representing the constraint_groups of which the topology_edge is a member.
endpoint0
A collection representing the pin, port, or topology_node to which the topology_edge's first
endpoint is connected. An empty collection indicates the endpoint is disconnected.
endpoint1
A collection representing the pin, port, or topology_node to which the topology_edge's
second endpoint is connected. An empty collection indicates the endpoint is disconnected.
full_name
A string attribute for the full name of the topology_edge.
max_layer
A collection representing the maximum layer constraint of this topology_edge.
Chapter 1:
1061
1-1061
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
min_layer
A collection representing the minimum layer constraint of this topology_edge.
name
A string attribute for the name of the topology_edge.
net
A collection representing the owner net of this topology_edge.
object_class
A string attribute with the value of "topology_edge".
spacing
A distance attribute specifying the spacing constraint of this topology_edge.
width
A distance attribute specifying the width constraint of this topology_edge.
SEE ALSO
get_topology_edges(2)
report_topology_edges(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
1062
topology_node_attributes
Description of the predefined attributes for topology_nodes.
DESCRIPTION
topology_node attributes are provided in the subsections that follow.
command.
Topology Node Attributes
adjacent_edges
A collection representing the topology_edges connected to the topology_node, i.e. the
topology_edges which have the topology_node as an endpoint.
boundary
A rectangle attribute for the constraint boundary of the topology_node. The format of a
full_name
A string attribute for the full name of the topology_node.
has_adjacent_edges
An boolean attribute for whether the topology_node has any topology_edges connected to
it, i.e. whether the topology_node is an endpoint of any topology_edges.
is_centroid
A Boolean attribute to specify whether the topology_node represents a virtual centroid pin..
Chapter 1:
1063
1-1063
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
is_driver
A Boolean attribute to specify whether the topology_node represents a virtual driver pin..
is_fixed
A Boolean attribute to specify whether the topology_node has locked physical_status.
layers
A collection representing the layer constraint as a set of specific layers of this
topology_node. The min_layer and max_layer attributes are mutually exclusive with the
layers attribute - either the layers attribute is non-empty, both min_layer and max_layer are
non-empty, or all three are empty. Setting min_layer or max_layer clears the layers attribute,
and setting the layers attribute to a collection of two or more layers clears the min_layer and
max_layer attributes.
max_layer
A collection representing the maximum layer constraint of this topology_node. The
min_layer and max_layer attributes are mutually exclusive with the layers attribute - either
the layers attribute is non-empty, both min_layer and max_layer are non-empty, or all three
are empty. Setting min_layer or max_layer clears the layers attribute, and setting the layers
attribute to a collection of two or more layers clears the min_layer and max_layer attributes.
min_layer
A collection representing the minimum layer constraint of this topology_node. The min_layer
and max_layer attributes are mutually exclusive with the layers attribute - either the layers
attribute is non-empty, both min_layer and max_layer are non-empty, or all three are empty.
Setting min_layer or max_layer clears the layers attribute, and setting the layers attribute to
a collection of two or more layers clears the min_layer and max_layer attributes.
name
A string attribute for the name of the topology_node.
net
A collection representing the owner net of this topology_node.
1064
num_adjacent_edges
An integer attribute for the number of topology_edges connected to the topology_node, i.e.
the topology_edges which have the topology_node as an endpoint.
object_class
A string attribute with the value of "topology_node".
physical_status
A string attribute representing the physical modification status of the topology node. Valid
values are unrestricted, minor_change, and locked.
SEE ALSO
get_topology_nodes(2)
report_topology_nodes(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
1065
1-1065
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
track_attributes
Lists the predefined attributes for tracks.
DESCRIPTION
track attributes are provided in the subsections that follow.
command.
Track Attributes
bbox
A rectangle attribute for the bounding-box of the track. The format of a rectangle
the rectangle.
design_name
A string attribute specifying the name of the design owning the track.
direction
A string attribute representing the routing direction of the track. Valid values are horizontal
and vertical.
full_name
A string attribute for the name of the track.
high
A distance attribute that specifies the highest x-coordinate for a track with horizontal tracks
or the highest y-coordinate for a track with vertical tracks.
track_attributes
1066
high_coordinate
A coordinate attribute that specifies the highest point of the track.
in_edit_group
A boolean attribute to specify whether the track belongs to an edit_group.
is_default
A boolean attribute to specify whether the track is a default track. A track may be either
default, non-reserved, or reserved. A default track may be used by any net and shape of any
width.
is_non_reserved
A boolean attribute to specify whether the track is a non-reserved track. A track may be
either default, non-reserved, or reserved. A non-reserved track is assigned a shape width
constraint. It may be used only by nets without a nondefault rule and shapes with widths
matching the track's assigned width constraint.
is_reserved
A boolean attribute to specify whether the track is a reserved track. A track may be either
default, non-reserved, or reserved. A reserved track is assigned a shape width constraint. It
may be used only by nets with a nondefault rule and shapes with widths matching the track's
assigned width constraint.
is_shadow
A boolean attribute to specify whether the track is pushed down from above.
layer
A collection attribute with the layer on which the track exists.
layer_name
A string attribute for the name of the layer on which the track exists.
layer_number
An integer attribute for the number of the layer on which the track exists.
Chapter 1:
track_attributes
1067
1-1067
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
low
A distance attribute that specifies the lowest x-coordinate for a track with horizontal tracks
or the lowest y-coordinate for a track with vertical tracks.
low_coordinate
A coordinate attribute that specifies the lowest point of the track.
name
A string attribute for the name of the track. This attribute is settable.
number_of_tracks
An integer attribute for the number of tracks in the track.
object_class
A string attribute with the value of "track".
object_id
An integer attribute that specifies the track identifier.
parent_block
A collection attribute with the owner block object for this track.
parent_block_cell
A collection attribute with the parent block cell object for this track.
parent_cell
A collection attribute with the owner cell object for this track.
shadow_status
A string attribute to represent the shadow status of the track. Valid values are copied_down,
copied_up, normal, pulled_up, pushed_down, and virtual_flat. This attribute is settable.
track_attributes
1068
space
A distance attribute that specifies the space between tracks.
start
A distance attribute that specifies the starting y-coordinate for a track with horizontal tracks
or the starting x-coordinate for a track with vertical tracks.
top_block
A collection attribute with the top block object for this track.
track_colors
A collection attribute with the list of colors used as a repeating pattern to define the colors
for the tracks. Each track (from low to high within the track coordinates) has a color based
on its numerical track value modulo the number of track colors, used as an index into the
track color collection. Note that the default for each track is "no_mask", indicating that no
specific mask is assigned to the track. Also note that the set of color masks is limited today
to three values, "mask_one", "mask_two", and "mask_three". Note that the pattern can
contain a maximum of five values that are repeated for all the tracks in the track
specification. Lastly, to remove a track color specification, set the attribute using an empty
list of values.
width
A distance attribute that specifies the shape width constraint for non-reserved and reserved
tracks.
SEE ALSO
get_attribute(2)
list_attributes(2)
Chapter 1:
track_attributes
1069
1-1069
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
utilization_config_attributes
Description of the predefined attributes for utilization_configs.
DESCRIPTION
Definitions for utilization_config attributes are provided in the subsections that follow.
command.
utilization_config Attributes
capacity
A string attribute based on which the utilization of the block will be reported.
exclusions
A string attribute stating the object types to be excluded from demand calculation. This
attribute accepts multiple values, in which case the value should be a list of strings.
name
A string attribute for the name of a utilization_config.
object_class
A string attribute with the value of "utilization_config".
scope
A string attribute indicating the scope of the utilization_config.
1070
SEE ALSO
create_utilization_configuration(2)
remove_utilization_configurations(2)
get_utilization_configurations(2)
report_utilization(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
1071
1-1071
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
via_attributes
Description of the predefined attributes for vias.
DESCRIPTION
Attributes are properties assigned to objects such as pins, cells and nets. Definitions for via
command.
Via Attributes
bbox
the rectangle.
cut_layers
A collection attribute for the cut layers of the via.
cut_layer_names
A string attribute for the cut layer names of the via.
design_name
A string attribute for the design_name of the via.
full_name
A string attribute for the full name of a via.
via_attributes
1072
has_net
A Boolean attribute. The value will be "true" if this via is connected to a net.
height
The height of the via.
in_edit_group
A Boolean attribute. The value will be "true" if this via is in any edit_group.
is_default_via
A Boolean attribute. The value will be "true" if this via is a default via for its upper and lower
metal layers.
is_shadow
A Boolean attribute. The value will be "true" if this via is a shadow via.
lower_layer
A collection representing the lower layer for the via.
lower_layer_name
Name of the lower layer for the via.
name
A string attribute for the name of a via.
net_type
The net type of net connected to the via. The value is one of, analog_ground, analog_power,
analog_signal, clock, deep_nwell, deep_pwell, ground, nwell, power, pwell, reset, scan,
signal, tie_high, tie_low or unset
number_of_columns
Number of columns if this is an array via.
Chapter 1:
via_attributes
1073
1-1073
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
number_of_rows
Number of rows if this is an array via.
object_class
A string attribute with the value of "via".
physical_status
A string attribute representing the physical modification status of the via. Valid values are
unrestricted, application_fixed, fixed, and locked. If status is unrestricted, the via may be
freely modified. If the status is application_fixed, the via is fixed by the application for
automatic changes (the application may change this status). If status is fixed, the via is fixed
by the user for automatic changes. If status is locked, the viae is fixed for automatic and
manual changes. This is a settable attribute.
shadow_status
A string attribute representing the shadow status of the via. The value is one of,
copied_down, copied_up, normal, pulled_up, pushed_down, or virtual_flat.
shape_use
A string attribute for shape use. The value is one of, area_fill, core_wire, detail_route,
follow_pin, global_route, lib_cell_pin_connect, macro_pin_connect, opc, rdl, ring,
shield_route, stripe, user_route or zero_skew.
upper_layer
A collection representing the upper layer for the via.
upper_layer_name
Name of the upper layer for the via.
via_def
A collection representing the via def for the via.
via_def_name
Via def name for the via.
via_attributes
1074
via_type
Via type for the via.
width
The width of the via.
x_pitch
Horizontal pitch if this is an array via
y_pitch
Vertical pitch if this is an array via
is_via_ladder
A bool attribute specifying whether via is part of a via ladder. This is not a settable attribute.
SEE ALSO
get_vias(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
via_attributes
1075
1-1075
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
via_def_attributes
Description of the predefined attributes for via_defs.
DESCRIPTION
Attributes are properties assigned to objects such as pins, cells and nets. Definitions for via
command.
Via_def Attributes
cut_height
The height of the cut_layer shape of a simple via_def.
cut_layer_names
A string attribute for the list of cut layer names for the via_def. A simple via_def has a single
cut_layer. A custom via_def may have more than one.
cut_layers
A collection representing the the cut layers of the via_def. A simple via_def has a single cut
layer. A custom via_def may have more than one.
cut_width
The width of the cut_layer shape of a simple via_def.
full_name
A string attribute for the full name of a via_def.
via_def_attributes
1076
is_default
A Boolean attribute. The value will be "true" if this via_def is a default via_def for its upper
and lower metal layers. Only a simple via_def may be a default via_def.
is_excluded_for_signal_route
A Boolean attribute. The value will be "true" if this via_def represents vias which are
excluded for use in signal (non-power) routing.
lower_enclosure_height
The height of the lower metal shape of a simple via_def.
lower_enclosure_width
The width of the lower metal shape of a simple via_def.
lower_layer
A collection representing the lower metal layer of a via_def.
lower_layer_name
Name of the lower metal layer of the via_def.
min_columns
The minimum number of columns of cuts on a via of this array simple via_def.
min_cut_spacing
The minimum cut spacing of a via with this array simple via_def.
min_rows
the minimum number of rows of cuts on a via of this array simple via_def.
name
A string attribute for the name of a via_def.
Chapter 1:
via_def_attributes
1077
1-1077
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
object_class
A string attribute with the value of "via_def".
owner
A collection representing the owner container of a via_def. The owner may be a block or a
tech.
shapes
A collection representing the shapes of a via_def. A custom via_def is defined by its shapes.
The shapes of a simple via_def are derived from its parameters.
source_type
A string attribute for the source type of a via_def. The value is one of: generated,
generated_for_special_nets, multiple_cut, multiple_cut_fixed, single_cut or
single_cut_fixed.
upper_enclosure_height
The height of the upper metal shape of a simple via_def.
upper_enclosure_width
The width of the upper metal shape of a simple via_def.
upper_layer
A collection representing the upper metal layer of a via_def.
upper_layer_name
Name of the upper metal layer of a via_def.
via_def_type
A string attribute for the type of a via_def. The value is one of: custom_via_def or
simple_via_def.
via_def_attributes
1078
SEE ALSO
get_via_defs(2)
report_via_defs(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
Chapter 1:
via_def_attributes
1079
1-1079
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
voltage_area_attributes
Description of the predefined attributes for voltage_areas.
DESCRIPTION
voltage_area attributes are provided in the subsections that follow.
command.
voltage_area Attributes
bbox
A rectangle attribute for the bounding-box of a voltage_area. The format of a rectangle
the rectangle.
cells
A collection attribute with the leaf cells explicitly or implicitly associated with this
voltage_area or its voltage_area_shapes.
color
An integer attribute for the color index of a voltage_area.
effective_guard_band_boundaries
A poly_list attribute for the effective guard_band boundaries of a voltage_area. The effective
guard_band boundary is calculated in the same way as in effective_shapes. The only
difference is that the region is expanded by the x and y guard_band margins.
1080
effective_rectangles
A poly_list attribute for the effective shapes of a voltage_area broken down into rectangles.
The format of a rectangle poly_list specification is { {{llx1 lly1} {urx1 ury1}} {{llx2 lly2} {urx2
ury2}}...}, which specifies a list of lower-left and upper-right corners of rectangles.
effective_shapes
A poly_list attribute for the effective shapes of a voltage_area. The effective_shape is
calculated by comparing the stacking_order of the voltage_area_shapes of a voltage_area
with all other voltage_area_shapes in the design and subtracting the overlapping region
from the regions with lower stacking_order, and merging abutting shapes within the same
voltage_area. The format of poly_list specification is {{{x11 y11} {x12 y12} ...} {{x21 y21} {x22
y22} ...} ...}, which specifies a list of points of rectilinear polygons.
full_name
A string attribute for the name of a voltage_area.
guard_bands
A guard_band_list attribute for the list of guard-bands of a voltage_area. The format of a
guard_band_list is {{guard_band_x1 guard_band_y1} {guard_band_x2 guard_band_y2}...},
which specify a list of horizontal and vertical spacings from the edges of each the
voltage_area_shape in the voltage_area. The guard band is the spacing along the boundary
of a voltage_area where cells cannot be placed because of the lack of power supply rails.
guard_bands_boundary
A poly_list attribute for the list of original guard-band-included regions in a voltage_area. It
is different from the effective_guard_bands_boundary attribute in that the original region is
preserved. Overlapped regions are not subtracted and abutted regions are not merged. The
format of a poly_list is {{{x11 y11} {x12 y12} ...} {{x21 y21} {x22 y22} ...}...}, which specify a
list of rectilinear polygons. Each polygon consists of a list of of points.
in_edit_group
A Boolean attribute to specify whether a voltage_area belongs to an edit_group.
is_fixed
A Boolean attribute to specify whether a voltage_area is in a fixed location. This attribute is
settable. It can only be set to true if the voltage_area contains at least one shape. This
Chapter 1:
1081
1-1081
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
is_legal
A Boolean attribute to specify whether a voltage_area is legal. A legal voltage_area is one
that is associated with one or more power domain and whose power and group supply, if
defined, match the primary power and group supplies of the associated power domains.
is_primary
A Boolean attribute to specify whether this is the primary voltage_area of the associated
power_domains.
is_fully_specified
A Boolean attribute to specify whether the flat voltage_area is fully specified. The flat voltage
area is not fully specified if the set of instances is associated with multiple set of regions of
multiple sub-blocks. Otherwise, if the association is simple, it is true.
is_shadow
A Boolean attribute to specify whether a voltage_area is pushed down from above. This
is_undoable
A Boolean attribute to specify whether a voltage_area object is undoable.
local_cells
A collection attribute with the leaf cells explicitly associated with this voltage_area.
name
A string attribute for the name of a voltage_area.
object_class
A string attribute with the value of "voltage_area".
power_domains
A collection attribute with the power_domain objects for this voltage_area.
1082
power_net
A collection attribute with a single power supply net object.
ground_net
A collection attribute with a single power ground net object.
physical_status
A string attribute representing the physical modification status of the voltage_area. Valid
values are unrestricted and locked. If status is unrestricted, the voltage_area may be freely
modified. If status is locked, the voltage_area is fixed for automatic and manual changes.
This is a settable attribute.
signature
A settable string attribute used to pair up a voltage area with its associated power domain
when the voltage area's name is different than its power domain.
shadow_status
A string attribute to represent the shadow status of a voltage_area. Valid values are
copied_down, copied_up, normal, pulled_up, and pushed_down.
shape_count
An integer attribute for the number shapes in a voltage_area.
shapes
A collection attribute with the voltage_area_shape objects in the voltage_area.
region
A poly_list attribute for the region of this voltage_area shape. The format of a boundary
specification is {{{x11 y11} {x12 y12} ...} {{x21 y21} {x22 y22} ...} ...}. This attribute is settable.
target_utilization
A double attribute to specify the utilization of the voltage_area. This attribute is settable.
Valid values are between 0.0 to 1.0.
Chapter 1:
1083
1-1083
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
use_power_domain_cells
A Boolean attribute to specify whether a voltage_area gets its cell membership implicitly
from its associated power domains.
SEE ALSO
create_voltage_area(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
1084
voltage_area_shape_attributes
Description of the predefined attributes for voltage_area_shapes.
DESCRIPTION
voltage_area_shape attributes are provided in the subsections that follow.
command.
voltage_area Attributes
bbox
A rectangle attribute for the bounding-box of a voltage_area_shape. The format of a
boundary
A polyrect attribute for the boundary of this voltage_area shape. The format of a boundary
specification is { {{llx1 lly1} {urx1 ury1}} {{llx2 lly2} {urx2 ury2}}...}. This attribute is settable.
cells
A collection attribute with the leaf cells explicitly associated with this voltage_area shape.
effective_guard_band_boundaries
A poly_list attribute for the effective guard-band expanded shapes of a voltage_area. The
effective guard_band boundary is calculated in the same way as effective_shapes. The only
difference is that the shape is expanded by the x and y guard-band margins during the
calculation.
Chapter 1:
1085
1-1085
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
effective_rectangles
A poly_list attribute for the effective shapes of a voltage_area broken down into rectangles.
The format of a rectangle poly_list specification is { {{llx1 lly1} {urx1 ury1}} {{llx2 lly2} {urx2
ury2}}...}, which specifies a list of lower-left and upper-right corners of rectangles.
effective_shapes
A poly_list attribute for the effective shapes of a voltage_area. The effective_shape is
calculated by comparing the stacking_order of the voltage_area_shapes of a voltage_area
with all other voltage_area_shapes in the design and subtracting the overlapping region
from the regions with lower stacking_order, and merging abutting shapes within the same
voltage_area. The format of poly_list specification is {{{x11 y11} {x12 y12} ...} {{x21 y21} {x22
y22} ...} ...}, which specifies a list of points of rectilinear polygons.
full_name
A string attribute for the name of a voltage_area_shape.
guard_band
A guard_band attribute for the horizontal and vertical guard-bands of a voltage_area_shape.
The format of a guard_band_list is {guard_band_x guard_band_y}, which specify the
horizontal and vertical margins from the edges of the voltage_area_shape. This attribute is
settable.
guard_band_boundary
A polyrect attribute for the boundary of this voltage_area shape expanded by the x and y
guard-band margins. The format of a boundary specification is { {{llx1 lly1} {urx1 ury1}} {{llx2
lly2} {urx2 ury2}}...}
is_exclusive
A Boolean attribute to specify whether a voltage_area_shape should be treated as an
exclusive area with respect to cells not associated with this shape (but are associated with
its voltage_area). This attribute is settable.
is_legal
A Boolean attribute to indicate if a voltage_area shape is legal.
1086
name
A string attribute for the name of a voltage_area_shape.
object_class
A string attribute with the value of "voltage_area_shape".
stacking_order
An integer attribute to specify the number of voltage_area_shapes above the bottom of the
voltage_area_shape position stack.
switch_cell_placement_type
A string attribute with the placement type of the switch cells in this voltage_area_shape.
target_utilization
A double attribute to specify the utilization of the voltage_area. This attribute is settable.
Valid values are between 0.0 to 1.0.
voltage_area
A collection attribute with the voltage_area object for this voltage_area_shape.
voltage_area_name
A string attribute with the name of the voltage_area object for this voltage_area_shape.
parent_block
A collection attribute with the owner block object for this voltage_area_shape.
parent_cell
A collection attribute with the owner cell object for this voltage_area_shape.
parent_block_cell
A collection attribute with the parent block cell object for this voltage_area_shape.
Chapter 1:
1087
1-1087
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
top_block
A collection attribute with the top block object for this voltage_area_shape.
SEE ALSO
create_voltage_area_shape(2)
get_attribute(2)
list_attributes(2)
set_attribute(2)
1088
wildcards
Describes supported wildcard characters and ways in which they can be escaped.
DESCRIPTION
The following characters are supported as wildcards:
Asterisks (*) substitute for a string of characters of any length.
Question marks (?) substitute for a single character.
The following commands support wildcard characters:

get_app_options
get_blocks
get_bound_shapes
get_bounds
get_bundles
get_cells
get_clock_groups
get_clocks
get_corners
get_designs
get_drc_error_data
get_drc_error_type
get_drc_errors
get_edit_groups
get_ems_databases
get_ems_groups
get_ems_messages
get_ems_rules
get_generated_clocks
get_io_guides
get_io_rings
get_layers
get_lib_cells
get_lib_pins
get_libs
get_message_ids
get_modes
get_modules
get_nets
get_parasitic_techs
get_path_groups
get_pg_regions
get_pin_blockages
get_pin_guides
get_pins
get_placement_blockages
get_ports
get_power_domains
get_power_strategies
Chapter 1:
wildcards
1089
1-1089
IC
Compiler II
II Application
Application Options
Options and
IC Compiler
and Attributes
Attributes
K-2015.06-SP4
get_related_supply_nets
get_routing_blockages
get_routing_corridor_shapes
get_routing_corridors
get_routing_guides
get_scenarios
get_shapes
get_site_rows
get_skew_groups
get_supply_nets
get_supply_ports
get_terminals
get_tracks
get_vias
get_voltage_area_shapes
get_voltage_area
In addition to these commands, commands that perform an implicit get also support the
wildcarding feature.
Escaping Wildcards
Wildcard characters must be escaped using double backslashes (\\) to remove their special
regular expression meaning. See the EXAMPLES section for more information.
Escaping Escape Character (\\)

This is similar to that of escaping wildcard characters, but needs one escape character each
to escape the escape character. See the EXAMPLES section for more information.
EXAMPLES
The following are examples of using wildcard characters.
Using Wildcards
The following example gets all nets in the current design that are prefixed by in and followed
by any two characters:
prompt> get_nets in??
{"in11" "in21"}
The following example gets all cells in the current design that are prefixed by U and followed
by a string of characters of any length:
prompt> get_cells U*
{"U1" "U2" "U3" "U4"}
wildcards
1090
Escaping Wildcards
The following are examples of escaping wildcard characters.
The following example gets design test?1 in the system.
prompt> get_designs {test\\?1}
{"test?1"}
The same example can be written using the Tcl list command:
prompt> get_designs [list {test\?1}]
{"test?1"}
If neither curly braces nor the list command is used, the syntax is as follows:
prompt> get_designs test\\\\?1
{"test?1"}
Escaping Escape Character (\\)

The following are examples of escaping an escape character.
The following example finds design test\1 in the system.
prompt> get_designs {test\\\\1}
{"test\1"}
The same above example can written using the Tcl list command:
prompt> get_designs [list {test\\1}]
{"test\1"}
If neither curly braces nor the list command is used, the syntax is as follows:
prompt> get_designs test\\\\\\\\1
{"test\1"}
Chapter 1:
wildcards
1091
1-1091

Icc23 PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Icc23 PDF

Uploaded by

Copyright:

Available Formats

IC Compiler II

Application Options and Attributes

Copyright Notice and Proprietary Information

Destination Control Statement

IC Compiler II Application Options and Attributes, Version K-2015.06-SP4

Copyright Notice for the Command-Line Editing Feature

Copyright Notice for the Line-Editing Library

IC Compiler II Application Options and Attributes, Version K-2015.06-SP4

IC Compiler II Application Options and Attributes, Version K-2015.06-SP4

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

Bound Shape Attributes

IC Compiler II Application Options and Attributes

Attributes of budget clock object

Attributes of budget path type object

IC Compiler II Application Options and Attributes

Attributes of budget pin object

IC Compiler II Application Options and Attributes

Attributes of budget pin data object

Attributes of budget pin constraint object

IC Compiler II Application Options and Attributes

Attributes of budget segment object

Returns the string "seg%d"

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

Attributes of budget clock object

IC Compiler II Application Options and Attributes

Attributes of budget path type object

IC Compiler II Application Options and Attributes

Attributes of budget pin object

IC Compiler II Application Options and Attributes

Attributes of budget pin constraint object

IC Compiler II Application Options and Attributes

Attributes of budget pin data object

IC Compiler II Application Options and Attributes

Attributes of budget segment object

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes

IC Compiler II Application Options and Attributes