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# VLSI Design, V sem B.

## E (E&C) [Aug-Dec 2016 Batch]

Assignment 1 [L. No. L1-L8]
Note: Assume any missing data suitably
I. Problems/ Descriptive Questions
 A 90 nm long MOS transistor has a gate oxide thickness of 16 . Find the value of gate
oxide capacitance per unit area. Given that o = 8.85 e 14 F/cm and ins = 4.
 Suppose VDD=1.2V and Vth = 0.4V. Determine Vout for the pass transistor circuit shown
in Fig. 2 for Vin = 0V, 0.6V, 0.9V and 1. 2V. Neglect body effect.
 A circuit designer intending to operate a MOSFET in saturation is considering the effect
of changing the device dimensions and operating voltages on the drain current.
Specifically, by what factor does change in each of the following cases?
(a) The channel length is halved.
(b) The channel width is doubled.
(c) The overdrive voltage is doubled.
(d) The drain-to-source voltage is doubled.
(e) Changes (a), (b), (c), and (d) are made simultaneously.
Which of these cases might cause the MOSFET to leave the saturation region?
 For the transistors shown in the Fig. 4 indicate the operating condition. Assume the
magnitude of Vth as 1 Volt in both the cases.
 Derive the expression for drain current for NMOS enhancement type device operated in
ohmic region and indicate on what factors it depends.
 Derive the expression for transconductance for NMOS enhancement type device operated
in saturation region.
 Explain how you will obtain the transfer characteristics for NMOS and CMOS inverter
using a graphical method.
 The PMOS transistor shown in Fig. 8, Vthp = -1 V, Kp = 60 A/ V2, W L = 10.
i)

## Find the range of VG for which the transistor conducts.

ii)

In terms of VG, find the range of VD for which the transistor operates in the triode
region.
1

iii)

In terms of VG, find the range of VD for which the transistor operates in
saturation.

 Find ID and VD for the circuit shown in Fig. 9. Verify the bias state consistency of your
choice. Given that Vthn = 1.0 V, Kn = 50 A/V2 and W/L = 2.
 The NMOS transistors in the circuit of Fig. 10 have Vthn = 1V, nCox = 120 A/V2 and
L1=L2=L3= 1m. Find the required values of gate width for each of Q1, Q2 and Q3 to
obtain the voltage and current values indicated.
 For the circuit of Fig. 11, Vt0 = 0.6 V, = 0.25, and F = 0.35 V. Calculate Vo.
 What width of NMOS is required for the flow of device current of 1 mA with V GS = 2V
and VDS = 3.3V. Given that L = 0.25 m, n = 650 cm2 Vsec, Vthn = 0.83 V, Cox =
0.185 F/cm2 .
 Consider the CMOS inverter with the following device parameters:
parameter

NMOS

PMOS

Cox

60 A/V 2

20 A/V 2

Vth

0.6 V

- 0.8 V

Vdd = 3 V, Vss = 0 V
Determine the ratio of

L n Wn
L p Wp

## . Given that the switching threshold voltage is 1.5 V.

 For the below given circuit of Fig. 14 (a) Give the transistor bias state, (b) Write the
appropriate model equation, (c) Calculate I D, where Vtp = 0.4 V, W/L = 4, and Kp = 200
A/V2.
 Given that Kn = 100 A/V2, Vthn = 0.6 V and W/L = 3 for transistor T1 shown in Fig.
15. Find the drain current IDS and VDS for the different values of VGS= .5V, 1.5V and 3V.
The bias state of T1 is not known
 Give the summary of different regions of operation in a CMOS Inverter. Give the DC
transfer characteristic of same.
 Derive Zpu/ Zpd for an NMOS inveter whose input is steered through pass transistor.
 Compare the characteristics of NMOS and CMOS Inverter.

Fig. 2
Fig. 4

Fig. 8

Fig. 9

Fig. 11
Fig. 10

Fig. 14

Fig. 15

1. Explain why present VLSI circuits use MOSFETs instead of BJTs?
2. Mention the three regions of operation of MOSFET and how are they used?
3. Draw Vds-Ids curve for an MOSFET. How it varies with (a) increasing Vgs (b) W/L ratio
(c) Channel length modulation
4. Which type of MOSFET acts as [i] normally ON device, [ii] normally OFF device?

5. State Moores first law and how the todays trends in the VLSI domain differ from Moores
prediction.

## 6. Can you practically use MOS device as a voltage variable resistor?

7. Bring out differences between Depletion type and Enhancement type MOSFETs?
8. Which MOS parameters are affected by channel length effect and bulk effect?
9. Is CMOS a ratioed logic? Give reason.
10. What do you understand by channel length effect? Explain in brief
11. Define the following. Give their units. Explain the significance of the same.
(i) electron transit time (ii) transconductance parameter (iii) Output conductance
(iv) Transconductance (v) Channel length modulation parameter (vi) Bulk effect coefficient
(vii) MOS transistor figure of merit (viii) threshold voltage
12. Differentiate between the threshold voltage of enhancement and depletion type MOSFET. Give
the typical value.
13. Is it possible to get good logic 0 and good logic 1 output using two NMOS inverter

configurations i.e., [i] NMOS inverter with depletion MOS pull-up [ii] NMOS inverter
with enhancement MOS pull-up? Elaborate the reason
14. Does the devices suffer due to bulk effect in NMOS inverter(s) and CMOS inverter?
Why?
15. Give a cross sectional view of an NMOS transistor. Show different device dimensions.
III. Fill in the blanks/ Multiple Choice Questions
1. A MOSFET has terminals
2.
[a]
[b]
[c]
[d]

## A MOSFET can be operated with ..

negative gate voltage only
positive gate voltage only
positive as well as negative gate voltage
none of the above

## 3. A MOSFET is sometimes called . JFET

[a] many gate
[b] open gate
[c] insulated gate
[d] shorted gate
4. Which of the following devices has the highest input impedance?
[a] JFET
[b] MOSFET
[c] Crystal diode
[d] ordinary transistor

## 5. The input impedance of a MOSFET is of the order of ..

[a]
[b] a few hundred
[c] k
[d] several M
6. A MOSFET differs from a JFET mainly because
[a] of power rating
[b] the MOSFET has two gates
[c] the JFET has a pn junction
[d] none of the above
7. A certain Depletion type MOSFET is biased at VGS = 0 V. Its data sheet specifies IDSS = 20 mA and
[a]
[b]
[c]
[d]

20 mA
0 mA
40 mA
10 mA

## 8. A n-channel D-MOSFET with a positive VGS is operating in

[a] the depletion-mode
[b] the enhancement-mode
[c] cut off
[d] saturation

9. A certain p-channel E-MOSFET has VGS(th) = -2V. If VGS= 0V, the drain current is
.
[a]
[b]
[c]
[d]

0 mA
ID(on)
maximum
IDSS

***