Microprocessors Jto Lice Study Material Sample

JTO LICE
MICROPROCESSORS
LICE- JTO
Limited Internal Competitive Examination
STUDY MATERIAL
MICROPROCESSOR
MICROPROCESSOR
28-B/7, Jia Sarai, Near IIT, HauzKhas, New Delhi-110016. Ph. 011-26514888. www.engineersinstitute.com
2016 ENGINEERS INSTITUTE OF INDIA .All Rights Reserved ( LICE/SSC/JTO)
JTO LICE
MICROPROCESSORS
CO N T E N T S
1. MICROPROCESSOR 8085
2. PERIPHERALS (8255, 8279,8155, 8259, ADC 0808, DAC 0800)
3. MICROPROCESSOR 8086
4. LICE Practices Set-I
5. LICE Practices Set-II
SYLLABUS:
MICROPROCESSOR
Architecture & programming of 8086/8088, Microprocessor based data

acquisition, memory address & DMA controllers, arithmetic co-processor,
other microprocessors, microprocessor applications. Study of Peripheral
Chips : 8255, 8279,8155, 8259. Study of ADC 0808, DAC 0800.
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MICROPROCESSORS
CHAPTER - 1
MICROPROCESSOR 8085
A microprocessor unit is generally referred as MPU
MPU is designed with ALU, control unit and some count of processing Registers
and these registers are used to store the data temporarily during program execution
Generally different MPUs available are specified like 8 bit, 16 bit, 32 bit and so on.
Bit capacity of MPU is defined as the no.of bits it can process at a time in parallel
.i.e. an 8 bit MPU can perform all 8 bit operations at a time
In general, the internal architecture of the microprocessor depends on the bit
capacity of the micro-processor
The system bus of MPU consist of 3 types of buses known as address bus ; data bus
and control bus.
Address signals are generated by MPU and sent to memory to identify the address of
the memory through address bus and it is unidirectional bus.
Data bus is used to transfer the data in between memory and MPU
Control signals are generated by MPU and these signals are transferred in between
memory and MPU and used to provide timing for various operations
Control signals are used to perform the required operations.
MPU can primarily perform 4 operations ; Memory Read ; Memory write ; I/O
Read and I/O write; and for each operation it generates the appropriate control
signals
8085 Microprocessor
It is a 40 pin I.C with operating voltage 5 volts
It is designed with 2 MH and 3.07 MHz frequencies
Max clock frequency of 8085 is 3.07 MHz (3MHZ)
Crystal frequency is double to its clock
8085 MPU is designed with on chip clock generator i.e. no external oscillator is
required
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8085 MPU has 74 basic instructions and 246 opcodes

8085 supports 5 no. of hardware interrupts and 8 no. of software interrupts
Hardware interrupts are Trap ; RST 7.5; RST 6.5; RST 5.5 and INTR
Trap has the highest priority among all
But trap has lower priority than DMAC during DMA
Trap is also known as RST 4.5
INTR has the lowest priority
No. of software interrupts for 8085 are 8, and range from RST 0 to RST 7
Opcode length varies from 1 byte to 3 byte
Instructions, having the 16 bit address in the given instruction known as 3 byte
instructions Ex : Call 2500H
Instructions, having the 8 bit data or port address in the given instruction is 2 byte
instruction Ex : MVI A, 35H
Instruction with neither 16 bit address nor 8 bit data is known as 1 byte instruction
Ex : MOV A, B
In 8085 MPU ; 5 No. of flags are available and these flags are also known as status
flags; known as carry (cy) ; Auxilary carry (Ac) ; Sign (s) ; parity (P) and zero (z)
8085 MPU has 2 no. of 16 bits Registers known as program counter (PC) and stack
pointer (SP)
PC always holds the address of the next instruction to be executed
SP always holds the address of the top of the stack
8085 MPU has 8 bit accumulator and 8 bit flag Register ; and this combination is
known as PSW (Program status word)
8085 MPU is designed with 6 no. of general purpose registers along with A and F ;
these register are known as B, C ; D E and H, L.
These 8 bit general purpose register can be used as 3 no. of 16 bit Register Pairs
when required like BC, DE and HL pairs
8085 MPU has 16 no. of address lines and 8 no. of data lines
Memory size of any MPU depends on the no. of address lines
Total no. of Memory locations that can be accessed by 8085 MPU is 216 =64 K =
65536
In Hex code ; the memory ranges from 0000 H to FFFFH
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The lower 8 no. of address lines are multiplexed with 8 data lines and specified as
AD0 to AD7
Multiplexing of address and data lines is used to reduce the hardware size of MPU
The no. of Machine clycles required to execute an 8085 MPU instruction varies from
one of five
Max no. of T states for executing an instruction are 18 and minimum no. of T
states required for executing an instruction are 4
Max no. of machine cycles required are 5 and minimum one
T state value depends on the clock frequency
Group of T states is known as machine cycle
Group of machine cycles is known as execution cycle
Signal description of 8085 MPU
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The 8085A Microprocessor Functional Diagram
Total no. of signal pins (40) are divided in to 6 Groups

1) Power supply and frequency
2) Serial I/O ports
3) Address Bus
4) Data bus
5) Interrupts and externally initiated signals
6) Status, control and Acknowledge signals
SID and SOD signals are used for serial communication
SIM and RIM instructions are used for serial I/O communication
A.L.E. is used to generate the lower order address lines (A, A0)
S1, S0 and IO/ M signals are called status signals
RD and WR signals are control signals
HOLD and HLDA are used for DMA operation
READY signal is used by the MPU to communicate with slow operating peripherals
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RESETIN is active low signal to chip Reset

RESET out signal is used to connect to RESETIN of other inter facing circuits used
in microprocessor based system
CLOCKOUT of 8085 will be connected to CLOCKIN of other interfacing ckts used
in microprocessor based system to synchronize the operation with 8085
So and S1 signals are used to indicate the current status of the processor
S1
S0
Status
Halt
Write
Read
Fetch
The process of getting / reading the opcode from memory to C.P.U is known as
opcode fetch
The process of getting / reading the data from memory is known as operand fetch
By combining the status signals IO/ M with control signals RD and WR we can
generate the following operations, MEMR , MEMW , IOR and IOW
IO/ M
RD
WR Operation
Memory Read
Memory write
I/O Read
I/O Write
All software interrupts are vectored interrupts

Hardware interrupts are of 2 types a) vectored interrupts b) Non vectored
interrupts
RST 7.5, RST 6.5, RST 5.5, and RST 4.5 are called Hardware vectored interrupts
INTR is called Hardware non vectored interrupt
Interrupts
vectored address
MICROPROCESSORS
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TRAP
0024H
RST 5.5
002CH
RST 6.5
0034H
RST 7.5
003CH
RST 0
0000H
RST 1
0008H
RST 2
0010H
RST 3
0018H
RST 4
0020H
RST 5
0028H
RST 6
0030H
RST 7
0038H
TRAP is a non-maskable interrupt and always in enable condition

RST 7.5, 6.5, 5.5 and INTR are maskable and these interrupts can be enabled /
disabled by EI and DI instructions respectively
RST 7.5, RST 6.5, and RST 5.5 interrupts can be masked or unmasked by using SIM
instruction
RST 7.5 is edge triggered interrupt
RST 6.5, RST 5.5 and INTR are level triggered interrupts
TRAP is both level triggered and edge triggered interrupt
SIM instruction is used for serial output data operation as well as to mask or unmask
different maskable interrupts
RIM instructions is used for serial input data operations as well as to read the status
of different maskable interrupts
8085 MPU has an 8 bit flag Register
In flag Register ; Out of 8 bits, 5 bits are used to represent valid flags and remaining
3 bits are dont cares
These flags are set / Reset according to the data conditions in the accumulator and
other Registers
Flags are affected by the arithmetic and logical operations in the ALU.
Flags are used to reflect the data conditions in the ALU
Position of different flags in flag Register
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D7 D6 D5 D4
S
D3 D2 D1 D0
AC X
CY
MSB in the flag Register is used to indicate the sign of the result for signed data
during Arithmetical operations and remaining 7 bits are used to represent the
magnitude of the number
After execution, if sign flag is set ; it indicate the result is Negative, the result is
positive when it is reset
If zero flag is set, then ALU operation result is zero
Auxiliary carry flag is used during BCD addition
AC flag is set when there is a carry from lower nibble to higher nibble
Parity flag will be set, when the result has an even no.of ones
Carry flag is also considered as Borrow flag during subtraction operation
During addition the carry flag is 1 when the result has 9 bits during 8 bit addition
Borrow flag is 1 when the subtraction operation is performed in between lower
value and Higher value
Instruction set :
Instruction set of 8085 MPU can be classified on their operation as the following
Groups
a) Data transfer
b) Arithmetical
c) Logical
d) Branch
e) Machine control
Data transfer instructions:

These are used to transfer the data in between Register to Register or from Register
to Memory
No flags will be affected
Different Mnemonics are
MOV, MVI, LXI, LDA, STA, LHLD,
SHLD, LDAX, STAX, XCHG, AND PCHL
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Arithmetical instructions:
In 8085 : the possible operations are Addition subtraction, increment and decrement
8085 MPU does not support multiplication and divisions operations
AC flag is used during the execution of DAA
For INX and DCX instructions ; no flags will be affected
For INR and DCR, carry flag is not affected
For DAD operation only carry flags may be affected
Different Arithmetic mnemonics are ADD, ADI, ADC, SUB, SUI, SBB, SBI, INR,
INX, DCR, DCX, DAD and DAA
Logical instructions :
During execution ; flags may be modified
Carry flag = 0 during AND, OR, XOR execution
Only carry flag may be modified during the execution of RLC, RRC, RAL, STC,
CMC,
Different mnemonics are ORA, ORI, ANA, ANI, XRA, XRI, CMP, CPI, CMA,
CMC, STC, RLC, RAL, RRC, RAR
Branch Instructions:
These are also called as program control instructions
These are divided into conditional unconditional
No flags will be affected
For executing the conditional Branch instructions it is compulsory to check the
condition of respective flag, assigned in the instruction
All jump and CALL instructions have 16 bit address
No address is required for RET instruction
PCHL is one byte and equivalent of 3 byte Jump instruction
RST n is one byte and equivalent of 3 byte call instruction
Un conditional Branch instructions :
JMP, CALL, RET, RSTn, (n = 0 to 7) and PCHL
Conditional Branch Instructions :
JZ, JNZ, JC, JNC, JP, JM, JPO, JPE, CZ, CNZ, JC, CMC, CP, CM,
CPO, CPE, RZ, RNZ, RC, RNC, RP, RM, RPO and RPE
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MICROPROCESSORS
Machine control Instructions.

EI, DI, SIM, RIM, NOP, HLT, OUT and IN; PUSH PSW; POP PSW; LXI SP,
SPHL, XTHL, and STC
IN and OUT instructions have 8 bit port address
When PUSH instruction is executed, SP Register content is decremented by 2
When POP instruction is executed SP Register content is incremented by 2
When CALL instruction or RST instruction is executed, SP Register content is
decremented by 2, because current content of PC will be pushed automatically on
the top two locations of the stack.
When RET instruction is executed, SP register content is incremented by 2, because
microprocessor retrieves address from top two locations of the stack and loaded in to
P.C
Comparison of PUSH and POP instructions with CALL and RET instructions
PUSH and POP
CALL and RET
The programmer uses the instruction When
CALL
is
executed
the
PUSH to save the contents of specified microprocessor automatically stores the 16

Register pair on the stack
bit address of the next instruction to CALL

on the Stack
When push is executed ; the SP is When CALL is executed, the SP is

decremented by 2
decremented by 2
The instruction POP transfer the contents The instruction RET transfers the content
of top two locations of the stack to the of the top 2 locations of the stack to
specified Register Pair
program counter
When the instruction POP is executed, the When the instruction RET is executed, the
SP is incremented by 2
SP is increment by 2
There are no conditional PUSH and POP There unconditional CALL and RET
instructions
instructions
along
with
conditional
instructions
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ADDRESSING MODES
>>It is the process of way of locating the operand (data)
8085 MPU supports 5 addressing modes
Implied Addressing mode : It is also known as implicit or Absolute addressing mode
This addressing mode is used to perform the given operation on the content of
Accumulator Ex : CMA, STC, RRC, RLC, RAR, etc.
Register Addressing mode : In this ; the operands are in the general purpose Register
The opcode specifies the address of the Register in addition to the operation to be
performed Ex : MOV A, B ; ADD B ; SUB C
Immediate Addressing mode : In this mode ; the operand is specified in the instruction
itself Ex : MVI, ADI, ORI, LXI, SBI, SUI, ANI, XRI
Direct Addressing mode :In this ; the address of the operand is given in the given
instruction Ex : STA, LDA, SHLD, LHLD, IN, OUT etc
Indirect addressing mode : In this addressing mode ; the address of the operand is
specified by a Register Pair. Example : STAX, LDAX, ADDM, DCRM.
In indirect addressing mode ; HL pair is used as memory pointer
EXECUTION DESCRIPTION
For executing any instruction ; Fetch machine cycle is compulsory
For FETCH; most of the instructions require four T states and some require 6 T
states
For performing any one operation of memory Read, memory write I/O Read and I/O
write ; Three T states are required
The following instructions require six T states for Opcode fetch
a) All CALL instructions
b) All conditional RET instructions
c) INX Rp
d) DCX Rp
e) PCHL
f) SPHL
g) PUSH Rp
h) All Restart instructions
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Note : POP and RET (unconditional) require only Four T states for fetching
During the execution of RST instructions, P.C. is modified with the address which is
available in page and allotted for separate address for each RST type instruction.
Different types of Machine cycles of 8085 are Opcode fetch, memory Read, memory
write ; I/O Read, I/O write, Interrupt Acknowledgement, and Bus idle cycles
The first Machine cycle of every instruction cycle is always Fetching
ALE signal is generated during T1 state of each Machine cycle
Machine cycle format is given below
M1
T1
T2 T3 T4 T5 T6
M2
T1
T2 T3
M3
T1
T2 T3
M4
T1
T2 T3
M5
T1
T2 T3
In the above diagram M stands for machine cycle and T stands for T states and M
is for fetching with the maximum length of 6 T states
Mapping : Assigning address to I/O devices or memory locations is called mapping
Memory mapping : Assigning the address of memory locations is called memory
mapping
Memory mapping can be changed by changing the hardware logic used for chip
selection
To inter face a memory chip with 8085, the necessary lower order address lines of
the 8085 address bus are connected to the address lines of the memory chip and the
higher order address lines are decoded to generate CS (chip select) signal to enable
the chip
Absolute decoding : In this decoding all the address lines which are not used for
memory chip to identify a memory Register must be decoded ; thus chip select can
be asserted by only one address
Linear Decoding : In this technic ; one address line is used for chip select(CS), and
other are left dontcares; this technic reduces hardware but generates multiple
addresses resulting in fold back memory space.
I/O devices can be connected to microprocessor in two different technique:
1) Memory mapped I/O technics
2) I/O mapped I/O technic
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Memory mapped I/O technique:

In this, the I/O devices are also treated as memory locations under that assumption
they will be given 16 bit address
In this ; data bytes are transferred by using memory related data transfer instructions
Ex : LDA ; STA ; MOV A,M ; MOV M,A
In this the input device is connected (key board) instead of memory and the input
device will have the 16 bit address specified by LDA instruction (When the device is
monitor ; STA instructions is used)
In memory mapped I/O MEMR and MEMW control signals are used to activate I/O
devices
In memory mapped I/O the entire memory map is shared by memory locations and
I/O devices and
One address can be used only once
This technic is used in a system where the no.of I/O devices are more
The max. no.of I/O devices that can be connected to microprocessor in this technic
are 216 = 65536
I/O mapped I/O technique:
In this ; I/O devices are identified by the microprocessor with separate 8 bit port
address
This technic uses separate control signals ( IORand IOW ) to activate I/O devices
and separate instructions ( IN and OUT) to communicate with I/O devices.
In this, the data bytes are transferred using IN and OUT instructions
Each IN and Out instructions followed by an 8 bit address of the device (OOH to
FFH)
In this only IN and OUT instructions are used.
In this, I/O mapping is independent of memory mapping and same address can be
used to identify input device and output device
This technic is used in a system where the no.of I/O devices are less
By using this method a maximum no.of 256 input devices and 256 output devices
can be connected to the processor
( total no. of devices to be connected = 512)
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INTERFACING
It is the process of designing Hardware circuit and writing software instructions to
enable the microprocessor to communicate with peripheral devices
There are two basic types of interfacing devices are available
a) Non programmable inter facing devices and
b) Programmable inter facing devices
Non programmable inter facing devices : once the microprocessor system is
designed; it is not possible to program this type of devices. Example : a) 8212 Non
programmable I/O port b) 74 LS 245 : bidirectional buffers c) 74 LS 373 : Trans parent
Latches
Programmable interfacing devices : These can be programmed by loading specific
binary word known as control word according to the internal logic
Different Programmable devices :
a) 8155 :
Programmable interfacing devices with 256 bytes RAM and 16 bit timer
/ counter
It is a general purpose interfacing device i.e. it can be used to
interface variety of I/O devices to the microprocessor
b) 8255 :
It has 3 no.of 8 bit ports known as port A, Port B and port C
c) 8253 :
Programmable interval Timer and It can work in 6 different modes
Mode 0 :
Interrupt on terminal count
Mode 1 :
Programmable one shot
Mode 2 :
Rate generator
Mode 3 :
Square wave generator
Mode 4 :
Software triggered strobe
Mode 5 :
Hard ware triggered strobe
d) 8251 : Programmable communication interfacing unit. It is called as USART

e) 8257 :
Programmable DMA
DMA transfer is an I/O technic used commonly for high speed data
transfer
It has 4 no.of DMA channels
g) 8259 : Programmable interrupt controller (PIC)

It is an equivalent to provide 8 INTR control pins on 8085 microprocessor
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For connecting 64 I/O devices, no.of PICs required are 9 (one for master and 8 for
salves.)
g) 8272 : programmable floppy disk controller
h) 8275 : Programmable CRT controller
i) 8279 : programmable keyboard and display interfacing circuit
by using this, it is possible to connect 16 seven segment displays and 64 keys (8 x 8
matrix) to the microprocessor
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JTO LICE

Architecture & programming of 8086/8088, Microprocessor based data

8085 MPU has 74 basic instructions and 246 opcodes

Signal description of 8085 MPU

The 8085A Microprocessor Functional Diagram

Total no. of signal pins (40) are divided in to 6 Groups

SID and SOD signals are used for serial communication

RESETIN is active low signal to chip Reset

All software interrupts are vectored interrupts

TRAP is a non-maskable interrupt and always in enable condition

Data transfer instructions:

Machine control Instructions.

CALL and RET

The programmer uses the instruction When

PUSH to save the contents of specified microprocessor automatically stores the 16

bit address of the next instruction to CALL

When push is executed ; the SP is When CALL is executed, the SP is

Memory mapped I/O technique:

It has 3 no.of 8 bit ports known as port A, Port B and port C

Programmable interval Timer and It can work in 6 different modes

Interrupt on terminal count

Programmable one shot

Square wave generator

Software triggered strobe

Hard ware triggered strobe

d) 8251 : Programmable communication interfacing unit. It is called as USART

g) 8259 : Programmable interrupt controller (PIC)

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