01.

Which of the following is the state

diagram for the Mealey machine shown
below.
D

X
input

04. What is the Mod number of the counter

circuit shown below? Assume initially reset.

Y
output

CLK

Q1

D Q0

Q1

Q
CLK

a.

1/0

0/0

0/0

a. 2
c. 4

b. 3
d. None

1/1

b.

0/0

04.Ans: c
0/0

1/1

05. The circuit shown below works as

0
0/0

c.

0/0

X
0/0

1/0
1

0
2:1
MUX
1 S

1/1

d.

1/0

0/0

1/1
1

0
0/0

a. Positive level triggered D Flip flop

b. Negative level triggered D Flip flop
c. Positive level triggered T Flip flop
d. None

01. Ans: a

05 Ans: b

02. Minimum number of 1:4 Demultiplexers

required to design a 8 256 decoder

06. Minimum number of 2 input NAND

gates required to implement the Boolean
function
A BX1 X 2 X 3 X 4 X 6 X 7 X 8

a. 85
b. 64
c. 21
d. decoder cant be designed with DEMUX.
02. Ans: a

03. Ans: a

b. 24
d. None

06. Ans:

03. How many 1 k 4 ROMs are required

to design a 16 k 16 ROM?
a. 64
c. 32

a. 23
c. 25

b. 16
d. None

07. The simplified Boolean expression for

function F(A,B,C,D) shown in the k map
is
AB
O

00

01

11

10

a. ABC D ABC D
b. ABC D A BC D
c. ABC D ABC D
d. None

{
If (B = 1) then
Y=0
If (B = 0) then
Y=1
}
If (A = 0)
{
If (B = 0) then
Y=0
If (B = 1) then
Y=1
}
The Boolean expression for Y is given by

07. Ans:
08. The transistor circuit shown below X & Y
are outputs of transistors Q1 & Q2
respectively.
5V

5V

Q1

b. A B A B
d. None

a. A+B
c. AB A B

Q2

10. Ans: b
11. How many TTL open collector NAND
gates are required to implement Boolean
. C D .
function f A B

The relation between X and Y is

a. X =Y
b. X Y 1
c. X + Y = 0
d. X + Y =1
08. Ans: d

a. 2
c. 6

09.

11. Ans: a

f = 10kHz

Q0

Q1

Schmitt
Trigger

b. 2kHz
d. None

09. Ans: c
10. Consider the software code implemented
on a computer. It is required to design an
equivalent digital Hardware for the software
code.
A
B

If (A = 1) then

Digital
Hardware

12. N inverters are connected in a Ring.

1

In the above circuit, a sinusoidal input of

frequency 10 kHz is given as input to Schmitt
trigger. The frequency fout is
a. 5 kHz
c. 2.5kHz

fout

b. 3
d. None

Each inverter has a propagation delay of

10ns.
The above circuit works an
a. Oscillator if N is odd & frequency of
50
MHz
operation is
N
b. Oscillator if N is even & frequency of
50
MHz
operation is
N
c. Oscillator if N is odd & frequency of
100
MHz
operation is
N
d. None
12. Ans: a

13.

15.
Valid Excess code

J=1
10 ns
X

1
0

Q
10ns

K=1

c0 = 1

4 Bit Ripple
carry Adder

10 ns
Clk = 1

In the circuit shown above: 4bit valid Excess

3 is given as input and the output is valid 4 bit
BCD code. In order to perform such an
operation value of Y should be

Propagation delay of flip flop & AND gate is

10ns each.
In the above circuit J & K are connected to
1 an clock input is made always HIGH
making the circuit operate in Race around
condition. What is the frequency of
oscillation at the pin Q?

a. 0011
c. 0100

a. 50MHz
c. 25MHz

Valid BCD code

b. 1100
d. 1101

b. 33.33MHz
d. 16.667MHz

13. Ans: b

15.Ans: c

14.

16.
A Fair die is rolled. The face value of the die
in encoded into 3bit binary. For example:
{ 1 001, 2 010, 3 011 -----}

x2 y2

x1 y1

x0 y0
ci: carry
si: sum

c2
Full
Adder

Full
Adder

Full
Adder c0=0
c1

c3

s2

c2

s1

Face value
of die

s0

Overflow
detector

0V

Adder circuit dealing with 2s complement

numbers. In the above circuit, the output 0V
is 1 when
a. c2 = c3
c. c3 + c2 = 0

b. c 2 c 3
d. None

Carry

Full
adder

encoder

Sum

The output of encoder is given to a full adder

circuit. What is the probability that carry = 1
& sum = 0?
a. 0.25
c. 0.75

b. 0.5
d. 1

16. Ans: b
17.
+5V

x(t)

14. Ans: b
R
C

x(t)

y(t)
0 10 ns

20 ns

In the above circuit x(t) is input, y(t) is the

output. The Fourier transform of the output
y(t) is

a. sinc function with zero crossing at

f = 100MHz, 200MHz, 300 MHZ
b. sinc function at zero crossing f = 50MHz,
100MHz, 150 MHZ
c. Rectangle function
d. None of the above.
17. Ans:
18. Given the following k-map which one of
the following represents minimal sum-of
products of the map.

21. Statement I: In a Mealey machine the

present output depends only on the present
state
Statement II: In Moore machine the present
outputs depends on present state as well as
present input
a. both S1 and S2 are true
b. S1 is true S2 false
c. S1 is false and S2 is true
d. Neither S1 nor S2 is true
21. Ans: d

00

22. The minimum decimal equivalent of

(23D)X is
a. 609
b. 607
c. 509
d. 574

01

22. Ans: c

11

10

23. Function f(A) is defined as f(A) = 2s

complement of A then f[f(f(f(A)))] =
a. A
b. A
c. 1
d. 0

WX
00
YZ

01

11

10

a. xy yz
c. w x yz xy

b. wx y xy xz
d. xz y

18. Ans:
19. Which of the following are essential
Prime Implicants in the Boolean expression
AB AC BC
a. AB, AC
b. AB, AC, BC
c. AC, BC
d. AB, BC
19. Ans: a

23. Ans: a
24. If f(A, B,C) = [A B] C, then
f C, A B, A is
a. AB C
b. A BC
c. A CB
d. None
24. Ans: a

25.
B

20. The characteristic equation of T Flip

flop is given by

a. Q(n+1) = TQ+ T Q
b. Qn 1 T Q T
c. Q(n+1) = T
d. none of the above

For the venn diagram shown above, the

equivalent function for the shaded region is

20. Ans:

a. A B C
c. A B
25. Ans:

b. A B
d. None

ABC
000
001
010
011
100
101
110
111

26. Match the following

Column - A
P.

Q.

x
y
x
y

XYZ
000
001
011
010
110
111
101
100

R.

The above circuit implements

a. Binary to Gray code conversion
b. Gray to Binary code conversion
c. BCD to Excess-3 code conversion
d. None

Column B
1.

0
2:1
MUX
1

27. Ans: a
28.

VR = 16V

2.
0

0
2:1
MUX
1

CLK

2 bit
free
running
counter

0
2:1
MUX
1

Match column A with column B

a. P 3
Q2
R1
b. P 3
Q1
R2
c. P 2
Q 3
R 1
d. None

27. The following data is stored in 23 3

ROM

2 3
ROM
3

24
Decoder 2
3
A

d3
d2
d1
d0

Digital to
Analog
Converter

The counter is free running up counter

starting at 00. The digital to analog
converter equation is given by
V0 VR 2 1 d 3 2 2 d 2 2 3 d1 2 4 d 0 . The
sequence of output voltages generated by
DAC is
a. 8V 4V 2V 1V
b. 1V 2V 4V 8V

26. Ans:

A
B
C

0
1

3
. y

A1

X
Y
Z

c. 1V 2V 3V 4V
d. None
28. Ans: a

V0

Directions:
The following 29 & 30
questions consists of two statements, one
labeled the Assertion A and the other
labeled the Reason R.
Your are to
examine these two statements carefully
and decide if the Assertion A and the
Reason R are explanation of the Assertion.
Select your answer to these its using the
codes given below and mark your answer
sheet accordingly
Codes :
a) both A and R are true and R is the correct
explanation of A
b) both A and R are true but R is not a
correct explanation of A
c) A is false and R is true
d) A is true and R is false
29. Assertion (A) : N bit flash ADC is faster
than N bit successive approximation ADC
Reason (R) : Flash ADC uses 2n1
comparators in parallel.
29. Ans:
30. Assertion (A): Emitter coupled logic
circuit have very less propagation delays.
Reason (R): ECL is unsaturated logic
family.
30. Ans: A