Data Sheet

26185.16A*

5833

BiMOS II 32-BIT SERIAL-INPUT,

LATCHED DRIVER
Designed to reduce logic supply current, chip size, and system
cost, the UCN5833A/EP integrated circuits offer high-speed operation
for thermal printers. These devices can also be used to drive multiplexed LED displays or incandescent lamps within their 125 mA peak
output current rating. The combination of bipolar and MOS technologies gives BiMOS II smart power ICs an interface flexibility beyond the
reach of standard buffers and power driver circuits.

OUT32

NC
40

OUTPUT ENABLE

41

SERIAL DATA OUT

43

OE 42

LOGIC
SUPPLY
CLOCK
CLK 44

SERIAL DATA IN

VDD 1

POWER GROUND

STROBE

NC
5

ST 4

OUT1
6

UCN5833EP

OUT 2

39

OUT31

OUT 3

38

OUT30

37

OUT29

36

OUT28

OUT 6

11

OUT 7

12

LATCHES

REGISTER

REGISTER

9
10

LATCHES

OUT 4
OUT 5

35

OUT27

34

OUT26

OUT 8

13

33

OUT25

OUT 9

14

32

OUT24

OUT10

15

31

OUT23

OUT11

16

30

OUT22

OUT 12

17

29

OUT21

NC 28

OUT20 27

OUT19 26

OUT18 25

OUT17 24

LOGIC GROUND 23

OUT16 22

OUT15 21

OUT14 20

NC 18

OUT13 19

SUB

These 32-bit drivers have bipolar open-collector npn Darlington

outputs, a CMOS data latch for each of the drivers, a 32-bit CMOS
shift register, and CMOS control circuitry. The high-speed CMOS shift
registers and latches allow operation with most microprocessor-based
systems at data input rates above 3.3 MHz. Use of these drivers with
TTL may require input pull-up resistors to ensure an input logic high.
The UCN5833A is supplied in a 40-pin dual in-line plastic package
with 0.600" (15.24 mm) row spacing. At an ambient temperature of
+75C, all outputs of the DlP-packaged device will sustain 50 mA
continuously. For high-density applications, the UCN5833EP is
available. This 44-lead plastic chip carrier (quad pack) is intended
for surface-mounting on solder lands with 0.050" (1.27 mm) centers.
CMOS serial data outputs permit cascading for applications requiring
additional drive lines.

Dwg. No. A-13,049

FEATURES
ABSOLUTE MAXIMUM RATINGS
at +25C Free-Air Temperature
Output Voltage, VOUT . . . . . . . . . . . 30 V
Logic Supply Voltage, VDD . . . . . . . 7.0 V
Input Voltage Range,
VIN . . . . . . . . . -0.3 V to VDD + 0.3 V
Continuous Output Current,
lOUT (each output) . . . . . . . . . . 125 mA
Package Power Dissipation, PD
(UCN5833A) . . . . . . . . . . . . . . . 3.5 W*
(UCN5833EP) . . . . . . . . . . . . . . 2.5 W*
Operating Temperature Range,
TA . . . . . . . . . . . . . . -20C to +85C
Storage Temperature Range,
TS . . . . . . . . . . . . . -55C to +150C

To 3.3 MHz Data Input Rate

30 V Minimum Output Breakdown
Darlington Current-Sink Outputs
Low-Power CMOS Logic and Latches

Always order by complete part number:

* Derate linearly to 0 W at +150C.

Caution: CMOS devices have input static protection

but are susceptible to damage when exposed to
extremely high static electrical charges.

Part Number

Package

UCN5833A

40-Pin DIP

UCN5833EP

44-Lead PLCC

5833
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVER
UCN5833A
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SUPPLY

SERIAL
DATA IN

POWER
GROUND

CLK

V DD

CLOCK
40 LOGIC
SUPPLY

39

OE

SERIAL
DATA OUT

38

OUTPUT
ENABLE

37

OUT

36

OUT 31

STROBE

OUT 1

OUT

35

OUT 30

34

OUT 29

33

OUT 28

32

OUT

OUT
OUT
OUT

5
6
7

10
11

LATCHES

REGISTER

OUT

LATCHES

OUT

REGISTER

ST

32

32-BIT SHIFT REGISTER

SERIAL
DATA IN

SERIAL DATA
OUT
LATCHES

STROBE

LOGIC
GROUND
SUB

OUTPUT
ENABLE

MOS
BIPOLAR

27

31 OUT
26
30

OUT 25

OUT 8

12

29

OUT 24

OUT 9

12

28

OUT

10 14

27

OUT 22

OUT 11 15

26

OUT 21

OUT

12 16

25

OUT 20

OUT 13 17

24

OUT 19

OUT

23 OUT 18

OUT

V DD
CLOCK

14 18

POWER OUT30 OUT31 OUT32

GROUND

Dwg. No. A-13,057

23

OUT 15 19

22

OUT 16 20

21 LOGIC
GROUND

SUB

OUT1 OUT2 OUT3

OUT 17

TYPICAL INPUT CIRCUIT

VDD

IN

Dwg. No. A-13,048

Dwg. No. A-13,050

SUB

TYPICAL OUTPUT DRIVER

OUT

Dwg. No. A-13,051

115 Northeast Cutoff, Box 15036

115
Northeast
Cutoff, Box 15036
Worcester,
Massachusetts
01615-0036 (508) 853-5000
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright 1986, 1995, Allegro MicroSystems, Inc.

5833
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25C, VDD = 5 V (unless otherwise noted).
Characteristic

Min.

Limits
Max.

Units

VOUT = 30 V, TA = 70C

10

lOUT = 50 mA

1.2

lOUT = 100 mA

1.7

VIN(1)

3.5

5.3

VIN(0)

-0.3

+0.8

Symbol

Output Leakage Current

ICEX

Collector-Emitter
Saturation Voltage

VCE(SAT)

Input Voltage

lIN(1)

VIN = 5.0 V

1.0

lIN(0)

VIN = 0 V

-1.0

VOUT(1)

IOUT = -200 A

4.5

VOUT(0)

IOUT = 200 A

0.3

One output ON, lOUT = 100 mA

1.0

mA

All outputs OFF

50

Input Current

Serial Output Voltage

Test Conditions

Supply Current

lDD

Output Rise Time

tr

lOUT = 100 mA, 10% to 90%

500

ns

Output Fall Time

tf

lOUT = 100 mA, 90% to 10%

500

ns

NOTE: Positive (negative) current is defined as going into (coming out of) the specified device pin.

TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN

Serial
Data Strobe
Output Input

Latch Contents
I1

I2

I3

...

IN-1

IN

Output
Enable
Input

Output Contents
I1 I2 I3 ... IN-1 IN

R1 R2 ...

RN-2 RN-1

RN-1

R1 R2 ...

RN-2 RN-1

RN-1

R1 R2 R3 ...

RN-1 RN

RN

R1 R2 R3 ...

RN-1 RN

PN

P1 P2 P3 ...

PN-1 PN

P1 P2 P3 ... PN-1 PN

H H H ... H

...

P1 P2 P3 ...

L = Low Logic Level

PN-1 PN

H = High Logic Level

X = Irrelevant

P = Present State

...

R = Previous State

5833
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVER
CLOCK

DATA IN
E
STROBE

OUTPUT
ENABLE
G
OUTN
Dwg. No. A-12,276A

TIMING CONDITIONS
(VDD = 5.0 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) .......................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width ............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transition ........................................................................... 500 ns

Serial Data present at the input is transferred to the shift register

on the logic 0 to logic 1 transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE tied
high) will require that the OUTPUT ENABLE input be low during serial
data entry.
When the OUTPUT ENABLE input is low, all of the output buffers
are disabled (OFF) without affecting the information stored in the
latches or shift register. With the OUTPUT ENABLE input high, the
outputs are controlled by the state of the latches.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

5833
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVER
UCN5833A
Dimensions in Inches
(controlling dimensions)
40

0.015
0.008

21

0.700
MAX

0.580
0.485

0.600
BSC

2
0.070
0.030

20
0.100

4
2.095
1.980

BSC

0.005
MIN

0.250
MAX

0.015

0.200
0.115

MIN

0.022
0.014

Dwg. MA-003-40 in

Dimensions in Millimeters
(for reference only)
40

0.381
0.204

21

17.78
MAX

14.73
12.32

15.24
BSC

2
1.77
0.77

2.54
53.2
50.3

BSC

20

0.13
MIN

6.35
MAX

0.39

5.08
2.93

MIN

0.558
0.356

NOTES: 1. Exact body and lead configuration at vendors option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.

Dwg. MA-003-40 mm

5833
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVER
UCN5833EP
Dimensions in Inches
(controlling dimensions)
18

28

29

17

0.032
0.026

0.319
0.291
0.695
0.685

0.021
0.013

0.656
0.650
0.319
0.291
0.050

INDEX AREA

BSC

39

40
0.020

44

0.656
0.650

MIN

0.695
0.685

0.180
0.165

Dwg. MA-005-44A in

Dimensions in Millimeters
(for reference only)
28

18

29

17

0.812
0.661

8.10
7.39
17.65
17.40

0.533
0.331

16.662
16.510

8.10
7.39

INDEX AREA

1.27
BSC

39

40
0.51
MIN

4.57
4.20

44

16.662
16.510
17.65
17.40
Dwg. MA-005-44A mm

NOTES: 1. Exact body and lead configuration at vendors option within limits shown.
2. Lead spacing tolerance is non-cumulative.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

5833
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVER

The products described here are manufactured under one or more

U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be required
to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.

5833
BiMOS II 32-BIT
SERIAL-INPUT,
LATCHED DRIVER

POWER
INTERFACE DRIVERS
Function

Output Ratings*

Part Number

SERIAL-INPUT LATCHED DRIVERS

8-Bit (saturated drivers)
8-Bit
8-Bit
8-Bit
8-Bit
8-Bit (constant-current LED driver)
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)

-120 mA
350 mA
350 mA
350 mA
350 mA
75 mA
250 mA
350 mA
100 mA

50 V
50 V
80 V
50 V
80 V
17 V
50 V
50 V
50 V

5895
5821
5822
5841
5842
6275
6595
6A595
6B595

10-Bit (active pull-downs)

-25 mA

60 V

5810-F and 6809/10

12-Bit (active pull-downs)

-25 mA

60 V

5811 and 6811

75 mA

17 V

6276

20-Bit (active pull-downs)

-25 mA

60 V

5812-F and 6812

32-Bit (active pull-downs)

32-Bit
32-Bit (saturated drivers)

-25 mA
100 mA
100 mA

60 V
30 V
40 V

5818-F and 6818

5833
5832

16-Bit (constant-current LED driver)

PARALLEL-INPUT LATCHED DRIVERS

4-Bit

350 mA

50 V

5800

8-Bit
8-Bit
8-Bit (DMOS drivers)
8-Bit (DMOS drivers)

-25 mA
350 mA
100 mA
250 mA

60 V
50 V
50 V
50 V

5815
5801
6B273
6273

SPECIAL-PURPOSE DEVICES
Unipolar Stepper Motor Translator/Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 8-Bit Decoder/DMOS Driver
Addressable 28-Line Decoder/Driver

1.25 A
250 mA
350 mA
100 mA
450 mA

50 V
50 V
50 V
50 V
30 V

5804
6259
6A259
6B259
6817

Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.

Complete part number includes additional characters to indicate operating temperature range and package style.

Internal transient-suppression diodes included for inductive-load protection.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

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