Concept Paper:

Prepared by: Engr. Re-Ann Cristine O. Calimpusan

Design of a Reduced EMI and Improved Signal Integrity Using Spread

Spectrum Clocking of a High Efficiency Green Mode SMPS Buck Regulator

The better efficiency means less heat dissipation and longer battery lifetime in wireless
communication products and other portable systems powered by batteries. Therefore, the power
management system with high efficiency is of great importance. As a solution, a green mode
SMPS (switch mode power supply) buck regulator is developed. Its efficiency is enhanced by so
called multi-mode operation; which controls the regulator to operate in PWM (pulse width
modulation) mode under heavy or medium loads and in burst mode under light load. In addition,
the use of internal synchronous rectifier is also beneficial to increase of the efficiency.
Unfortunately EMI is also becoming an issue with digital power supplies, which increase
their efficiency by using higher switching frequencies. The situation grows worse with every
new product generation given the combination of steady increases in clock speeds and decreases
in supply voltages that reduce overall noise margins. If left unattended, these high frequency
signals and their harmonics (see Figure 1) can have peak energy levels that exceed FCC Class A
and Class B Part 15 EMI limits and delay products from being released to market. These issues,
coupled with shorter design cycles, increasing sensitivity to cost imposed by high-volume
markets and shorter product life spans, make it challenging for developers to produce quality
products in a timely fashion.

Thus, this paper presents a Design of a Reduced EMI, Improved Signal Integrity Using
Spread Spectrum Clocking of a High Efficiency Green Mode SMPS Buck Regulator

SYSTEM DESIGN AND ANALYSIS

Green Mode SMPS
Buck Regulator

Spread Spectrum
Clocking

The proposed IC is a highly efficient, monolithic synchronous buck regulator with peak current
programmed control architecture and a reduced EMI and Improved Signal Integrity Using
Spread Spectrum Clocking. Its output voltage is adjusted via an external resistor divider. Both
the main power switch (P-channel MOSFET) and synchronous (N-channel MOSFET) switch are
on-chip integrated. The block diagram is shown in Figure 1.
The system diagram for a Green Mode SMPS Buck Regulator and the functions of the system
will be discussed in this part.

A. Main Control Loop Operation Description

During normal operation, when the clock signal triggers the RS latch in each cycle, the on-chip
integrated power switch turns on and causes the inductor current to rise, until it reaches the peak

value. Then the output of the current ComparatorICOMP resets the RS latch and the power
switch turns off. The reset peak value of the inductor current is controlled by the output of error
amplifier EA. The feedback signal received from an external resistive divider by EA indicates the
load condition. When the load current increases, the feedback voltage decreases slightly from the
reference of 0.613V, which in turn causes the output of the EA to increase until the average
inductor current matches the new load current. And vice versa. Since the traditional buck
converter uses the Schottky diode as the rectifier, the power loss of diode is unavoidable. To
lower conductive loss , the synchronous rectification technique is involved here. It will enhance
the efficiency and eliminate the need of an external Schottky diode. When the power MOSFET
turns off, the synchronous MOSFET turns on for current freewheeling. During the switch
transients, the anti-shoot-through function generates two dead-times to prevent the power
MOSFET and synchronous MOSFET from simultaneous turning on.
If the converter works at discontinuous current mode (DCM), the current of synchronous switch
reverses, which will cause power wasting and low efficiency. So the reverse comparator is
employed to detect the SW signal. It will give a reverse signal to shut down the synchronous
MOSFET

when the SW voltage

gets from

negative to positive.

ICOMP resets the RS latch and the power switch turns off. The reset peak value of the inductor
current is controlled by the output of error amplifier EA. The feedback signal received from an
external resistive divider by EA indicates the load condition. When the load current increases, the
feedback voltage decreases slightly from the reference of 0.613V, which in turn causes the output
of the EA to increase until the average inductor current matches the new load current. And vice
versa. Since the traditional buck converter uses the Schottky diode as the rectifier, the power loss

of diode is unavoidable. To lower conductive loss , the synchronous rectification technique is

involved here. It will enhance the efficiency and eliminate the need of an external Schottky
diode. When the power MOSFET turns off, the synchronous MOSFET turns on for current
freewheeling. During the switch transients, the anti-shoot-through function generates two deadtimes to prevent the power MOSFET and synchronous MOSFET from simultaneous turning on.
If the converter works at discontinuous current mode (DCM), the current of synchronous switch
reverses, which will cause power wasting and low efficiency. So the reverse comparator is
employed to detect the SW signal. It will give a reverse signal to shut down the synchronous
MOSFET when the SW voltage gets from negative to positive.

B. Burst Mode Operation Description

The Green Mode SMPS Buck Regulator is capable of burst mode operating, in which the power
MOSFET turns on intermittently based on light load demand, thus reducing the switch loss and
quiescent current at the same time.
When the regulator operates in burst mode, the minimum peak current of the inductor is set to
approximately 150mA regardless of the output load. Each burst event can last from a few cycles
with long sleep intervals under light load to almost continuously cycling with short sleep
intervals under moderate load. Between these burst sleep events, the power switch and any
unnecessary circuits are turned off to reduce the quiescent current. In this sleep status, the load
current is supplied solely by the output capacitor. Along with the output voltage drops, the
feedback voltage decreases below the sleep threshold, and the BURST comparator is signaled to
trip and turn the power
MOSFET on. This process repeats at a rate depending on the load condition. The BURST
comparator is a typical bilateral hysteresis comparator and the hysteresis window determines the
output ripple voltage in the burst mode.
It is common sense that overshoot voltage is harmful for apparatus, but it does exist in most
multi-mode controlled regulators. As a solution, different reference voltages from PWM mode to
burst mode are helpful to suppress the overshoot voltage between the mode transitions. During
burst mode operation, the controller sets the output voltage slightly higher than normal output

voltage during PWM mode, allowing additional headroom for voltage increment during a load
transient . As shown in Figure 2, when the load is heavy, the regulator works in PWM mode.
Along with the load decreases, the peak current will never change with light load, thus cause the
output voltage up. When the output voltage rises above the high burst threshold, then the power
MOSFET turns off and the regulator gets into the burst mode operation. Conversely, if the load
changes from light to heavy, the output voltage will decrease below the EA_REF and the
regulator will turn back to the PWM mode
operation.

C. On-chip Current Sensing Circuit Design

Prevailing current sensing method employs a small value resistor in series with power stage to
sense the inductor current. But if this resistor is integrated on the chip, it will take a large area.
Especially in low-voltage design, the efficiency degradation and poor current-sensing accuracy
are serious problems. So on-chip current sensing technique is introduced in. It has higher
precision and lower power dissipation than the resistive sensing.

In this design, the current sensing block uses the current mirror topology to mirror the current
through the power switch with a constant coefficient [8]. The circuit diagram of the current
sensing block is shown in Figure 3. PM_P stands for power switch, and NM_P stands for
synchronous switch.

The PM0 and the PM_P compose a current mirror. The amplifier CSA is a two stage folded
cascade structure having wide bandwidth and quick response. The amplifier enforces the
voltages at CSA+ and CSA- to be equal. The PM1 prevents the CSA+ point shorting to the
ground when NM_P turns on. If the CSA+ point shorts to the ground in the power switch off
time, it will take a long recovery time in power switch on time in the next cycle. Then that will

influence the sensing precision. Since the power MOSFET works in linear region when its gate is
connected to the ground, the different

VDS between PM0 and PM_P will cause an imprecision on the current mirror. Therefore the
VDS of PM1 must be reduced by using a high aspect ratio. In the design, the size ratio of PM0
and power MOSFET is 1:3000, so the current ratio of ISENSE and IPOWER_MOS is 1:3000.
Figure 4 shows the simulation results of the current sensing module. Note that the sensed current
can perfectly follow the current of power MOS under heavy load, but exhibit a little delay when
the load decreases, it is restricted by the response of the CSA. The sensing precision is about
98.8% at heavy load (500mA load) and about 86% at light load (50mA load) in simulation.

D.

Spread Spectrum Clocking

One of the most effective and efficient approaches to controlling and reducing EMI is
to use spread spectrum clock generation (SSCG) technology. Instead of maintaining a
constant frequency, spread spectrum techniques modulate the system clock across a much
smaller frequency that creates a frequency spectrum with sideband harmonics. By
intentionally spreading the narrowband repetitive clock across a broader band, the peak
spectral energy of both the fundamental and harmonic frequencies can be reduced
simultaneously (see Figure 7). The modulation frequency (FM) is typically 30 to 33 kHz,
which is broad enough to spread the energy around the carrier yet narrow enough to avoid
creating timing and tracking issues in the system.

Figure 7.SSCG Reduces EMI at any Single

Frequency