Design Of CMOS Operational Ampilfier

Electronics II Semester Project

Waqar Arshad (FA08-BET-087)

(FA08 Umar Khan (FA08-BET-137)
Saad Wasiq (FA08-BET
BET-096) Rabish Manzoor(FA08-BET-094)
Bachelors in Telecommunication Engineering, Electrical Engineering Department
COMSATS Institute of Information Technology, Islamabad

1.Abstract
The report describes use of MOSIS fabricated CMOS
Operational Amplifiers as a real world design
experience in senior level Analog Integrated Circuit
Courses in Electrical Engineering.Design offered at our
department, design of a CMOS Operational Amplifier is
required as a term project. Students are given a set of
minimum specifications and are required to apply the
learning they had into the designsign of a NMOS-input
NMOS
Operational Amplifier that can be implemented in an N- N
well CMOS process. The specifications include open
loop gain, gain-bandwidth
bandwidth product, phase margin,
common-mode
mode rejection range, slew rate and output
swing on a specified load including
ding capacitive loading.
The requirements are (1) to create a Mathematica file of
their design calculations, (2) verify the design with
appropriate SPICE simulations, (3) create a layout
design that passes all design rules, and (4) write a report
and do a Powerpoint presentation to the class at the end.
However, typical turn-around
around times do not allow the
graduating class to have a chance to test and verify their
design, and get the satisfaction and the real world
experience of testing.

2.Introduction
The report
eport describes how MOSFETS fabricated CMOS
Operational Amplifiers are used as a real world design
experience in a senior level Analog Integrated Circuit
Course in Electrical Engineering at COMSATS.
Figure CMOS OpAmp
Design is the requirement that every engineering student
should experience before graduation. Although this
experience can be left to the capstone project most disciplines, it is desirable that the design experience be
engineering programs require, considering the diversity incorporated into individualcourses particularly those at
of electrical engineering the senior level. This ensures that the design experience
and exposure is not limited to the narrow topic of the
student’s capstone project. Implementing it in the senior
level courses makes itpossible that a level of
sophistication and depth can be demanded and
achievedbased on an accumulation of learning and
experimentation from at least three years of prior
engineering education.
presenting them clearly and consicely using figures,
charts and tables and describing and making
comments on the successes/failures and
suggested/implemented improvements. ”. PROBE
plots can be screen captured and pasted into this
document. (For writing this document students are
expected to use MS Word/Office which is available.

Design Specifications
3.Design Project: Description and
Specifications
Supply
The term project assigned is chosen to include as much Voltage: +/- 1.6 VDC dual supply
of the topics covered as possible, while taking into
Supply
accounts the time left in a semester and limitations of the
student versions of the tools available. For this reason a
Current: ≤ 341 uA
CMOS OpAmp design using a 2 micron N-well CMOS
process became the standard and default project over the
years. Below is copy of a handout given to the students Output
that gives details of project specifications and outcomes. Voltage Swing : +/-1.6V
It has been reformatted to comply with the paper’s
format. =3 (including a source
Stages: follower output stage)
CMOS Operational Amplifier Design
Area: 402.4*10^-12 m^2
Design a CMOS Operational Amplifier that
satisfies the specifications listed below. Differential Gain: 11000 V/V
CommonModeRange+/-1.6V
Submit,
1. Mathematica Design File: A file including all steps
of the design procedure used, i.e. starting from a set of
design specifications, and using, in a logical sequence,
design equations, assumptions, approximations and
calculations leading to the choices made of all transistor
and capacitor W/L ratios as well as their operating point
values.

2. A set of LTSPICE schematics files and

STIMULATIONS plots verifying the design
specifications are met.LEDIT layout which passes and
generates a LTPICE netlist that verifies consistency with
the schematics and W and L values verified earlier with
SPICE simulations. This step is crucial to determine if
the design is ready (worth) to be sent out and fabricated
on Silicon.

3. Report (document) file including “Discussions and

Conclusions" and highligthing the results obtained,
4.Design Project: Samples of Design work
and Spice Verifications
Figure 1 shows a typical NMOS-input input CMOS
Operational Amplifier circuit employed in the design
projects. It is a 3-stage
stage design comprising a differential
input single- ended output differential amplifier,
followed by a DC- coupled high-gain inverting
nverting amplifier,
and the last stage, a source -follower
follower unity gain buffer
output stage for low output resistance and improved
drive capacity to meet the slew rate and output swing
requirements on the 50K // 50 pF load. Biasing is
accomplished with a 1 Mohm ohm external resistor which
delivers 9 uA current to a four transistor current mirror
(transistors M8, M5, M7 and M9) to control the bias
currents supplied to three stages of the OpAmp

Figure 3CMOS OpAmp AC Analysis

Figure 1CMOS OpAmp

Figure 2 Spice Error Log

Figure 4CMOS OpAmp Transient Analysis Vin=10u
 FOM ---- 24.3 p W m^2

Rout <10 Ohms 1.6m Ohms

Statement:
We have achieved the specifications given by our
instructor successfully.Though we have not minimized
the losses but we are just right into the desired values.

Figure 4CMOS OpAmp Transient Analysis

Rout=1.6mOhms
Note:
The required value of Rout was 10 Ohms but we have
desingned the op amp having Rout 1.6m Ohms.

5.Conclusions& Results
MOSFET W/L Id( m) |Vds|( V)
M1 20 1.2 1.683
M2 11 1.2 1.5
M3 3.2 .340 .937
M4 1.6 .179 1.640
M5 60 .171 1.5
M6 60 .171 1.5
M7 75 .171 .865
M8 75 .171 .865
M9 75 .179 1.559
M10 20 .170 2.3
M11 1.6 .170 .9

PARAMETER SPECIFICATIONS RESULTS ACHIEVED

GAIN 10,000 v/v 11,292 v/v

TOTAL POWER ---- 6mW

DISSIPATION
CMRR ---- 75.055dB
75.055

TOTAL AREA ---- 402.4p m^2