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Debug Scheme with Selective Data

Capture for Post-silicon Validation

Binod Kumar
CADSL Group Seminar
IITB

outline

Introduction(Prologue)

Motivation

Problem Statement

Proposed Debug Scheme[Yang et. al,TVLSI


2013 ]

Results

Drawbacks

Post Silicon Validation : Why?

Post Silicon Validation : Why?

PROLOGUE

Trace buffers are utilised to store data while


execution of the chip and this data is then offloaded for debug analysis.
Popular Compression techniques (MISR etc.)
can be used to enable storage of larger
quantities of data in the limited trace buffers.

PREVIOUS DEBUG
ARCHITECTURE

Debug architecture * requires re-running the debug session


many times which compacts the observed signals in a MISR.
MISR signatures are stored in the trace buffer over
progressively finer resolutions of time in each debug
session.
This approach implements an accelerated binary search that
gradually zooms in on clock cycles in which errors may
occur.

* E. Anis and N. Nicolici, Low cost debug architecture using lossy compression
for silicon debug, Proc. Design, Autom., Test Euro., pp. 16,2007
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MOTIVATION
GOLDEN RESPONSE

RESPONSE DUE TO BUG(S)

CY 1

CY2

CY 3

CY 4

CY 5

FF A

FF B

FF C

FF D

FF E

Capture in only few


clock cycles(1,4,5)

CY 1

CY 2

CY 3

CY 4

CY 5

FF A

FF B

FF C 0

FF D 0

FF E

PROBLEM STATEMENT: FORMAL


DEFINITION

Expand depth of observation window (i.e


number of clock cycles) of debug data to be
stored in trace buffer.
One method to achieve is this selective
capture of debug data (i.e skipping storage of
data of those clock cycles in which golden
response is same as response due to
bug/bugs)

PROPOSED DEBUG SCHEME

There are 3 steps (sessions) in the debug procedure:*


Step-1: Parity generation
The debug module computes the parity of the data word each
clock cycle and stores it in the trace buffer.
This information is downloaded to a workstation and
compared with the fault-free parity values
By comparing the fault-free parity with the observed parity, the
number of erroneous data words can be roughly estimated.

* Joon-Sung Yang and Nur A. Touba ,Improved Trace Buffer Observation via Selective Data Capture Using
2-D Compaction for Post-Silicon Debug TVLSI, 2013.
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PROPOSED DEBUG SCHEME


Step-2 : Compaction to identify suspect clock
cycles
In the second debug session, during the clock
cycles in the maximum expanded observation
window range from the first debug session,
compaction is activated to determine the
suspect set of clock cycles in which errors may
occur.

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PROPOSED DEBUG SCHEME


Step 3 : Capturing erroneous data

During the suspect clock cycles,debug data is


captured in the trace buffer.
Capturing all suspect clock cycles guarantees
that all errors in the expanded observation
window will be captured in the trace buffer.

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Session 1: Parity generation

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Error rate calculation

Count the number of errors in the parity bits.


Error rate is proportional to (parity
errors/number of bits to be stored.)

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Session 2:Compaction

K locations are allocated to store MISR signatures &


M locations are for storing cycling register signatures.
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Session 2 : Compaction
Illustration(Example 1)

Suspect clock cycles are identified by


intersection of mismatching signatures.
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Finding Suspect Clock cycles

window_size is expanded observation


window size. K MISR signatures are
generated.
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Session 3 : Capturing Suspect


Clock Cycles

Suspect clock cycles are selectively captured in


a trace buffer using the tag information.
During Session 3, when in the expanded
observation window, the trace buffer captures
data whenever the tag bit for the corresponding
clock cycle has a value of 1 indicating it is a
suspect.
For Example 1, 20 bit tag information is
00000000000010000000
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CONTENTS OF TRACE BUFFER :


EXAMPLE 1

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SCHEMATIC OF THE ENTIRE


DEBUG MODULE

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nd

DEBUG FLOW: 2 Illustration

C13 and C23 are


erroneous.
MS3, MS4 and CR3
gets corrupted.
Tag bit is generated
due to intersection of
mismatching
signatures.

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Compression of tag bits

C13, C18 and C23 are suspect clock cycles.

30 bit tag data generated is:


000000000000100001000010000000

This can be compressed into 15 bits(1


compressed bit for a group of two bits)
000000101001000

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Selective Debug Data Capture with


tag bits

Cycle tag bit shift register is used to provide serial access to the
tag bits so they can be checked one bit at a time each clock cycle.
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CONTENTS OF TRACE BUFFER :


EXAMPLE 2

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Experimental Results

[14]J. Shen and J. A. Abraham, Verification of processor microarchitectures, in Proc. IEEE VLSI Test Symp., 1999, pp. 189
194.

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DrawbacksNeed of further
investigation
1.As the tag data is read out of the trace buffer, it
can be overwritten in the trace buffer by the
captured data.
2.There is a need to calculate the area overhead
due to the debug module & look for ways to reduce
it.
3.Aliasing may also happen in the signatures.
4.Reducing the amount of tag bits that are
generated.
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THANKS FOR YOUR KIND ATTENTION.

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