INRODUCTION TO MICROPROCESSOR, UNIT 4

Prepared by: Er. Sarbesh Chaudhary

UNIT 4
INTERFACING I/O & MEMORY DEVICES

T-states
It is defined as one sub division of the operation performed in one clock period. These sub division are internal
states synchronized with system clock and each T states precisely equal to one clock period.

Machine cycle
It is defined as the time required to complete one operation of accessing memory, i/p, o/p or acknowledging and
external request. This cycle may consist of 3 to 6 T states.

Timing diagram
The necessary steps which are carried in a machine cycle can represented graphically. Such graphical
representation is called timing diagram.

Instruction cycle
The necessary steps that the CPU carries out to fetch an instruction and necessary data from the memory and to
execute it constitute and instruction cycle it is defined as the time required to complete the execution of an
instruction. An instruction cycle consists of fetch cycle and execute cycle. In fetch cycle CPU fetches opcode from
the memory . The necessary steps which are carried out to fetch an opcode from memory constitute a fetch cycle.
The necessary steps which are carried out to get data if any from the memory and to perform the specific
operation specified in an instruction constitute and execute cycle. The total time required to execute an
instruction given by IC = FC+ EC. The 8085 consists of 1-6 machine cycles or operations.

8085 Machine Cycles and their Timings

8085 has seven machine cycles. These are
1.Opcode Fetch Cycle
2.Memory Read Cycle
4.I/O Read Cycle
5.I/O Write Cycle
7.Bus Idle

3.Memory Write Cycle

6.Interrupt Acknowledge

Opcode Fetch Cycle

The first machine cycle of Microprocessor is always opcode fetch cycle in which Microprocessor finds the type of
instruction to be executed. Figure below shows the data flow and timing diagram for opcode fetch cycle. The
steps involved in opcode fetch cycle are illustrated below. Length of this cycle is 4 to 6 T-states.

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Step 1 (T1-state): In this state, 8085 places 16-bit memory address from the program counter on to the address
bus. The higher order byte of memory address is placed on A 7-A15 and the lower-order byte is placed on AD0-AD7
lines which stays ON till T1. Thus, Microprocessor activates ALE signal high.
8085 also sends three status signals i.e. IO/M= 0, which indicates it is memory related operation and signals S 1=1,
S2=1, which indicates this is opcode fetch operation.

Step 2 (T2-state): In T2, 8085 sends RD signal low in order to enable the addressed memory location. The memory
device then places the content of that memory location on to the data bus AD 0-AD7.
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INRODUCTION TO MICROPROCESSOR, UNIT 4

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Step 3 (T3-state): during T3, 8085 loads the data from data bus to the Instruction Register and makes RD signal
low to disable memory device.
Step 4 (T4-state): In T4, instruction decoder decodes the opcode and on the basis of the instruction received 8085
decides whether to enter T5 or to enter T1 of next machine cycles. One byte instructions which operate on 8-bit
data (operand) are executed in T4. For e.g.: MOV A,B ; ADD B etc.
Step 5 (T5 & T6): One byte instructions which operates on 16-bit data (operand) executes in T5 & T6. In these
states, 8085 performs stack write, internal 16-bit and conditional return operations depending upon the type of
instructions. For e.g.: INX H, DCX H, SPHL etc.

Memory READ Cycle

In order to execute 2-byte instructions consisting of an opcode and operand, two machine cycles are required.
Among these two machine cycles first one is opcode fetch and another one is memory read. 8085 executes
memory read cycle to read the contents of R/W memory or ROM. The length of this machine cycle is 3 T-states.
Figure below shows the and timing diagram for memory read cycle. The steps involved in memory read cycle are
illustrated below.
Step 1 (T1-state): In T1 8085 places the address on the address bus from stack pointer, general purpose register
pair or program counter and activates ALE signal HIGH in order to latch lower order byte of address. During T 1
8085 sends status signals i.e IO/M= 0 and S1=1, S0=0 for memory read machine cycle.
Step 2 (T2-state): In T2, 8085 sends RD signal high to enable the addressed memory location. The memory device
then places the content of that memory location on to the data bus AD 0-AD7.
Step 3 (T3-state): During T3, 8085 loads the data from the data bus to the specified register (A, B, C, D, E, H, L) and
raises RD to high which disables the memory device.

Memory WRITE Cycle

The 8085 executes the memory write machine cycle to store the data into data memory or stack memory. The
length of this machine cycle is 3 T-states. Figure below shows the timing diagram for memory write cycle. The
steps involved in memory write cycle are illustrated below.
Step 1 (T1-state): In T1 8085 places the address on the address bus from stack pointer, general purpose register
pair and activates ALE signal HIGH in order to latch lower order byte of address. During T 1 8085 sends status
signals i.e IO/M= 0 and S1=0, S0=1 for memory write machine cycle.
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INRODUCTION TO MICROPROCESSOR, UNIT 4

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Step 2 (T2-state): In T2, 8085 places data into the data bus and sends WR signal low to write into the addressed
memory location.
Step 3 (T3-state): During T3, WR signal goes high, which disables the memory device and terminates the write
operation.

Fig (a): Memory READ Machine Cycle

Fig (a): Memory WRITE Machine Cycle

I/O READ & WRITE Cycle

The I/O read and I/O write machine cycle is similar to Memory READ and Memory WRITE machine cycles
respectively. The only difference is that IO/M signal is high during I/O read and Write machine cycles. The high
IO/M signal indicates that it is an I/O operation. Figure below shows the diagram of I/O read and I/O write cycles
respectively.

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Fig (a): I/O read Machine Cycle

Prepared by: Er. Sarbesh Chaudhary

Fig (b): I/O write Machine Cycle

I/O INTERFACING
The I/O devices such as keyboard and display devices are the communication path for the Microprocessor to
communicate with outside world. Data can enter or transfer in serial mode or parallel mode. For the
communication of Microprocessor and I/O device a circuit is required which is knows as interfacing circuit. The
design of interfacing circuit depends upon instructions to be used for data transfer. There are two schemes for I/O
interfacing, they are 1. I/O mapped I/O & 2. Memory mapped I/O scheme.

I/O MAPPED I/O

Some CPUs provide one or more control lines (for example, IO/ M line for 8085), the status of which indicates
either memory or I/O operation. When the status of IO/ M line is high, it indicates I/O operation and when low, it
points to memory operation. Thus, in this case, the same address may be assigned to either memory or an I/O
device depending on the status of IO/M line.
The above scheme is referred to as I/O mapped I/O scheme. Here two separate address spaces existone space is
meant exclusively for memory operations and the other for I/O operations. Usually, the space earmarked for I/O is
8
much smaller than memory space. I/O mapped I/O is also known as standard I/O. A maximum of 2 = 256 I/Os
can be addressed in this mode, because in this mode a 1-byte address is specified.

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INRODUCTION TO MICROPROCESSOR, UNIT 4

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MEMORY MAPPED I/O

In this scheme, there is only one address space. This address space is allocated to both memory and I/O devices.
Some addresses are assigned to memories and some to I/O devices. The address for I/O devices is different from
the addresses which have been assigned to memories. An I/O device is also treated as a memory location. In this
scheme one address is assigned to each memory location and one address is assigned to each I/O device.
In this scheme, all data transfer instructions of the microprocessor can be used for transferring data from and to
either memory or I/O devices. For example, MOV D,M instruction would transfer one byte of data from a memory
location or an input device to the register D, depending on whether the address in the H-L register pair is assigned
to a memory location or to an input device. If H-L contains address of a memory location, data will be transferred
from that memory location to register D, while if H-L pair contains the address of an input device, data will be
transferred from that input device to register D.
This scheme is suitable for small systems. In this scheme, IO/ M signal is not used to distinguish between memory
and I/O devices. An I/O device is interfaced in the same manner as a memory device .
COMPARISON BETWEEN MEMORY MAPPED I/O AND I/O MAPPED I/O

Interfacing: The objective of interfacing an output device is to get information or a result out of the processor
and to display it; similarly the input device is interfaced to get information into the processor. To do that three
common steps are undertaken.
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INRODUCTION TO MICROPROCESSOR, UNIT 4

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1. Decode the address bus to generate a unique pulse corresponding to the device address on the bus; this is
called I/O address pulse.
2. Combine (AND) the device address pulse with the control signal to generate a device select (I/O select) pulse
that is generated only when both signals are applied.
3. Use the I/O select pulse to active the interfacing device (I/O ports)
The diagram below illustrates the steps:

The address lines A7 A0 are connected to a decoder which will generate a unique pulse corresponding to each
address on the address lines. This pulse is combined with the control signal to generate a device select pulse
which is used to enable an output latch or an input buffer.
Interfacing output display: The figure below shows an output interfacing circuit for LED display

Here:
The address bus A7 A0 is decoded by using an 8 input NAND gate.
The output of the NAND gate goes low only when the address line carries the address FF H.
The output of the NAND gate combines with the microprocessor control signal IOW in a NOR gate
(connected as a negative AND). The output of NOR gate (74LS02) goes high to generate on I/O select pulse
when both inputs are low (or both signals are asserted).
Meanwhile the contents of the accumulator have been put on the data bus.
The I/O select pulse is used to activate the latch and data are latched and displayed on the diodes.(LEDs)

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INRODUCTION TO MICROPROCESSOR, UNIT 4

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Interfacing an Input device (DIP switches): The figure below shows an input interfacing circuit for DIP
switches.

Here:
The address bus A7 A0 is decoded using a decoder.
The output of the decoder (O4) goes low only when the address line carries the address 84H.
The output of the decoder combines with the P control signal IOR in a negative NAND gate. The output of
this gate goes low to generate an I/O select pulse when both inputs are low.
The I/O select pulse is used to activate the buffer and the data from the DIP switches (F8H) is put on the
data.

UNIQUE & NON-UNIQUE ADRESS DECODING

If only a portion of the addressable space is going to be implemented there are two basic address decoding
strategies they are as follows:
1. UNIQUE (or Full) address decoding
All the address lines are used to specify a memory location
Each physical memory location is identified by a unique address
2. Non-UNIQUE (or Partial) address decoding
Since not all the address space is implemented, only a subset of the address lines are needed to point to
the physical memory locations
Each physical memory location is identified by several possible addresses (using all combinations of the
address lines that were not used)

MEMORY STRUCTURE
A memory is a device that stores information in electrical, magnetic or optical form. A C based system, which
operates on digital logic, holds binary information. Semiconductor memories are used in C based system.
Semiconductor memories have become very popular and widely used because of their high reliability, low cost,
high speed and ease with which memory size can be expanded. It can be categorized into two ways:
Primary memory or main memory or working memory.
Secondary memory or auxiliary memory or mass storage.
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RAM and ROM comprise the primary memory while magnetic tapes, magnetic disks, floppy disks or compact disks
(CDs) are examples of secondary memory. Difference between the two types of memories are given below,

Primary Memory:
It is the storage area where all programs are executed. The microprocessor can directly access only those items
that are stored in the primary memory. Hence, all programs and data must be within the primary memory prior to
execution. Usually, the size of the primary memory is much larger than that of processor memory and its
operating speed is much slower than processors registers. Primary memories can be divided into two main
groups:
1. Read only memory (ROM)
2. Random Access memory. (RAM)
Random Access memory OR Read/Write memory:
It is a volatile memory and is used in store programs and datas for immediate use of the processor. Data can be
readily written into and read from a RAM at any selected address in any sequence. Two types of read/write
memories are available:
Static RAM
Dynamic RAM
Comparison of SRAM and DRAM
SRAM
DRAM
It stands for static RAM
It stands for Dynamic RAM
This memory is made up of flip-flops and bits are This memory is made up of MOS transistor gates and
stored in the form of voltage.
stores bits as charge.
It has low density.
It has high density.
It has high speed.
It has low speed.
It is more expensive.
It is less expensive.
It consumes less power.
It consumes more power.
Does not need to be refreshed.
As the data is stored in the form of charge, it leaks, so
memory has to be refreshed.
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Read only memory (ROM):

ROM is a non volatile memory and can be read only. It is used to store data and programs that are not to be
altered. ROM is constructed using diodes. Among other things ROM is needed for storing an initial program called
boot strap loader. The bootstrap loader is a program whose function is to start the computer software operating
when power is turned on. Since RAM is volatile, its contents are destroyed when power is turned off. The contents
of ROM remain unaltered after power is turned off and on again. The startup of a computer consists of turning the
power on and starting the execution of an initial program. Thus when power is turned on, the hardware of the
computer sets the program counter to the first address of the bootstrap loader. The bootstrap program loads a
portion of the operation of the operating system from disk to main memory and control is then transferred to the
operating system, which prepares the computer for general use. There are five types of ROM, they are discussed
below.
Masked ROM: In this ROM, a bit pattern is permanently stored. Memory manufactures are generally equipped to
do this.
PROM (Programmable ROM): This memory has nichrome or polysilicon wires arranged in a matrix. These wires
can be functionally viewed as diode or fuse. This memory can be programmed by the user with a special PROM
programmer that selectively burns the fuses (applying high current) according to the bit patters to be stored. The
process is known as burning the PROM, and the information stored is permanent.
EPROM (Erasable PROM): EPROM uses MOSFETS. Data is stored with PROM programmer. Later data can be
erased with ultraviolet light. The effect is to wipe out the stored contents. In other word, the EPROM is ultravioletlight-erasable and electrically programmable. Once the chip is programmed the window is covered with opaque
tape to avoid accidental erasing.
EEPROM (Electrically erasable PROM): This is nonvolatile like EPROM but does not require U-V rays to be erased.
It can be completely erased or have certain byes changed, using electrical pulses. Writing to EEPROM is slower
than writing to RAM, so it cannot be used in high speed circuits.
FLASH MEMORY: This is a modified EEPROM. The difference is the erasure procedure. EEPROM can be erased
at a register level, but flash memory must be erased either in its entirety or at the sector (block) level.

MEMORY INTERFACING
To communicate with the memory Microprocessor selects the chips, identifies the register and then read from or
writes into the register. For this purpose following are the requirement for memory chip.
1. A memory chip requires address line to identify a memory register.
2. A memory chip requires a chip select signal (CS) to enable the chip.
3. Address lines connected to CS selects the chip & address lines connected to address lines of memory chip
selects the register.
4. Two control signals RD & WR are required. RD enables the output buffer while WR enables to input buffer.

INTERNAL STRUCTURE OF MEMORY:

The internal structure of a 8 8 memory is shown below. Every memory unit has the similar types of structure.
Internally a memory consists of address decoder, input buffer, output buffer, registers, address lines, data lines,
RD, WR, CS control lines as shown in the figure below.
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The number of address lines will be determined by

the memory capacity. The number of data lines will
be determined by memory size. For example for
memory capacity 1k 8 will have 10 address lines
and data lines. 2k 4 chip will have 11 address lines
and 4 data lines. For 2n k m memory capacity the
number of address lines = n and number of data
lines = m.
Lets consider the 8 8 memory device with 8
registers, a 3 to 8 decoder, an input buffer and an
output buffer. The device will have 3 address lines
and eight data lines. It will also have control lines RD,
WR and CS.
To write an 8 bit word the p places the
register address on the three address line e.g. to
write in the register 7, p places 111 on the address
lines.
The decoder decodes the address and selects
the register 7.
Then the p places the data on the data bus and sends the active low WR control signal.
The control signal enables the input buffer and data are placed in the selected register.
To read from this memory, the process is similar to that of write operation except that output buffer is
enabled with RD active low signal.
The remaining address lines of the p address bus are used to select the chip (CS).

INTERFACING RAM
To interface RAM chip following steps should be taken into
consideration
1. 8085 places a 16-bit address on an address bus & with this address
only one register must be selected. For RAM chip only 11 lines are
required to identify 2048 registers. So, address lines A0-A10 are
connected to the memory chip.
2. The remaining address lines A11-A15 should be decoded to generate a
chip select signal CS.
3. In order to read from memory, MEMR signal will be generated & in
order to write into memory, MEMW signal will be generated to enable
the appropriate buffer.

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Address Decoding for RAM chips: Address decoding of RAM can be achieved in two ways, they are by using
decoders and by using NAND gate, both type of decoding are given below.
1. By using 3:8 Decoder

For interfacing the chip with 8085 p we just need and additional 3 to 8 decoder to select the chip. The register
inside the chip can be identified by the internal address decoder and input or output buffers can be enabled by
the control signals RD or WR.
The memory chip 2048 8 requires 11 address lines to identify the 2048 register. Therefore the lower address
lines A10 A0 form the P are connected to the chip. The remaining address line (A15 A11) should be decoded to
generate a chip select (CS) signal unique for that chip.
The remaining five lines are connected to the decoder (3 to 8 decoder) as shown is the figure above.

The decoder is enabled by IO / M signal is addition to address lines A15 and A14
The output O1 of the decoder is connected to CS of the memory chip.
The input line lines to the decoder are A15, A12, and A11. These activate the output O1 to select the
memory chip.
Thus to select the memory chip we must have the output O1 to selected by the 3 to 8 decoder, which
means we need A13 = 0, A12 = 0, A11 = 1
Also to enable the 3 to 8 decoder we need IO / M low and A14 = 0 , A15 = 1

Thus the chip is selected by 10001 at lines A15 A11 of the address bus. And hence the range of address for the
memory chip would be
10001 00000000000 = 8800 H
10001 11111111111 = 8FFF H
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INRODUCTION TO MICROPROCESSOR, UNIT 4

2. By using NAND gate

In this case, the higher address lines A15 A11 are

connected to the NAND gate for decoding and
lower address lines A0-A10 are connected to
memory chip.

INTERFACING ROM
To interface RAM chip following steps should be taken into consideration
1.8085 places a 16-bit address on an address bus & with this address only
one register must be selected. For ROM chip only 12 lines are required to
identify 4096 registers. So, address lines

A0-A11

are connected to the

memory chip.
2. The remaining address lines A12-A15 should be decoded to generate a
chip select signal CS.
3. In order to read from memory, MEMR signal will be generated to enable
the appropriate buffer.
Address Decoding for ROM chips: Address decoding of ROM can also be achieved in two ways, they are by using
decoders and by using NAND gate same as for RAM, both type of decoding are given below.
1. By using 3:8 Decoder

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Similarly the ROM can be interfaced with 8085. The only difference would be, there would be no WR lines
connection, as this memory is not used for write operation. The interfacing is as shown above.
2. By using NAND gate

DMA (Direct Memory Access)

Instruction set of a processor provides for data transfer between processor registers and memory or I/O device.
Thus when data transfer between memory and an I/O device is needed, it is done in two steps, from memory to
accumulator of processor and then to I/O device or reverse. This slows down data transfer. DMA mode is
introduced to overcome this.
In DMA mode, straight data exchange takes place between memory and I/O device bypassing the processor. This
is done with the help of a DMA controller. In DMA mode, the DMA controller acts as a Master and the
processor as a Slave. This is a process where data is transferred between two peripherals directly without the
involvement of the microprocessor. This process employs the HOLD & HLDA pin on the microprocessor.
Steps involved in DMA transfer scheme are as follows
1. The external DMA controller sends a high signal on the HOLD pin to the microprocessor.
2. The microprocessor completes the current operation and sends a signal on HLDA and stops using the buses.
3. DMA controller takes control of buses and transfers the data.
4. Once the DMA controller finishes its task, it turns off the HOLD signal and the microprocessor takes back
control of the buses.

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