Course 1: Logic Course 1: Logic Design for VLSI Engineers

Design for VLSI

Engineers
( E-learning with Assessments and Practice
Sessions: 10 hours A student would need to
spend
30-35 hours learning this material. It is
recommended that a student spend no more
than 1-2
hours each day for two weeks before the lab
session to truly benefit from the program.
Concept Labs and Project Work*: 16 hours
(2 days)

E-learning topics:
Combinational and Sequential Circuit Design
techniques
Timing parameters for digital logic gates and flip
flops
Glitches and Hazards in combinational circuits
Combinational circuit design techniques
Sequential circuit design techniques
Finite State Machines (FSM)
Introduction to Memories
Practice sessions
Assessments

Concept Labs:
1. Implement a full
adder using a mux
2: Design an electronic
voting machine for
given specifications
3: Optimize the logic
between sequential
cells to meet timing
requirements

Projects:
1. To design a digital watch by
identifying the basic building blocks
of the system for the given
specifications
2: To design the transmitter block of a
Universal Asynchronous Receiver
Transmitter( UART) for the given
specifications

4. Adaptive online
assessment - 2 hours
*Note: In Logic Design for VLSI
Engineers course, the concept
labs and projects are instructorled
paper based activities
The concept labs and projects
may vary depending on the
competency level of participants.
Additional concepts and projects
are offered for learners after
completion of mandatory
exercises.

Course 2: RTL
Course 2: RTL Verification using Verilog
Verification using Verilog E-learning with Assessments and Practice
Sessions: 12 hours. A student would need to
spend
36-42 hours learning this material. It is
recommended that a student spend no more
than 1-2
hours each day for two weeks before the lab
session to truly benefit from the program.
Concept Labs and Project Work: 16 hours (2
days)

E-learning topics:
Introduction to RTL Verification
o Introduction to RTL verification
o Evolution of verification process
o Overview of basic concepts and terminology
o Assessments and questions
o Introduction to a test bench
Verification planning
o Introduction to Verification Planning
o Assessments and questions
o Development of a verification plan for an
arithmetic logic unit (ALU)
Testbench Architecture
o Test bench development and simulation
o Running the test bench on a RTL simulator
(Demo)
Advances in RTL Verification
o Overview of advanced terminologies and
concepts
o Advances in RTL Verification

Concept Labs:
1: To simulate the Half-Adder
testbench on an RTL simulator to
familiarize with the usage of the
simulator
2: To simulate a testbench for a threebit
Counter on an RTL simulator and
gain familiarity with the simulator
3: Perform feature extraction and
develop the verification plan from
the design specification
4: To perform feature extraction and
develop the verification plan for the
given design specification
5: To run the ALU testbench on an RTL
simulator and check the code
coverage. Improve the code
coverage for the given specifications

Projects:
1: To develop a Verilog testbench to
verify a FIFO for the given design
specifications. Perform simulations,
debug and achieve 100% code
coverage
2: To develop a Verilog testbench to
verify a Programmable Up / Down
Counter for the given specifications.
Perform simulations, debug and
achieve 100% code coverage

Adaptive Online Assessment 2 hours

Note: The concept labs and projects may vary
depending on the competency level of
participants. Additional concepts and projects are
offered for learners after completion of
mandatory exercises.

Course 3: RTL Design using Course 3: RTL Design using Verilog

Verilog
E-learning with Assessments and Practice
Sessions: 12 hours. A student would need to
spend
36-42 hours learning this material. It is
recommended that a student spend no more than
1-2
hours each day for two weeks before the lab
session to truly benefit from the program.
Concept Labs and Project Work: 16 hours (2
days)

E-learning topics:
Introduction to digital design using
HDLs
Overview of frequently used Verilog
constructs
Hardware Inference of Verilog code
General coding guidelines for Verilog
Modeling FSMs and memories in Verilog
Evolution of Verilog standards
Deliverables of an RTL design engineer

Concept Labs:
1:To design and implement an Adder
cum Subtractor for the given
specifications and perform
functional simulation to verify the
design specification
2: To complete the design of a Barrel
Shifter design in accordance with
the design specification using
Verilog and perform functional
simulation to verify the design
specification
3: Debug the given design file against
the design specifications and
compile the design to fix the errors
4: Design a memory module for the
given specifications and perform
functional simulation to verify the
specifications
5: Modify the given design to meet
the design specifications and
perform functional simulation to
verify the design
6: Realize a programmable baud rate
generator for the given
specifications and perform
functional simulation to verify the
design
7: Modify the given design file as per
the verilog coding guidelines and
simulate the design to verify the
design specification

Projects:
1: Design a daisy chain arbiter for the
given design specifications, compile
the design to fix the errors and
perform simulation to verify the
specifications of the design
2: Design a daisy chain arbiter for the
given design specifications, compile
the design to fix the errors and
perform simulation to verify the
specifications of the design

Adaptive Online Assessment 2 hours

Note: The concept labs and projects may vary
depending on the competency level of
participants. Additional concepts and projects
are offered for learners after completion of
mandatory exercises.

Course 4: Fundamentals
of Static Timing Analysis
(STA)

Course 4: Fundamentals of Static Timing

Analysis (STA)
E-learning with Assessments and Practice
Sessions: 12 hours. A student would need to
spend 36-42 hours learning this material. It is
recommended that a student spend no more
than 1-2 hours each day for two weeks before
the lab session to truly benefit from the
program.
Concept Labs and Project Work: 16 hours (2
days)

E-learning topics:
Introduction to timing analysis
Terminologies used in Static Timing
Analysis
Estimating path delays in
combinational logic circuits
Estimating path delays in
sequential logic circuits
Clocks and their characteristics
Understanding timing reports

Concept Labs:
1: To analyze the timing report and
derive the schematic with necessary
parameters
2: To compute the setup slack for a
given sequential logic circuit and
maximum operating frequency
3: To measure the delay between input
and output ports of a combinational
logic circuit
4: To calculate the recovery and
removal slack for a sequential circuit
5: To measure the Arrival and Required
Time for the given specifications and
calculate the setup and hold slack

Projects:
1: Analyze the timing specifications of
the given circuit and perform pre
layout and post layout timing checks
to measure the setup and hold slack
under varied operating conditions.
2: Run timing analysis to measure
setup and hold slack and review the
timing report to identify the multiple
timing paths in the design to validate
timing specifications of each path

Adaptive Online Assessment 2 hours

Note: The concept labs and projects may vary
depending on the competency level of
participants. Additional concepts and projects
are offered for learners after completion of
mandatory exercises.

Course 5: Advanced Static Timing

Analysis (STA)

Course 5: Advanced Static Timing Analysis

(STA)
E-learning with Assessments and Practice
Sessions: 16 hours. A student would need to
spend 40-45
hours learning this material. It is recommended
that a student spend no more than 1-2 hours
each
day for two weeks before the lab session to truly
benefit from the program.
Concept Labs and Project Work: 16 hours (2
days)

E-learning topics:
Introduction to timing analysis
Terminologies used in Static Timing Analysis
Estimating path delays in combinational logic
circuits
Estimating path delays in sequential logic circuits
Clocks and their characteristics
Understanding timing reports
PVT variations and their effect on Timing

Concept Labs:
1 To analyze the timing report and derive the
schematic with necessary parameters
2: To compute the setup slack for a given
sequential logic circuit and
maximum operating frequency
3: To measure the delay between input
and output ports of a combinational
logic circuit
4: To calculate the recovery and
removal slack for a sequential circuit
5: To measure the Arrival and Required
Time for the given specifications and
calculate the setup and hold slack

Projects:
1: Analyze the timing specifications
of
the given circuit and perform pre
layout and post layout timing
checks
to measure the setup and hold
slack
under varied operating conditions.
2: Run timing analysis to measure
setup and hold slack and review the
timing report to identify the
multiple
timing paths in the design to
validate
timing specifications of each path

Adaptive Online Assessment 2 hours

Note: The concept labs and projects may vary
depending on the competency level of
participants.
Additional concepts and projects are offered for
learners after completion of mandatory
exercises.

Course
Course 1: Logic Design for
VLSI Engineers

E-Learning
Course 1: Logic Design for VLSI Engineers
( E-learning with Assessments and Practice
Sessions: 10 hours A student would need to
spend
30-35 hours learning this material. It is
recommended that a student spend no more than
1-2
hours each day for two weeks before the lab
session to truly benefit from the program.
Concept Labs and Project Work*: 16 hours (2
days)

Course 2: RTL Verification

using Verilog

Course 2: RTL Verification using Verilog

E-learning with Assessments and Practice
Sessions: 12 hours. A student would need to spend
36-42 hours learning this material. It is
recommended that a student spend no more than
1-2
hours each day for two weeks before the lab
session to truly benefit from the program.
Concept Labs and Project Work: 16 hours (2
days)

Course 3: RTL Design using

Verilog

Course 3: RTL Design using Verilog

E-learning with Assessments and Practice
Sessions: 12 hours. A student would need to spend
36-42 hours learning this material. It is
recommended that a student spend no more than
1-2
hours each day for two weeks before the lab
session to truly benefit from the program.
Concept Labs and Project Work: 16 hours (2
days)

Course 4: Fundamentals of
Static Timing Analysis (STA)

Course 4: Fundamentals of Static Timing

Analysis (STA)
E-learning with Assessments and Practice
Sessions: 12 hours. A student would need to
spend 36-42 hours learning this material. It is
recommended that a student spend no more
than 1-2 hours each day for two weeks before the
lab session to truly benefit from the
program.
Concept Labs and Project Work: 16 hours (2
days)

Course 5: Advanced Static

Timing Analysis (STA)

Course 5: Advanced Static Timing Analysis

(STA)
E-learning with Assessments and Practice
Sessions: 16 hours. A student would need to spend
40-45
hours learning this material. It is recommended
that a student spend no more than 1-2 hours each
day for two weeks before the lab session to truly
benefit from the program.
Concept Labs and Project Work: 16 hours (2
days)

E-Learning Topics
E-learning topics:
Combinational and Sequential Circuit Design
techniques
Timing parameters for digital logic gates and flip
flops
Glitches and Hazards in combinational circuits
Combinational circuit design techniques
Sequential circuit design techniques
Finite State Machines (FSM)
Introduction to Memories
Practice sessions
Assessments

E-learning topics:
Introduction to RTL Verification
o Introduction to RTL verification
o Evolution of verification process
o Overview of basic concepts and terminology
o Assessments and questions
o Introduction to a test bench
Verification planning
o Introduction to Verification Planning
o Assessments and questions
o Development of a verification plan for an arithmetic
logic unit (ALU)
Testbench Architecture
o Test bench development and simulation
o Running the test bench on a RTL simulator (Demo)
Advances in RTL Verification
o Overview of advanced terminologies and concepts
o Advances in RTL Verification

E-learning topics:
Introduction to digital design using HDLs
Overview of frequently used Verilog constructs
Hardware Inference of Verilog code
General coding guidelines for Verilog
Modeling FSMs and memories in Verilog
Evolution of Verilog standards
Deliverables of an RTL design engineer

E-learning topics:
Introduction to timing analysis
Terminologies used in Static Timing Analysis
Estimating path delays in combinational logic circuits
Estimating path delays in sequential logic circuits
Clocks and their characteristics
Understanding timing reports

E-learning topics:
Introduction to timing analysis
Terminologies used in Static Timing Analysis
Estimating path delays in combinational logic circuits
Estimating path delays in sequential logic circuits
Clocks and their characteristics
Understanding timing reports
PVT variations and their effect on Timing

Concept Labs
Concept Labs:
1. Implement a full
adder using a mux
2: Design an electronic
voting machine for
given specifications
3: Optimize the logic
between sequential
cells to meet timing
requirements

Projects
Projects:
1. To design a digital watch by
identifying the basic building blocks
of the system for the given
specifications
2: To design the transmitter block of a
Universal Asynchronous Receiver
Transmitter( UART) for the given
specifications

Concept Labs:
1: To simulate the Half-Adder
testbench on an RTL simulator to
familiarize with the usage of the
simulator
2: To simulate a testbench for a threebit
Counter on an RTL simulator and
gain familiarity with the simulator
3: Perform feature extraction and
develop the verification plan from
the design specification
4: To perform feature extraction and
develop the verification plan for the
given design specification
5: To run the ALU testbench on an RTL
simulator and check the code
coverage. Improve the code
coverage for the given specifications

Projects:
1: To develop a Verilog testbench to
verify a FIFO for the given design
specifications. Perform simulations,
debug and achieve 100% code
coverage
2: To develop a Verilog testbench to
verify a Programmable Up / Down
Counter for the given specifications.
Perform simulations, debug and
achieve 100% code coverage

Concept Labs:
1:To design and implement an Adder
cum Subtractor for the given
specifications and perform
functional simulation to verify the
design specification
2: To complete the design of a Barrel
Shifter design in accordance with
the design specification using
Verilog and perform functional
simulation to verify the design
specification
3: Debug the given design file against
the design specifications and
compile the design to fix the errors
4: Design a memory module for the
given specifications and perform
functional simulation to verify the
specifications
5: Modify the given design to meet
the design specifications and
perform functional simulation to
verify the design
6: Realize a programmable baud rate
generator for the given
specifications and perform
functional simulation to verify the
design
7: Modify the given design file as per
the verilog coding guidelines and
simulate the design to verify the
design specification
Concept Labs:
1: To analyze the timing report and
derive the schematic with necessary
parameters
2: To compute the setup slack for a
given sequential logic circuit and
maximum operating frequency
3: To measure the delay between input
and output ports of a combinational
logic circuit
4: To calculate the recovery and
removal slack for a sequential circuit
5: To measure the Arrival and Required
Time for the given specifications and
calculate the setup and hold slack

Projects:
1: Design a daisy chain arbiter for the
given design specifications, compile
the design to fix the errors and
perform simulation to verify the
specifications of the design
2: Design a daisy chain arbiter for the
given design specifications, compile
the design to fix the errors and
perform simulation to verify the
specifications of the design

Projects:
1: Analyze the timing specifications of
the given circuit and perform pre
layout and post layout timing checks
to measure the setup and hold slack
under varied operating conditions.
2: Run timing analysis to measure
setup and hold slack and review the
timing report to identify the multiple
timing paths in the design to validate
timing specifications of each path

Concept Labs:
1 To analyze the timing report and derive
the schematic with necessary parameters
2: To compute the setup slack for a given
sequential logic circuit and
maximum operating frequency
3: To measure the delay between input
and output ports of a combinational
logic circuit
4: To calculate the recovery and
removal slack for a sequential circuit
5: To measure the Arrival and Required
Time for the given specifications and
calculate the setup and hold slack

Projects:
1: Analyze the timing specifications of
the given circuit and perform pre
layout and post layout timing checks
to measure the setup and hold slack
under varied operating conditions.
2: Run timing analysis to measure
setup and hold slack and review the
timing report to identify the multiple
timing paths in the design to validate
timing specifications of each path

Adaptive Online assesment

4. Adaptive online assessment - 2 hours
*Note: In Logic Design for VLSI Engineers course,
the concept labs and projects are instructorled
paper based activities
The concept labs and projects may vary
depending on the competency level of
participants.
Additional concepts and projects are offered for
learners after completion of mandatory
exercises.

Adaptive Online Assessment 2 hours

Note: The concept labs and projects may vary
depending on the competency level of
participants. Additional concepts and projects
are offered for learners after completion of
mandatory exercises.

Adaptive Online Assessment 2 hours

Note: The concept labs and projects may vary
depending on the competency level of
participants. Additional concepts and projects
are offered for learners after completion of
mandatory exercises.

Adaptive Online Assessment 2 hours

Note: The concept labs and projects may vary
depending on the competency level of
participants. Additional concepts and projects
are offered for learners after completion of
mandatory exercises.

Adaptive Online Assessment 2 hours

Note: The concept labs and projects may vary
depending on the competency level of
participants.
Additional concepts and projects are offered for
learners after completion of mandatory
exercises.