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SpyGlassLint

SpyGlassLint
EarlyDesignAnalysisforLogicDesigners
Overview
InefficienciesduringRTLdesignusuallysurfaceascriticaldesignbugsduringthelatestagesofdesignimplementation.If
detected,thesebugswilloftenleadtoiterations,andifleftundetected,theywillleadtosiliconrespins.TheSpyGlassproduct
familyistheindustrystandardforearlydesignanalysiswiththemostindepthanalysisattheRTLdesignphase.SpyGlass
providesanintegratedsolutionforanalysis,debugandfixingwithacomprehensivesetofcapabilitiesforstructuralandelectrical
issuesalltiedtotheRTLdescriptionofdesign.
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Introduction
Withsoaringcomplexityandsizeofchips,achievingpredictabledesignclosurehasbecomeachallenge.Amultitudeofcoding
style,structuralandelectricaldesignissuescanmanifestthemselvesasdesignbugsandresultindesigniterations,orworststill
siliconrespins.Othertoolsmaydetectdesignbugsbutoftenatlatestagesofdesignimplementation,afterasignificantinvestment
intimeandefforthasalreadybeenmade.Asdesignteamsbecomegeographicallydispersed,consistencyandcorrectnessof
designintentbecomesakeychallengeforchipintegrationteams.EmphasisondesignreuseandIPintegrationrequiresthat
designelementsbeintegratedandmeetguidelinesforcorrectnessandconsistency.

Figure1:SpyGlassRTLSignoffSolution

SpyGlassLint:StructuralRTLChecks
SpyGlasslintingintegratesindustrystandardbestpractices,aswellasSynopsysownextensiveexperienceworkingwith
industryleadingcustomers.LintchecksincludedesignreusecompliancecheckssuchasSTARCandOpenMOREtoenforcea
consistentstylethroughoutthedesign,easetheintegrationofmultiteamandmultivendorIPandpromotedesignreuse.

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Figure2:TheSpyGlasssolutionacceleratesandeconomizesICdevelopmentby
minimizingcostly,timeconsumingdesignanddebugiterations

Figure3:SpyGlassLintforRTLAnalysis

SpyGlassLintAdvanced:Smarter,FasterandDeeperDesignAnalysisWithTurboandFormal
Technologies
SynopsyssnextgenerationSpyGlassLintAdvancedSolutionprovidesathreeprongedattackontheissuesfacingSoCRTL
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signoff.
SmarteranalysisinTurbomodewithviolationcategorizationbyrootcauseforfasterdebug
Fasterhierarchicalflowwithabstractmodelswithupto10Xperformancegain
Deeperanalysisusingformaltechnologytomitigatefunctionalerrorsoncorrespondingstructurallintrulesandtoremove
uncertaintywithconclusiveresults
Usingadvancedformalanalysis,SpyGlasspinpointsdeeperfunctionalproblemsinRTLdesignswithoutrequiringtestbenchesor
assertions.SpyGlassensuresthatdesignintentiscorrectbyverifyingcontrollogic(FSM),synchronousFIFOs,signalstoggling,
busintegrity(contention,floatingstate,indexoverflow)anddesigninitialization.TheresultingRTLismoreoptimizedand
verifiablewithcomprehensiveFSMstylereportinganddetectionoflogicredundancies(deadcode).Thisimprovesthearea,
timing,powerandtestabilityofyourdesign.SpyGlassalsoprovidesadesigncomplexityDashBoardfortrackingRTLqualityasit
isdeveloped.

EarlyDetectionofImplementationChallenges
SynopsysSpyGlasssolutiongreatlyreducestheriskofdevelopingcomplexmultimilliongate,nanometerscaleICsbyaccurately
detectingdesignissuesatRTL.TheSpyGlasssolutionflagsareasofthedesignthatarelikelytopresentimplementation
challenges.
SophisticatedstaticanddynamicanalysisidentifiescriticaldesignissuesatRTL
Acomprehensivesetofelectricalruleschecktoensurenetlistintegrity
Includesdesignreusecompliancechecks,suchasSTARCandOpenMOREtoenforceaconsistentstylethroughoutthe
design
Customizableframeworktocaptureandautomatecompanyexpertise
Integrateddebugenvironmentenableseasycrossprobingamongviolationreports,schematicandRTLsource
Themostcomprehensiveknowledgebaseofdesignexpertiseandindustrybestpractices
SupportsVerilog,VHDL,V2K,SystemVerilogandmixedlanguagedesigns
Tclshellforefficientruleexecutionanddesignquery
SoCabstractionflowforfasterperformanceandlownoise

AdvancedMethodology
SpyGlassLintprovidesastructured,easytouseandcomprehensivemethodforsolvingRTLdesignissues,therebyensuring
highqualityRTLwithfewerbutmeaningfulviolations.
GuideWaremethodologydocumentationandrulesetsincluded
Infrastructureforruleselectionandcustomizationalignedwithdesignmilestones
WalksusersthroughaseriesofrecommendedstepstoensuredesigncompliancetoHDLstandards,codingstyle,
synthesis,simulation,verification,connectivity,clockandresetissues
Stepbystepapproachdetectsandfixesdesignbugsinalignmentwithdesignmilestones,andensurespredictabledesign
closurewithoutanylastminutesurprisesorhighvolumeofviolations

SeamlessIntegrationIncreasesEfficiency
SpyGlassLintsupportscorrectbyconstructiondesign,leadingtoearlydesignclosureandminimizingcostlybackend
debugginganditerations.
IntegrateswithadvancedSpyGlasscapabilitieslikeCDC,Constraints,Power,DFTandPhysicalfeasibilityanalysis
Easytorampupandbeginproductiveusewithinhalfaday,evenfornonexperts
Structuredmethodologyenablesquickadoptionbyengineersandconstraintsoptimizeddesigns
Reducesoreliminatesneedforrespins,potentiallysavingmillionsofdollars
EnablesearlyclosureofhandoffreadyRTLdesign
ElevatesdesignoptimizationfromgateleveltoRTL,whereitismostcosteffective
Helpsdisperseddesignteamstocreatemoreconsistent,highqualitydesigns
EnableseffectivedesignreuseandIPintegration
Integratesseamlesslyintoexistingdesignenvironments,dramaticallyenhancingefficiencyofinstalledtoolsand
methodologies
SpyGlassPredictiveAnalyzersignificantlyimprovesdesignefficiencyfortheworldsleadingsemiconductorandconsumer
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electronicscompanies.Patentedsolutionsprovideearlydesigninsightintothedemandingperformance,powerandarea
requirementsofthecomplexsystemonchips(SoCs)fuelingtodaysconsumerelectronics.

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